2 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 /* Resource binding slots and sampler states (each described with 8 or
26 * 4 dwords) are stored in lists in memory which is accessed by shaders
27 * using scalar load instructions.
29 * This file is responsible for managing such lists. It keeps a copy of all
30 * descriptors in CPU memory and re-uploads a whole list if some slots have
33 * This code is also reponsible for updating shader pointers to those lists.
35 * Note that CP DMA can't be used for updating the lists, because a GPU hang
36 * could leave the list in a mid-IB state and the next IB would get wrong
37 * descriptors and the whole context would be unusable at that point.
38 * (Note: The register shadowing can't be used due to the same reason)
40 * Also, uploading descriptors to newly allocated memory doesn't require
44 * Possible scenarios for one 16 dword image+sampler slot:
46 * | Image | w/ FMASK | Buffer | NULL
47 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
48 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
49 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
50 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
52 * FMASK implies MSAA, therefore no sampler state.
53 * Sampler states are never unbound except when FMASK is bound.
59 #include "util/hash_table.h"
60 #include "util/u_idalloc.h"
61 #include "util/u_format.h"
62 #include "util/u_memory.h"
63 #include "util/u_upload_mgr.h"
66 /* NULL image and buffer descriptor for textures (alpha = 1) and images
69 * For images, all fields must be zero except for the swizzle, which
70 * supports arbitrary combinations of 0s and 1s. The texture type must be
71 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
73 * For buffers, all fields must be zero. If they are not, the hw hangs.
75 * This is the only reason why the buffer descriptor must be in words [4:7].
77 static uint32_t null_texture_descriptor
[8] = {
81 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) |
82 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
83 /* the rest must contain zeros, which is also used by the buffer
87 static uint32_t null_image_descriptor
[8] = {
91 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
92 /* the rest must contain zeros, which is also used by the buffer
96 static uint64_t si_desc_extract_buffer_address(const uint32_t *desc
)
98 uint64_t va
= desc
[0] |
99 ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
101 /* Sign-extend the 48-bit address. */
103 va
= (int64_t)va
>> 16;
107 static void si_init_descriptor_list(uint32_t *desc_list
,
108 unsigned element_dw_size
,
109 unsigned num_elements
,
110 const uint32_t *null_descriptor
)
114 /* Initialize the array to NULL descriptors if the element size is 8. */
115 if (null_descriptor
) {
116 assert(element_dw_size
% 8 == 0);
117 for (i
= 0; i
< num_elements
* element_dw_size
/ 8; i
++)
118 memcpy(desc_list
+ i
* 8, null_descriptor
, 8 * 4);
122 static void si_init_descriptors(struct si_descriptors
*desc
,
123 short shader_userdata_rel_index
,
124 unsigned element_dw_size
,
125 unsigned num_elements
)
127 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
128 desc
->element_dw_size
= element_dw_size
;
129 desc
->num_elements
= num_elements
;
130 desc
->shader_userdata_offset
= shader_userdata_rel_index
* 4;
131 desc
->slot_index_to_bind_directly
= -1;
134 static void si_release_descriptors(struct si_descriptors
*desc
)
136 si_resource_reference(&desc
->buffer
, NULL
);
140 static bool si_upload_descriptors(struct si_context
*sctx
,
141 struct si_descriptors
*desc
)
143 unsigned slot_size
= desc
->element_dw_size
* 4;
144 unsigned first_slot_offset
= desc
->first_active_slot
* slot_size
;
145 unsigned upload_size
= desc
->num_active_slots
* slot_size
;
147 /* Skip the upload if no shader is using the descriptors. dirty_mask
148 * will stay dirty and the descriptors will be uploaded when there is
149 * a shader using them.
154 /* If there is just one active descriptor, bind it directly. */
155 if ((int)desc
->first_active_slot
== desc
->slot_index_to_bind_directly
&&
156 desc
->num_active_slots
== 1) {
157 uint32_t *descriptor
= &desc
->list
[desc
->slot_index_to_bind_directly
*
158 desc
->element_dw_size
];
160 /* The buffer is already in the buffer list. */
161 si_resource_reference(&desc
->buffer
, NULL
);
162 desc
->gpu_list
= NULL
;
163 desc
->gpu_address
= si_desc_extract_buffer_address(descriptor
);
164 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
169 unsigned buffer_offset
;
170 u_upload_alloc(sctx
->b
.const_uploader
, first_slot_offset
, upload_size
,
171 si_optimal_tcc_alignment(sctx
, upload_size
),
172 &buffer_offset
, (struct pipe_resource
**)&desc
->buffer
,
175 desc
->gpu_address
= 0;
176 return false; /* skip the draw call */
179 util_memcpy_cpu_to_le32(ptr
, (char*)desc
->list
+ first_slot_offset
,
181 desc
->gpu_list
= ptr
- first_slot_offset
/ 4;
183 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, desc
->buffer
,
184 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
186 /* The shader pointer should point to slot 0. */
187 buffer_offset
-= first_slot_offset
;
188 desc
->gpu_address
= desc
->buffer
->gpu_address
+ buffer_offset
;
190 assert(desc
->buffer
->flags
& RADEON_FLAG_32BIT
);
191 assert((desc
->buffer
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
192 assert((desc
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
194 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
199 si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
204 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, desc
->buffer
,
205 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
210 static inline enum radeon_bo_priority
211 si_get_sampler_view_priority(struct si_resource
*res
)
213 if (res
->b
.b
.target
== PIPE_BUFFER
)
214 return RADEON_PRIO_SAMPLER_BUFFER
;
216 if (res
->b
.b
.nr_samples
> 1)
217 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
219 return RADEON_PRIO_SAMPLER_TEXTURE
;
222 static struct si_descriptors
*
223 si_sampler_and_image_descriptors(struct si_context
*sctx
, unsigned shader
)
225 return &sctx
->descriptors
[si_sampler_and_image_descriptors_idx(shader
)];
228 static void si_release_sampler_views(struct si_samplers
*samplers
)
232 for (i
= 0; i
< ARRAY_SIZE(samplers
->views
); i
++) {
233 pipe_sampler_view_reference(&samplers
->views
[i
], NULL
);
237 static void si_sampler_view_add_buffer(struct si_context
*sctx
,
238 struct pipe_resource
*resource
,
239 enum radeon_bo_usage usage
,
240 bool is_stencil_sampler
,
243 struct si_texture
*tex
= (struct si_texture
*)resource
;
244 enum radeon_bo_priority priority
;
249 /* Use the flushed depth texture if direct sampling is unsupported. */
250 if (resource
->target
!= PIPE_BUFFER
&&
251 tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil_sampler
))
252 tex
= tex
->flushed_depth_texture
;
254 priority
= si_get_sampler_view_priority(&tex
->buffer
);
255 radeon_add_to_gfx_buffer_list_check_mem(sctx
, &tex
->buffer
, usage
, priority
,
258 if (resource
->target
== PIPE_BUFFER
)
261 /* Add separate DCC. */
262 if (tex
->dcc_separate_buffer
) {
263 radeon_add_to_gfx_buffer_list_check_mem(sctx
, tex
->dcc_separate_buffer
,
264 usage
, RADEON_PRIO_SEPARATE_META
, check_mem
);
268 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
,
269 struct si_samplers
*samplers
)
271 unsigned mask
= samplers
->enabled_mask
;
273 /* Add buffers to the CS. */
275 int i
= u_bit_scan(&mask
);
276 struct si_sampler_view
*sview
= (struct si_sampler_view
*)samplers
->views
[i
];
278 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
280 sview
->is_stencil_sampler
, false);
284 /* Set buffer descriptor fields that can be changed by reallocations. */
285 static void si_set_buf_desc_address(struct si_resource
*buf
,
286 uint64_t offset
, uint32_t *state
)
288 uint64_t va
= buf
->gpu_address
+ offset
;
291 state
[1] &= C_008F04_BASE_ADDRESS_HI
;
292 state
[1] |= S_008F04_BASE_ADDRESS_HI(va
>> 32);
295 /* Set texture descriptor fields that can be changed by reallocations.
298 * \param base_level_info information of the level of BASE_ADDRESS
299 * \param base_level the level of BASE_ADDRESS
300 * \param first_level pipe_sampler_view.u.tex.first_level
301 * \param block_width util_format_get_blockwidth()
302 * \param is_stencil select between separate Z & Stencil
303 * \param state descriptor to update
305 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
306 struct si_texture
*tex
,
307 const struct legacy_surf_level
*base_level_info
,
308 unsigned base_level
, unsigned first_level
,
309 unsigned block_width
, bool is_stencil
,
312 uint64_t va
, meta_va
= 0;
314 if (tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil
)) {
315 tex
= tex
->flushed_depth_texture
;
319 va
= tex
->buffer
.gpu_address
;
321 if (sscreen
->info
.chip_class
>= GFX9
) {
322 /* Only stencil_offset needs to be added here. */
324 va
+= tex
->surface
.u
.gfx9
.stencil_offset
;
326 va
+= tex
->surface
.u
.gfx9
.surf_offset
;
328 va
+= base_level_info
->offset
;
332 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
333 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
335 /* Only macrotiled modes can set tile swizzle.
336 * GFX9 doesn't use (legacy) base_level_info.
338 if (sscreen
->info
.chip_class
>= GFX9
||
339 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
340 state
[0] |= tex
->surface
.tile_swizzle
;
342 if (sscreen
->info
.chip_class
>= GFX8
) {
343 state
[6] &= C_008F28_COMPRESSION_EN
;
346 if (vi_dcc_enabled(tex
, first_level
)) {
347 meta_va
= (!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) +
350 if (sscreen
->info
.chip_class
== GFX8
) {
351 meta_va
+= base_level_info
->dcc_offset
;
352 assert(base_level_info
->mode
== RADEON_SURF_MODE_2D
);
355 meta_va
|= (uint32_t)tex
->surface
.tile_swizzle
<< 8;
356 } else if (vi_tc_compat_htile_enabled(tex
, first_level
)) {
357 meta_va
= tex
->buffer
.gpu_address
+ tex
->htile_offset
;
361 state
[6] |= S_008F28_COMPRESSION_EN(1);
362 state
[7] = meta_va
>> 8;
366 if (sscreen
->info
.chip_class
>= GFX9
) {
367 state
[3] &= C_008F1C_SW_MODE
;
368 state
[4] &= C_008F20_PITCH
;
371 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
372 state
[4] |= S_008F20_PITCH(tex
->surface
.u
.gfx9
.stencil
.epitch
);
374 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
375 state
[4] |= S_008F20_PITCH(tex
->surface
.u
.gfx9
.surf
.epitch
);
378 state
[5] &= C_008F24_META_DATA_ADDRESS
&
379 C_008F24_META_PIPE_ALIGNED
&
380 C_008F24_META_RB_ALIGNED
;
382 struct gfx9_surf_meta_flags meta
;
385 meta
= tex
->surface
.u
.gfx9
.dcc
;
387 meta
= tex
->surface
.u
.gfx9
.htile
;
389 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
390 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
391 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
395 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
396 unsigned index
= si_tile_mode_index(tex
, base_level
, is_stencil
);
398 state
[3] &= C_008F1C_TILING_INDEX
;
399 state
[3] |= S_008F1C_TILING_INDEX(index
);
400 state
[4] &= C_008F20_PITCH
;
401 state
[4] |= S_008F20_PITCH(pitch
- 1);
405 static void si_set_sampler_state_desc(struct si_sampler_state
*sstate
,
406 struct si_sampler_view
*sview
,
407 struct si_texture
*tex
,
410 if (sview
&& sview
->is_integer
)
411 memcpy(desc
, sstate
->integer_val
, 4*4);
412 else if (tex
&& tex
->upgraded_depth
&&
413 (!sview
|| !sview
->is_stencil_sampler
))
414 memcpy(desc
, sstate
->upgraded_depth_val
, 4*4);
416 memcpy(desc
, sstate
->val
, 4*4);
419 static void si_set_sampler_view_desc(struct si_context
*sctx
,
420 struct si_sampler_view
*sview
,
421 struct si_sampler_state
*sstate
,
424 struct pipe_sampler_view
*view
= &sview
->base
;
425 struct si_texture
*tex
= (struct si_texture
*)view
->texture
;
426 bool is_buffer
= tex
->buffer
.b
.b
.target
== PIPE_BUFFER
;
428 if (unlikely(!is_buffer
&& sview
->dcc_incompatible
)) {
429 if (vi_dcc_enabled(tex
, view
->u
.tex
.first_level
))
430 if (!si_texture_disable_dcc(sctx
, tex
))
431 si_decompress_dcc(sctx
, tex
);
433 sview
->dcc_incompatible
= false;
436 assert(tex
); /* views with texture == NULL aren't supported */
437 memcpy(desc
, sview
->state
, 8*4);
440 si_set_buf_desc_address(&tex
->buffer
,
441 sview
->base
.u
.buf
.offset
,
444 bool is_separate_stencil
= tex
->db_compatible
&&
445 sview
->is_stencil_sampler
;
447 si_set_mutable_tex_desc_fields(sctx
->screen
, tex
,
448 sview
->base_level_info
,
450 sview
->base
.u
.tex
.first_level
,
456 if (!is_buffer
&& tex
->surface
.fmask_size
) {
457 memcpy(desc
+ 8, sview
->fmask_state
, 8*4);
459 /* Disable FMASK and bind sampler state in [12:15]. */
460 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
463 si_set_sampler_state_desc(sstate
, sview
,
464 is_buffer
? NULL
: tex
,
469 static bool color_needs_decompression(struct si_texture
*tex
)
471 return tex
->surface
.fmask_size
||
472 (tex
->dirty_level_mask
&&
473 (tex
->cmask_buffer
|| tex
->dcc_offset
));
476 static bool depth_needs_decompression(struct si_texture
*tex
)
478 /* If the depth/stencil texture is TC-compatible, no decompression
479 * will be done. The decompression function will only flush DB caches
480 * to make it coherent with shaders. That's necessary because the driver
481 * doesn't flush DB caches in any other case.
483 return tex
->db_compatible
;
486 static void si_set_sampler_view(struct si_context
*sctx
,
488 unsigned slot
, struct pipe_sampler_view
*view
,
489 bool disallow_early_out
)
491 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
492 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
493 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
494 unsigned desc_slot
= si_get_sampler_slot(slot
);
495 uint32_t *desc
= descs
->list
+ desc_slot
* 16;
497 if (samplers
->views
[slot
] == view
&& !disallow_early_out
)
501 struct si_texture
*tex
= (struct si_texture
*)view
->texture
;
503 si_set_sampler_view_desc(sctx
, sview
,
504 samplers
->sampler_states
[slot
], desc
);
506 if (tex
->buffer
.b
.b
.target
== PIPE_BUFFER
) {
507 tex
->buffer
.bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
508 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
509 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
511 if (depth_needs_decompression(tex
)) {
512 samplers
->needs_depth_decompress_mask
|= 1u << slot
;
514 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
516 if (color_needs_decompression(tex
)) {
517 samplers
->needs_color_decompress_mask
|= 1u << slot
;
519 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
522 if (tex
->dcc_offset
&&
523 p_atomic_read(&tex
->framebuffers_bound
))
524 sctx
->need_check_render_feedback
= true;
527 pipe_sampler_view_reference(&samplers
->views
[slot
], view
);
528 samplers
->enabled_mask
|= 1u << slot
;
530 /* Since this can flush, it must be done after enabled_mask is
532 si_sampler_view_add_buffer(sctx
, view
->texture
,
534 sview
->is_stencil_sampler
, true);
536 pipe_sampler_view_reference(&samplers
->views
[slot
], NULL
);
537 memcpy(desc
, null_texture_descriptor
, 8*4);
538 /* Only clear the lower dwords of FMASK. */
539 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
540 /* Re-set the sampler state if we are transitioning from FMASK. */
541 if (samplers
->sampler_states
[slot
])
542 si_set_sampler_state_desc(samplers
->sampler_states
[slot
], NULL
, NULL
,
545 samplers
->enabled_mask
&= ~(1u << slot
);
546 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
547 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
550 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
553 static void si_update_shader_needs_decompress_mask(struct si_context
*sctx
,
556 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
557 unsigned shader_bit
= 1 << shader
;
559 if (samplers
->needs_depth_decompress_mask
||
560 samplers
->needs_color_decompress_mask
||
561 sctx
->images
[shader
].needs_color_decompress_mask
)
562 sctx
->shader_needs_decompress_mask
|= shader_bit
;
564 sctx
->shader_needs_decompress_mask
&= ~shader_bit
;
567 static void si_set_sampler_views(struct pipe_context
*ctx
,
568 enum pipe_shader_type shader
, unsigned start
,
570 struct pipe_sampler_view
**views
)
572 struct si_context
*sctx
= (struct si_context
*)ctx
;
575 if (!count
|| shader
>= SI_NUM_SHADERS
)
579 for (i
= 0; i
< count
; i
++)
580 si_set_sampler_view(sctx
, shader
, start
+ i
, views
[i
], false);
582 for (i
= 0; i
< count
; i
++)
583 si_set_sampler_view(sctx
, shader
, start
+ i
, NULL
, false);
586 si_update_shader_needs_decompress_mask(sctx
, shader
);
590 si_samplers_update_needs_color_decompress_mask(struct si_samplers
*samplers
)
592 unsigned mask
= samplers
->enabled_mask
;
595 int i
= u_bit_scan(&mask
);
596 struct pipe_resource
*res
= samplers
->views
[i
]->texture
;
598 if (res
&& res
->target
!= PIPE_BUFFER
) {
599 struct si_texture
*tex
= (struct si_texture
*)res
;
601 if (color_needs_decompression(tex
)) {
602 samplers
->needs_color_decompress_mask
|= 1u << i
;
604 samplers
->needs_color_decompress_mask
&= ~(1u << i
);
613 si_release_image_views(struct si_images
*images
)
617 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
618 struct pipe_image_view
*view
= &images
->views
[i
];
620 pipe_resource_reference(&view
->resource
, NULL
);
625 si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images
*images
)
627 uint mask
= images
->enabled_mask
;
629 /* Add buffers to the CS. */
631 int i
= u_bit_scan(&mask
);
632 struct pipe_image_view
*view
= &images
->views
[i
];
634 assert(view
->resource
);
636 si_sampler_view_add_buffer(sctx
, view
->resource
,
637 RADEON_USAGE_READWRITE
, false, false);
642 si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
644 struct si_images
*images
= &ctx
->images
[shader
];
646 if (images
->enabled_mask
& (1u << slot
)) {
647 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
648 unsigned desc_slot
= si_get_image_slot(slot
);
650 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
651 images
->needs_color_decompress_mask
&= ~(1 << slot
);
653 memcpy(descs
->list
+ desc_slot
*8, null_image_descriptor
, 8*4);
654 images
->enabled_mask
&= ~(1u << slot
);
655 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
660 si_mark_image_range_valid(const struct pipe_image_view
*view
)
662 struct si_resource
*res
= si_resource(view
->resource
);
664 if (res
->b
.b
.target
!= PIPE_BUFFER
)
667 util_range_add(&res
->valid_buffer_range
,
669 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
672 static void si_set_shader_image_desc(struct si_context
*ctx
,
673 const struct pipe_image_view
*view
,
674 bool skip_decompress
,
675 uint32_t *desc
, uint32_t *fmask_desc
)
677 struct si_screen
*screen
= ctx
->screen
;
678 struct si_resource
*res
;
680 res
= si_resource(view
->resource
);
682 if (res
->b
.b
.target
== PIPE_BUFFER
||
683 view
->shader_access
& SI_IMAGE_ACCESS_AS_BUFFER
) {
684 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
685 si_mark_image_range_valid(view
);
687 si_make_buffer_descriptor(screen
, res
,
690 view
->u
.buf
.size
, desc
);
691 si_set_buf_desc_address(res
, view
->u
.buf
.offset
, desc
+ 4);
693 static const unsigned char swizzle
[4] = { 0, 1, 2, 3 };
694 struct si_texture
*tex
= (struct si_texture
*)res
;
695 unsigned level
= view
->u
.tex
.level
;
696 unsigned width
, height
, depth
, hw_level
;
697 bool uses_dcc
= vi_dcc_enabled(tex
, level
);
698 unsigned access
= view
->access
;
700 /* Clear the write flag when writes can't occur.
701 * Note that DCC_DECOMPRESS for MSAA doesn't work in some cases,
702 * so we don't wanna trigger it.
705 (!fmask_desc
&& tex
->surface
.fmask_size
!= 0)) {
706 assert(!"Z/S and MSAA image stores are not supported");
707 access
&= ~PIPE_IMAGE_ACCESS_WRITE
;
710 assert(!tex
->is_depth
);
711 assert(fmask_desc
|| tex
->surface
.fmask_size
== 0);
713 if (uses_dcc
&& !skip_decompress
&&
714 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
||
715 !vi_dcc_formats_compatible(res
->b
.b
.format
, view
->format
))) {
716 /* If DCC can't be disabled, at least decompress it.
717 * The decompression is relatively cheap if the surface
718 * has been decompressed already.
720 if (!si_texture_disable_dcc(ctx
, tex
))
721 si_decompress_dcc(ctx
, tex
);
724 if (ctx
->chip_class
>= GFX9
) {
725 /* Always set the base address. The swizzle modes don't
726 * allow setting mipmap level offsets as the base.
728 width
= res
->b
.b
.width0
;
729 height
= res
->b
.b
.height0
;
730 depth
= res
->b
.b
.depth0
;
733 /* Always force the base level to the selected level.
735 * This is required for 3D textures, where otherwise
736 * selecting a single slice for non-layered bindings
737 * fails. It doesn't hurt the other targets.
739 width
= u_minify(res
->b
.b
.width0
, level
);
740 height
= u_minify(res
->b
.b
.height0
, level
);
741 depth
= u_minify(res
->b
.b
.depth0
, level
);
745 si_make_texture_descriptor(screen
, tex
,
746 false, res
->b
.b
.target
,
747 view
->format
, swizzle
,
749 view
->u
.tex
.first_layer
,
750 view
->u
.tex
.last_layer
,
751 width
, height
, depth
,
753 si_set_mutable_tex_desc_fields(screen
, tex
,
754 &tex
->surface
.u
.legacy
.level
[level
],
756 util_format_get_blockwidth(view
->format
),
761 static void si_set_shader_image(struct si_context
*ctx
,
763 unsigned slot
, const struct pipe_image_view
*view
,
764 bool skip_decompress
)
766 struct si_images
*images
= &ctx
->images
[shader
];
767 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
768 struct si_resource
*res
;
769 unsigned desc_slot
= si_get_image_slot(slot
);
770 uint32_t *desc
= descs
->list
+ desc_slot
* 8;
772 if (!view
|| !view
->resource
) {
773 si_disable_shader_image(ctx
, shader
, slot
);
777 res
= si_resource(view
->resource
);
779 if (&images
->views
[slot
] != view
)
780 util_copy_image_view(&images
->views
[slot
], view
);
782 si_set_shader_image_desc(ctx
, view
, skip_decompress
, desc
, NULL
);
784 if (res
->b
.b
.target
== PIPE_BUFFER
||
785 view
->shader_access
& SI_IMAGE_ACCESS_AS_BUFFER
) {
786 images
->needs_color_decompress_mask
&= ~(1 << slot
);
787 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
789 struct si_texture
*tex
= (struct si_texture
*)res
;
790 unsigned level
= view
->u
.tex
.level
;
792 if (color_needs_decompression(tex
)) {
793 images
->needs_color_decompress_mask
|= 1 << slot
;
795 images
->needs_color_decompress_mask
&= ~(1 << slot
);
798 if (vi_dcc_enabled(tex
, level
) &&
799 p_atomic_read(&tex
->framebuffers_bound
))
800 ctx
->need_check_render_feedback
= true;
803 images
->enabled_mask
|= 1u << slot
;
804 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
806 /* Since this can flush, it must be done after enabled_mask is updated. */
807 si_sampler_view_add_buffer(ctx
, &res
->b
.b
,
808 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
) ?
809 RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
,
814 si_set_shader_images(struct pipe_context
*pipe
,
815 enum pipe_shader_type shader
,
816 unsigned start_slot
, unsigned count
,
817 const struct pipe_image_view
*views
)
819 struct si_context
*ctx
= (struct si_context
*)pipe
;
822 assert(shader
< SI_NUM_SHADERS
);
827 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
830 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
831 si_set_shader_image(ctx
, shader
, slot
, &views
[i
], false);
833 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
834 si_set_shader_image(ctx
, shader
, slot
, NULL
, false);
837 si_update_shader_needs_decompress_mask(ctx
, shader
);
841 si_images_update_needs_color_decompress_mask(struct si_images
*images
)
843 unsigned mask
= images
->enabled_mask
;
846 int i
= u_bit_scan(&mask
);
847 struct pipe_resource
*res
= images
->views
[i
].resource
;
849 if (res
&& res
->target
!= PIPE_BUFFER
) {
850 struct si_texture
*tex
= (struct si_texture
*)res
;
852 if (color_needs_decompression(tex
)) {
853 images
->needs_color_decompress_mask
|= 1 << i
;
855 images
->needs_color_decompress_mask
&= ~(1 << i
);
861 void si_update_ps_colorbuf0_slot(struct si_context
*sctx
)
863 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
864 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
865 unsigned slot
= SI_PS_IMAGE_COLORBUF0
;
866 struct pipe_surface
*surf
= NULL
;
868 /* si_texture_disable_dcc can get us here again. */
869 if (sctx
->blitter
->running
)
872 /* See whether FBFETCH is used and color buffer 0 is set. */
873 if (sctx
->ps_shader
.cso
&&
874 sctx
->ps_shader
.cso
->info
.opcode_count
[TGSI_OPCODE_FBFETCH
] &&
875 sctx
->framebuffer
.state
.nr_cbufs
&&
876 sctx
->framebuffer
.state
.cbufs
[0])
877 surf
= sctx
->framebuffer
.state
.cbufs
[0];
879 /* Return if FBFETCH transitions from disabled to disabled. */
880 if (!buffers
->buffers
[slot
] && !surf
)
883 sctx
->ps_uses_fbfetch
= surf
!= NULL
;
884 si_update_ps_iter_samples(sctx
);
887 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
888 struct pipe_image_view view
;
891 assert(!tex
->is_depth
);
893 /* Disable DCC, because the texture is used as both a sampler
896 si_texture_disable_dcc(sctx
, tex
);
898 if (tex
->buffer
.b
.b
.nr_samples
<= 1 && tex
->cmask_buffer
) {
900 assert(tex
->cmask_buffer
!= &tex
->buffer
);
901 si_eliminate_fast_color_clear(sctx
, tex
);
902 si_texture_discard_cmask(sctx
->screen
, tex
);
905 view
.resource
= surf
->texture
;
906 view
.format
= surf
->format
;
907 view
.access
= PIPE_IMAGE_ACCESS_READ
;
908 view
.u
.tex
.first_layer
= surf
->u
.tex
.first_layer
;
909 view
.u
.tex
.last_layer
= surf
->u
.tex
.last_layer
;
910 view
.u
.tex
.level
= surf
->u
.tex
.level
;
912 /* Set the descriptor. */
913 uint32_t *desc
= descs
->list
+ slot
*4;
914 memset(desc
, 0, 16 * 4);
915 si_set_shader_image_desc(sctx
, &view
, true, desc
, desc
+ 8);
917 pipe_resource_reference(&buffers
->buffers
[slot
], &tex
->buffer
.b
.b
);
918 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
919 &tex
->buffer
, RADEON_USAGE_READ
,
920 RADEON_PRIO_SHADER_RW_IMAGE
);
921 buffers
->enabled_mask
|= 1u << slot
;
923 /* Clear the descriptor. */
924 memset(descs
->list
+ slot
*4, 0, 8*4);
925 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
926 buffers
->enabled_mask
&= ~(1u << slot
);
929 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
934 static void si_bind_sampler_states(struct pipe_context
*ctx
,
935 enum pipe_shader_type shader
,
936 unsigned start
, unsigned count
, void **states
)
938 struct si_context
*sctx
= (struct si_context
*)ctx
;
939 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
940 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, shader
);
941 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
944 if (!count
|| shader
>= SI_NUM_SHADERS
|| !sstates
)
947 for (i
= 0; i
< count
; i
++) {
948 unsigned slot
= start
+ i
;
949 unsigned desc_slot
= si_get_sampler_slot(slot
);
952 sstates
[i
] == samplers
->sampler_states
[slot
])
956 assert(sstates
[i
]->magic
== SI_SAMPLER_STATE_MAGIC
);
958 samplers
->sampler_states
[slot
] = sstates
[i
];
960 /* If FMASK is bound, don't overwrite it.
961 * The sampler state will be set after FMASK is unbound.
963 struct si_sampler_view
*sview
=
964 (struct si_sampler_view
*)samplers
->views
[slot
];
966 struct si_texture
*tex
= NULL
;
968 if (sview
&& sview
->base
.texture
&&
969 sview
->base
.texture
->target
!= PIPE_BUFFER
)
970 tex
= (struct si_texture
*)sview
->base
.texture
;
972 if (tex
&& tex
->surface
.fmask_size
)
975 si_set_sampler_state_desc(sstates
[i
], sview
, tex
,
976 desc
->list
+ desc_slot
* 16 + 12);
978 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
982 /* BUFFER RESOURCES */
984 static void si_init_buffer_resources(struct si_buffer_resources
*buffers
,
985 struct si_descriptors
*descs
,
986 unsigned num_buffers
,
987 short shader_userdata_rel_index
,
988 enum radeon_bo_priority priority
,
989 enum radeon_bo_priority priority_constbuf
)
991 buffers
->priority
= priority
;
992 buffers
->priority_constbuf
= priority_constbuf
;
993 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
994 buffers
->offsets
= CALLOC(num_buffers
, sizeof(buffers
->offsets
[0]));
996 si_init_descriptors(descs
, shader_userdata_rel_index
, 4, num_buffers
);
999 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
1000 struct si_descriptors
*descs
)
1004 for (i
= 0; i
< descs
->num_elements
; i
++) {
1005 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
1008 FREE(buffers
->buffers
);
1009 FREE(buffers
->offsets
);
1012 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
1013 struct si_buffer_resources
*buffers
)
1015 unsigned mask
= buffers
->enabled_mask
;
1017 /* Add buffers to the CS. */
1019 int i
= u_bit_scan(&mask
);
1021 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1022 si_resource(buffers
->buffers
[i
]),
1023 buffers
->writable_mask
& (1u << i
) ? RADEON_USAGE_READWRITE
:
1025 i
< SI_NUM_SHADER_BUFFERS
? buffers
->priority
:
1026 buffers
->priority_constbuf
);
1030 static void si_get_buffer_from_descriptors(struct si_buffer_resources
*buffers
,
1031 struct si_descriptors
*descs
,
1032 unsigned idx
, struct pipe_resource
**buf
,
1033 unsigned *offset
, unsigned *size
)
1035 pipe_resource_reference(buf
, buffers
->buffers
[idx
]);
1037 struct si_resource
*res
= si_resource(*buf
);
1038 const uint32_t *desc
= descs
->list
+ idx
* 4;
1043 assert(G_008F04_STRIDE(desc
[1]) == 0);
1044 va
= si_desc_extract_buffer_address(desc
);
1046 assert(va
>= res
->gpu_address
&& va
+ *size
<= res
->gpu_address
+ res
->bo_size
);
1047 *offset
= va
- res
->gpu_address
;
1051 /* VERTEX BUFFERS */
1053 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
1055 int count
= sctx
->vertex_elements
? sctx
->vertex_elements
->count
: 0;
1058 for (i
= 0; i
< count
; i
++) {
1059 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1061 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1063 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1066 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1067 si_resource(sctx
->vertex_buffer
[vb
].buffer
.resource
),
1068 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1071 if (!sctx
->vb_descriptors_buffer
)
1073 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1074 sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1075 RADEON_PRIO_DESCRIPTORS
);
1078 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
1080 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
1082 unsigned desc_list_byte_size
;
1083 unsigned first_vb_use_mask
;
1086 if (!sctx
->vertex_buffers_dirty
|| !velems
)
1089 count
= velems
->count
;
1094 desc_list_byte_size
= velems
->desc_list_byte_size
;
1095 first_vb_use_mask
= velems
->first_vb_use_mask
;
1097 /* Vertex buffer descriptors are the only ones which are uploaded
1098 * directly through a staging buffer and don't go through
1099 * the fine-grained upload path.
1101 u_upload_alloc(sctx
->b
.const_uploader
, 0,
1102 desc_list_byte_size
,
1103 si_optimal_tcc_alignment(sctx
, desc_list_byte_size
),
1104 &sctx
->vb_descriptors_offset
,
1105 (struct pipe_resource
**)&sctx
->vb_descriptors_buffer
,
1107 if (!sctx
->vb_descriptors_buffer
) {
1108 sctx
->vb_descriptors_offset
= 0;
1109 sctx
->vb_descriptors_gpu_list
= NULL
;
1113 sctx
->vb_descriptors_gpu_list
= ptr
;
1114 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1115 sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1116 RADEON_PRIO_DESCRIPTORS
);
1118 assert(count
<= SI_MAX_ATTRIBS
);
1120 for (i
= 0; i
< count
; i
++) {
1121 struct pipe_vertex_buffer
*vb
;
1122 struct si_resource
*buf
;
1123 unsigned vbo_index
= velems
->vertex_buffer_index
[i
];
1124 uint32_t *desc
= &ptr
[i
*4];
1126 vb
= &sctx
->vertex_buffer
[vbo_index
];
1127 buf
= si_resource(vb
->buffer
.resource
);
1129 memset(desc
, 0, 16);
1133 int64_t offset
= (int64_t)((int)vb
->buffer_offset
) +
1134 velems
->src_offset
[i
];
1135 uint64_t va
= buf
->gpu_address
+ offset
;
1137 int64_t num_records
= (int64_t)buf
->b
.b
.width0
- offset
;
1138 if (sctx
->chip_class
!= GFX8
&& vb
->stride
) {
1139 /* Round up by rounding down and adding 1 */
1140 num_records
= (num_records
- velems
->format_size
[i
]) /
1143 assert(num_records
>= 0 && num_records
<= UINT_MAX
);
1146 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1147 S_008F04_STRIDE(vb
->stride
);
1148 desc
[2] = num_records
;
1149 desc
[3] = velems
->rsrc_word3
[i
];
1151 if (first_vb_use_mask
& (1 << i
)) {
1152 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1153 si_resource(vb
->buffer
.resource
),
1154 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1158 /* Don't flush the const cache. It would have a very negative effect
1159 * on performance (confirmed by testing). New descriptors are always
1160 * uploaded to a fresh new buffer, so I don't think flushing the const
1161 * cache is needed. */
1162 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
1163 sctx
->vertex_buffers_dirty
= false;
1164 sctx
->vertex_buffer_pointer_dirty
= true;
1165 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VBO_DESCRIPTORS
;
1170 /* CONSTANT BUFFERS */
1172 static struct si_descriptors
*
1173 si_const_and_shader_buffer_descriptors(struct si_context
*sctx
, unsigned shader
)
1175 return &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(shader
)];
1178 void si_upload_const_buffer(struct si_context
*sctx
, struct si_resource
**buf
,
1179 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
)
1183 u_upload_alloc(sctx
->b
.const_uploader
, 0, size
,
1184 si_optimal_tcc_alignment(sctx
, size
),
1186 (struct pipe_resource
**)buf
, &tmp
);
1188 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
1191 static void si_set_constant_buffer(struct si_context
*sctx
,
1192 struct si_buffer_resources
*buffers
,
1193 unsigned descriptors_idx
,
1194 uint slot
, const struct pipe_constant_buffer
*input
)
1196 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1197 assert(slot
< descs
->num_elements
);
1198 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1200 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1201 * with a NULL buffer). We need to use a dummy buffer instead. */
1202 if (sctx
->chip_class
== GFX7
&&
1203 (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
1204 input
= &sctx
->null_const_buf
;
1206 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1207 struct pipe_resource
*buffer
= NULL
;
1209 unsigned buffer_offset
;
1211 /* Upload the user buffer if needed. */
1212 if (input
->user_buffer
) {
1213 si_upload_const_buffer(sctx
,
1214 (struct si_resource
**)&buffer
, input
->user_buffer
,
1215 input
->buffer_size
, &buffer_offset
);
1217 /* Just unbind on failure. */
1218 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1222 pipe_resource_reference(&buffer
, input
->buffer
);
1223 buffer_offset
= input
->buffer_offset
;
1226 va
= si_resource(buffer
)->gpu_address
+ buffer_offset
;
1228 /* Set the descriptor. */
1229 uint32_t *desc
= descs
->list
+ slot
*4;
1231 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1233 desc
[2] = input
->buffer_size
;
1234 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1235 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1236 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1237 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1238 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1239 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1241 buffers
->buffers
[slot
] = buffer
;
1242 buffers
->offsets
[slot
] = buffer_offset
;
1243 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1244 si_resource(buffer
),
1246 buffers
->priority_constbuf
, true);
1247 buffers
->enabled_mask
|= 1u << slot
;
1249 /* Clear the descriptor. */
1250 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1251 buffers
->enabled_mask
&= ~(1u << slot
);
1254 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1257 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
,
1258 enum pipe_shader_type shader
, uint slot
,
1259 const struct pipe_constant_buffer
*input
)
1261 struct si_context
*sctx
= (struct si_context
*)ctx
;
1263 if (shader
>= SI_NUM_SHADERS
)
1266 if (slot
== 0 && input
&& input
->buffer
&&
1267 !(si_resource(input
->buffer
)->flags
& RADEON_FLAG_32BIT
)) {
1268 assert(!"constant buffer 0 must have a 32-bit VM address, use const_uploader");
1272 if (input
&& input
->buffer
)
1273 si_resource(input
->buffer
)->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
1275 slot
= si_get_constbuf_slot(slot
);
1276 si_set_constant_buffer(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1277 si_const_and_shader_buffer_descriptors_idx(shader
),
1281 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
1282 uint slot
, struct pipe_constant_buffer
*cbuf
)
1284 cbuf
->user_buffer
= NULL
;
1285 si_get_buffer_from_descriptors(
1286 &sctx
->const_and_shader_buffers
[shader
],
1287 si_const_and_shader_buffer_descriptors(sctx
, shader
),
1288 si_get_constbuf_slot(slot
),
1289 &cbuf
->buffer
, &cbuf
->buffer_offset
, &cbuf
->buffer_size
);
1292 /* SHADER BUFFERS */
1294 static void si_set_shader_buffer(struct si_context
*sctx
,
1295 struct si_buffer_resources
*buffers
,
1296 unsigned descriptors_idx
,
1297 uint slot
, const struct pipe_shader_buffer
*sbuffer
,
1298 bool writable
, enum radeon_bo_priority priority
)
1300 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1301 uint32_t *desc
= descs
->list
+ slot
* 4;
1303 if (!sbuffer
|| !sbuffer
->buffer
) {
1304 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1305 memset(desc
, 0, sizeof(uint32_t) * 4);
1306 buffers
->enabled_mask
&= ~(1u << slot
);
1307 buffers
->writable_mask
&= ~(1u << slot
);
1308 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1312 struct si_resource
*buf
= si_resource(sbuffer
->buffer
);
1313 uint64_t va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1316 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1318 desc
[2] = sbuffer
->buffer_size
;
1319 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1320 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1321 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1322 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1323 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1324 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1326 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1327 buffers
->offsets
[slot
] = sbuffer
->buffer_offset
;
1328 radeon_add_to_gfx_buffer_list_check_mem(sctx
, buf
,
1329 writable
? RADEON_USAGE_READWRITE
:
1333 buffers
->writable_mask
|= 1u << slot
;
1335 buffers
->writable_mask
&= ~(1u << slot
);
1337 buffers
->enabled_mask
|= 1u << slot
;
1338 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1340 util_range_add(&buf
->valid_buffer_range
, sbuffer
->buffer_offset
,
1341 sbuffer
->buffer_offset
+ sbuffer
->buffer_size
);
1344 static void si_set_shader_buffers(struct pipe_context
*ctx
,
1345 enum pipe_shader_type shader
,
1346 unsigned start_slot
, unsigned count
,
1347 const struct pipe_shader_buffer
*sbuffers
,
1348 unsigned writable_bitmask
)
1350 struct si_context
*sctx
= (struct si_context
*)ctx
;
1351 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1352 unsigned descriptors_idx
= si_const_and_shader_buffer_descriptors_idx(shader
);
1355 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1357 for (i
= 0; i
< count
; ++i
) {
1358 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1359 unsigned slot
= si_get_shaderbuf_slot(start_slot
+ i
);
1361 if (sbuffer
&& sbuffer
->buffer
)
1362 si_resource(sbuffer
->buffer
)->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1364 si_set_shader_buffer(sctx
, buffers
, descriptors_idx
, slot
, sbuffer
,
1365 !!(writable_bitmask
& (1u << i
)),
1370 void si_get_shader_buffers(struct si_context
*sctx
,
1371 enum pipe_shader_type shader
,
1372 uint start_slot
, uint count
,
1373 struct pipe_shader_buffer
*sbuf
)
1375 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1376 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1378 for (unsigned i
= 0; i
< count
; ++i
) {
1379 si_get_buffer_from_descriptors(
1381 si_get_shaderbuf_slot(start_slot
+ i
),
1382 &sbuf
[i
].buffer
, &sbuf
[i
].buffer_offset
,
1383 &sbuf
[i
].buffer_size
);
1389 void si_set_rw_buffer(struct si_context
*sctx
,
1390 uint slot
, const struct pipe_constant_buffer
*input
)
1392 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
, SI_DESCS_RW_BUFFERS
,
1396 void si_set_rw_shader_buffer(struct si_context
*sctx
, uint slot
,
1397 const struct pipe_shader_buffer
*sbuffer
)
1399 si_set_shader_buffer(sctx
, &sctx
->rw_buffers
, SI_DESCS_RW_BUFFERS
,
1400 slot
, sbuffer
, true, RADEON_PRIO_SHADER_RW_BUFFER
);
1403 void si_set_ring_buffer(struct si_context
*sctx
, uint slot
,
1404 struct pipe_resource
*buffer
,
1405 unsigned stride
, unsigned num_records
,
1406 bool add_tid
, bool swizzle
,
1407 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1409 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1410 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1412 /* The stride field in the resource descriptor has 14 bits */
1413 assert(stride
< (1 << 14));
1415 assert(slot
< descs
->num_elements
);
1416 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1421 va
= si_resource(buffer
)->gpu_address
+ offset
;
1423 switch (element_size
) {
1425 assert(!"Unsupported ring buffer element size");
1441 switch (index_stride
) {
1443 assert(!"Unsupported ring buffer index stride");
1459 if (sctx
->chip_class
>= GFX8
&& stride
)
1460 num_records
*= stride
;
1462 /* Set the descriptor. */
1463 uint32_t *desc
= descs
->list
+ slot
*4;
1465 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1466 S_008F04_STRIDE(stride
) |
1467 S_008F04_SWIZZLE_ENABLE(swizzle
);
1468 desc
[2] = num_records
;
1469 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1470 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1471 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1472 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1473 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1474 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1475 S_008F0C_INDEX_STRIDE(index_stride
) |
1476 S_008F0C_ADD_TID_ENABLE(add_tid
);
1478 if (sctx
->chip_class
>= GFX9
)
1479 assert(!swizzle
|| element_size
== 1); /* always 4 bytes on GFX9 */
1481 desc
[3] |= S_008F0C_ELEMENT_SIZE(element_size
);
1483 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1484 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1485 si_resource(buffer
),
1486 RADEON_USAGE_READWRITE
, buffers
->priority
);
1487 buffers
->enabled_mask
|= 1u << slot
;
1489 /* Clear the descriptor. */
1490 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1491 buffers
->enabled_mask
&= ~(1u << slot
);
1494 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1497 /* INTERNAL CONST BUFFERS */
1499 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
1500 const struct pipe_poly_stipple
*state
)
1502 struct si_context
*sctx
= (struct si_context
*)ctx
;
1503 struct pipe_constant_buffer cb
= {};
1504 unsigned stipple
[32];
1507 for (i
= 0; i
< 32; i
++)
1508 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1510 cb
.user_buffer
= stipple
;
1511 cb
.buffer_size
= sizeof(stipple
);
1513 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1516 /* TEXTURE METADATA ENABLE/DISABLE */
1519 si_resident_handles_update_needs_color_decompress(struct si_context
*sctx
)
1521 util_dynarray_clear(&sctx
->resident_tex_needs_color_decompress
);
1522 util_dynarray_clear(&sctx
->resident_img_needs_color_decompress
);
1524 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1525 struct si_texture_handle
*, tex_handle
) {
1526 struct pipe_resource
*res
= (*tex_handle
)->view
->texture
;
1527 struct si_texture
*tex
;
1529 if (!res
|| res
->target
== PIPE_BUFFER
)
1532 tex
= (struct si_texture
*)res
;
1533 if (!color_needs_decompression(tex
))
1536 util_dynarray_append(&sctx
->resident_tex_needs_color_decompress
,
1537 struct si_texture_handle
*, *tex_handle
);
1540 util_dynarray_foreach(&sctx
->resident_img_handles
,
1541 struct si_image_handle
*, img_handle
) {
1542 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1543 struct pipe_resource
*res
= view
->resource
;
1544 struct si_texture
*tex
;
1546 if (!res
|| res
->target
== PIPE_BUFFER
)
1549 tex
= (struct si_texture
*)res
;
1550 if (!color_needs_decompression(tex
))
1553 util_dynarray_append(&sctx
->resident_img_needs_color_decompress
,
1554 struct si_image_handle
*, *img_handle
);
1558 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1559 * while the texture is bound, possibly by a different context. In that case,
1560 * call this function to update needs_*_decompress_masks.
1562 void si_update_needs_color_decompress_masks(struct si_context
*sctx
)
1564 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1565 si_samplers_update_needs_color_decompress_mask(&sctx
->samplers
[i
]);
1566 si_images_update_needs_color_decompress_mask(&sctx
->images
[i
]);
1567 si_update_shader_needs_decompress_mask(sctx
, i
);
1570 si_resident_handles_update_needs_color_decompress(sctx
);
1573 /* BUFFER DISCARD/INVALIDATION */
1575 /* Reset descriptors of buffer resources after \p buf has been invalidated.
1576 * If buf == NULL, reset all descriptors.
1578 static void si_reset_buffer_resources(struct si_context
*sctx
,
1579 struct si_buffer_resources
*buffers
,
1580 unsigned descriptors_idx
,
1582 struct pipe_resource
*buf
,
1583 enum radeon_bo_priority priority
)
1585 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1586 unsigned mask
= buffers
->enabled_mask
& slot_mask
;
1589 unsigned i
= u_bit_scan(&mask
);
1590 struct pipe_resource
*buffer
= buffers
->buffers
[i
];
1592 if (buffer
&& (!buf
|| buffer
== buf
)) {
1593 si_set_buf_desc_address(si_resource(buffer
), buffers
->offsets
[i
],
1595 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1597 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1598 si_resource(buffer
),
1599 buffers
->writable_mask
& (1u << i
) ?
1600 RADEON_USAGE_READWRITE
:
1607 /* Update all buffer bindings where the buffer is bound, including
1608 * all resource descriptors. This is invalidate_buffer without
1611 * If buf == NULL, update all buffer bindings.
1613 void si_rebind_buffer(struct si_context
*sctx
, struct pipe_resource
*buf
)
1615 struct si_resource
*buffer
= si_resource(buf
);
1617 unsigned num_elems
= sctx
->vertex_elements
?
1618 sctx
->vertex_elements
->count
: 0;
1620 /* We changed the buffer, now we need to bind it where the old one
1621 * was bound. This consists of 2 things:
1622 * 1) Updating the resource descriptor and dirtying it.
1623 * 2) Adding a relocation to the CS, so that it's usable.
1626 /* Vertex buffers. */
1629 sctx
->vertex_buffers_dirty
= true;
1630 } else if (buffer
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
1631 for (i
= 0; i
< num_elems
; i
++) {
1632 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1634 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1636 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1639 if (sctx
->vertex_buffer
[vb
].buffer
.resource
== buf
) {
1640 sctx
->vertex_buffers_dirty
= true;
1646 /* Streamout buffers. (other internal buffers can't be invalidated) */
1647 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
1648 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1649 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1650 struct si_descriptors
*descs
=
1651 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1652 struct pipe_resource
*buffer
= buffers
->buffers
[i
];
1654 if (!buffer
|| (buf
&& buffer
!= buf
))
1657 si_set_buf_desc_address(si_resource(buffer
), buffers
->offsets
[i
],
1659 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1661 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1662 si_resource(buffer
),
1664 RADEON_PRIO_SHADER_RW_BUFFER
,
1667 /* Update the streamout state. */
1668 if (sctx
->streamout
.begin_emitted
)
1669 si_emit_streamout_end(sctx
);
1670 sctx
->streamout
.append_bitmask
=
1671 sctx
->streamout
.enabled_mask
;
1672 si_streamout_buffers_dirty(sctx
);
1676 /* Constant and shader buffers. */
1677 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1678 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1679 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1680 si_const_and_shader_buffer_descriptors_idx(shader
),
1681 u_bit_consecutive(SI_NUM_SHADER_BUFFERS
, SI_NUM_CONST_BUFFERS
),
1683 sctx
->const_and_shader_buffers
[shader
].priority_constbuf
);
1686 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
1687 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1688 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1689 si_const_and_shader_buffer_descriptors_idx(shader
),
1690 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
),
1692 sctx
->const_and_shader_buffers
[shader
].priority
);
1695 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
1696 /* Texture buffers - update bindings. */
1697 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1698 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1699 struct si_descriptors
*descs
=
1700 si_sampler_and_image_descriptors(sctx
, shader
);
1701 unsigned mask
= samplers
->enabled_mask
;
1704 unsigned i
= u_bit_scan(&mask
);
1705 struct pipe_resource
*buffer
= samplers
->views
[i
]->texture
;
1707 if (buffer
&& buffer
->target
== PIPE_BUFFER
&&
1708 (!buf
|| buffer
== buf
)) {
1709 unsigned desc_slot
= si_get_sampler_slot(i
);
1711 si_set_buf_desc_address(si_resource(buffer
),
1712 samplers
->views
[i
]->u
.buf
.offset
,
1713 descs
->list
+ desc_slot
* 16 + 4);
1714 sctx
->descriptors_dirty
|=
1715 1u << si_sampler_and_image_descriptors_idx(shader
);
1717 radeon_add_to_gfx_buffer_list_check_mem(
1718 sctx
, si_resource(buffer
),
1720 RADEON_PRIO_SAMPLER_BUFFER
, true);
1727 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
1728 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1729 struct si_images
*images
= &sctx
->images
[shader
];
1730 struct si_descriptors
*descs
=
1731 si_sampler_and_image_descriptors(sctx
, shader
);
1732 unsigned mask
= images
->enabled_mask
;
1735 unsigned i
= u_bit_scan(&mask
);
1736 struct pipe_resource
*buffer
= images
->views
[i
].resource
;
1738 if (buffer
&& buffer
->target
== PIPE_BUFFER
&&
1739 (!buf
|| buffer
== buf
)) {
1740 unsigned desc_slot
= si_get_image_slot(i
);
1742 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1743 si_mark_image_range_valid(&images
->views
[i
]);
1745 si_set_buf_desc_address(si_resource(buffer
),
1746 images
->views
[i
].u
.buf
.offset
,
1747 descs
->list
+ desc_slot
* 8 + 4);
1748 sctx
->descriptors_dirty
|=
1749 1u << si_sampler_and_image_descriptors_idx(shader
);
1751 radeon_add_to_gfx_buffer_list_check_mem(
1752 sctx
, si_resource(buffer
),
1753 RADEON_USAGE_READWRITE
,
1754 RADEON_PRIO_SAMPLER_BUFFER
, true);
1760 /* Bindless texture handles */
1761 if (!buffer
|| buffer
->texture_handle_allocated
) {
1762 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1764 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1765 struct si_texture_handle
*, tex_handle
) {
1766 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
1767 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1768 struct pipe_resource
*buffer
= view
->texture
;
1770 if (buffer
&& buffer
->target
== PIPE_BUFFER
&&
1771 (!buf
|| buffer
== buf
)) {
1772 si_set_buf_desc_address(si_resource(buffer
),
1775 desc_slot
* 16 + 4);
1777 (*tex_handle
)->desc_dirty
= true;
1778 sctx
->bindless_descriptors_dirty
= true;
1780 radeon_add_to_gfx_buffer_list_check_mem(
1781 sctx
, si_resource(buffer
),
1783 RADEON_PRIO_SAMPLER_BUFFER
, true);
1788 /* Bindless image handles */
1789 if (!buffer
|| buffer
->image_handle_allocated
) {
1790 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1792 util_dynarray_foreach(&sctx
->resident_img_handles
,
1793 struct si_image_handle
*, img_handle
) {
1794 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1795 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1796 struct pipe_resource
*buffer
= view
->resource
;
1798 if (buffer
&& buffer
->target
== PIPE_BUFFER
&&
1799 (!buf
|| buffer
== buf
)) {
1800 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
1801 si_mark_image_range_valid(view
);
1803 si_set_buf_desc_address(si_resource(buffer
),
1806 desc_slot
* 16 + 4);
1808 (*img_handle
)->desc_dirty
= true;
1809 sctx
->bindless_descriptors_dirty
= true;
1811 radeon_add_to_gfx_buffer_list_check_mem(
1812 sctx
, si_resource(buffer
),
1813 RADEON_USAGE_READWRITE
,
1814 RADEON_PRIO_SAMPLER_BUFFER
, true);
1820 /* Do the same for other contexts. They will invoke this function
1821 * with buffer == NULL.
1823 unsigned new_counter
= p_atomic_inc_return(&sctx
->screen
->dirty_buf_counter
);
1825 /* Skip the update for the current context, because we have already updated
1826 * the buffer bindings.
1828 if (new_counter
== sctx
->last_dirty_buf_counter
+ 1)
1829 sctx
->last_dirty_buf_counter
= new_counter
;
1833 static void si_upload_bindless_descriptor(struct si_context
*sctx
,
1835 unsigned num_dwords
)
1837 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1838 unsigned desc_slot_offset
= desc_slot
* 16;
1842 data
= desc
->list
+ desc_slot_offset
;
1843 va
= desc
->gpu_address
+ desc_slot_offset
* 4;
1845 si_cp_write_data(sctx
, desc
->buffer
, va
- desc
->buffer
->gpu_address
,
1846 num_dwords
* 4, V_370_TC_L2
, V_370_ME
, data
);
1849 static void si_upload_bindless_descriptors(struct si_context
*sctx
)
1851 if (!sctx
->bindless_descriptors_dirty
)
1854 /* Wait for graphics/compute to be idle before updating the resident
1855 * descriptors directly in memory, in case the GPU is using them.
1857 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
1858 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1859 si_emit_cache_flush(sctx
);
1861 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1862 struct si_texture_handle
*, tex_handle
) {
1863 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1865 if (!(*tex_handle
)->desc_dirty
)
1868 si_upload_bindless_descriptor(sctx
, desc_slot
, 16);
1869 (*tex_handle
)->desc_dirty
= false;
1872 util_dynarray_foreach(&sctx
->resident_img_handles
,
1873 struct si_image_handle
*, img_handle
) {
1874 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1876 if (!(*img_handle
)->desc_dirty
)
1879 si_upload_bindless_descriptor(sctx
, desc_slot
, 8);
1880 (*img_handle
)->desc_dirty
= false;
1883 /* Invalidate L1 because it doesn't know that L2 changed. */
1884 sctx
->flags
|= SI_CONTEXT_INV_SMEM_L1
;
1885 si_emit_cache_flush(sctx
);
1887 sctx
->bindless_descriptors_dirty
= false;
1890 /* Update mutable image descriptor fields of all resident textures. */
1891 static void si_update_bindless_texture_descriptor(struct si_context
*sctx
,
1892 struct si_texture_handle
*tex_handle
)
1894 struct si_sampler_view
*sview
= (struct si_sampler_view
*)tex_handle
->view
;
1895 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1896 unsigned desc_slot_offset
= tex_handle
->desc_slot
* 16;
1897 uint32_t desc_list
[16];
1899 if (sview
->base
.texture
->target
== PIPE_BUFFER
)
1902 memcpy(desc_list
, desc
->list
+ desc_slot_offset
, sizeof(desc_list
));
1903 si_set_sampler_view_desc(sctx
, sview
, &tex_handle
->sstate
,
1904 desc
->list
+ desc_slot_offset
);
1906 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1907 sizeof(desc_list
))) {
1908 tex_handle
->desc_dirty
= true;
1909 sctx
->bindless_descriptors_dirty
= true;
1913 static void si_update_bindless_image_descriptor(struct si_context
*sctx
,
1914 struct si_image_handle
*img_handle
)
1916 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1917 unsigned desc_slot_offset
= img_handle
->desc_slot
* 16;
1918 struct pipe_image_view
*view
= &img_handle
->view
;
1919 uint32_t desc_list
[8];
1921 if (view
->resource
->target
== PIPE_BUFFER
)
1924 memcpy(desc_list
, desc
->list
+ desc_slot_offset
,
1926 si_set_shader_image_desc(sctx
, view
, true,
1927 desc
->list
+ desc_slot_offset
, NULL
);
1929 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1930 sizeof(desc_list
))) {
1931 img_handle
->desc_dirty
= true;
1932 sctx
->bindless_descriptors_dirty
= true;
1936 static void si_update_all_resident_texture_descriptors(struct si_context
*sctx
)
1938 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1939 struct si_texture_handle
*, tex_handle
) {
1940 si_update_bindless_texture_descriptor(sctx
, *tex_handle
);
1943 util_dynarray_foreach(&sctx
->resident_img_handles
,
1944 struct si_image_handle
*, img_handle
) {
1945 si_update_bindless_image_descriptor(sctx
, *img_handle
);
1948 si_upload_bindless_descriptors(sctx
);
1951 /* Update mutable image descriptor fields of all bound textures. */
1952 void si_update_all_texture_descriptors(struct si_context
*sctx
)
1956 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1957 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1958 struct si_images
*images
= &sctx
->images
[shader
];
1962 mask
= images
->enabled_mask
;
1964 unsigned i
= u_bit_scan(&mask
);
1965 struct pipe_image_view
*view
= &images
->views
[i
];
1967 if (!view
->resource
||
1968 view
->resource
->target
== PIPE_BUFFER
)
1971 si_set_shader_image(sctx
, shader
, i
, view
, true);
1974 /* Sampler views. */
1975 mask
= samplers
->enabled_mask
;
1977 unsigned i
= u_bit_scan(&mask
);
1978 struct pipe_sampler_view
*view
= samplers
->views
[i
];
1982 view
->texture
->target
== PIPE_BUFFER
)
1985 si_set_sampler_view(sctx
, shader
, i
,
1986 samplers
->views
[i
], true);
1989 si_update_shader_needs_decompress_mask(sctx
, shader
);
1992 si_update_all_resident_texture_descriptors(sctx
);
1993 si_update_ps_colorbuf0_slot(sctx
);
1996 /* SHADER USER DATA */
1998 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
,
2001 sctx
->shader_pointers_dirty
|=
2002 u_bit_consecutive(SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
,
2003 SI_NUM_SHADER_DESCS
);
2005 if (shader
== PIPE_SHADER_VERTEX
)
2006 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
2008 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
2011 static void si_shader_pointers_begin_new_cs(struct si_context
*sctx
)
2013 sctx
->shader_pointers_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2014 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
2015 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
2016 sctx
->graphics_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
2017 sctx
->compute_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
2020 /* Set a base register address for user data constants in the given shader.
2021 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
2023 static void si_set_user_data_base(struct si_context
*sctx
,
2024 unsigned shader
, uint32_t new_base
)
2026 uint32_t *base
= &sctx
->shader_pointers
.sh_base
[shader
];
2028 if (*base
!= new_base
) {
2032 si_mark_shader_pointers_dirty(sctx
, shader
);
2034 /* Any change in enabled shader stages requires re-emitting
2035 * the VS state SGPR, because it contains the clamp_vertex_color
2036 * state, which can be done in VS, TES, and GS.
2038 sctx
->last_vs_state
= ~0;
2042 /* This must be called when these shaders are changed from non-NULL to NULL
2045 * - tessellation control shader
2046 * - tessellation evaluation shader
2048 void si_shader_change_notify(struct si_context
*sctx
)
2050 /* VS can be bound as VS, ES, or LS. */
2051 if (sctx
->tes_shader
.cso
) {
2052 if (sctx
->chip_class
>= GFX9
) {
2053 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2054 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2056 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2057 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2059 } else if (sctx
->gs_shader
.cso
) {
2060 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2061 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2063 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2064 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2067 /* TES can be bound as ES, VS, or not bound. */
2068 if (sctx
->tes_shader
.cso
) {
2069 if (sctx
->gs_shader
.cso
)
2070 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2071 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2073 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2074 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2076 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
2080 static void si_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
2082 unsigned pointer_count
)
2084 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
, 0));
2085 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
2088 static void si_emit_shader_pointer_body(struct si_screen
*sscreen
,
2089 struct radeon_cmdbuf
*cs
,
2092 radeon_emit(cs
, va
);
2094 assert(va
== 0 || (va
>> 32) == sscreen
->info
.address32_hi
);
2097 static void si_emit_shader_pointer(struct si_context
*sctx
,
2098 struct si_descriptors
*desc
,
2101 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2102 unsigned sh_offset
= sh_base
+ desc
->shader_userdata_offset
;
2104 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2105 si_emit_shader_pointer_body(sctx
->screen
, cs
, desc
->gpu_address
);
2108 static void si_emit_consecutive_shader_pointers(struct si_context
*sctx
,
2109 unsigned pointer_mask
,
2115 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2116 unsigned mask
= sctx
->shader_pointers_dirty
& pointer_mask
;
2120 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
2122 struct si_descriptors
*descs
= &sctx
->descriptors
[start
];
2123 unsigned sh_offset
= sh_base
+ descs
->shader_userdata_offset
;
2125 si_emit_shader_pointer_head(cs
, sh_offset
, count
);
2126 for (int i
= 0; i
< count
; i
++)
2127 si_emit_shader_pointer_body(sctx
->screen
, cs
,
2128 descs
[i
].gpu_address
);
2132 static void si_emit_global_shader_pointers(struct si_context
*sctx
,
2133 struct si_descriptors
*descs
)
2135 if (sctx
->chip_class
== GFX9
) {
2136 /* Broadcast it to all shader stages. */
2137 si_emit_shader_pointer(sctx
, descs
,
2138 R_00B530_SPI_SHADER_USER_DATA_COMMON_0
);
2142 si_emit_shader_pointer(sctx
, descs
,
2143 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2144 si_emit_shader_pointer(sctx
, descs
,
2145 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2146 si_emit_shader_pointer(sctx
, descs
,
2147 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2148 si_emit_shader_pointer(sctx
, descs
,
2149 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2150 si_emit_shader_pointer(sctx
, descs
,
2151 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2152 si_emit_shader_pointer(sctx
, descs
,
2153 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2156 void si_emit_graphics_shader_pointers(struct si_context
*sctx
)
2158 uint32_t *sh_base
= sctx
->shader_pointers
.sh_base
;
2160 if (sctx
->shader_pointers_dirty
& (1 << SI_DESCS_RW_BUFFERS
)) {
2161 si_emit_global_shader_pointers(sctx
,
2162 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2165 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(VERTEX
),
2166 sh_base
[PIPE_SHADER_VERTEX
]);
2167 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_EVAL
),
2168 sh_base
[PIPE_SHADER_TESS_EVAL
]);
2169 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(FRAGMENT
),
2170 sh_base
[PIPE_SHADER_FRAGMENT
]);
2171 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_CTRL
),
2172 sh_base
[PIPE_SHADER_TESS_CTRL
]);
2173 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(GEOMETRY
),
2174 sh_base
[PIPE_SHADER_GEOMETRY
]);
2176 sctx
->shader_pointers_dirty
&=
2177 ~u_bit_consecutive(SI_DESCS_RW_BUFFERS
, SI_DESCS_FIRST_COMPUTE
);
2179 if (sctx
->vertex_buffer_pointer_dirty
) {
2180 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2182 /* Find the location of the VB descriptor pointer. */
2183 /* TODO: In the future, the pointer will be packed in unused
2184 * bits of the first 2 VB descriptors. */
2185 unsigned sh_dw_offset
= SI_VS_NUM_USER_SGPR
;
2186 if (sctx
->chip_class
>= GFX9
) {
2187 if (sctx
->tes_shader
.cso
)
2188 sh_dw_offset
= GFX9_TCS_NUM_USER_SGPR
;
2189 else if (sctx
->gs_shader
.cso
)
2190 sh_dw_offset
= GFX9_VSGS_NUM_USER_SGPR
;
2193 unsigned sh_offset
= sh_base
[PIPE_SHADER_VERTEX
] + sh_dw_offset
* 4;
2194 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2195 si_emit_shader_pointer_body(sctx
->screen
, cs
,
2196 sctx
->vb_descriptors_buffer
->gpu_address
+
2197 sctx
->vb_descriptors_offset
);
2198 sctx
->vertex_buffer_pointer_dirty
= false;
2201 if (sctx
->graphics_bindless_pointer_dirty
) {
2202 si_emit_global_shader_pointers(sctx
,
2203 &sctx
->bindless_descriptors
);
2204 sctx
->graphics_bindless_pointer_dirty
= false;
2208 void si_emit_compute_shader_pointers(struct si_context
*sctx
)
2210 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
2212 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(COMPUTE
),
2213 R_00B900_COMPUTE_USER_DATA_0
);
2214 sctx
->shader_pointers_dirty
&= ~SI_DESCS_SHADER_MASK(COMPUTE
);
2216 if (sctx
->compute_bindless_pointer_dirty
) {
2217 si_emit_shader_pointer(sctx
, &sctx
->bindless_descriptors
, base
);
2218 sctx
->compute_bindless_pointer_dirty
= false;
2224 static void si_init_bindless_descriptors(struct si_context
*sctx
,
2225 struct si_descriptors
*desc
,
2226 short shader_userdata_rel_index
,
2227 unsigned num_elements
)
2229 MAYBE_UNUSED
unsigned desc_slot
;
2231 si_init_descriptors(desc
, shader_userdata_rel_index
, 16, num_elements
);
2232 sctx
->bindless_descriptors
.num_active_slots
= num_elements
;
2234 /* The first bindless descriptor is stored at slot 1, because 0 is not
2235 * considered to be a valid handle.
2237 sctx
->num_bindless_descriptors
= 1;
2239 /* Track which bindless slots are used (or not). */
2240 util_idalloc_init(&sctx
->bindless_used_slots
);
2241 util_idalloc_resize(&sctx
->bindless_used_slots
, num_elements
);
2243 /* Reserve slot 0 because it's an invalid handle for bindless. */
2244 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2245 assert(desc_slot
== 0);
2248 static void si_release_bindless_descriptors(struct si_context
*sctx
)
2250 si_release_descriptors(&sctx
->bindless_descriptors
);
2251 util_idalloc_fini(&sctx
->bindless_used_slots
);
2254 static unsigned si_get_first_free_bindless_slot(struct si_context
*sctx
)
2256 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2259 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2260 if (desc_slot
>= desc
->num_elements
) {
2261 /* The array of bindless descriptors is full, resize it. */
2262 unsigned slot_size
= desc
->element_dw_size
* 4;
2263 unsigned new_num_elements
= desc
->num_elements
* 2;
2265 desc
->list
= REALLOC(desc
->list
, desc
->num_elements
* slot_size
,
2266 new_num_elements
* slot_size
);
2267 desc
->num_elements
= new_num_elements
;
2268 desc
->num_active_slots
= new_num_elements
;
2276 si_create_bindless_descriptor(struct si_context
*sctx
, uint32_t *desc_list
,
2279 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2280 unsigned desc_slot
, desc_slot_offset
;
2282 /* Find a free slot. */
2283 desc_slot
= si_get_first_free_bindless_slot(sctx
);
2285 /* For simplicity, sampler and image bindless descriptors use fixed
2286 * 16-dword slots for now. Image descriptors only need 8-dword but this
2287 * doesn't really matter because no real apps use image handles.
2289 desc_slot_offset
= desc_slot
* 16;
2291 /* Copy the descriptor into the array. */
2292 memcpy(desc
->list
+ desc_slot_offset
, desc_list
, size
);
2294 /* Re-upload the whole array of bindless descriptors into a new buffer.
2296 if (!si_upload_descriptors(sctx
, desc
))
2299 /* Make sure to re-emit the shader pointers for all stages. */
2300 sctx
->graphics_bindless_pointer_dirty
= true;
2301 sctx
->compute_bindless_pointer_dirty
= true;
2306 static void si_update_bindless_buffer_descriptor(struct si_context
*sctx
,
2308 struct pipe_resource
*resource
,
2312 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2313 struct si_resource
*buf
= si_resource(resource
);
2314 unsigned desc_slot_offset
= desc_slot
* 16;
2315 uint32_t *desc_list
= desc
->list
+ desc_slot_offset
+ 4;
2316 uint64_t old_desc_va
;
2318 assert(resource
->target
== PIPE_BUFFER
);
2320 /* Retrieve the old buffer addr from the descriptor. */
2321 old_desc_va
= si_desc_extract_buffer_address(desc_list
);
2323 if (old_desc_va
!= buf
->gpu_address
+ offset
) {
2324 /* The buffer has been invalidated when the handle wasn't
2325 * resident, update the descriptor and the dirty flag.
2327 si_set_buf_desc_address(buf
, offset
, &desc_list
[0]);
2333 static uint64_t si_create_texture_handle(struct pipe_context
*ctx
,
2334 struct pipe_sampler_view
*view
,
2335 const struct pipe_sampler_state
*state
)
2337 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
2338 struct si_context
*sctx
= (struct si_context
*)ctx
;
2339 struct si_texture_handle
*tex_handle
;
2340 struct si_sampler_state
*sstate
;
2341 uint32_t desc_list
[16];
2344 tex_handle
= CALLOC_STRUCT(si_texture_handle
);
2348 memset(desc_list
, 0, sizeof(desc_list
));
2349 si_init_descriptor_list(&desc_list
[0], 16, 1, null_texture_descriptor
);
2351 sstate
= ctx
->create_sampler_state(ctx
, state
);
2357 si_set_sampler_view_desc(sctx
, sview
, sstate
, &desc_list
[0]);
2358 memcpy(&tex_handle
->sstate
, sstate
, sizeof(*sstate
));
2359 ctx
->delete_sampler_state(ctx
, sstate
);
2361 tex_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2363 if (!tex_handle
->desc_slot
) {
2368 handle
= tex_handle
->desc_slot
;
2370 if (!_mesa_hash_table_insert(sctx
->tex_handles
,
2371 (void *)(uintptr_t)handle
,
2377 pipe_sampler_view_reference(&tex_handle
->view
, view
);
2379 si_resource(sview
->base
.texture
)->texture_handle_allocated
= true;
2384 static void si_delete_texture_handle(struct pipe_context
*ctx
, uint64_t handle
)
2386 struct si_context
*sctx
= (struct si_context
*)ctx
;
2387 struct si_texture_handle
*tex_handle
;
2388 struct hash_entry
*entry
;
2390 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2391 (void *)(uintptr_t)handle
);
2395 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2397 /* Allow this descriptor slot to be re-used. */
2398 util_idalloc_free(&sctx
->bindless_used_slots
, tex_handle
->desc_slot
);
2400 pipe_sampler_view_reference(&tex_handle
->view
, NULL
);
2401 _mesa_hash_table_remove(sctx
->tex_handles
, entry
);
2405 static void si_make_texture_handle_resident(struct pipe_context
*ctx
,
2406 uint64_t handle
, bool resident
)
2408 struct si_context
*sctx
= (struct si_context
*)ctx
;
2409 struct si_texture_handle
*tex_handle
;
2410 struct si_sampler_view
*sview
;
2411 struct hash_entry
*entry
;
2413 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2414 (void *)(uintptr_t)handle
);
2418 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2419 sview
= (struct si_sampler_view
*)tex_handle
->view
;
2422 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2423 struct si_texture
*tex
=
2424 (struct si_texture
*)sview
->base
.texture
;
2426 if (depth_needs_decompression(tex
)) {
2427 util_dynarray_append(
2428 &sctx
->resident_tex_needs_depth_decompress
,
2429 struct si_texture_handle
*,
2433 if (color_needs_decompression(tex
)) {
2434 util_dynarray_append(
2435 &sctx
->resident_tex_needs_color_decompress
,
2436 struct si_texture_handle
*,
2440 if (tex
->dcc_offset
&&
2441 p_atomic_read(&tex
->framebuffers_bound
))
2442 sctx
->need_check_render_feedback
= true;
2444 si_update_bindless_texture_descriptor(sctx
, tex_handle
);
2446 si_update_bindless_buffer_descriptor(sctx
,
2447 tex_handle
->desc_slot
,
2448 sview
->base
.texture
,
2449 sview
->base
.u
.buf
.offset
,
2450 &tex_handle
->desc_dirty
);
2453 /* Re-upload the descriptor if it has been updated while it
2456 if (tex_handle
->desc_dirty
)
2457 sctx
->bindless_descriptors_dirty
= true;
2459 /* Add the texture handle to the per-context list. */
2460 util_dynarray_append(&sctx
->resident_tex_handles
,
2461 struct si_texture_handle
*, tex_handle
);
2463 /* Add the buffers to the current CS in case si_begin_new_cs()
2464 * is not going to be called.
2466 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2468 sview
->is_stencil_sampler
, false);
2470 /* Remove the texture handle from the per-context list. */
2471 util_dynarray_delete_unordered(&sctx
->resident_tex_handles
,
2472 struct si_texture_handle
*,
2475 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2476 util_dynarray_delete_unordered(
2477 &sctx
->resident_tex_needs_depth_decompress
,
2478 struct si_texture_handle
*, tex_handle
);
2480 util_dynarray_delete_unordered(
2481 &sctx
->resident_tex_needs_color_decompress
,
2482 struct si_texture_handle
*, tex_handle
);
2487 static uint64_t si_create_image_handle(struct pipe_context
*ctx
,
2488 const struct pipe_image_view
*view
)
2490 struct si_context
*sctx
= (struct si_context
*)ctx
;
2491 struct si_image_handle
*img_handle
;
2492 uint32_t desc_list
[8];
2495 if (!view
|| !view
->resource
)
2498 img_handle
= CALLOC_STRUCT(si_image_handle
);
2502 memset(desc_list
, 0, sizeof(desc_list
));
2503 si_init_descriptor_list(&desc_list
[0], 8, 1, null_image_descriptor
);
2505 si_set_shader_image_desc(sctx
, view
, false, &desc_list
[0], NULL
);
2507 img_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2509 if (!img_handle
->desc_slot
) {
2514 handle
= img_handle
->desc_slot
;
2516 if (!_mesa_hash_table_insert(sctx
->img_handles
,
2517 (void *)(uintptr_t)handle
,
2523 util_copy_image_view(&img_handle
->view
, view
);
2525 si_resource(view
->resource
)->image_handle_allocated
= true;
2530 static void si_delete_image_handle(struct pipe_context
*ctx
, uint64_t handle
)
2532 struct si_context
*sctx
= (struct si_context
*)ctx
;
2533 struct si_image_handle
*img_handle
;
2534 struct hash_entry
*entry
;
2536 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2537 (void *)(uintptr_t)handle
);
2541 img_handle
= (struct si_image_handle
*)entry
->data
;
2543 util_copy_image_view(&img_handle
->view
, NULL
);
2544 _mesa_hash_table_remove(sctx
->img_handles
, entry
);
2548 static void si_make_image_handle_resident(struct pipe_context
*ctx
,
2549 uint64_t handle
, unsigned access
,
2552 struct si_context
*sctx
= (struct si_context
*)ctx
;
2553 struct si_image_handle
*img_handle
;
2554 struct pipe_image_view
*view
;
2555 struct si_resource
*res
;
2556 struct hash_entry
*entry
;
2558 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2559 (void *)(uintptr_t)handle
);
2563 img_handle
= (struct si_image_handle
*)entry
->data
;
2564 view
= &img_handle
->view
;
2565 res
= si_resource(view
->resource
);
2568 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2569 struct si_texture
*tex
= (struct si_texture
*)res
;
2570 unsigned level
= view
->u
.tex
.level
;
2572 if (color_needs_decompression(tex
)) {
2573 util_dynarray_append(
2574 &sctx
->resident_img_needs_color_decompress
,
2575 struct si_image_handle
*,
2579 if (vi_dcc_enabled(tex
, level
) &&
2580 p_atomic_read(&tex
->framebuffers_bound
))
2581 sctx
->need_check_render_feedback
= true;
2583 si_update_bindless_image_descriptor(sctx
, img_handle
);
2585 si_update_bindless_buffer_descriptor(sctx
,
2586 img_handle
->desc_slot
,
2589 &img_handle
->desc_dirty
);
2592 /* Re-upload the descriptor if it has been updated while it
2595 if (img_handle
->desc_dirty
)
2596 sctx
->bindless_descriptors_dirty
= true;
2598 /* Add the image handle to the per-context list. */
2599 util_dynarray_append(&sctx
->resident_img_handles
,
2600 struct si_image_handle
*, img_handle
);
2602 /* Add the buffers to the current CS in case si_begin_new_cs()
2603 * is not going to be called.
2605 si_sampler_view_add_buffer(sctx
, view
->resource
,
2606 (access
& PIPE_IMAGE_ACCESS_WRITE
) ?
2607 RADEON_USAGE_READWRITE
:
2608 RADEON_USAGE_READ
, false, false);
2610 /* Remove the image handle from the per-context list. */
2611 util_dynarray_delete_unordered(&sctx
->resident_img_handles
,
2612 struct si_image_handle
*,
2615 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2616 util_dynarray_delete_unordered(
2617 &sctx
->resident_img_needs_color_decompress
,
2618 struct si_image_handle
*,
2624 static void si_resident_buffers_add_all_to_bo_list(struct si_context
*sctx
)
2626 unsigned num_resident_tex_handles
, num_resident_img_handles
;
2628 num_resident_tex_handles
= sctx
->resident_tex_handles
.size
/
2629 sizeof(struct si_texture_handle
*);
2630 num_resident_img_handles
= sctx
->resident_img_handles
.size
/
2631 sizeof(struct si_image_handle
*);
2633 /* Add all resident texture handles. */
2634 util_dynarray_foreach(&sctx
->resident_tex_handles
,
2635 struct si_texture_handle
*, tex_handle
) {
2636 struct si_sampler_view
*sview
=
2637 (struct si_sampler_view
*)(*tex_handle
)->view
;
2639 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2641 sview
->is_stencil_sampler
, false);
2644 /* Add all resident image handles. */
2645 util_dynarray_foreach(&sctx
->resident_img_handles
,
2646 struct si_image_handle
*, img_handle
) {
2647 struct pipe_image_view
*view
= &(*img_handle
)->view
;
2649 si_sampler_view_add_buffer(sctx
, view
->resource
,
2650 RADEON_USAGE_READWRITE
,
2654 sctx
->num_resident_handles
+= num_resident_tex_handles
+
2655 num_resident_img_handles
;
2656 assert(sctx
->bo_list_add_all_resident_resources
);
2657 sctx
->bo_list_add_all_resident_resources
= false;
2660 /* INIT/DEINIT/UPLOAD */
2662 void si_init_all_descriptors(struct si_context
*sctx
)
2665 unsigned first_shader
=
2666 sctx
->has_graphics
? 0 : PIPE_SHADER_COMPUTE
;
2668 for (i
= first_shader
; i
< SI_NUM_SHADERS
; i
++) {
2669 bool is_2nd
= sctx
->chip_class
>= GFX9
&&
2670 (i
== PIPE_SHADER_TESS_CTRL
||
2671 i
== PIPE_SHADER_GEOMETRY
);
2672 unsigned num_sampler_slots
= SI_NUM_IMAGES
/ 2 + SI_NUM_SAMPLERS
;
2673 unsigned num_buffer_slots
= SI_NUM_SHADER_BUFFERS
+ SI_NUM_CONST_BUFFERS
;
2675 struct si_descriptors
*desc
;
2678 if (i
== PIPE_SHADER_TESS_CTRL
) {
2679 rel_dw_offset
= (R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
-
2680 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2681 } else { /* PIPE_SHADER_GEOMETRY */
2682 rel_dw_offset
= (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
-
2683 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2686 rel_dw_offset
= SI_SGPR_CONST_AND_SHADER_BUFFERS
;
2688 desc
= si_const_and_shader_buffer_descriptors(sctx
, i
);
2689 si_init_buffer_resources(&sctx
->const_and_shader_buffers
[i
], desc
,
2690 num_buffer_slots
, rel_dw_offset
,
2691 RADEON_PRIO_SHADER_RW_BUFFER
,
2692 RADEON_PRIO_CONST_BUFFER
);
2693 desc
->slot_index_to_bind_directly
= si_get_constbuf_slot(0);
2696 if (i
== PIPE_SHADER_TESS_CTRL
) {
2697 rel_dw_offset
= (R_00B40C_SPI_SHADER_USER_DATA_ADDR_HI_HS
-
2698 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2699 } else { /* PIPE_SHADER_GEOMETRY */
2700 rel_dw_offset
= (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS
-
2701 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2704 rel_dw_offset
= SI_SGPR_SAMPLERS_AND_IMAGES
;
2707 desc
= si_sampler_and_image_descriptors(sctx
, i
);
2708 si_init_descriptors(desc
, rel_dw_offset
, 16, num_sampler_slots
);
2711 for (j
= 0; j
< SI_NUM_IMAGES
; j
++)
2712 memcpy(desc
->list
+ j
* 8, null_image_descriptor
, 8 * 4);
2713 for (; j
< SI_NUM_IMAGES
+ SI_NUM_SAMPLERS
* 2; j
++)
2714 memcpy(desc
->list
+ j
* 8, null_texture_descriptor
, 8 * 4);
2717 si_init_buffer_resources(&sctx
->rw_buffers
,
2718 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
2719 SI_NUM_RW_BUFFERS
, SI_SGPR_RW_BUFFERS
,
2720 /* The second priority is used by
2721 * const buffers in RW buffer slots. */
2722 RADEON_PRIO_SHADER_RINGS
, RADEON_PRIO_CONST_BUFFER
);
2723 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
= SI_NUM_RW_BUFFERS
;
2725 /* Initialize an array of 1024 bindless descriptors, when the limit is
2726 * reached, just make it larger and re-upload the whole array.
2728 si_init_bindless_descriptors(sctx
, &sctx
->bindless_descriptors
,
2729 SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
,
2732 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2734 /* Set pipe_context functions. */
2735 sctx
->b
.bind_sampler_states
= si_bind_sampler_states
;
2736 sctx
->b
.set_shader_images
= si_set_shader_images
;
2737 sctx
->b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
2738 sctx
->b
.set_shader_buffers
= si_set_shader_buffers
;
2739 sctx
->b
.set_sampler_views
= si_set_sampler_views
;
2740 sctx
->b
.create_texture_handle
= si_create_texture_handle
;
2741 sctx
->b
.delete_texture_handle
= si_delete_texture_handle
;
2742 sctx
->b
.make_texture_handle_resident
= si_make_texture_handle_resident
;
2743 sctx
->b
.create_image_handle
= si_create_image_handle
;
2744 sctx
->b
.delete_image_handle
= si_delete_image_handle
;
2745 sctx
->b
.make_image_handle_resident
= si_make_image_handle_resident
;
2747 if (!sctx
->has_graphics
)
2750 sctx
->b
.set_polygon_stipple
= si_set_polygon_stipple
;
2752 /* Shader user data. */
2753 sctx
->atoms
.s
.shader_pointers
.emit
= si_emit_graphics_shader_pointers
;
2755 /* Set default and immutable mappings. */
2756 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2758 if (sctx
->chip_class
>= GFX9
) {
2759 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2760 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2761 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2762 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2764 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2765 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2766 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2767 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2769 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2772 static bool si_upload_shader_descriptors(struct si_context
*sctx
, unsigned mask
)
2774 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2776 /* Assume nothing will go wrong: */
2777 sctx
->shader_pointers_dirty
|= dirty
;
2780 unsigned i
= u_bit_scan(&dirty
);
2782 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
]))
2786 sctx
->descriptors_dirty
&= ~mask
;
2788 si_upload_bindless_descriptors(sctx
);
2793 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
2795 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
2796 return si_upload_shader_descriptors(sctx
, mask
);
2799 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
2801 /* Does not update rw_buffers as that is not needed for compute shaders
2802 * and the input buffer is using the same SGPR's anyway.
2804 const unsigned mask
= u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
,
2805 SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
2806 return si_upload_shader_descriptors(sctx
, mask
);
2809 void si_release_all_descriptors(struct si_context
*sctx
)
2813 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2814 si_release_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2815 si_const_and_shader_buffer_descriptors(sctx
, i
));
2816 si_release_sampler_views(&sctx
->samplers
[i
]);
2817 si_release_image_views(&sctx
->images
[i
]);
2819 si_release_buffer_resources(&sctx
->rw_buffers
,
2820 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2821 for (i
= 0; i
< SI_NUM_VERTEX_BUFFERS
; i
++)
2822 pipe_vertex_buffer_unreference(&sctx
->vertex_buffer
[i
]);
2824 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2825 si_release_descriptors(&sctx
->descriptors
[i
]);
2827 si_resource_reference(&sctx
->vb_descriptors_buffer
, NULL
);
2828 sctx
->vb_descriptors_gpu_list
= NULL
; /* points into a mapped buffer */
2830 si_release_bindless_descriptors(sctx
);
2833 void si_gfx_resources_add_all_to_bo_list(struct si_context
*sctx
)
2835 for (unsigned i
= 0; i
< SI_NUM_GRAPHICS_SHADERS
; i
++) {
2836 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2837 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
]);
2838 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
2840 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2841 si_vertex_buffers_begin_new_cs(sctx
);
2843 if (sctx
->bo_list_add_all_resident_resources
)
2844 si_resident_buffers_add_all_to_bo_list(sctx
);
2846 assert(sctx
->bo_list_add_all_gfx_resources
);
2847 sctx
->bo_list_add_all_gfx_resources
= false;
2850 void si_compute_resources_add_all_to_bo_list(struct si_context
*sctx
)
2852 unsigned sh
= PIPE_SHADER_COMPUTE
;
2854 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[sh
]);
2855 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[sh
]);
2856 si_image_views_begin_new_cs(sctx
, &sctx
->images
[sh
]);
2857 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2859 if (sctx
->bo_list_add_all_resident_resources
)
2860 si_resident_buffers_add_all_to_bo_list(sctx
);
2862 assert(sctx
->bo_list_add_all_compute_resources
);
2863 sctx
->bo_list_add_all_compute_resources
= false;
2866 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
2868 for (unsigned i
= 0; i
< SI_NUM_DESCS
; ++i
)
2869 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
2870 si_descriptors_begin_new_cs(sctx
, &sctx
->bindless_descriptors
);
2872 si_shader_pointers_begin_new_cs(sctx
);
2874 sctx
->bo_list_add_all_resident_resources
= true;
2875 sctx
->bo_list_add_all_gfx_resources
= true;
2876 sctx
->bo_list_add_all_compute_resources
= true;
2879 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
2880 uint64_t new_active_mask
)
2882 struct si_descriptors
*desc
= &sctx
->descriptors
[desc_idx
];
2884 /* Ignore no-op updates and updates that disable all slots. */
2885 if (!new_active_mask
||
2886 new_active_mask
== u_bit_consecutive64(desc
->first_active_slot
,
2887 desc
->num_active_slots
))
2891 u_bit_scan_consecutive_range64(&new_active_mask
, &first
, &count
);
2892 assert(new_active_mask
== 0);
2894 /* Upload/dump descriptors if slots are being enabled. */
2895 if (first
< desc
->first_active_slot
||
2896 first
+ count
> desc
->first_active_slot
+ desc
->num_active_slots
)
2897 sctx
->descriptors_dirty
|= 1u << desc_idx
;
2899 desc
->first_active_slot
= first
;
2900 desc
->num_active_slots
= count
;
2903 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
2904 struct si_shader_selector
*sel
)
2909 si_set_active_descriptors(sctx
,
2910 si_const_and_shader_buffer_descriptors_idx(sel
->type
),
2911 sel
->active_const_and_shader_buffers
);
2912 si_set_active_descriptors(sctx
,
2913 si_sampler_and_image_descriptors_idx(sel
->type
),
2914 sel
->active_samplers_and_images
);