projects / mesa.git / blob
? search:


48146188ffc09cf4ed099fc0365f92ccc0004b59
[mesa.git] / src / gallium / drivers / radeonsi / si_descriptors.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Marek Olšák <marek.olsak@amd.com>
25 */
26
27 /* Resource binding slots and sampler states (each described with 8 or
28 * 4 dwords) are stored in lists in memory which is accessed by shaders
29 * using scalar load instructions.
30 *
31 * This file is responsible for managing such lists. It keeps a copy of all
32 * descriptors in CPU memory and re-uploads a whole list if some slots have
33 * been changed.
34 *
35 * This code is also reponsible for updating shader pointers to those lists.
36 *
37 * Note that CP DMA can't be used for updating the lists, because a GPU hang
38 * could leave the list in a mid-IB state and the next IB would get wrong
39 * descriptors and the whole context would be unusable at that point.
40 * (Note: The register shadowing can't be used due to the same reason)
41 *
42 * Also, uploading descriptors to newly allocated memory doesn't require
43 * a KCACHE flush.
44 *
45 *
46 * Possible scenarios for one 16 dword image+sampler slot:
47 *
48 * | Image | w/ FMASK | Buffer | NULL
49 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
50 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
51 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
52 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
53 *
54 * FMASK implies MSAA, therefore no sampler state.
55 * Sampler states are never unbound except when FMASK is bound.
56 */
57
58 #include "radeon/r600_cs.h"
59 #include "si_pipe.h"
60 #include "si_shader.h"
61 #include "sid.h"
62
63 #include "util/u_format.h"
64 #include "util/u_math.h"
65 #include "util/u_memory.h"
66 #include "util/u_suballoc.h"
67 #include "util/u_upload_mgr.h"
68
69
70 /* NULL image and buffer descriptor for textures (alpha = 1) and images
71 * (alpha = 0).
72 *
73 * For images, all fields must be zero except for the swizzle, which
74 * supports arbitrary combinations of 0s and 1s. The texture type must be
75 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
76 *
77 * For buffers, all fields must be zero. If they are not, the hw hangs.
78 *
79 * This is the only reason why the buffer descriptor must be in words [4:7].
80 */
81 static uint32_t null_texture_descriptor[8] = {
82 0,
83 0,
84 0,
85 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1) |
86 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
87 /* the rest must contain zeros, which is also used by the buffer
88 * descriptor */
89 };
90
91 static uint32_t null_image_descriptor[8] = {
92 0,
93 0,
94 0,
95 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
96 /* the rest must contain zeros, which is also used by the buffer
97 * descriptor */
98 };
99
100 static void si_init_descriptors(struct si_descriptors *desc,
101 unsigned shader_userdata_index,
102 unsigned element_dw_size,
103 unsigned num_elements,
104 const uint32_t *null_descriptor,
105 unsigned *ce_offset)
106 {
107 int i;
108
109 assert(num_elements <= sizeof(desc->dirty_mask)*8);
110
111 desc->list = CALLOC(num_elements, element_dw_size * 4);
112 desc->element_dw_size = element_dw_size;
113 desc->num_elements = num_elements;
114 desc->dirty_mask = num_elements == 32 ? ~0u : (1u << num_elements) - 1;
115 desc->shader_userdata_offset = shader_userdata_index * 4;
116
117 if (ce_offset) {
118 desc->ce_offset = *ce_offset;
119
120 /* make sure that ce_offset stays 32 byte aligned */
121 *ce_offset += align(element_dw_size * num_elements * 4, 32);
122 }
123
124 /* Initialize the array to NULL descriptors if the element size is 8. */
125 if (null_descriptor) {
126 assert(element_dw_size % 8 == 0);
127 for (i = 0; i < num_elements * element_dw_size / 8; i++)
128 memcpy(desc->list + i * 8, null_descriptor,
129 8 * 4);
130 }
131 }
132
133 static void si_release_descriptors(struct si_descriptors *desc)
134 {
135 pipe_resource_reference((struct pipe_resource**)&desc->buffer, NULL);
136 FREE(desc->list);
137 }
138
139 static bool si_ce_upload(struct si_context *sctx, unsigned ce_offset, unsigned size,
140 unsigned *out_offset, struct r600_resource **out_buf) {
141 uint64_t va;
142
143 u_suballocator_alloc(sctx->ce_suballocator, size, 64, out_offset,
144 (struct pipe_resource**)out_buf);
145 if (!out_buf)
146 return false;
147
148 va = (*out_buf)->gpu_address + *out_offset;
149
150 radeon_emit(sctx->ce_ib, PKT3(PKT3_DUMP_CONST_RAM, 3, 0));
151 radeon_emit(sctx->ce_ib, ce_offset);
152 radeon_emit(sctx->ce_ib, size / 4);
153 radeon_emit(sctx->ce_ib, va);
154 radeon_emit(sctx->ce_ib, va >> 32);
155
156 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, *out_buf,
157 RADEON_USAGE_READWRITE, RADEON_PRIO_DESCRIPTORS);
158
159 sctx->ce_need_synchronization = true;
160 return true;
161 }
162
163 static void si_reinitialize_ce_ram(struct si_context *sctx,
164 struct si_descriptors *desc)
165 {
166 if (desc->buffer) {
167 struct r600_resource *buffer = (struct r600_resource*)desc->buffer;
168 unsigned list_size = desc->num_elements * desc->element_dw_size * 4;
169 uint64_t va = buffer->gpu_address + desc->buffer_offset;
170 struct radeon_winsys_cs *ib = sctx->ce_preamble_ib;
171
172 if (!ib)
173 ib = sctx->ce_ib;
174
175 list_size = align(list_size, 32);
176
177 radeon_emit(ib, PKT3(PKT3_LOAD_CONST_RAM, 3, 0));
178 radeon_emit(ib, va);
179 radeon_emit(ib, va >> 32);
180 radeon_emit(ib, list_size / 4);
181 radeon_emit(ib, desc->ce_offset);
182
183 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
184 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
185 }
186 desc->ce_ram_dirty = false;
187 }
188
189 void si_ce_enable_loads(struct radeon_winsys_cs *ib)
190 {
191 radeon_emit(ib, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
192 radeon_emit(ib, CONTEXT_CONTROL_LOAD_ENABLE(1) |
193 CONTEXT_CONTROL_LOAD_CE_RAM(1));
194 radeon_emit(ib, CONTEXT_CONTROL_SHADOW_ENABLE(1));
195 }
196
197 static bool si_upload_descriptors(struct si_context *sctx,
198 struct si_descriptors *desc,
199 struct r600_atom * atom)
200 {
201 unsigned list_size = desc->num_elements * desc->element_dw_size * 4;
202
203 if (!desc->dirty_mask)
204 return true;
205
206 if (sctx->ce_ib) {
207 uint32_t const* list = (uint32_t const*)desc->list;
208
209 if (desc->ce_ram_dirty)
210 si_reinitialize_ce_ram(sctx, desc);
211
212 while(desc->dirty_mask) {
213 int begin, count;
214 u_bit_scan_consecutive_range(&desc->dirty_mask, &begin,
215 &count);
216
217 begin *= desc->element_dw_size;
218 count *= desc->element_dw_size;
219
220 radeon_emit(sctx->ce_ib,
221 PKT3(PKT3_WRITE_CONST_RAM, count, 0));
222 radeon_emit(sctx->ce_ib, desc->ce_offset + begin * 4);
223 radeon_emit_array(sctx->ce_ib, list + begin, count);
224 }
225
226 if (!si_ce_upload(sctx, desc->ce_offset, list_size,
227 &desc->buffer_offset, &desc->buffer))
228 return false;
229 } else {
230 void *ptr;
231
232 u_upload_alloc(sctx->b.uploader, 0, list_size, 256,
233 &desc->buffer_offset,
234 (struct pipe_resource**)&desc->buffer, &ptr);
235 if (!desc->buffer)
236 return false; /* skip the draw call */
237
238 util_memcpy_cpu_to_le32(ptr, desc->list, list_size);
239
240 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
241 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
242 }
243 desc->pointer_dirty = true;
244 desc->dirty_mask = 0;
245
246 if (atom)
247 si_mark_atom_dirty(sctx, atom);
248
249 return true;
250 }
251
252 static void
253 si_descriptors_begin_new_cs(struct si_context *sctx, struct si_descriptors *desc)
254 {
255 desc->ce_ram_dirty = true;
256
257 if (!desc->buffer)
258 return;
259
260 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
261 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
262 }
263
264 /* SAMPLER VIEWS */
265
266 static unsigned
267 si_sampler_descriptors_idx(unsigned shader)
268 {
269 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
270 SI_SHADER_DESCS_SAMPLERS;
271 }
272
273 static struct si_descriptors *
274 si_sampler_descriptors(struct si_context *sctx, unsigned shader)
275 {
276 return &sctx->descriptors[si_sampler_descriptors_idx(shader)];
277 }
278
279 static void si_release_sampler_views(struct si_sampler_views *views)
280 {
281 int i;
282
283 for (i = 0; i < ARRAY_SIZE(views->views); i++) {
284 pipe_sampler_view_reference(&views->views[i], NULL);
285 }
286 }
287
288 static void si_sampler_view_add_buffer(struct si_context *sctx,
289 struct pipe_resource *resource,
290 enum radeon_bo_usage usage)
291 {
292 struct r600_resource *rres = (struct r600_resource*)resource;
293
294 if (!resource)
295 return;
296
297 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, rres, usage,
298 r600_get_sampler_view_priority(rres));
299 }
300
301 static void si_sampler_views_begin_new_cs(struct si_context *sctx,
302 struct si_sampler_views *views)
303 {
304 unsigned mask = views->enabled_mask;
305
306 /* Add buffers to the CS. */
307 while (mask) {
308 int i = u_bit_scan(&mask);
309
310 si_sampler_view_add_buffer(sctx, views->views[i]->texture,
311 RADEON_USAGE_READ);
312 }
313 }
314
315 void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
316 const struct radeon_surf_level *base_level_info,
317 unsigned base_level, unsigned block_width,
318 bool is_stencil, uint32_t *state)
319 {
320 uint64_t va = tex->resource.gpu_address + base_level_info->offset;
321 unsigned pitch = base_level_info->nblk_x * block_width;
322
323 state[1] &= C_008F14_BASE_ADDRESS_HI;
324 state[3] &= C_008F1C_TILING_INDEX;
325 state[4] &= C_008F20_PITCH;
326 state[6] &= C_008F28_COMPRESSION_EN;
327
328 state[0] = va >> 8;
329 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
330 state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(tex, base_level,
331 is_stencil));
332 state[4] |= S_008F20_PITCH(pitch - 1);
333
334 if (tex->dcc_offset) {
335 state[6] |= S_008F28_COMPRESSION_EN(1);
336 state[7] = (tex->resource.gpu_address +
337 tex->dcc_offset +
338 base_level_info->dcc_offset) >> 8;
339 }
340 }
341
342 static void si_set_sampler_view(struct si_context *sctx,
343 unsigned shader,
344 unsigned slot, struct pipe_sampler_view *view,
345 bool disallow_early_out)
346 {
347 struct si_sampler_views *views = &sctx->samplers[shader].views;
348 struct si_sampler_view *rview = (struct si_sampler_view*)view;
349 struct si_descriptors *descs = si_sampler_descriptors(sctx, shader);
350
351 if (views->views[slot] == view && !disallow_early_out)
352 return;
353
354 if (view) {
355 struct r600_texture *rtex = (struct r600_texture *)view->texture;
356 uint32_t *desc = descs->list + slot * 16;
357
358 si_sampler_view_add_buffer(sctx, view->texture,
359 RADEON_USAGE_READ);
360
361 pipe_sampler_view_reference(&views->views[slot], view);
362 memcpy(desc, rview->state, 8*4);
363
364 if (view->texture && view->texture->target != PIPE_BUFFER) {
365 bool is_separate_stencil =
366 rtex->is_depth && !rtex->is_flushing_texture &&
367 rview->is_stencil_sampler;
368
369 si_set_mutable_tex_desc_fields(rtex,
370 rview->base_level_info,
371 rview->base_level,
372 rview->block_width,
373 is_separate_stencil,
374 desc);
375 }
376
377 if (view->texture && view->texture->target != PIPE_BUFFER &&
378 rtex->fmask.size) {
379 memcpy(desc + 8,
380 rview->fmask_state, 8*4);
381 } else {
382 /* Disable FMASK and bind sampler state in [12:15]. */
383 memcpy(desc + 8,
384 null_texture_descriptor, 4*4);
385
386 if (views->sampler_states[slot])
387 memcpy(desc + 12,
388 views->sampler_states[slot], 4*4);
389 }
390
391 views->enabled_mask |= 1u << slot;
392 } else {
393 pipe_sampler_view_reference(&views->views[slot], NULL);
394 memcpy(descs->list + slot*16, null_texture_descriptor, 8*4);
395 /* Only clear the lower dwords of FMASK. */
396 memcpy(descs->list + slot*16 + 8, null_texture_descriptor, 4*4);
397 views->enabled_mask &= ~(1u << slot);
398 }
399
400 descs->dirty_mask |= 1u << slot;
401 }
402
403 static bool is_compressed_colortex(struct r600_texture *rtex)
404 {
405 return rtex->cmask.size || rtex->fmask.size ||
406 (rtex->dcc_offset && rtex->dirty_level_mask);
407 }
408
409 static void si_set_sampler_views(struct pipe_context *ctx,
410 unsigned shader, unsigned start,
411 unsigned count,
412 struct pipe_sampler_view **views)
413 {
414 struct si_context *sctx = (struct si_context *)ctx;
415 struct si_textures_info *samplers = &sctx->samplers[shader];
416 int i;
417
418 if (!count || shader >= SI_NUM_SHADERS)
419 return;
420
421 for (i = 0; i < count; i++) {
422 unsigned slot = start + i;
423
424 if (!views || !views[i]) {
425 samplers->depth_texture_mask &= ~(1u << slot);
426 samplers->compressed_colortex_mask &= ~(1u << slot);
427 si_set_sampler_view(sctx, shader, slot, NULL, false);
428 continue;
429 }
430
431 si_set_sampler_view(sctx, shader, slot, views[i], false);
432
433 if (views[i]->texture && views[i]->texture->target != PIPE_BUFFER) {
434 struct r600_texture *rtex =
435 (struct r600_texture*)views[i]->texture;
436
437 if (rtex->is_depth && !rtex->is_flushing_texture) {
438 samplers->depth_texture_mask |= 1u << slot;
439 } else {
440 samplers->depth_texture_mask &= ~(1u << slot);
441 }
442 if (is_compressed_colortex(rtex)) {
443 samplers->compressed_colortex_mask |= 1u << slot;
444 } else {
445 samplers->compressed_colortex_mask &= ~(1u << slot);
446 }
447
448 if (rtex->dcc_offset &&
449 p_atomic_read(&rtex->framebuffers_bound))
450 sctx->need_check_render_feedback = true;
451 } else {
452 samplers->depth_texture_mask &= ~(1u << slot);
453 samplers->compressed_colortex_mask &= ~(1u << slot);
454 }
455 }
456 }
457
458 static void
459 si_samplers_update_compressed_colortex_mask(struct si_textures_info *samplers)
460 {
461 unsigned mask = samplers->views.enabled_mask;
462
463 while (mask) {
464 int i = u_bit_scan(&mask);
465 struct pipe_resource *res = samplers->views.views[i]->texture;
466
467 if (res && res->target != PIPE_BUFFER) {
468 struct r600_texture *rtex = (struct r600_texture *)res;
469
470 if (is_compressed_colortex(rtex)) {
471 samplers->compressed_colortex_mask |= 1u << i;
472 } else {
473 samplers->compressed_colortex_mask &= ~(1u << i);
474 }
475 }
476 }
477 }
478
479 /* IMAGE VIEWS */
480
481 static unsigned
482 si_image_descriptors_idx(unsigned shader)
483 {
484 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
485 SI_SHADER_DESCS_IMAGES;
486 }
487
488 static struct si_descriptors*
489 si_image_descriptors(struct si_context *sctx, unsigned shader)
490 {
491 return &sctx->descriptors[si_image_descriptors_idx(shader)];
492 }
493
494 static void
495 si_release_image_views(struct si_images_info *images)
496 {
497 unsigned i;
498
499 for (i = 0; i < SI_NUM_IMAGES; ++i) {
500 struct pipe_image_view *view = &images->views[i];
501
502 pipe_resource_reference(&view->resource, NULL);
503 }
504 }
505
506 static void
507 si_image_views_begin_new_cs(struct si_context *sctx, struct si_images_info *images)
508 {
509 uint mask = images->enabled_mask;
510
511 /* Add buffers to the CS. */
512 while (mask) {
513 int i = u_bit_scan(&mask);
514 struct pipe_image_view *view = &images->views[i];
515
516 assert(view->resource);
517
518 si_sampler_view_add_buffer(sctx, view->resource,
519 RADEON_USAGE_READWRITE);
520 }
521 }
522
523 static void
524 si_disable_shader_image(struct si_context *ctx, unsigned shader, unsigned slot)
525 {
526 struct si_images_info *images = &ctx->images[shader];
527
528 if (images->enabled_mask & (1u << slot)) {
529 struct si_descriptors *descs = si_image_descriptors(ctx, shader);
530
531 pipe_resource_reference(&images->views[slot].resource, NULL);
532 images->compressed_colortex_mask &= ~(1 << slot);
533
534 memcpy(descs->list + slot*8, null_image_descriptor, 8*4);
535 images->enabled_mask &= ~(1u << slot);
536 descs->dirty_mask |= 1u << slot;
537 }
538 }
539
540 static void
541 si_mark_image_range_valid(struct pipe_image_view *view)
542 {
543 struct r600_resource *res = (struct r600_resource *)view->resource;
544 const struct util_format_description *desc;
545 unsigned stride;
546
547 assert(res && res->b.b.target == PIPE_BUFFER);
548
549 desc = util_format_description(view->format);
550 stride = desc->block.bits / 8;
551
552 util_range_add(&res->valid_buffer_range,
553 stride * (view->u.buf.first_element),
554 stride * (view->u.buf.last_element + 1));
555 }
556
557 static void si_set_shader_image(struct si_context *ctx,
558 unsigned shader,
559 unsigned slot, struct pipe_image_view *view)
560 {
561 struct si_screen *screen = ctx->screen;
562 struct si_images_info *images = &ctx->images[shader];
563 struct si_descriptors *descs = si_image_descriptors(ctx, shader);
564 struct r600_resource *res;
565
566 if (!view || !view->resource) {
567 si_disable_shader_image(ctx, shader, slot);
568 return;
569 }
570
571 res = (struct r600_resource *)view->resource;
572
573 if (&images->views[slot] != view)
574 util_copy_image_view(&images->views[slot], view);
575
576 si_sampler_view_add_buffer(ctx, &res->b.b,
577 RADEON_USAGE_READWRITE);
578
579 if (res->b.b.target == PIPE_BUFFER) {
580 if (view->access & PIPE_IMAGE_ACCESS_WRITE)
581 si_mark_image_range_valid(view);
582
583 si_make_buffer_descriptor(screen, res,
584 view->format,
585 view->u.buf.first_element,
586 view->u.buf.last_element,
587 descs->list + slot * 8);
588 images->compressed_colortex_mask &= ~(1 << slot);
589 } else {
590 static const unsigned char swizzle[4] = { 0, 1, 2, 3 };
591 struct r600_texture *tex = (struct r600_texture *)res;
592 unsigned level;
593 unsigned width, height, depth;
594 uint32_t *desc = descs->list + slot * 8;
595
596 assert(!tex->is_depth);
597 assert(tex->fmask.size == 0);
598
599 if (tex->dcc_offset &&
600 view->access & PIPE_IMAGE_ACCESS_WRITE) {
601 /* If DCC can't be disabled, at least decompress it.
602 * The decompression is relatively cheap if the surface
603 * has been decompressed already.
604 */
605 if (!r600_texture_disable_dcc(&screen->b, tex))
606 ctx->b.decompress_dcc(&ctx->b.b, tex);
607 }
608
609 if (is_compressed_colortex(tex)) {
610 images->compressed_colortex_mask |= 1 << slot;
611 } else {
612 images->compressed_colortex_mask &= ~(1 << slot);
613 }
614
615 if (tex->dcc_offset &&
616 p_atomic_read(&tex->framebuffers_bound))
617 ctx->need_check_render_feedback = true;
618
619 /* Always force the base level to the selected level.
620 *
621 * This is required for 3D textures, where otherwise
622 * selecting a single slice for non-layered bindings
623 * fails. It doesn't hurt the other targets.
624 */
625 level = view->u.tex.level;
626 width = u_minify(res->b.b.width0, level);
627 height = u_minify(res->b.b.height0, level);
628 depth = u_minify(res->b.b.depth0, level);
629
630 si_make_texture_descriptor(screen, tex,
631 false, res->b.b.target,
632 view->format, swizzle,
633 0, 0,
634 view->u.tex.first_layer,
635 view->u.tex.last_layer,
636 width, height, depth,
637 desc, NULL);
638 si_set_mutable_tex_desc_fields(tex, &tex->surface.level[level], level,
639 util_format_get_blockwidth(view->format),
640 false, desc);
641 }
642
643 images->enabled_mask |= 1u << slot;
644 descs->dirty_mask |= 1u << slot;
645 }
646
647 static void
648 si_set_shader_images(struct pipe_context *pipe, unsigned shader,
649 unsigned start_slot, unsigned count,
650 struct pipe_image_view *views)
651 {
652 struct si_context *ctx = (struct si_context *)pipe;
653 unsigned i, slot;
654
655 assert(shader < SI_NUM_SHADERS);
656
657 if (!count)
658 return;
659
660 assert(start_slot + count <= SI_NUM_IMAGES);
661
662 if (views) {
663 for (i = 0, slot = start_slot; i < count; ++i, ++slot)
664 si_set_shader_image(ctx, shader, slot, &views[i]);
665 } else {
666 for (i = 0, slot = start_slot; i < count; ++i, ++slot)
667 si_set_shader_image(ctx, shader, slot, NULL);
668 }
669 }
670
671 static void
672 si_images_update_compressed_colortex_mask(struct si_images_info *images)
673 {
674 unsigned mask = images->enabled_mask;
675
676 while (mask) {
677 int i = u_bit_scan(&mask);
678 struct pipe_resource *res = images->views[i].resource;
679
680 if (res && res->target != PIPE_BUFFER) {
681 struct r600_texture *rtex = (struct r600_texture *)res;
682
683 if (is_compressed_colortex(rtex)) {
684 images->compressed_colortex_mask |= 1 << i;
685 } else {
686 images->compressed_colortex_mask &= ~(1 << i);
687 }
688 }
689 }
690 }
691
692 /* SAMPLER STATES */
693
694 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
695 unsigned start, unsigned count, void **states)
696 {
697 struct si_context *sctx = (struct si_context *)ctx;
698 struct si_textures_info *samplers = &sctx->samplers[shader];
699 struct si_descriptors *desc = si_sampler_descriptors(sctx, shader);
700 struct si_sampler_state **sstates = (struct si_sampler_state**)states;
701 int i;
702
703 if (!count || shader >= SI_NUM_SHADERS)
704 return;
705
706 for (i = 0; i < count; i++) {
707 unsigned slot = start + i;
708
709 if (!sstates[i] ||
710 sstates[i] == samplers->views.sampler_states[slot])
711 continue;
712
713 samplers->views.sampler_states[slot] = sstates[i];
714
715 /* If FMASK is bound, don't overwrite it.
716 * The sampler state will be set after FMASK is unbound.
717 */
718 if (samplers->views.views[i] &&
719 samplers->views.views[i]->texture &&
720 samplers->views.views[i]->texture->target != PIPE_BUFFER &&
721 ((struct r600_texture*)samplers->views.views[i]->texture)->fmask.size)
722 continue;
723
724 memcpy(desc->list + slot * 16 + 12, sstates[i]->val, 4*4);
725 desc->dirty_mask |= 1u << slot;
726 }
727 }
728
729 /* BUFFER RESOURCES */
730
731 static void si_init_buffer_resources(struct si_buffer_resources *buffers,
732 struct si_descriptors *descs,
733 unsigned num_buffers,
734 unsigned shader_userdata_index,
735 enum radeon_bo_usage shader_usage,
736 enum radeon_bo_priority priority,
737 unsigned *ce_offset)
738 {
739 buffers->shader_usage = shader_usage;
740 buffers->priority = priority;
741 buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource*));
742
743 si_init_descriptors(descs, shader_userdata_index, 4,
744 num_buffers, NULL, ce_offset);
745 }
746
747 static void si_release_buffer_resources(struct si_buffer_resources *buffers,
748 struct si_descriptors *descs)
749 {
750 int i;
751
752 for (i = 0; i < descs->num_elements; i++) {
753 pipe_resource_reference(&buffers->buffers[i], NULL);
754 }
755
756 FREE(buffers->buffers);
757 }
758
759 static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
760 struct si_buffer_resources *buffers)
761 {
762 unsigned mask = buffers->enabled_mask;
763
764 /* Add buffers to the CS. */
765 while (mask) {
766 int i = u_bit_scan(&mask);
767
768 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
769 (struct r600_resource*)buffers->buffers[i],
770 buffers->shader_usage, buffers->priority);
771 }
772 }
773
774 /* VERTEX BUFFERS */
775
776 static void si_vertex_buffers_begin_new_cs(struct si_context *sctx)
777 {
778 struct si_descriptors *desc = &sctx->vertex_buffers;
779 int count = sctx->vertex_elements ? sctx->vertex_elements->count : 0;
780 int i;
781
782 for (i = 0; i < count; i++) {
783 int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
784
785 if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
786 continue;
787 if (!sctx->vertex_buffer[vb].buffer)
788 continue;
789
790 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
791 (struct r600_resource*)sctx->vertex_buffer[vb].buffer,
792 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
793 }
794
795 if (!desc->buffer)
796 return;
797 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
798 desc->buffer, RADEON_USAGE_READ,
799 RADEON_PRIO_DESCRIPTORS);
800 }
801
802 static bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
803 {
804 struct si_descriptors *desc = &sctx->vertex_buffers;
805 bool bound[SI_NUM_VERTEX_BUFFERS] = {};
806 unsigned i, count = sctx->vertex_elements->count;
807 uint64_t va;
808 uint32_t *ptr;
809
810 if (!sctx->vertex_buffers_dirty)
811 return true;
812 if (!count || !sctx->vertex_elements)
813 return true;
814
815 /* Vertex buffer descriptors are the only ones which are uploaded
816 * directly through a staging buffer and don't go through
817 * the fine-grained upload path.
818 */
819 u_upload_alloc(sctx->b.uploader, 0, count * 16, 256, &desc->buffer_offset,
820 (struct pipe_resource**)&desc->buffer, (void**)&ptr);
821 if (!desc->buffer)
822 return false;
823
824 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
825 desc->buffer, RADEON_USAGE_READ,
826 RADEON_PRIO_DESCRIPTORS);
827
828 assert(count <= SI_NUM_VERTEX_BUFFERS);
829
830 for (i = 0; i < count; i++) {
831 struct pipe_vertex_element *ve = &sctx->vertex_elements->elements[i];
832 struct pipe_vertex_buffer *vb;
833 struct r600_resource *rbuffer;
834 unsigned offset;
835 uint32_t *desc = &ptr[i*4];
836
837 if (ve->vertex_buffer_index >= ARRAY_SIZE(sctx->vertex_buffer)) {
838 memset(desc, 0, 16);
839 continue;
840 }
841
842 vb = &sctx->vertex_buffer[ve->vertex_buffer_index];
843 rbuffer = (struct r600_resource*)vb->buffer;
844 if (!rbuffer) {
845 memset(desc, 0, 16);
846 continue;
847 }
848
849 offset = vb->buffer_offset + ve->src_offset;
850 va = rbuffer->gpu_address + offset;
851
852 /* Fill in T# buffer resource description */
853 desc[0] = va;
854 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
855 S_008F04_STRIDE(vb->stride);
856
857 if (sctx->b.chip_class <= CIK && vb->stride)
858 /* Round up by rounding down and adding 1 */
859 desc[2] = (vb->buffer->width0 - offset -
860 sctx->vertex_elements->format_size[i]) /
861 vb->stride + 1;
862 else
863 desc[2] = vb->buffer->width0 - offset;
864
865 desc[3] = sctx->vertex_elements->rsrc_word3[i];
866
867 if (!bound[ve->vertex_buffer_index]) {
868 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
869 (struct r600_resource*)vb->buffer,
870 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
871 bound[ve->vertex_buffer_index] = true;
872 }
873 }
874
875 /* Don't flush the const cache. It would have a very negative effect
876 * on performance (confirmed by testing). New descriptors are always
877 * uploaded to a fresh new buffer, so I don't think flushing the const
878 * cache is needed. */
879 desc->pointer_dirty = true;
880 si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
881 sctx->vertex_buffers_dirty = false;
882 return true;
883 }
884
885
886 /* CONSTANT BUFFERS */
887
888 static unsigned
889 si_const_buffer_descriptors_idx(unsigned shader)
890 {
891 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
892 SI_SHADER_DESCS_CONST_BUFFERS;
893 }
894
895 static struct si_descriptors *
896 si_const_buffer_descriptors(struct si_context *sctx, unsigned shader)
897 {
898 return &sctx->descriptors[si_const_buffer_descriptors_idx(shader)];
899 }
900
901 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
902 const uint8_t *ptr, unsigned size, uint32_t *const_offset)
903 {
904 void *tmp;
905
906 u_upload_alloc(sctx->b.uploader, 0, size, 256, const_offset,
907 (struct pipe_resource**)rbuffer, &tmp);
908 if (*rbuffer)
909 util_memcpy_cpu_to_le32(tmp, ptr, size);
910 }
911
912 static void si_set_constant_buffer(struct si_context *sctx,
913 struct si_buffer_resources *buffers,
914 unsigned descriptors_idx,
915 uint slot, struct pipe_constant_buffer *input)
916 {
917 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
918 assert(slot < descs->num_elements);
919 pipe_resource_reference(&buffers->buffers[slot], NULL);
920
921 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
922 * with a NULL buffer). We need to use a dummy buffer instead. */
923 if (sctx->b.chip_class == CIK &&
924 (!input || (!input->buffer && !input->user_buffer)))
925 input = &sctx->null_const_buf;
926
927 if (input && (input->buffer || input->user_buffer)) {
928 struct pipe_resource *buffer = NULL;
929 uint64_t va;
930
931 /* Upload the user buffer if needed. */
932 if (input->user_buffer) {
933 unsigned buffer_offset;
934
935 si_upload_const_buffer(sctx,
936 (struct r600_resource**)&buffer, input->user_buffer,
937 input->buffer_size, &buffer_offset);
938 if (!buffer) {
939 /* Just unbind on failure. */
940 si_set_constant_buffer(sctx, buffers, descriptors_idx, slot, NULL);
941 return;
942 }
943 va = r600_resource(buffer)->gpu_address + buffer_offset;
944 } else {
945 pipe_resource_reference(&buffer, input->buffer);
946 va = r600_resource(buffer)->gpu_address + input->buffer_offset;
947 }
948
949 /* Set the descriptor. */
950 uint32_t *desc = descs->list + slot*4;
951 desc[0] = va;
952 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
953 S_008F04_STRIDE(0);
954 desc[2] = input->buffer_size;
955 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
956 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
957 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
958 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
959 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
960 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
961
962 buffers->buffers[slot] = buffer;
963 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
964 (struct r600_resource*)buffer,
965 buffers->shader_usage, buffers->priority);
966 buffers->enabled_mask |= 1u << slot;
967 } else {
968 /* Clear the descriptor. */
969 memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4);
970 buffers->enabled_mask &= ~(1u << slot);
971 }
972
973 descs->dirty_mask |= 1u << slot;
974 }
975
976 void si_set_rw_buffer(struct si_context *sctx,
977 uint slot, struct pipe_constant_buffer *input)
978 {
979 si_set_constant_buffer(sctx, &sctx->rw_buffers,
980 SI_DESCS_RW_BUFFERS, slot, input);
981 }
982
983 static void si_pipe_set_constant_buffer(struct pipe_context *ctx,
984 uint shader, uint slot,
985 struct pipe_constant_buffer *input)
986 {
987 struct si_context *sctx = (struct si_context *)ctx;
988
989 if (shader >= SI_NUM_SHADERS)
990 return;
991
992 si_set_constant_buffer(sctx, &sctx->const_buffers[shader],
993 si_const_buffer_descriptors_idx(shader),
994 slot, input);
995 }
996
997 /* SHADER BUFFERS */
998
999 static unsigned
1000 si_shader_buffer_descriptors_idx(unsigned shader)
1001 {
1002 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
1003 SI_SHADER_DESCS_SHADER_BUFFERS;
1004 }
1005
1006 static struct si_descriptors *
1007 si_shader_buffer_descriptors(struct si_context *sctx, unsigned shader)
1008 {
1009 return &sctx->descriptors[si_shader_buffer_descriptors_idx(shader)];
1010 }
1011
1012 static void si_set_shader_buffers(struct pipe_context *ctx, unsigned shader,
1013 unsigned start_slot, unsigned count,
1014 struct pipe_shader_buffer *sbuffers)
1015 {
1016 struct si_context *sctx = (struct si_context *)ctx;
1017 struct si_buffer_resources *buffers = &sctx->shader_buffers[shader];
1018 struct si_descriptors *descs = si_shader_buffer_descriptors(sctx, shader);
1019 unsigned i;
1020
1021 assert(start_slot + count <= SI_NUM_SHADER_BUFFERS);
1022
1023 for (i = 0; i < count; ++i) {
1024 struct pipe_shader_buffer *sbuffer = sbuffers ? &sbuffers[i] : NULL;
1025 struct r600_resource *buf;
1026 unsigned slot = start_slot + i;
1027 uint32_t *desc = descs->list + slot * 4;
1028 uint64_t va;
1029
1030 if (!sbuffer || !sbuffer->buffer) {
1031 pipe_resource_reference(&buffers->buffers[slot], NULL);
1032 memset(desc, 0, sizeof(uint32_t) * 4);
1033 buffers->enabled_mask &= ~(1u << slot);
1034 descs->dirty_mask |= 1u << slot;
1035 continue;
1036 }
1037
1038 buf = (struct r600_resource *)sbuffer->buffer;
1039 va = buf->gpu_address + sbuffer->buffer_offset;
1040
1041 desc[0] = va;
1042 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1043 S_008F04_STRIDE(0);
1044 desc[2] = sbuffer->buffer_size;
1045 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1046 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1047 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1048 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1049 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1050 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1051
1052 pipe_resource_reference(&buffers->buffers[slot], &buf->b.b);
1053 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buf,
1054 buffers->shader_usage, buffers->priority);
1055 buffers->enabled_mask |= 1u << slot;
1056 descs->dirty_mask |= 1u << slot;
1057 }
1058 }
1059
1060 /* RING BUFFERS */
1061
1062 void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
1063 struct pipe_resource *buffer,
1064 unsigned stride, unsigned num_records,
1065 bool add_tid, bool swizzle,
1066 unsigned element_size, unsigned index_stride, uint64_t offset)
1067 {
1068 struct si_context *sctx = (struct si_context *)ctx;
1069 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1070 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1071
1072 /* The stride field in the resource descriptor has 14 bits */
1073 assert(stride < (1 << 14));
1074
1075 assert(slot < descs->num_elements);
1076 pipe_resource_reference(&buffers->buffers[slot], NULL);
1077
1078 if (buffer) {
1079 uint64_t va;
1080
1081 va = r600_resource(buffer)->gpu_address + offset;
1082
1083 switch (element_size) {
1084 default:
1085 assert(!"Unsupported ring buffer element size");
1086 case 0:
1087 case 2:
1088 element_size = 0;
1089 break;
1090 case 4:
1091 element_size = 1;
1092 break;
1093 case 8:
1094 element_size = 2;
1095 break;
1096 case 16:
1097 element_size = 3;
1098 break;
1099 }
1100
1101 switch (index_stride) {
1102 default:
1103 assert(!"Unsupported ring buffer index stride");
1104 case 0:
1105 case 8:
1106 index_stride = 0;
1107 break;
1108 case 16:
1109 index_stride = 1;
1110 break;
1111 case 32:
1112 index_stride = 2;
1113 break;
1114 case 64:
1115 index_stride = 3;
1116 break;
1117 }
1118
1119 if (sctx->b.chip_class >= VI && stride)
1120 num_records *= stride;
1121
1122 /* Set the descriptor. */
1123 uint32_t *desc = descs->list + slot*4;
1124 desc[0] = va;
1125 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1126 S_008F04_STRIDE(stride) |
1127 S_008F04_SWIZZLE_ENABLE(swizzle);
1128 desc[2] = num_records;
1129 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1130 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1131 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1132 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1133 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1134 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1135 S_008F0C_ELEMENT_SIZE(element_size) |
1136 S_008F0C_INDEX_STRIDE(index_stride) |
1137 S_008F0C_ADD_TID_ENABLE(add_tid);
1138
1139 pipe_resource_reference(&buffers->buffers[slot], buffer);
1140 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1141 (struct r600_resource*)buffer,
1142 buffers->shader_usage, buffers->priority);
1143 buffers->enabled_mask |= 1u << slot;
1144 } else {
1145 /* Clear the descriptor. */
1146 memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4);
1147 buffers->enabled_mask &= ~(1u << slot);
1148 }
1149
1150 descs->dirty_mask |= 1u << slot;
1151 }
1152
1153 /* STREAMOUT BUFFERS */
1154
1155 static void si_set_streamout_targets(struct pipe_context *ctx,
1156 unsigned num_targets,
1157 struct pipe_stream_output_target **targets,
1158 const unsigned *offsets)
1159 {
1160 struct si_context *sctx = (struct si_context *)ctx;
1161 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1162 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1163 unsigned old_num_targets = sctx->b.streamout.num_targets;
1164 unsigned i, bufidx;
1165
1166 /* We are going to unbind the buffers. Mark which caches need to be flushed. */
1167 if (sctx->b.streamout.num_targets && sctx->b.streamout.begin_emitted) {
1168 /* Since streamout uses vector writes which go through TC L2
1169 * and most other clients can use TC L2 as well, we don't need
1170 * to flush it.
1171 *
1172 * The only case which requires flushing it is VGT DMA index
1173 * fetching, which is a rare case. Thus, flag the TC L2
1174 * dirtiness in the resource and handle it when index fetching
1175 * is used.
1176 */
1177 for (i = 0; i < sctx->b.streamout.num_targets; i++)
1178 if (sctx->b.streamout.targets[i])
1179 r600_resource(sctx->b.streamout.targets[i]->b.buffer)->TC_L2_dirty = true;
1180
1181 /* Invalidate the scalar cache in case a streamout buffer is
1182 * going to be used as a constant buffer.
1183 *
1184 * Invalidate TC L1, because streamout bypasses it (done by
1185 * setting GLC=1 in the store instruction), but it can contain
1186 * outdated data of streamout buffers.
1187 *
1188 * VS_PARTIAL_FLUSH is required if the buffers are going to be
1189 * used as an input immediately.
1190 */
1191 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
1192 SI_CONTEXT_INV_VMEM_L1 |
1193 SI_CONTEXT_VS_PARTIAL_FLUSH;
1194 }
1195
1196 /* All readers of the streamout targets need to be finished before we can
1197 * start writing to the targets.
1198 */
1199 if (num_targets)
1200 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
1201 SI_CONTEXT_CS_PARTIAL_FLUSH;
1202
1203 /* Streamout buffers must be bound in 2 places:
1204 * 1) in VGT by setting the VGT_STRMOUT registers
1205 * 2) as shader resources
1206 */
1207
1208 /* Set the VGT regs. */
1209 r600_set_streamout_targets(ctx, num_targets, targets, offsets);
1210
1211 /* Set the shader resources.*/
1212 for (i = 0; i < num_targets; i++) {
1213 bufidx = SI_VS_STREAMOUT_BUF0 + i;
1214
1215 if (targets[i]) {
1216 struct pipe_resource *buffer = targets[i]->buffer;
1217 uint64_t va = r600_resource(buffer)->gpu_address;
1218
1219 /* Set the descriptor.
1220 *
1221 * On VI, the format must be non-INVALID, otherwise
1222 * the buffer will be considered not bound and store
1223 * instructions will be no-ops.
1224 */
1225 uint32_t *desc = descs->list + bufidx*4;
1226 desc[0] = va;
1227 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1228 desc[2] = 0xffffffff;
1229 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1230 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1231 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1232 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1233 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1234
1235 /* Set the resource. */
1236 pipe_resource_reference(&buffers->buffers[bufidx],
1237 buffer);
1238 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1239 (struct r600_resource*)buffer,
1240 buffers->shader_usage, buffers->priority);
1241 buffers->enabled_mask |= 1u << bufidx;
1242 } else {
1243 /* Clear the descriptor and unset the resource. */
1244 memset(descs->list + bufidx*4, 0,
1245 sizeof(uint32_t) * 4);
1246 pipe_resource_reference(&buffers->buffers[bufidx],
1247 NULL);
1248 buffers->enabled_mask &= ~(1u << bufidx);
1249 }
1250 descs->dirty_mask |= 1u << bufidx;
1251 }
1252 for (; i < old_num_targets; i++) {
1253 bufidx = SI_VS_STREAMOUT_BUF0 + i;
1254 /* Clear the descriptor and unset the resource. */
1255 memset(descs->list + bufidx*4, 0, sizeof(uint32_t) * 4);
1256 pipe_resource_reference(&buffers->buffers[bufidx], NULL);
1257 buffers->enabled_mask &= ~(1u << bufidx);
1258 descs->dirty_mask |= 1u << bufidx;
1259 }
1260 }
1261
1262 static void si_desc_reset_buffer_offset(struct pipe_context *ctx,
1263 uint32_t *desc, uint64_t old_buf_va,
1264 struct pipe_resource *new_buf)
1265 {
1266 /* Retrieve the buffer offset from the descriptor. */
1267 uint64_t old_desc_va =
1268 desc[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc[1]) << 32);
1269
1270 assert(old_buf_va <= old_desc_va);
1271 uint64_t offset_within_buffer = old_desc_va - old_buf_va;
1272
1273 /* Update the descriptor. */
1274 uint64_t va = r600_resource(new_buf)->gpu_address + offset_within_buffer;
1275
1276 desc[0] = va;
1277 desc[1] = (desc[1] & C_008F04_BASE_ADDRESS_HI) |
1278 S_008F04_BASE_ADDRESS_HI(va >> 32);
1279 }
1280
1281 /* INTERNAL CONST BUFFERS */
1282
1283 static void si_set_polygon_stipple(struct pipe_context *ctx,
1284 const struct pipe_poly_stipple *state)
1285 {
1286 struct si_context *sctx = (struct si_context *)ctx;
1287 struct pipe_constant_buffer cb = {};
1288 unsigned stipple[32];
1289 int i;
1290
1291 for (i = 0; i < 32; i++)
1292 stipple[i] = util_bitreverse(state->stipple[i]);
1293
1294 cb.user_buffer = stipple;
1295 cb.buffer_size = sizeof(stipple);
1296
1297 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE, &cb);
1298 }
1299
1300 /* TEXTURE METADATA ENABLE/DISABLE */
1301
1302 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1303 * while the texture is bound, possibly by a different context. In that case,
1304 * call this function to update compressed_colortex_masks.
1305 */
1306 void si_update_compressed_colortex_masks(struct si_context *sctx)
1307 {
1308 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
1309 si_samplers_update_compressed_colortex_mask(&sctx->samplers[i]);
1310 si_images_update_compressed_colortex_mask(&sctx->images[i]);
1311 }
1312 }
1313
1314 /* BUFFER DISCARD/INVALIDATION */
1315
1316 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1317 static void si_reset_buffer_resources(struct si_context *sctx,
1318 struct si_buffer_resources *buffers,
1319 unsigned descriptors_idx,
1320 struct pipe_resource *buf,
1321 uint64_t old_va)
1322 {
1323 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
1324 unsigned mask = buffers->enabled_mask;
1325
1326 while (mask) {
1327 unsigned i = u_bit_scan(&mask);
1328 if (buffers->buffers[i] == buf) {
1329 si_desc_reset_buffer_offset(&sctx->b.b,
1330 descs->list + i*4,
1331 old_va, buf);
1332 descs->dirty_mask |= 1u << i;
1333
1334 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1335 (struct r600_resource *)buf,
1336 buffers->shader_usage,
1337 buffers->priority);
1338 }
1339 }
1340 }
1341
1342 /* Reallocate a buffer a update all resource bindings where the buffer is
1343 * bound.
1344 *
1345 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
1346 * idle by discarding its contents. Apps usually tell us when to do this using
1347 * map_buffer flags, for example.
1348 */
1349 static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
1350 {
1351 struct si_context *sctx = (struct si_context*)ctx;
1352 struct r600_resource *rbuffer = r600_resource(buf);
1353 unsigned i, shader, alignment = rbuffer->buf->alignment;
1354 uint64_t old_va = rbuffer->gpu_address;
1355 unsigned num_elems = sctx->vertex_elements ?
1356 sctx->vertex_elements->count : 0;
1357 struct si_sampler_view *view;
1358
1359 /* Reallocate the buffer in the same pipe_resource. */
1360 r600_init_resource(&sctx->screen->b, rbuffer, rbuffer->b.b.width0,
1361 alignment);
1362
1363 /* We changed the buffer, now we need to bind it where the old one
1364 * was bound. This consists of 2 things:
1365 * 1) Updating the resource descriptor and dirtying it.
1366 * 2) Adding a relocation to the CS, so that it's usable.
1367 */
1368
1369 /* Vertex buffers. */
1370 for (i = 0; i < num_elems; i++) {
1371 int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
1372
1373 if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
1374 continue;
1375 if (!sctx->vertex_buffer[vb].buffer)
1376 continue;
1377
1378 if (sctx->vertex_buffer[vb].buffer == buf) {
1379 sctx->vertex_buffers_dirty = true;
1380 break;
1381 }
1382 }
1383
1384 /* Streamout buffers. (other internal buffers can't be invalidated) */
1385 for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) {
1386 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1387 struct si_descriptors *descs =
1388 &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1389
1390 if (buffers->buffers[i] != buf)
1391 continue;
1392
1393 si_desc_reset_buffer_offset(ctx, descs->list + i*4,
1394 old_va, buf);
1395 descs->dirty_mask |= 1u << i;
1396
1397 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1398 rbuffer, buffers->shader_usage,
1399 buffers->priority);
1400
1401 /* Update the streamout state. */
1402 if (sctx->b.streamout.begin_emitted)
1403 r600_emit_streamout_end(&sctx->b);
1404 sctx->b.streamout.append_bitmask =
1405 sctx->b.streamout.enabled_mask;
1406 r600_streamout_buffers_dirty(&sctx->b);
1407 }
1408
1409 /* Constant and shader buffers. */
1410 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1411 si_reset_buffer_resources(sctx, &sctx->const_buffers[shader],
1412 si_const_buffer_descriptors_idx(shader),
1413 buf, old_va);
1414 si_reset_buffer_resources(sctx, &sctx->shader_buffers[shader],
1415 si_shader_buffer_descriptors_idx(shader),
1416 buf, old_va);
1417 }
1418
1419 /* Texture buffers - update virtual addresses in sampler view descriptors. */
1420 LIST_FOR_EACH_ENTRY(view, &sctx->b.texture_buffers, list) {
1421 if (view->base.texture == buf) {
1422 si_desc_reset_buffer_offset(ctx, &view->state[4], old_va, buf);
1423 }
1424 }
1425 /* Texture buffers - update bindings. */
1426 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1427 struct si_sampler_views *views = &sctx->samplers[shader].views;
1428 struct si_descriptors *descs =
1429 si_sampler_descriptors(sctx, shader);
1430 unsigned mask = views->enabled_mask;
1431
1432 while (mask) {
1433 unsigned i = u_bit_scan(&mask);
1434 if (views->views[i]->texture == buf) {
1435 si_desc_reset_buffer_offset(ctx,
1436 descs->list +
1437 i * 16 + 4,
1438 old_va, buf);
1439 descs->dirty_mask |= 1u << i;
1440
1441 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1442 rbuffer, RADEON_USAGE_READ,
1443 RADEON_PRIO_SAMPLER_BUFFER);
1444 }
1445 }
1446 }
1447
1448 /* Shader images */
1449 for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
1450 struct si_images_info *images = &sctx->images[shader];
1451 struct si_descriptors *descs =
1452 si_image_descriptors(sctx, shader);
1453 unsigned mask = images->enabled_mask;
1454
1455 while (mask) {
1456 unsigned i = u_bit_scan(&mask);
1457
1458 if (images->views[i].resource == buf) {
1459 if (images->views[i].access & PIPE_IMAGE_ACCESS_WRITE)
1460 si_mark_image_range_valid(&images->views[i]);
1461
1462 si_desc_reset_buffer_offset(
1463 ctx, descs->list + i * 8 + 4,
1464 old_va, buf);
1465 descs->dirty_mask |= 1u << i;
1466
1467 radeon_add_to_buffer_list(
1468 &sctx->b, &sctx->b.gfx, rbuffer,
1469 RADEON_USAGE_READWRITE,
1470 RADEON_PRIO_SAMPLER_BUFFER);
1471 }
1472 }
1473 }
1474 }
1475
1476 /* Update mutable image descriptor fields of all bound textures. */
1477 void si_update_all_texture_descriptors(struct si_context *sctx)
1478 {
1479 unsigned shader;
1480
1481 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1482 struct si_sampler_views *samplers = &sctx->samplers[shader].views;
1483 struct si_images_info *images = &sctx->images[shader];
1484 unsigned mask;
1485
1486 /* Images. */
1487 mask = images->enabled_mask;
1488 while (mask) {
1489 unsigned i = u_bit_scan(&mask);
1490 struct pipe_image_view *view = &images->views[i];
1491
1492 if (!view->resource ||
1493 view->resource->target == PIPE_BUFFER)
1494 continue;
1495
1496 si_set_shader_image(sctx, shader, i, view);
1497 }
1498
1499 /* Sampler views. */
1500 mask = samplers->enabled_mask;
1501 while (mask) {
1502 unsigned i = u_bit_scan(&mask);
1503 struct pipe_sampler_view *view = samplers->views[i];
1504
1505 if (!view ||
1506 !view->texture ||
1507 view->texture->target == PIPE_BUFFER)
1508 continue;
1509
1510 si_set_sampler_view(sctx, shader, i,
1511 samplers->views[i], true);
1512 }
1513 }
1514 }
1515
1516 /* SHADER USER DATA */
1517
1518 static void si_mark_shader_pointers_dirty(struct si_context *sctx,
1519 unsigned shader)
1520 {
1521 struct si_descriptors *descs =
1522 &sctx->descriptors[SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS];
1523
1524 for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs)
1525 descs->pointer_dirty = true;
1526
1527 if (shader == PIPE_SHADER_VERTEX)
1528 sctx->vertex_buffers.pointer_dirty = true;
1529
1530 si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
1531 }
1532
1533 static void si_shader_userdata_begin_new_cs(struct si_context *sctx)
1534 {
1535 int i;
1536
1537 for (i = 0; i < SI_NUM_SHADERS; i++) {
1538 si_mark_shader_pointers_dirty(sctx, i);
1539 }
1540 sctx->descriptors[SI_DESCS_RW_BUFFERS].pointer_dirty = true;
1541 }
1542
1543 /* Set a base register address for user data constants in the given shader.
1544 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1545 */
1546 static void si_set_user_data_base(struct si_context *sctx,
1547 unsigned shader, uint32_t new_base)
1548 {
1549 uint32_t *base = &sctx->shader_userdata.sh_base[shader];
1550
1551 if (*base != new_base) {
1552 *base = new_base;
1553
1554 if (new_base)
1555 si_mark_shader_pointers_dirty(sctx, shader);
1556 }
1557 }
1558
1559 /* This must be called when these shaders are changed from non-NULL to NULL
1560 * and vice versa:
1561 * - geometry shader
1562 * - tessellation control shader
1563 * - tessellation evaluation shader
1564 */
1565 void si_shader_change_notify(struct si_context *sctx)
1566 {
1567 /* VS can be bound as VS, ES, or LS. */
1568 if (sctx->tes_shader.cso)
1569 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1570 R_00B530_SPI_SHADER_USER_DATA_LS_0);
1571 else if (sctx->gs_shader.cso)
1572 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1573 R_00B330_SPI_SHADER_USER_DATA_ES_0);
1574 else
1575 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1576 R_00B130_SPI_SHADER_USER_DATA_VS_0);
1577
1578 /* TES can be bound as ES, VS, or not bound. */
1579 if (sctx->tes_shader.cso) {
1580 if (sctx->gs_shader.cso)
1581 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
1582 R_00B330_SPI_SHADER_USER_DATA_ES_0);
1583 else
1584 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
1585 R_00B130_SPI_SHADER_USER_DATA_VS_0);
1586 } else {
1587 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, 0);
1588 }
1589 }
1590
1591 static void si_emit_shader_pointer(struct si_context *sctx,
1592 struct si_descriptors *desc,
1593 unsigned sh_base, bool keep_dirty)
1594 {
1595 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1596 uint64_t va;
1597
1598 if (!desc->pointer_dirty || !desc->buffer)
1599 return;
1600
1601 va = desc->buffer->gpu_address +
1602 desc->buffer_offset;
1603
1604 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0));
1605 radeon_emit(cs, (sh_base + desc->shader_userdata_offset - SI_SH_REG_OFFSET) >> 2);
1606 radeon_emit(cs, va);
1607 radeon_emit(cs, va >> 32);
1608
1609 desc->pointer_dirty = keep_dirty;
1610 }
1611
1612 void si_emit_graphics_shader_userdata(struct si_context *sctx,
1613 struct r600_atom *atom)
1614 {
1615 unsigned shader;
1616 uint32_t *sh_base = sctx->shader_userdata.sh_base;
1617 struct si_descriptors *descs;
1618
1619 descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1620
1621 if (descs->pointer_dirty) {
1622 si_emit_shader_pointer(sctx, descs,
1623 R_00B030_SPI_SHADER_USER_DATA_PS_0, true);
1624 si_emit_shader_pointer(sctx, descs,
1625 R_00B130_SPI_SHADER_USER_DATA_VS_0, true);
1626 si_emit_shader_pointer(sctx, descs,
1627 R_00B230_SPI_SHADER_USER_DATA_GS_0, true);
1628 si_emit_shader_pointer(sctx, descs,
1629 R_00B330_SPI_SHADER_USER_DATA_ES_0, true);
1630 si_emit_shader_pointer(sctx, descs,
1631 R_00B430_SPI_SHADER_USER_DATA_HS_0, true);
1632 descs->pointer_dirty = false;
1633 }
1634
1635 descs = &sctx->descriptors[SI_DESCS_FIRST_SHADER];
1636
1637 for (shader = 0; shader < SI_NUM_GRAPHICS_SHADERS; shader++) {
1638 unsigned base = sh_base[shader];
1639 unsigned i;
1640
1641 if (!base)
1642 continue;
1643
1644 for (i = 0; i < SI_NUM_SHADER_DESCS; i++, descs++)
1645 si_emit_shader_pointer(sctx, descs, base, false);
1646 }
1647 si_emit_shader_pointer(sctx, &sctx->vertex_buffers, sh_base[PIPE_SHADER_VERTEX], false);
1648 }
1649
1650 void si_emit_compute_shader_userdata(struct si_context *sctx)
1651 {
1652 unsigned base = R_00B900_COMPUTE_USER_DATA_0;
1653 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_FIRST_COMPUTE];
1654
1655 for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs)
1656 si_emit_shader_pointer(sctx, descs, base, false);
1657 }
1658
1659 /* INIT/DEINIT/UPLOAD */
1660
1661 void si_init_all_descriptors(struct si_context *sctx)
1662 {
1663 int i;
1664 unsigned ce_offset = 0;
1665
1666 for (i = 0; i < SI_NUM_SHADERS; i++) {
1667 si_init_buffer_resources(&sctx->const_buffers[i],
1668 si_const_buffer_descriptors(sctx, i),
1669 SI_NUM_CONST_BUFFERS, SI_SGPR_CONST_BUFFERS,
1670 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER,
1671 &ce_offset);
1672 si_init_buffer_resources(&sctx->shader_buffers[i],
1673 si_shader_buffer_descriptors(sctx, i),
1674 SI_NUM_SHADER_BUFFERS, SI_SGPR_SHADER_BUFFERS,
1675 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RW_BUFFER,
1676 &ce_offset);
1677
1678 si_init_descriptors(si_sampler_descriptors(sctx, i),
1679 SI_SGPR_SAMPLERS, 16, SI_NUM_SAMPLERS,
1680 null_texture_descriptor, &ce_offset);
1681
1682 si_init_descriptors(si_image_descriptors(sctx, i),
1683 SI_SGPR_IMAGES, 8, SI_NUM_IMAGES,
1684 null_image_descriptor, &ce_offset);
1685 }
1686
1687 si_init_buffer_resources(&sctx->rw_buffers,
1688 &sctx->descriptors[SI_DESCS_RW_BUFFERS],
1689 SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS,
1690 RADEON_USAGE_READWRITE, RADEON_PRIO_RINGS_STREAMOUT,
1691 &ce_offset);
1692 si_init_descriptors(&sctx->vertex_buffers, SI_SGPR_VERTEX_BUFFERS,
1693 4, SI_NUM_VERTEX_BUFFERS, NULL, NULL);
1694
1695 assert(ce_offset <= 32768);
1696
1697 /* Set pipe_context functions. */
1698 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
1699 sctx->b.b.set_shader_images = si_set_shader_images;
1700 sctx->b.b.set_constant_buffer = si_pipe_set_constant_buffer;
1701 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
1702 sctx->b.b.set_shader_buffers = si_set_shader_buffers;
1703 sctx->b.b.set_sampler_views = si_set_sampler_views;
1704 sctx->b.b.set_stream_output_targets = si_set_streamout_targets;
1705 sctx->b.invalidate_buffer = si_invalidate_buffer;
1706
1707 /* Shader user data. */
1708 si_init_atom(sctx, &sctx->shader_userdata.atom, &sctx->atoms.s.shader_userdata,
1709 si_emit_graphics_shader_userdata);
1710
1711 /* Set default and immutable mappings. */
1712 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
1713 si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, R_00B430_SPI_SHADER_USER_DATA_HS_0);
1714 si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, R_00B230_SPI_SHADER_USER_DATA_GS_0);
1715 si_set_user_data_base(sctx, PIPE_SHADER_FRAGMENT, R_00B030_SPI_SHADER_USER_DATA_PS_0);
1716 }
1717
1718 bool si_upload_graphics_shader_descriptors(struct si_context *sctx)
1719 {
1720 int i;
1721
1722 for (i = 0; i < SI_DESCS_FIRST_COMPUTE; ++i) {
1723 if (!si_upload_descriptors(sctx, &sctx->descriptors[i],
1724 &sctx->shader_userdata.atom))
1725 return false;
1726 }
1727
1728 return si_upload_vertex_buffer_descriptors(sctx);
1729 }
1730
1731 bool si_upload_compute_shader_descriptors(struct si_context *sctx)
1732 {
1733 /* Does not update rw_buffers as that is not needed for compute shaders
1734 * and the input buffer is using the same SGPR's anyway.
1735 */
1736 unsigned i;
1737
1738 for (i = SI_DESCS_FIRST_COMPUTE; i < SI_NUM_DESCS; ++i) {
1739 if (!si_upload_descriptors(sctx, &sctx->descriptors[i], NULL))
1740 return false;
1741 }
1742
1743 return true;
1744 }
1745
1746 void si_release_all_descriptors(struct si_context *sctx)
1747 {
1748 int i;
1749
1750 for (i = 0; i < SI_NUM_SHADERS; i++) {
1751 si_release_buffer_resources(&sctx->const_buffers[i],
1752 si_const_buffer_descriptors(sctx, i));
1753 si_release_buffer_resources(&sctx->shader_buffers[i],
1754 si_shader_buffer_descriptors(sctx, i));
1755 si_release_sampler_views(&sctx->samplers[i].views);
1756 si_release_image_views(&sctx->images[i]);
1757 }
1758 si_release_buffer_resources(&sctx->rw_buffers,
1759 &sctx->descriptors[SI_DESCS_RW_BUFFERS]);
1760
1761 for (i = 0; i < SI_NUM_DESCS; ++i)
1762 si_release_descriptors(&sctx->descriptors[i]);
1763 si_release_descriptors(&sctx->vertex_buffers);
1764 }
1765
1766 void si_all_descriptors_begin_new_cs(struct si_context *sctx)
1767 {
1768 int i;
1769
1770 for (i = 0; i < SI_NUM_SHADERS; i++) {
1771 si_buffer_resources_begin_new_cs(sctx, &sctx->const_buffers[i]);
1772 si_buffer_resources_begin_new_cs(sctx, &sctx->shader_buffers[i]);
1773 si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i].views);
1774 si_image_views_begin_new_cs(sctx, &sctx->images[i]);
1775 }
1776 si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers);
1777 si_vertex_buffers_begin_new_cs(sctx);
1778
1779 for (i = 0; i < SI_NUM_DESCS; ++i)
1780 si_descriptors_begin_new_cs(sctx, &sctx->descriptors[i]);
1781
1782 si_shader_userdata_begin_new_cs(sctx);
1783 }