2 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 /* Resource binding slots and sampler states (each described with 8 or
26 * 4 dwords) are stored in lists in memory which is accessed by shaders
27 * using scalar load instructions.
29 * This file is responsible for managing such lists. It keeps a copy of all
30 * descriptors in CPU memory and re-uploads a whole list if some slots have
33 * This code is also reponsible for updating shader pointers to those lists.
35 * Note that CP DMA can't be used for updating the lists, because a GPU hang
36 * could leave the list in a mid-IB state and the next IB would get wrong
37 * descriptors and the whole context would be unusable at that point.
38 * (Note: The register shadowing can't be used due to the same reason)
40 * Also, uploading descriptors to newly allocated memory doesn't require
44 * Possible scenarios for one 16 dword image+sampler slot:
46 * | Image | w/ FMASK | Buffer | NULL
47 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
48 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
49 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
50 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
52 * FMASK implies MSAA, therefore no sampler state.
53 * Sampler states are never unbound except when FMASK is bound.
60 #include "util/hash_table.h"
61 #include "util/u_idalloc.h"
62 #include "util/u_format.h"
63 #include "util/u_memory.h"
64 #include "util/u_upload_mgr.h"
67 /* NULL image and buffer descriptor for textures (alpha = 1) and images
70 * For images, all fields must be zero except for the swizzle, which
71 * supports arbitrary combinations of 0s and 1s. The texture type must be
72 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
74 * For buffers, all fields must be zero. If they are not, the hw hangs.
76 * This is the only reason why the buffer descriptor must be in words [4:7].
78 static uint32_t null_texture_descriptor
[8] = {
82 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) |
83 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
84 /* the rest must contain zeros, which is also used by the buffer
88 static uint32_t null_image_descriptor
[8] = {
92 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
93 /* the rest must contain zeros, which is also used by the buffer
97 static uint64_t si_desc_extract_buffer_address(uint32_t *desc
)
99 uint64_t va
= desc
[0] |
100 ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
102 /* Sign-extend the 48-bit address. */
103 if (va
& (1ull << 47))
104 va
|= 0xffffull
<< 48;
108 static void si_init_descriptor_list(uint32_t *desc_list
,
109 unsigned element_dw_size
,
110 unsigned num_elements
,
111 const uint32_t *null_descriptor
)
115 /* Initialize the array to NULL descriptors if the element size is 8. */
116 if (null_descriptor
) {
117 assert(element_dw_size
% 8 == 0);
118 for (i
= 0; i
< num_elements
* element_dw_size
/ 8; i
++)
119 memcpy(desc_list
+ i
* 8, null_descriptor
, 8 * 4);
123 static void si_init_descriptors(struct si_descriptors
*desc
,
124 short shader_userdata_rel_index
,
125 unsigned element_dw_size
,
126 unsigned num_elements
)
128 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
129 desc
->element_dw_size
= element_dw_size
;
130 desc
->num_elements
= num_elements
;
131 desc
->shader_userdata_offset
= shader_userdata_rel_index
* 4;
132 desc
->slot_index_to_bind_directly
= -1;
135 static void si_release_descriptors(struct si_descriptors
*desc
)
137 r600_resource_reference(&desc
->buffer
, NULL
);
141 static bool si_upload_descriptors(struct si_context
*sctx
,
142 struct si_descriptors
*desc
)
144 unsigned slot_size
= desc
->element_dw_size
* 4;
145 unsigned first_slot_offset
= desc
->first_active_slot
* slot_size
;
146 unsigned upload_size
= desc
->num_active_slots
* slot_size
;
148 /* Skip the upload if no shader is using the descriptors. dirty_mask
149 * will stay dirty and the descriptors will be uploaded when there is
150 * a shader using them.
155 /* If there is just one active descriptor, bind it directly. */
156 if ((int)desc
->first_active_slot
== desc
->slot_index_to_bind_directly
&&
157 desc
->num_active_slots
== 1) {
158 uint32_t *descriptor
= &desc
->list
[desc
->slot_index_to_bind_directly
*
159 desc
->element_dw_size
];
161 /* The buffer is already in the buffer list. */
162 r600_resource_reference(&desc
->buffer
, NULL
);
163 desc
->gpu_list
= NULL
;
164 desc
->gpu_address
= si_desc_extract_buffer_address(descriptor
);
165 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
170 unsigned buffer_offset
;
171 u_upload_alloc(sctx
->b
.const_uploader
, first_slot_offset
, upload_size
,
172 si_optimal_tcc_alignment(sctx
, upload_size
),
173 &buffer_offset
, (struct pipe_resource
**)&desc
->buffer
,
176 desc
->gpu_address
= 0;
177 return false; /* skip the draw call */
180 util_memcpy_cpu_to_le32(ptr
, (char*)desc
->list
+ first_slot_offset
,
182 desc
->gpu_list
= ptr
- first_slot_offset
/ 4;
184 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, desc
->buffer
,
185 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
187 /* The shader pointer should point to slot 0. */
188 buffer_offset
-= first_slot_offset
;
189 desc
->gpu_address
= desc
->buffer
->gpu_address
+ buffer_offset
;
191 assert(desc
->buffer
->flags
& RADEON_FLAG_32BIT
);
192 assert((desc
->buffer
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
193 assert((desc
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
195 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
200 si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
205 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, desc
->buffer
,
206 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
211 static inline enum radeon_bo_priority
212 si_get_sampler_view_priority(struct r600_resource
*res
)
214 if (res
->b
.b
.target
== PIPE_BUFFER
)
215 return RADEON_PRIO_SAMPLER_BUFFER
;
217 if (res
->b
.b
.nr_samples
> 1)
218 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
220 return RADEON_PRIO_SAMPLER_TEXTURE
;
224 si_sampler_and_image_descriptors_idx(unsigned shader
)
226 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
227 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
;
230 static struct si_descriptors
*
231 si_sampler_and_image_descriptors(struct si_context
*sctx
, unsigned shader
)
233 return &sctx
->descriptors
[si_sampler_and_image_descriptors_idx(shader
)];
236 static void si_release_sampler_views(struct si_samplers
*samplers
)
240 for (i
= 0; i
< ARRAY_SIZE(samplers
->views
); i
++) {
241 pipe_sampler_view_reference(&samplers
->views
[i
], NULL
);
245 static void si_sampler_view_add_buffer(struct si_context
*sctx
,
246 struct pipe_resource
*resource
,
247 enum radeon_bo_usage usage
,
248 bool is_stencil_sampler
,
251 struct r600_resource
*rres
;
252 struct r600_texture
*rtex
;
253 enum radeon_bo_priority priority
;
258 if (resource
->target
!= PIPE_BUFFER
) {
259 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
261 if (tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil_sampler
))
262 resource
= &tex
->flushed_depth_texture
->resource
.b
.b
;
265 rres
= (struct r600_resource
*)resource
;
266 priority
= si_get_sampler_view_priority(rres
);
268 radeon_add_to_gfx_buffer_list_check_mem(sctx
, rres
, usage
, priority
,
271 if (resource
->target
== PIPE_BUFFER
)
274 /* Now add separate DCC or HTILE. */
275 rtex
= (struct r600_texture
*)resource
;
276 if (rtex
->dcc_separate_buffer
) {
277 radeon_add_to_gfx_buffer_list_check_mem(sctx
, rtex
->dcc_separate_buffer
,
278 usage
, RADEON_PRIO_DCC
, check_mem
);
282 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
,
283 struct si_samplers
*samplers
)
285 unsigned mask
= samplers
->enabled_mask
;
287 /* Add buffers to the CS. */
289 int i
= u_bit_scan(&mask
);
290 struct si_sampler_view
*sview
= (struct si_sampler_view
*)samplers
->views
[i
];
292 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
294 sview
->is_stencil_sampler
, false);
298 /* Set buffer descriptor fields that can be changed by reallocations. */
299 static void si_set_buf_desc_address(struct r600_resource
*buf
,
300 uint64_t offset
, uint32_t *state
)
302 uint64_t va
= buf
->gpu_address
+ offset
;
305 state
[1] &= C_008F04_BASE_ADDRESS_HI
;
306 state
[1] |= S_008F04_BASE_ADDRESS_HI(va
>> 32);
309 /* Set texture descriptor fields that can be changed by reallocations.
312 * \param base_level_info information of the level of BASE_ADDRESS
313 * \param base_level the level of BASE_ADDRESS
314 * \param first_level pipe_sampler_view.u.tex.first_level
315 * \param block_width util_format_get_blockwidth()
316 * \param is_stencil select between separate Z & Stencil
317 * \param state descriptor to update
319 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
320 struct r600_texture
*tex
,
321 const struct legacy_surf_level
*base_level_info
,
322 unsigned base_level
, unsigned first_level
,
323 unsigned block_width
, bool is_stencil
,
326 uint64_t va
, meta_va
= 0;
328 if (tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil
)) {
329 tex
= tex
->flushed_depth_texture
;
333 va
= tex
->resource
.gpu_address
;
335 if (sscreen
->info
.chip_class
>= GFX9
) {
336 /* Only stencil_offset needs to be added here. */
338 va
+= tex
->surface
.u
.gfx9
.stencil_offset
;
340 va
+= tex
->surface
.u
.gfx9
.surf_offset
;
342 va
+= base_level_info
->offset
;
346 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
347 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
349 /* Only macrotiled modes can set tile swizzle.
350 * GFX9 doesn't use (legacy) base_level_info.
352 if (sscreen
->info
.chip_class
>= GFX9
||
353 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
354 state
[0] |= tex
->surface
.tile_swizzle
;
356 if (sscreen
->info
.chip_class
>= VI
) {
357 state
[6] &= C_008F28_COMPRESSION_EN
;
360 if (vi_dcc_enabled(tex
, first_level
)) {
361 meta_va
= (!tex
->dcc_separate_buffer
? tex
->resource
.gpu_address
: 0) +
364 if (sscreen
->info
.chip_class
== VI
) {
365 meta_va
+= base_level_info
->dcc_offset
;
366 assert(base_level_info
->mode
== RADEON_SURF_MODE_2D
);
369 meta_va
|= (uint32_t)tex
->surface
.tile_swizzle
<< 8;
370 } else if (vi_tc_compat_htile_enabled(tex
, first_level
)) {
371 meta_va
= tex
->resource
.gpu_address
+ tex
->htile_offset
;
375 state
[6] |= S_008F28_COMPRESSION_EN(1);
376 state
[7] = meta_va
>> 8;
380 if (sscreen
->info
.chip_class
>= GFX9
) {
381 state
[3] &= C_008F1C_SW_MODE
;
382 state
[4] &= C_008F20_PITCH_GFX9
;
385 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
386 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.stencil
.epitch
);
388 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
389 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.surf
.epitch
);
392 state
[5] &= C_008F24_META_DATA_ADDRESS
&
393 C_008F24_META_PIPE_ALIGNED
&
394 C_008F24_META_RB_ALIGNED
;
396 struct gfx9_surf_meta_flags meta
;
399 meta
= tex
->surface
.u
.gfx9
.dcc
;
401 meta
= tex
->surface
.u
.gfx9
.htile
;
403 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
404 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
405 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
409 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
410 unsigned index
= si_tile_mode_index(tex
, base_level
, is_stencil
);
412 state
[3] &= C_008F1C_TILING_INDEX
;
413 state
[3] |= S_008F1C_TILING_INDEX(index
);
414 state
[4] &= C_008F20_PITCH_GFX6
;
415 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
419 static void si_set_sampler_state_desc(struct si_sampler_state
*sstate
,
420 struct si_sampler_view
*sview
,
421 struct r600_texture
*tex
,
424 if (sview
&& sview
->is_integer
)
425 memcpy(desc
, sstate
->integer_val
, 4*4);
426 else if (tex
&& tex
->upgraded_depth
&&
427 (!sview
|| !sview
->is_stencil_sampler
))
428 memcpy(desc
, sstate
->upgraded_depth_val
, 4*4);
430 memcpy(desc
, sstate
->val
, 4*4);
433 static void si_set_sampler_view_desc(struct si_context
*sctx
,
434 struct si_sampler_view
*sview
,
435 struct si_sampler_state
*sstate
,
438 struct pipe_sampler_view
*view
= &sview
->base
;
439 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
440 bool is_buffer
= rtex
->resource
.b
.b
.target
== PIPE_BUFFER
;
442 if (unlikely(!is_buffer
&& sview
->dcc_incompatible
)) {
443 if (vi_dcc_enabled(rtex
, view
->u
.tex
.first_level
))
444 if (!si_texture_disable_dcc(sctx
, rtex
))
445 si_decompress_dcc(sctx
, rtex
);
447 sview
->dcc_incompatible
= false;
450 assert(rtex
); /* views with texture == NULL aren't supported */
451 memcpy(desc
, sview
->state
, 8*4);
454 si_set_buf_desc_address(&rtex
->resource
,
455 sview
->base
.u
.buf
.offset
,
458 bool is_separate_stencil
= rtex
->db_compatible
&&
459 sview
->is_stencil_sampler
;
461 si_set_mutable_tex_desc_fields(sctx
->screen
, rtex
,
462 sview
->base_level_info
,
464 sview
->base
.u
.tex
.first_level
,
470 if (!is_buffer
&& rtex
->fmask
.size
) {
471 memcpy(desc
+ 8, sview
->fmask_state
, 8*4);
473 /* Disable FMASK and bind sampler state in [12:15]. */
474 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
477 si_set_sampler_state_desc(sstate
, sview
,
478 is_buffer
? NULL
: rtex
,
483 static bool color_needs_decompression(struct r600_texture
*rtex
)
485 return rtex
->fmask
.size
||
486 (rtex
->dirty_level_mask
&&
487 (rtex
->cmask
.size
|| rtex
->dcc_offset
));
490 static bool depth_needs_decompression(struct r600_texture
*rtex
)
492 /* If the depth/stencil texture is TC-compatible, no decompression
493 * will be done. The decompression function will only flush DB caches
494 * to make it coherent with shaders. That's necessary because the driver
495 * doesn't flush DB caches in any other case.
497 return rtex
->db_compatible
;
500 static void si_set_sampler_view(struct si_context
*sctx
,
502 unsigned slot
, struct pipe_sampler_view
*view
,
503 bool disallow_early_out
)
505 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
506 struct si_sampler_view
*rview
= (struct si_sampler_view
*)view
;
507 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
508 unsigned desc_slot
= si_get_sampler_slot(slot
);
509 uint32_t *desc
= descs
->list
+ desc_slot
* 16;
511 if (samplers
->views
[slot
] == view
&& !disallow_early_out
)
515 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
517 si_set_sampler_view_desc(sctx
, rview
,
518 samplers
->sampler_states
[slot
], desc
);
520 if (rtex
->resource
.b
.b
.target
== PIPE_BUFFER
) {
521 rtex
->resource
.bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
522 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
523 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
525 if (depth_needs_decompression(rtex
)) {
526 samplers
->needs_depth_decompress_mask
|= 1u << slot
;
528 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
530 if (color_needs_decompression(rtex
)) {
531 samplers
->needs_color_decompress_mask
|= 1u << slot
;
533 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
536 if (rtex
->dcc_offset
&&
537 p_atomic_read(&rtex
->framebuffers_bound
))
538 sctx
->need_check_render_feedback
= true;
541 pipe_sampler_view_reference(&samplers
->views
[slot
], view
);
542 samplers
->enabled_mask
|= 1u << slot
;
544 /* Since this can flush, it must be done after enabled_mask is
546 si_sampler_view_add_buffer(sctx
, view
->texture
,
548 rview
->is_stencil_sampler
, true);
550 pipe_sampler_view_reference(&samplers
->views
[slot
], NULL
);
551 memcpy(desc
, null_texture_descriptor
, 8*4);
552 /* Only clear the lower dwords of FMASK. */
553 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
554 /* Re-set the sampler state if we are transitioning from FMASK. */
555 if (samplers
->sampler_states
[slot
])
556 si_set_sampler_state_desc(samplers
->sampler_states
[slot
], NULL
, NULL
,
559 samplers
->enabled_mask
&= ~(1u << slot
);
560 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
561 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
564 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
567 static void si_update_shader_needs_decompress_mask(struct si_context
*sctx
,
570 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
571 unsigned shader_bit
= 1 << shader
;
573 if (samplers
->needs_depth_decompress_mask
||
574 samplers
->needs_color_decompress_mask
||
575 sctx
->images
[shader
].needs_color_decompress_mask
)
576 sctx
->shader_needs_decompress_mask
|= shader_bit
;
578 sctx
->shader_needs_decompress_mask
&= ~shader_bit
;
581 static void si_set_sampler_views(struct pipe_context
*ctx
,
582 enum pipe_shader_type shader
, unsigned start
,
584 struct pipe_sampler_view
**views
)
586 struct si_context
*sctx
= (struct si_context
*)ctx
;
589 if (!count
|| shader
>= SI_NUM_SHADERS
)
593 for (i
= 0; i
< count
; i
++)
594 si_set_sampler_view(sctx
, shader
, start
+ i
, views
[i
], false);
596 for (i
= 0; i
< count
; i
++)
597 si_set_sampler_view(sctx
, shader
, start
+ i
, NULL
, false);
600 si_update_shader_needs_decompress_mask(sctx
, shader
);
604 si_samplers_update_needs_color_decompress_mask(struct si_samplers
*samplers
)
606 unsigned mask
= samplers
->enabled_mask
;
609 int i
= u_bit_scan(&mask
);
610 struct pipe_resource
*res
= samplers
->views
[i
]->texture
;
612 if (res
&& res
->target
!= PIPE_BUFFER
) {
613 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
615 if (color_needs_decompression(rtex
)) {
616 samplers
->needs_color_decompress_mask
|= 1u << i
;
618 samplers
->needs_color_decompress_mask
&= ~(1u << i
);
627 si_release_image_views(struct si_images
*images
)
631 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
632 struct pipe_image_view
*view
= &images
->views
[i
];
634 pipe_resource_reference(&view
->resource
, NULL
);
639 si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images
*images
)
641 uint mask
= images
->enabled_mask
;
643 /* Add buffers to the CS. */
645 int i
= u_bit_scan(&mask
);
646 struct pipe_image_view
*view
= &images
->views
[i
];
648 assert(view
->resource
);
650 si_sampler_view_add_buffer(sctx
, view
->resource
,
651 RADEON_USAGE_READWRITE
, false, false);
656 si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
658 struct si_images
*images
= &ctx
->images
[shader
];
660 if (images
->enabled_mask
& (1u << slot
)) {
661 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
662 unsigned desc_slot
= si_get_image_slot(slot
);
664 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
665 images
->needs_color_decompress_mask
&= ~(1 << slot
);
667 memcpy(descs
->list
+ desc_slot
*8, null_image_descriptor
, 8*4);
668 images
->enabled_mask
&= ~(1u << slot
);
669 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
674 si_mark_image_range_valid(const struct pipe_image_view
*view
)
676 struct r600_resource
*res
= (struct r600_resource
*)view
->resource
;
678 assert(res
&& res
->b
.b
.target
== PIPE_BUFFER
);
680 util_range_add(&res
->valid_buffer_range
,
682 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
685 static void si_set_shader_image_desc(struct si_context
*ctx
,
686 const struct pipe_image_view
*view
,
687 bool skip_decompress
,
688 uint32_t *desc
, uint32_t *fmask_desc
)
690 struct si_screen
*screen
= ctx
->screen
;
691 struct r600_resource
*res
;
693 res
= (struct r600_resource
*)view
->resource
;
695 if (res
->b
.b
.target
== PIPE_BUFFER
) {
696 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
697 si_mark_image_range_valid(view
);
699 si_make_buffer_descriptor(screen
, res
,
702 view
->u
.buf
.size
, desc
);
703 si_set_buf_desc_address(res
, view
->u
.buf
.offset
, desc
+ 4);
705 static const unsigned char swizzle
[4] = { 0, 1, 2, 3 };
706 struct r600_texture
*tex
= (struct r600_texture
*)res
;
707 unsigned level
= view
->u
.tex
.level
;
708 unsigned width
, height
, depth
, hw_level
;
709 bool uses_dcc
= vi_dcc_enabled(tex
, level
);
710 unsigned access
= view
->access
;
712 /* Clear the write flag when writes can't occur.
713 * Note that DCC_DECOMPRESS for MSAA doesn't work in some cases,
714 * so we don't wanna trigger it.
717 (!fmask_desc
&& tex
->fmask
.size
!= 0)) {
718 assert(!"Z/S and MSAA image stores are not supported");
719 access
&= ~PIPE_IMAGE_ACCESS_WRITE
;
722 assert(!tex
->is_depth
);
723 assert(fmask_desc
|| tex
->fmask
.size
== 0);
725 if (uses_dcc
&& !skip_decompress
&&
726 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
||
727 !vi_dcc_formats_compatible(res
->b
.b
.format
, view
->format
))) {
728 /* If DCC can't be disabled, at least decompress it.
729 * The decompression is relatively cheap if the surface
730 * has been decompressed already.
732 if (!si_texture_disable_dcc(ctx
, tex
))
733 si_decompress_dcc(ctx
, tex
);
736 if (ctx
->chip_class
>= GFX9
) {
737 /* Always set the base address. The swizzle modes don't
738 * allow setting mipmap level offsets as the base.
740 width
= res
->b
.b
.width0
;
741 height
= res
->b
.b
.height0
;
742 depth
= res
->b
.b
.depth0
;
745 /* Always force the base level to the selected level.
747 * This is required for 3D textures, where otherwise
748 * selecting a single slice for non-layered bindings
749 * fails. It doesn't hurt the other targets.
751 width
= u_minify(res
->b
.b
.width0
, level
);
752 height
= u_minify(res
->b
.b
.height0
, level
);
753 depth
= u_minify(res
->b
.b
.depth0
, level
);
757 si_make_texture_descriptor(screen
, tex
,
758 false, res
->b
.b
.target
,
759 view
->format
, swizzle
,
761 view
->u
.tex
.first_layer
,
762 view
->u
.tex
.last_layer
,
763 width
, height
, depth
,
765 si_set_mutable_tex_desc_fields(screen
, tex
,
766 &tex
->surface
.u
.legacy
.level
[level
],
768 util_format_get_blockwidth(view
->format
),
773 static void si_set_shader_image(struct si_context
*ctx
,
775 unsigned slot
, const struct pipe_image_view
*view
,
776 bool skip_decompress
)
778 struct si_images
*images
= &ctx
->images
[shader
];
779 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
780 struct r600_resource
*res
;
781 unsigned desc_slot
= si_get_image_slot(slot
);
782 uint32_t *desc
= descs
->list
+ desc_slot
* 8;
784 if (!view
|| !view
->resource
) {
785 si_disable_shader_image(ctx
, shader
, slot
);
789 res
= (struct r600_resource
*)view
->resource
;
791 if (&images
->views
[slot
] != view
)
792 util_copy_image_view(&images
->views
[slot
], view
);
794 si_set_shader_image_desc(ctx
, view
, skip_decompress
, desc
, NULL
);
796 if (res
->b
.b
.target
== PIPE_BUFFER
) {
797 images
->needs_color_decompress_mask
&= ~(1 << slot
);
798 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
800 struct r600_texture
*tex
= (struct r600_texture
*)res
;
801 unsigned level
= view
->u
.tex
.level
;
803 if (color_needs_decompression(tex
)) {
804 images
->needs_color_decompress_mask
|= 1 << slot
;
806 images
->needs_color_decompress_mask
&= ~(1 << slot
);
809 if (vi_dcc_enabled(tex
, level
) &&
810 p_atomic_read(&tex
->framebuffers_bound
))
811 ctx
->need_check_render_feedback
= true;
814 images
->enabled_mask
|= 1u << slot
;
815 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
817 /* Since this can flush, it must be done after enabled_mask is updated. */
818 si_sampler_view_add_buffer(ctx
, &res
->b
.b
,
819 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
) ?
820 RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
,
825 si_set_shader_images(struct pipe_context
*pipe
,
826 enum pipe_shader_type shader
,
827 unsigned start_slot
, unsigned count
,
828 const struct pipe_image_view
*views
)
830 struct si_context
*ctx
= (struct si_context
*)pipe
;
833 assert(shader
< SI_NUM_SHADERS
);
838 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
841 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
842 si_set_shader_image(ctx
, shader
, slot
, &views
[i
], false);
844 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
845 si_set_shader_image(ctx
, shader
, slot
, NULL
, false);
848 si_update_shader_needs_decompress_mask(ctx
, shader
);
852 si_images_update_needs_color_decompress_mask(struct si_images
*images
)
854 unsigned mask
= images
->enabled_mask
;
857 int i
= u_bit_scan(&mask
);
858 struct pipe_resource
*res
= images
->views
[i
].resource
;
860 if (res
&& res
->target
!= PIPE_BUFFER
) {
861 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
863 if (color_needs_decompression(rtex
)) {
864 images
->needs_color_decompress_mask
|= 1 << i
;
866 images
->needs_color_decompress_mask
&= ~(1 << i
);
872 void si_update_ps_colorbuf0_slot(struct si_context
*sctx
)
874 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
875 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
876 unsigned slot
= SI_PS_IMAGE_COLORBUF0
;
877 struct pipe_surface
*surf
= NULL
;
879 /* si_texture_disable_dcc can get us here again. */
880 if (sctx
->blitter
->running
)
883 /* See whether FBFETCH is used and color buffer 0 is set. */
884 if (sctx
->ps_shader
.cso
&&
885 sctx
->ps_shader
.cso
->info
.opcode_count
[TGSI_OPCODE_FBFETCH
] &&
886 sctx
->framebuffer
.state
.nr_cbufs
&&
887 sctx
->framebuffer
.state
.cbufs
[0])
888 surf
= sctx
->framebuffer
.state
.cbufs
[0];
890 /* Return if FBFETCH transitions from disabled to disabled. */
891 if (!buffers
->buffers
[slot
] && !surf
)
894 sctx
->ps_uses_fbfetch
= surf
!= NULL
;
895 si_update_ps_iter_samples(sctx
);
898 struct r600_texture
*tex
= (struct r600_texture
*)surf
->texture
;
899 struct pipe_image_view view
;
902 assert(!tex
->is_depth
);
904 /* Disable DCC, because the texture is used as both a sampler
907 si_texture_disable_dcc(sctx
, tex
);
909 if (tex
->resource
.b
.b
.nr_samples
<= 1 && tex
->cmask_buffer
) {
911 assert(tex
->cmask_buffer
!= &tex
->resource
);
912 si_eliminate_fast_color_clear(sctx
, tex
);
913 si_texture_discard_cmask(sctx
->screen
, tex
);
916 view
.resource
= surf
->texture
;
917 view
.format
= surf
->format
;
918 view
.access
= PIPE_IMAGE_ACCESS_READ
;
919 view
.u
.tex
.first_layer
= surf
->u
.tex
.first_layer
;
920 view
.u
.tex
.last_layer
= surf
->u
.tex
.last_layer
;
921 view
.u
.tex
.level
= surf
->u
.tex
.level
;
923 /* Set the descriptor. */
924 uint32_t *desc
= descs
->list
+ slot
*4;
925 memset(desc
, 0, 16 * 4);
926 si_set_shader_image_desc(sctx
, &view
, true, desc
, desc
+ 8);
928 pipe_resource_reference(&buffers
->buffers
[slot
], &tex
->resource
.b
.b
);
929 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
930 &tex
->resource
, RADEON_USAGE_READ
,
931 RADEON_PRIO_SHADER_RW_IMAGE
);
932 buffers
->enabled_mask
|= 1u << slot
;
934 /* Clear the descriptor. */
935 memset(descs
->list
+ slot
*4, 0, 8*4);
936 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
937 buffers
->enabled_mask
&= ~(1u << slot
);
940 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
945 static void si_bind_sampler_states(struct pipe_context
*ctx
,
946 enum pipe_shader_type shader
,
947 unsigned start
, unsigned count
, void **states
)
949 struct si_context
*sctx
= (struct si_context
*)ctx
;
950 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
951 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, shader
);
952 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
955 if (!count
|| shader
>= SI_NUM_SHADERS
)
958 for (i
= 0; i
< count
; i
++) {
959 unsigned slot
= start
+ i
;
960 unsigned desc_slot
= si_get_sampler_slot(slot
);
963 sstates
[i
] == samplers
->sampler_states
[slot
])
967 assert(sstates
[i
]->magic
== SI_SAMPLER_STATE_MAGIC
);
969 samplers
->sampler_states
[slot
] = sstates
[i
];
971 /* If FMASK is bound, don't overwrite it.
972 * The sampler state will be set after FMASK is unbound.
974 struct si_sampler_view
*sview
=
975 (struct si_sampler_view
*)samplers
->views
[slot
];
977 struct r600_texture
*tex
= NULL
;
979 if (sview
&& sview
->base
.texture
&&
980 sview
->base
.texture
->target
!= PIPE_BUFFER
)
981 tex
= (struct r600_texture
*)sview
->base
.texture
;
983 if (tex
&& tex
->fmask
.size
)
986 si_set_sampler_state_desc(sstates
[i
], sview
, tex
,
987 desc
->list
+ desc_slot
* 16 + 12);
989 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
993 /* BUFFER RESOURCES */
995 static void si_init_buffer_resources(struct si_buffer_resources
*buffers
,
996 struct si_descriptors
*descs
,
997 unsigned num_buffers
,
998 short shader_userdata_rel_index
,
999 enum radeon_bo_usage shader_usage
,
1000 enum radeon_bo_usage shader_usage_constbuf
,
1001 enum radeon_bo_priority priority
,
1002 enum radeon_bo_priority priority_constbuf
)
1004 buffers
->shader_usage
= shader_usage
;
1005 buffers
->shader_usage_constbuf
= shader_usage_constbuf
;
1006 buffers
->priority
= priority
;
1007 buffers
->priority_constbuf
= priority_constbuf
;
1008 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
1010 si_init_descriptors(descs
, shader_userdata_rel_index
, 4, num_buffers
);
1013 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
1014 struct si_descriptors
*descs
)
1018 for (i
= 0; i
< descs
->num_elements
; i
++) {
1019 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
1022 FREE(buffers
->buffers
);
1025 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
1026 struct si_buffer_resources
*buffers
)
1028 unsigned mask
= buffers
->enabled_mask
;
1030 /* Add buffers to the CS. */
1032 int i
= u_bit_scan(&mask
);
1034 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1035 r600_resource(buffers
->buffers
[i
]),
1036 i
< SI_NUM_SHADER_BUFFERS
? buffers
->shader_usage
:
1037 buffers
->shader_usage_constbuf
,
1038 i
< SI_NUM_SHADER_BUFFERS
? buffers
->priority
:
1039 buffers
->priority_constbuf
);
1043 static void si_get_buffer_from_descriptors(struct si_buffer_resources
*buffers
,
1044 struct si_descriptors
*descs
,
1045 unsigned idx
, struct pipe_resource
**buf
,
1046 unsigned *offset
, unsigned *size
)
1048 pipe_resource_reference(buf
, buffers
->buffers
[idx
]);
1050 struct r600_resource
*res
= r600_resource(*buf
);
1051 const uint32_t *desc
= descs
->list
+ idx
* 4;
1056 assert(G_008F04_STRIDE(desc
[1]) == 0);
1057 va
= ((uint64_t)desc
[1] << 32) | desc
[0];
1059 assert(va
>= res
->gpu_address
&& va
+ *size
<= res
->gpu_address
+ res
->bo_size
);
1060 *offset
= va
- res
->gpu_address
;
1064 /* VERTEX BUFFERS */
1066 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
1068 int count
= sctx
->vertex_elements
? sctx
->vertex_elements
->count
: 0;
1071 for (i
= 0; i
< count
; i
++) {
1072 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1074 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1076 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1079 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1080 (struct r600_resource
*)sctx
->vertex_buffer
[vb
].buffer
.resource
,
1081 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1084 if (!sctx
->vb_descriptors_buffer
)
1086 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1087 sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1088 RADEON_PRIO_DESCRIPTORS
);
1091 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
1093 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
1095 unsigned desc_list_byte_size
;
1096 unsigned first_vb_use_mask
;
1099 if (!sctx
->vertex_buffers_dirty
|| !velems
)
1102 count
= velems
->count
;
1107 desc_list_byte_size
= velems
->desc_list_byte_size
;
1108 first_vb_use_mask
= velems
->first_vb_use_mask
;
1110 /* Vertex buffer descriptors are the only ones which are uploaded
1111 * directly through a staging buffer and don't go through
1112 * the fine-grained upload path.
1114 u_upload_alloc(sctx
->b
.const_uploader
, 0,
1115 desc_list_byte_size
,
1116 si_optimal_tcc_alignment(sctx
, desc_list_byte_size
),
1117 &sctx
->vb_descriptors_offset
,
1118 (struct pipe_resource
**)&sctx
->vb_descriptors_buffer
,
1120 if (!sctx
->vb_descriptors_buffer
) {
1121 sctx
->vb_descriptors_offset
= 0;
1122 sctx
->vb_descriptors_gpu_list
= NULL
;
1126 sctx
->vb_descriptors_gpu_list
= ptr
;
1127 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1128 sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1129 RADEON_PRIO_DESCRIPTORS
);
1131 assert(count
<= SI_MAX_ATTRIBS
);
1133 for (i
= 0; i
< count
; i
++) {
1134 struct pipe_vertex_buffer
*vb
;
1135 struct r600_resource
*rbuffer
;
1136 unsigned vbo_index
= velems
->vertex_buffer_index
[i
];
1137 uint32_t *desc
= &ptr
[i
*4];
1139 vb
= &sctx
->vertex_buffer
[vbo_index
];
1140 rbuffer
= (struct r600_resource
*)vb
->buffer
.resource
;
1142 memset(desc
, 0, 16);
1146 int64_t offset
= (int64_t)((int)vb
->buffer_offset
) +
1147 velems
->src_offset
[i
];
1148 uint64_t va
= rbuffer
->gpu_address
+ offset
;
1150 int64_t num_records
= (int64_t)rbuffer
->b
.b
.width0
- offset
;
1151 if (sctx
->chip_class
!= VI
&& vb
->stride
) {
1152 /* Round up by rounding down and adding 1 */
1153 num_records
= (num_records
- velems
->format_size
[i
]) /
1156 assert(num_records
>= 0 && num_records
<= UINT_MAX
);
1159 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1160 S_008F04_STRIDE(vb
->stride
);
1161 desc
[2] = num_records
;
1162 desc
[3] = velems
->rsrc_word3
[i
];
1164 if (first_vb_use_mask
& (1 << i
)) {
1165 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1166 (struct r600_resource
*)vb
->buffer
.resource
,
1167 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1171 /* Don't flush the const cache. It would have a very negative effect
1172 * on performance (confirmed by testing). New descriptors are always
1173 * uploaded to a fresh new buffer, so I don't think flushing the const
1174 * cache is needed. */
1175 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1176 sctx
->vertex_buffers_dirty
= false;
1177 sctx
->vertex_buffer_pointer_dirty
= true;
1178 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VBO_DESCRIPTORS
;
1183 /* CONSTANT BUFFERS */
1186 si_const_and_shader_buffer_descriptors_idx(unsigned shader
)
1188 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
1189 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
;
1192 static struct si_descriptors
*
1193 si_const_and_shader_buffer_descriptors(struct si_context
*sctx
, unsigned shader
)
1195 return &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(shader
)];
1198 void si_upload_const_buffer(struct si_context
*sctx
, struct r600_resource
**rbuffer
,
1199 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
)
1203 u_upload_alloc(sctx
->b
.const_uploader
, 0, size
,
1204 si_optimal_tcc_alignment(sctx
, size
),
1206 (struct pipe_resource
**)rbuffer
, &tmp
);
1208 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
1211 static void si_set_constant_buffer(struct si_context
*sctx
,
1212 struct si_buffer_resources
*buffers
,
1213 unsigned descriptors_idx
,
1214 uint slot
, const struct pipe_constant_buffer
*input
)
1216 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1217 assert(slot
< descs
->num_elements
);
1218 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1220 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1221 * with a NULL buffer). We need to use a dummy buffer instead. */
1222 if (sctx
->chip_class
== CIK
&&
1223 (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
1224 input
= &sctx
->null_const_buf
;
1226 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1227 struct pipe_resource
*buffer
= NULL
;
1230 /* Upload the user buffer if needed. */
1231 if (input
->user_buffer
) {
1232 unsigned buffer_offset
;
1234 si_upload_const_buffer(sctx
,
1235 (struct r600_resource
**)&buffer
, input
->user_buffer
,
1236 input
->buffer_size
, &buffer_offset
);
1238 /* Just unbind on failure. */
1239 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1242 va
= r600_resource(buffer
)->gpu_address
+ buffer_offset
;
1244 pipe_resource_reference(&buffer
, input
->buffer
);
1245 va
= r600_resource(buffer
)->gpu_address
+ input
->buffer_offset
;
1246 /* Only track usage for non-user buffers. */
1247 r600_resource(buffer
)->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
1250 /* Set the descriptor. */
1251 uint32_t *desc
= descs
->list
+ slot
*4;
1253 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1255 desc
[2] = input
->buffer_size
;
1256 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1257 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1258 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1259 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1260 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1261 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1263 buffers
->buffers
[slot
] = buffer
;
1264 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1265 (struct r600_resource
*)buffer
,
1266 buffers
->shader_usage_constbuf
,
1267 buffers
->priority_constbuf
, true);
1268 buffers
->enabled_mask
|= 1u << slot
;
1270 /* Clear the descriptor. */
1271 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1272 buffers
->enabled_mask
&= ~(1u << slot
);
1275 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1278 void si_set_rw_buffer(struct si_context
*sctx
,
1279 uint slot
, const struct pipe_constant_buffer
*input
)
1281 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
,
1282 SI_DESCS_RW_BUFFERS
, slot
, input
);
1285 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
,
1286 enum pipe_shader_type shader
, uint slot
,
1287 const struct pipe_constant_buffer
*input
)
1289 struct si_context
*sctx
= (struct si_context
*)ctx
;
1291 if (shader
>= SI_NUM_SHADERS
)
1294 if (slot
== 0 && input
&& input
->buffer
&&
1295 !(r600_resource(input
->buffer
)->flags
& RADEON_FLAG_32BIT
)) {
1296 assert(!"constant buffer 0 must have a 32-bit VM address, use const_uploader");
1300 slot
= si_get_constbuf_slot(slot
);
1301 si_set_constant_buffer(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1302 si_const_and_shader_buffer_descriptors_idx(shader
),
1306 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
1307 uint slot
, struct pipe_constant_buffer
*cbuf
)
1309 cbuf
->user_buffer
= NULL
;
1310 si_get_buffer_from_descriptors(
1311 &sctx
->const_and_shader_buffers
[shader
],
1312 si_const_and_shader_buffer_descriptors(sctx
, shader
),
1313 si_get_constbuf_slot(slot
),
1314 &cbuf
->buffer
, &cbuf
->buffer_offset
, &cbuf
->buffer_size
);
1317 /* SHADER BUFFERS */
1319 static void si_set_shader_buffers(struct pipe_context
*ctx
,
1320 enum pipe_shader_type shader
,
1321 unsigned start_slot
, unsigned count
,
1322 const struct pipe_shader_buffer
*sbuffers
)
1324 struct si_context
*sctx
= (struct si_context
*)ctx
;
1325 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1326 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1329 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1331 for (i
= 0; i
< count
; ++i
) {
1332 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1333 struct r600_resource
*buf
;
1334 unsigned slot
= si_get_shaderbuf_slot(start_slot
+ i
);
1335 uint32_t *desc
= descs
->list
+ slot
* 4;
1338 if (!sbuffer
|| !sbuffer
->buffer
) {
1339 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1340 memset(desc
, 0, sizeof(uint32_t) * 4);
1341 buffers
->enabled_mask
&= ~(1u << slot
);
1342 sctx
->descriptors_dirty
|=
1343 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1347 buf
= (struct r600_resource
*)sbuffer
->buffer
;
1348 va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1351 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1353 desc
[2] = sbuffer
->buffer_size
;
1354 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1355 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1356 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1357 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1358 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1359 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1361 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1362 radeon_add_to_gfx_buffer_list_check_mem(sctx
, buf
,
1363 buffers
->shader_usage
,
1364 buffers
->priority
, true);
1365 buf
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1367 buffers
->enabled_mask
|= 1u << slot
;
1368 sctx
->descriptors_dirty
|=
1369 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1371 util_range_add(&buf
->valid_buffer_range
, sbuffer
->buffer_offset
,
1372 sbuffer
->buffer_offset
+ sbuffer
->buffer_size
);
1376 void si_get_shader_buffers(struct si_context
*sctx
,
1377 enum pipe_shader_type shader
,
1378 uint start_slot
, uint count
,
1379 struct pipe_shader_buffer
*sbuf
)
1381 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1382 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1384 for (unsigned i
= 0; i
< count
; ++i
) {
1385 si_get_buffer_from_descriptors(
1387 si_get_shaderbuf_slot(start_slot
+ i
),
1388 &sbuf
[i
].buffer
, &sbuf
[i
].buffer_offset
,
1389 &sbuf
[i
].buffer_size
);
1395 void si_set_ring_buffer(struct si_context
*sctx
, uint slot
,
1396 struct pipe_resource
*buffer
,
1397 unsigned stride
, unsigned num_records
,
1398 bool add_tid
, bool swizzle
,
1399 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1401 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1402 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1404 /* The stride field in the resource descriptor has 14 bits */
1405 assert(stride
< (1 << 14));
1407 assert(slot
< descs
->num_elements
);
1408 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1413 va
= r600_resource(buffer
)->gpu_address
+ offset
;
1415 switch (element_size
) {
1417 assert(!"Unsupported ring buffer element size");
1433 switch (index_stride
) {
1435 assert(!"Unsupported ring buffer index stride");
1451 if (sctx
->chip_class
>= VI
&& stride
)
1452 num_records
*= stride
;
1454 /* Set the descriptor. */
1455 uint32_t *desc
= descs
->list
+ slot
*4;
1457 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1458 S_008F04_STRIDE(stride
) |
1459 S_008F04_SWIZZLE_ENABLE(swizzle
);
1460 desc
[2] = num_records
;
1461 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1462 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1463 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1464 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1465 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1466 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1467 S_008F0C_INDEX_STRIDE(index_stride
) |
1468 S_008F0C_ADD_TID_ENABLE(add_tid
);
1470 if (sctx
->chip_class
>= GFX9
)
1471 assert(!swizzle
|| element_size
== 1); /* always 4 bytes on GFX9 */
1473 desc
[3] |= S_008F0C_ELEMENT_SIZE(element_size
);
1475 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1476 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1477 (struct r600_resource
*)buffer
,
1478 buffers
->shader_usage
, buffers
->priority
);
1479 buffers
->enabled_mask
|= 1u << slot
;
1481 /* Clear the descriptor. */
1482 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1483 buffers
->enabled_mask
&= ~(1u << slot
);
1486 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1489 static void si_desc_reset_buffer_offset(uint32_t *desc
, uint64_t old_buf_va
,
1490 struct pipe_resource
*new_buf
)
1492 /* Retrieve the buffer offset from the descriptor. */
1493 uint64_t old_desc_va
= si_desc_extract_buffer_address(desc
);
1495 assert(old_buf_va
<= old_desc_va
);
1496 uint64_t offset_within_buffer
= old_desc_va
- old_buf_va
;
1498 /* Update the descriptor. */
1499 si_set_buf_desc_address(r600_resource(new_buf
), offset_within_buffer
,
1503 /* INTERNAL CONST BUFFERS */
1505 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
1506 const struct pipe_poly_stipple
*state
)
1508 struct si_context
*sctx
= (struct si_context
*)ctx
;
1509 struct pipe_constant_buffer cb
= {};
1510 unsigned stipple
[32];
1513 for (i
= 0; i
< 32; i
++)
1514 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1516 cb
.user_buffer
= stipple
;
1517 cb
.buffer_size
= sizeof(stipple
);
1519 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1522 /* TEXTURE METADATA ENABLE/DISABLE */
1525 si_resident_handles_update_needs_color_decompress(struct si_context
*sctx
)
1527 util_dynarray_clear(&sctx
->resident_tex_needs_color_decompress
);
1528 util_dynarray_clear(&sctx
->resident_img_needs_color_decompress
);
1530 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1531 struct si_texture_handle
*, tex_handle
) {
1532 struct pipe_resource
*res
= (*tex_handle
)->view
->texture
;
1533 struct r600_texture
*rtex
;
1535 if (!res
|| res
->target
== PIPE_BUFFER
)
1538 rtex
= (struct r600_texture
*)res
;
1539 if (!color_needs_decompression(rtex
))
1542 util_dynarray_append(&sctx
->resident_tex_needs_color_decompress
,
1543 struct si_texture_handle
*, *tex_handle
);
1546 util_dynarray_foreach(&sctx
->resident_img_handles
,
1547 struct si_image_handle
*, img_handle
) {
1548 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1549 struct pipe_resource
*res
= view
->resource
;
1550 struct r600_texture
*rtex
;
1552 if (!res
|| res
->target
== PIPE_BUFFER
)
1555 rtex
= (struct r600_texture
*)res
;
1556 if (!color_needs_decompression(rtex
))
1559 util_dynarray_append(&sctx
->resident_img_needs_color_decompress
,
1560 struct si_image_handle
*, *img_handle
);
1564 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1565 * while the texture is bound, possibly by a different context. In that case,
1566 * call this function to update needs_*_decompress_masks.
1568 void si_update_needs_color_decompress_masks(struct si_context
*sctx
)
1570 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1571 si_samplers_update_needs_color_decompress_mask(&sctx
->samplers
[i
]);
1572 si_images_update_needs_color_decompress_mask(&sctx
->images
[i
]);
1573 si_update_shader_needs_decompress_mask(sctx
, i
);
1576 si_resident_handles_update_needs_color_decompress(sctx
);
1579 /* BUFFER DISCARD/INVALIDATION */
1581 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1582 static void si_reset_buffer_resources(struct si_context
*sctx
,
1583 struct si_buffer_resources
*buffers
,
1584 unsigned descriptors_idx
,
1586 struct pipe_resource
*buf
,
1588 enum radeon_bo_usage usage
,
1589 enum radeon_bo_priority priority
)
1591 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1592 unsigned mask
= buffers
->enabled_mask
& slot_mask
;
1595 unsigned i
= u_bit_scan(&mask
);
1596 if (buffers
->buffers
[i
] == buf
) {
1597 si_desc_reset_buffer_offset(descs
->list
+ i
*4,
1599 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1601 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1602 (struct r600_resource
*)buf
,
1603 usage
, priority
, true);
1608 /* Update all resource bindings where the buffer is bound, including
1609 * all resource descriptors. This is invalidate_buffer without
1610 * the invalidation. */
1611 void si_rebind_buffer(struct si_context
*sctx
, struct pipe_resource
*buf
,
1614 struct r600_resource
*rbuffer
= r600_resource(buf
);
1616 unsigned num_elems
= sctx
->vertex_elements
?
1617 sctx
->vertex_elements
->count
: 0;
1619 /* We changed the buffer, now we need to bind it where the old one
1620 * was bound. This consists of 2 things:
1621 * 1) Updating the resource descriptor and dirtying it.
1622 * 2) Adding a relocation to the CS, so that it's usable.
1625 /* Vertex buffers. */
1626 if (rbuffer
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
1627 for (i
= 0; i
< num_elems
; i
++) {
1628 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1630 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1632 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1635 if (sctx
->vertex_buffer
[vb
].buffer
.resource
== buf
) {
1636 sctx
->vertex_buffers_dirty
= true;
1642 /* Streamout buffers. (other internal buffers can't be invalidated) */
1643 if (rbuffer
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
1644 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1645 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1646 struct si_descriptors
*descs
=
1647 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1649 if (buffers
->buffers
[i
] != buf
)
1652 si_desc_reset_buffer_offset(descs
->list
+ i
*4,
1654 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1656 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1657 rbuffer
, buffers
->shader_usage
,
1658 RADEON_PRIO_SHADER_RW_BUFFER
,
1661 /* Update the streamout state. */
1662 if (sctx
->streamout
.begin_emitted
)
1663 si_emit_streamout_end(sctx
);
1664 sctx
->streamout
.append_bitmask
=
1665 sctx
->streamout
.enabled_mask
;
1666 si_streamout_buffers_dirty(sctx
);
1670 /* Constant and shader buffers. */
1671 if (rbuffer
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1672 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1673 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1674 si_const_and_shader_buffer_descriptors_idx(shader
),
1675 u_bit_consecutive(SI_NUM_SHADER_BUFFERS
, SI_NUM_CONST_BUFFERS
),
1677 sctx
->const_and_shader_buffers
[shader
].shader_usage_constbuf
,
1678 sctx
->const_and_shader_buffers
[shader
].priority_constbuf
);
1681 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
1682 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1683 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1684 si_const_and_shader_buffer_descriptors_idx(shader
),
1685 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
),
1687 sctx
->const_and_shader_buffers
[shader
].shader_usage
,
1688 sctx
->const_and_shader_buffers
[shader
].priority
);
1691 if (rbuffer
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
1692 /* Texture buffers - update bindings. */
1693 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1694 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1695 struct si_descriptors
*descs
=
1696 si_sampler_and_image_descriptors(sctx
, shader
);
1697 unsigned mask
= samplers
->enabled_mask
;
1700 unsigned i
= u_bit_scan(&mask
);
1701 if (samplers
->views
[i
]->texture
== buf
) {
1702 unsigned desc_slot
= si_get_sampler_slot(i
);
1704 si_desc_reset_buffer_offset(descs
->list
+
1707 sctx
->descriptors_dirty
|=
1708 1u << si_sampler_and_image_descriptors_idx(shader
);
1710 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1711 rbuffer
, RADEON_USAGE_READ
,
1712 RADEON_PRIO_SAMPLER_BUFFER
,
1720 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
1721 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1722 struct si_images
*images
= &sctx
->images
[shader
];
1723 struct si_descriptors
*descs
=
1724 si_sampler_and_image_descriptors(sctx
, shader
);
1725 unsigned mask
= images
->enabled_mask
;
1728 unsigned i
= u_bit_scan(&mask
);
1730 if (images
->views
[i
].resource
== buf
) {
1731 unsigned desc_slot
= si_get_image_slot(i
);
1733 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1734 si_mark_image_range_valid(&images
->views
[i
]);
1736 si_desc_reset_buffer_offset(
1737 descs
->list
+ desc_slot
* 8 + 4,
1739 sctx
->descriptors_dirty
|=
1740 1u << si_sampler_and_image_descriptors_idx(shader
);
1742 radeon_add_to_gfx_buffer_list_check_mem(
1744 RADEON_USAGE_READWRITE
,
1745 RADEON_PRIO_SAMPLER_BUFFER
, true);
1751 /* Bindless texture handles */
1752 if (rbuffer
->texture_handle_allocated
) {
1753 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1755 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1756 struct si_texture_handle
*, tex_handle
) {
1757 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
1758 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1760 if (view
->texture
== buf
) {
1761 si_set_buf_desc_address(rbuffer
,
1764 desc_slot
* 16 + 4);
1766 (*tex_handle
)->desc_dirty
= true;
1767 sctx
->bindless_descriptors_dirty
= true;
1769 radeon_add_to_gfx_buffer_list_check_mem(
1772 RADEON_PRIO_SAMPLER_BUFFER
, true);
1777 /* Bindless image handles */
1778 if (rbuffer
->image_handle_allocated
) {
1779 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1781 util_dynarray_foreach(&sctx
->resident_img_handles
,
1782 struct si_image_handle
*, img_handle
) {
1783 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1784 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1786 if (view
->resource
== buf
) {
1787 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
1788 si_mark_image_range_valid(view
);
1790 si_set_buf_desc_address(rbuffer
,
1793 desc_slot
* 16 + 4);
1795 (*img_handle
)->desc_dirty
= true;
1796 sctx
->bindless_descriptors_dirty
= true;
1798 radeon_add_to_gfx_buffer_list_check_mem(
1800 RADEON_USAGE_READWRITE
,
1801 RADEON_PRIO_SAMPLER_BUFFER
, true);
1807 static void si_upload_bindless_descriptor(struct si_context
*sctx
,
1809 unsigned num_dwords
)
1811 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1812 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
1813 unsigned desc_slot_offset
= desc_slot
* 16;
1817 data
= desc
->list
+ desc_slot_offset
;
1818 va
= desc
->gpu_address
+ desc_slot_offset
* 4;
1820 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + num_dwords
, 0));
1821 radeon_emit(cs
, S_370_DST_SEL(V_370_TC_L2
) |
1822 S_370_WR_CONFIRM(1) |
1823 S_370_ENGINE_SEL(V_370_ME
));
1824 radeon_emit(cs
, va
);
1825 radeon_emit(cs
, va
>> 32);
1826 radeon_emit_array(cs
, data
, num_dwords
);
1829 static void si_upload_bindless_descriptors(struct si_context
*sctx
)
1831 if (!sctx
->bindless_descriptors_dirty
)
1834 /* Wait for graphics/compute to be idle before updating the resident
1835 * descriptors directly in memory, in case the GPU is using them.
1837 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
1838 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1839 si_emit_cache_flush(sctx
);
1841 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1842 struct si_texture_handle
*, tex_handle
) {
1843 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1845 if (!(*tex_handle
)->desc_dirty
)
1848 si_upload_bindless_descriptor(sctx
, desc_slot
, 16);
1849 (*tex_handle
)->desc_dirty
= false;
1852 util_dynarray_foreach(&sctx
->resident_img_handles
,
1853 struct si_image_handle
*, img_handle
) {
1854 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1856 if (!(*img_handle
)->desc_dirty
)
1859 si_upload_bindless_descriptor(sctx
, desc_slot
, 8);
1860 (*img_handle
)->desc_dirty
= false;
1863 /* Invalidate L1 because it doesn't know that L2 changed. */
1864 sctx
->flags
|= SI_CONTEXT_INV_SMEM_L1
;
1865 si_emit_cache_flush(sctx
);
1867 sctx
->bindless_descriptors_dirty
= false;
1870 /* Update mutable image descriptor fields of all resident textures. */
1871 static void si_update_bindless_texture_descriptor(struct si_context
*sctx
,
1872 struct si_texture_handle
*tex_handle
)
1874 struct si_sampler_view
*sview
= (struct si_sampler_view
*)tex_handle
->view
;
1875 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1876 unsigned desc_slot_offset
= tex_handle
->desc_slot
* 16;
1877 uint32_t desc_list
[16];
1879 if (sview
->base
.texture
->target
== PIPE_BUFFER
)
1882 memcpy(desc_list
, desc
->list
+ desc_slot_offset
, sizeof(desc_list
));
1883 si_set_sampler_view_desc(sctx
, sview
, &tex_handle
->sstate
,
1884 desc
->list
+ desc_slot_offset
);
1886 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1887 sizeof(desc_list
))) {
1888 tex_handle
->desc_dirty
= true;
1889 sctx
->bindless_descriptors_dirty
= true;
1893 static void si_update_bindless_image_descriptor(struct si_context
*sctx
,
1894 struct si_image_handle
*img_handle
)
1896 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1897 unsigned desc_slot_offset
= img_handle
->desc_slot
* 16;
1898 struct pipe_image_view
*view
= &img_handle
->view
;
1899 uint32_t desc_list
[8];
1901 if (view
->resource
->target
== PIPE_BUFFER
)
1904 memcpy(desc_list
, desc
->list
+ desc_slot_offset
,
1906 si_set_shader_image_desc(sctx
, view
, true,
1907 desc
->list
+ desc_slot_offset
, NULL
);
1909 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1910 sizeof(desc_list
))) {
1911 img_handle
->desc_dirty
= true;
1912 sctx
->bindless_descriptors_dirty
= true;
1916 static void si_update_all_resident_texture_descriptors(struct si_context
*sctx
)
1918 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1919 struct si_texture_handle
*, tex_handle
) {
1920 si_update_bindless_texture_descriptor(sctx
, *tex_handle
);
1923 util_dynarray_foreach(&sctx
->resident_img_handles
,
1924 struct si_image_handle
*, img_handle
) {
1925 si_update_bindless_image_descriptor(sctx
, *img_handle
);
1928 si_upload_bindless_descriptors(sctx
);
1931 /* Update mutable image descriptor fields of all bound textures. */
1932 void si_update_all_texture_descriptors(struct si_context
*sctx
)
1936 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1937 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1938 struct si_images
*images
= &sctx
->images
[shader
];
1942 mask
= images
->enabled_mask
;
1944 unsigned i
= u_bit_scan(&mask
);
1945 struct pipe_image_view
*view
= &images
->views
[i
];
1947 if (!view
->resource
||
1948 view
->resource
->target
== PIPE_BUFFER
)
1951 si_set_shader_image(sctx
, shader
, i
, view
, true);
1954 /* Sampler views. */
1955 mask
= samplers
->enabled_mask
;
1957 unsigned i
= u_bit_scan(&mask
);
1958 struct pipe_sampler_view
*view
= samplers
->views
[i
];
1962 view
->texture
->target
== PIPE_BUFFER
)
1965 si_set_sampler_view(sctx
, shader
, i
,
1966 samplers
->views
[i
], true);
1969 si_update_shader_needs_decompress_mask(sctx
, shader
);
1972 si_update_all_resident_texture_descriptors(sctx
);
1973 si_update_ps_colorbuf0_slot(sctx
);
1976 /* SHADER USER DATA */
1978 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
,
1981 sctx
->shader_pointers_dirty
|=
1982 u_bit_consecutive(SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
,
1983 SI_NUM_SHADER_DESCS
);
1985 if (shader
== PIPE_SHADER_VERTEX
)
1986 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
1988 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1991 static void si_shader_pointers_begin_new_cs(struct si_context
*sctx
)
1993 sctx
->shader_pointers_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
1994 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
1995 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1996 sctx
->graphics_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
1997 sctx
->compute_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
2000 /* Set a base register address for user data constants in the given shader.
2001 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
2003 static void si_set_user_data_base(struct si_context
*sctx
,
2004 unsigned shader
, uint32_t new_base
)
2006 uint32_t *base
= &sctx
->shader_pointers
.sh_base
[shader
];
2008 if (*base
!= new_base
) {
2012 si_mark_shader_pointers_dirty(sctx
, shader
);
2014 if (shader
== PIPE_SHADER_VERTEX
)
2015 sctx
->last_vs_state
= ~0;
2020 /* This must be called when these shaders are changed from non-NULL to NULL
2023 * - tessellation control shader
2024 * - tessellation evaluation shader
2026 void si_shader_change_notify(struct si_context
*sctx
)
2028 /* VS can be bound as VS, ES, or LS. */
2029 if (sctx
->tes_shader
.cso
) {
2030 if (sctx
->chip_class
>= GFX9
) {
2031 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2032 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2034 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2035 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2037 } else if (sctx
->gs_shader
.cso
) {
2038 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2039 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2041 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2042 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2045 /* TES can be bound as ES, VS, or not bound. */
2046 if (sctx
->tes_shader
.cso
) {
2047 if (sctx
->gs_shader
.cso
)
2048 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2049 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2051 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2052 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2054 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
2058 static void si_emit_shader_pointer_head(struct radeon_winsys_cs
*cs
,
2060 unsigned pointer_count
)
2062 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* (HAVE_32BIT_POINTERS
? 1 : 2), 0));
2063 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
2066 static void si_emit_shader_pointer_body(struct si_screen
*sscreen
,
2067 struct radeon_winsys_cs
*cs
,
2070 radeon_emit(cs
, va
);
2072 if (HAVE_32BIT_POINTERS
)
2073 assert(va
== 0 || (va
>> 32) == sscreen
->info
.address32_hi
);
2075 radeon_emit(cs
, va
>> 32);
2078 static void si_emit_shader_pointer(struct si_context
*sctx
,
2079 struct si_descriptors
*desc
,
2082 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
2083 unsigned sh_offset
= sh_base
+ desc
->shader_userdata_offset
;
2085 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2086 si_emit_shader_pointer_body(sctx
->screen
, cs
, desc
->gpu_address
);
2089 static void si_emit_consecutive_shader_pointers(struct si_context
*sctx
,
2090 unsigned pointer_mask
,
2096 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
2097 unsigned mask
= sctx
->shader_pointers_dirty
& pointer_mask
;
2101 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
2103 struct si_descriptors
*descs
= &sctx
->descriptors
[start
];
2104 unsigned sh_offset
= sh_base
+ descs
->shader_userdata_offset
;
2106 si_emit_shader_pointer_head(cs
, sh_offset
, count
);
2107 for (int i
= 0; i
< count
; i
++)
2108 si_emit_shader_pointer_body(sctx
->screen
, cs
,
2109 descs
[i
].gpu_address
);
2113 static void si_emit_disjoint_shader_pointers(struct si_context
*sctx
,
2114 unsigned pointer_mask
,
2120 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
2121 unsigned mask
= sctx
->shader_pointers_dirty
& pointer_mask
;
2124 struct si_descriptors
*descs
= &sctx
->descriptors
[u_bit_scan(&mask
)];
2125 unsigned sh_offset
= sh_base
+ descs
->shader_userdata_offset
;
2127 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2128 si_emit_shader_pointer_body(sctx
->screen
, cs
, descs
->gpu_address
);
2132 static void si_emit_global_shader_pointers(struct si_context
*sctx
,
2133 struct si_descriptors
*descs
)
2135 if (sctx
->chip_class
== GFX9
) {
2136 /* Broadcast it to all shader stages. */
2137 si_emit_shader_pointer(sctx
, descs
,
2138 R_00B530_SPI_SHADER_USER_DATA_COMMON_0
);
2142 si_emit_shader_pointer(sctx
, descs
,
2143 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2144 si_emit_shader_pointer(sctx
, descs
,
2145 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2146 si_emit_shader_pointer(sctx
, descs
,
2147 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2148 si_emit_shader_pointer(sctx
, descs
,
2149 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2150 si_emit_shader_pointer(sctx
, descs
,
2151 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2152 si_emit_shader_pointer(sctx
, descs
,
2153 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2156 void si_emit_graphics_shader_pointers(struct si_context
*sctx
,
2157 struct r600_atom
*atom
)
2159 uint32_t *sh_base
= sctx
->shader_pointers
.sh_base
;
2161 if (sctx
->shader_pointers_dirty
& (1 << SI_DESCS_RW_BUFFERS
)) {
2162 si_emit_global_shader_pointers(sctx
,
2163 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2166 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(VERTEX
),
2167 sh_base
[PIPE_SHADER_VERTEX
]);
2168 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_EVAL
),
2169 sh_base
[PIPE_SHADER_TESS_EVAL
]);
2170 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(FRAGMENT
),
2171 sh_base
[PIPE_SHADER_FRAGMENT
]);
2172 if (HAVE_32BIT_POINTERS
|| sctx
->chip_class
<= VI
) {
2173 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_CTRL
),
2174 sh_base
[PIPE_SHADER_TESS_CTRL
]);
2175 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(GEOMETRY
),
2176 sh_base
[PIPE_SHADER_GEOMETRY
]);
2178 si_emit_disjoint_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_CTRL
),
2179 sh_base
[PIPE_SHADER_TESS_CTRL
]);
2180 si_emit_disjoint_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(GEOMETRY
),
2181 sh_base
[PIPE_SHADER_GEOMETRY
]);
2184 sctx
->shader_pointers_dirty
&=
2185 ~u_bit_consecutive(SI_DESCS_RW_BUFFERS
, SI_DESCS_FIRST_COMPUTE
);
2187 if (sctx
->vertex_buffer_pointer_dirty
) {
2188 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
2190 /* Find the location of the VB descriptor pointer. */
2191 /* TODO: In the future, the pointer will be packed in unused
2192 * bits of the first 2 VB descriptors. */
2193 unsigned sh_dw_offset
= SI_VS_NUM_USER_SGPR
;
2194 if (sctx
->chip_class
>= GFX9
) {
2195 if (sctx
->tes_shader
.cso
)
2196 sh_dw_offset
= GFX9_TCS_NUM_USER_SGPR
;
2197 else if (sctx
->gs_shader
.cso
)
2198 sh_dw_offset
= GFX9_VSGS_NUM_USER_SGPR
;
2201 unsigned sh_offset
= sh_base
[PIPE_SHADER_VERTEX
] + sh_dw_offset
* 4;
2202 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2203 si_emit_shader_pointer_body(sctx
->screen
, cs
,
2204 sctx
->vb_descriptors_buffer
->gpu_address
+
2205 sctx
->vb_descriptors_offset
);
2206 sctx
->vertex_buffer_pointer_dirty
= false;
2209 if (sctx
->graphics_bindless_pointer_dirty
) {
2210 si_emit_global_shader_pointers(sctx
,
2211 &sctx
->bindless_descriptors
);
2212 sctx
->graphics_bindless_pointer_dirty
= false;
2216 void si_emit_compute_shader_pointers(struct si_context
*sctx
)
2218 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
2220 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(COMPUTE
),
2221 R_00B900_COMPUTE_USER_DATA_0
);
2222 sctx
->shader_pointers_dirty
&= ~SI_DESCS_SHADER_MASK(COMPUTE
);
2224 if (sctx
->compute_bindless_pointer_dirty
) {
2225 si_emit_shader_pointer(sctx
, &sctx
->bindless_descriptors
, base
);
2226 sctx
->compute_bindless_pointer_dirty
= false;
2232 static void si_init_bindless_descriptors(struct si_context
*sctx
,
2233 struct si_descriptors
*desc
,
2234 short shader_userdata_rel_index
,
2235 unsigned num_elements
)
2237 MAYBE_UNUSED
unsigned desc_slot
;
2239 si_init_descriptors(desc
, shader_userdata_rel_index
, 16, num_elements
);
2240 sctx
->bindless_descriptors
.num_active_slots
= num_elements
;
2242 /* The first bindless descriptor is stored at slot 1, because 0 is not
2243 * considered to be a valid handle.
2245 sctx
->num_bindless_descriptors
= 1;
2247 /* Track which bindless slots are used (or not). */
2248 util_idalloc_init(&sctx
->bindless_used_slots
);
2249 util_idalloc_resize(&sctx
->bindless_used_slots
, num_elements
);
2251 /* Reserve slot 0 because it's an invalid handle for bindless. */
2252 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2253 assert(desc_slot
== 0);
2256 static void si_release_bindless_descriptors(struct si_context
*sctx
)
2258 si_release_descriptors(&sctx
->bindless_descriptors
);
2259 util_idalloc_fini(&sctx
->bindless_used_slots
);
2262 static unsigned si_get_first_free_bindless_slot(struct si_context
*sctx
)
2264 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2267 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2268 if (desc_slot
>= desc
->num_elements
) {
2269 /* The array of bindless descriptors is full, resize it. */
2270 unsigned slot_size
= desc
->element_dw_size
* 4;
2271 unsigned new_num_elements
= desc
->num_elements
* 2;
2273 desc
->list
= REALLOC(desc
->list
, desc
->num_elements
* slot_size
,
2274 new_num_elements
* slot_size
);
2275 desc
->num_elements
= new_num_elements
;
2276 desc
->num_active_slots
= new_num_elements
;
2284 si_create_bindless_descriptor(struct si_context
*sctx
, uint32_t *desc_list
,
2287 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2288 unsigned desc_slot
, desc_slot_offset
;
2290 /* Find a free slot. */
2291 desc_slot
= si_get_first_free_bindless_slot(sctx
);
2293 /* For simplicity, sampler and image bindless descriptors use fixed
2294 * 16-dword slots for now. Image descriptors only need 8-dword but this
2295 * doesn't really matter because no real apps use image handles.
2297 desc_slot_offset
= desc_slot
* 16;
2299 /* Copy the descriptor into the array. */
2300 memcpy(desc
->list
+ desc_slot_offset
, desc_list
, size
);
2302 /* Re-upload the whole array of bindless descriptors into a new buffer.
2304 if (!si_upload_descriptors(sctx
, desc
))
2307 /* Make sure to re-emit the shader pointers for all stages. */
2308 sctx
->graphics_bindless_pointer_dirty
= true;
2309 sctx
->compute_bindless_pointer_dirty
= true;
2314 static void si_update_bindless_buffer_descriptor(struct si_context
*sctx
,
2316 struct pipe_resource
*resource
,
2320 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2321 struct r600_resource
*buf
= r600_resource(resource
);
2322 unsigned desc_slot_offset
= desc_slot
* 16;
2323 uint32_t *desc_list
= desc
->list
+ desc_slot_offset
+ 4;
2324 uint64_t old_desc_va
;
2326 assert(resource
->target
== PIPE_BUFFER
);
2328 /* Retrieve the old buffer addr from the descriptor. */
2329 old_desc_va
= si_desc_extract_buffer_address(desc_list
);
2331 if (old_desc_va
!= buf
->gpu_address
+ offset
) {
2332 /* The buffer has been invalidated when the handle wasn't
2333 * resident, update the descriptor and the dirty flag.
2335 si_set_buf_desc_address(buf
, offset
, &desc_list
[0]);
2341 static uint64_t si_create_texture_handle(struct pipe_context
*ctx
,
2342 struct pipe_sampler_view
*view
,
2343 const struct pipe_sampler_state
*state
)
2345 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
2346 struct si_context
*sctx
= (struct si_context
*)ctx
;
2347 struct si_texture_handle
*tex_handle
;
2348 struct si_sampler_state
*sstate
;
2349 uint32_t desc_list
[16];
2352 tex_handle
= CALLOC_STRUCT(si_texture_handle
);
2356 memset(desc_list
, 0, sizeof(desc_list
));
2357 si_init_descriptor_list(&desc_list
[0], 16, 1, null_texture_descriptor
);
2359 sstate
= ctx
->create_sampler_state(ctx
, state
);
2365 si_set_sampler_view_desc(sctx
, sview
, sstate
, &desc_list
[0]);
2366 memcpy(&tex_handle
->sstate
, sstate
, sizeof(*sstate
));
2367 ctx
->delete_sampler_state(ctx
, sstate
);
2369 tex_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2371 if (!tex_handle
->desc_slot
) {
2376 handle
= tex_handle
->desc_slot
;
2378 if (!_mesa_hash_table_insert(sctx
->tex_handles
,
2379 (void *)(uintptr_t)handle
,
2385 pipe_sampler_view_reference(&tex_handle
->view
, view
);
2387 r600_resource(sview
->base
.texture
)->texture_handle_allocated
= true;
2392 static void si_delete_texture_handle(struct pipe_context
*ctx
, uint64_t handle
)
2394 struct si_context
*sctx
= (struct si_context
*)ctx
;
2395 struct si_texture_handle
*tex_handle
;
2396 struct hash_entry
*entry
;
2398 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2399 (void *)(uintptr_t)handle
);
2403 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2405 /* Allow this descriptor slot to be re-used. */
2406 util_idalloc_free(&sctx
->bindless_used_slots
, tex_handle
->desc_slot
);
2408 pipe_sampler_view_reference(&tex_handle
->view
, NULL
);
2409 _mesa_hash_table_remove(sctx
->tex_handles
, entry
);
2413 static void si_make_texture_handle_resident(struct pipe_context
*ctx
,
2414 uint64_t handle
, bool resident
)
2416 struct si_context
*sctx
= (struct si_context
*)ctx
;
2417 struct si_texture_handle
*tex_handle
;
2418 struct si_sampler_view
*sview
;
2419 struct hash_entry
*entry
;
2421 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2422 (void *)(uintptr_t)handle
);
2426 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2427 sview
= (struct si_sampler_view
*)tex_handle
->view
;
2430 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2431 struct r600_texture
*rtex
=
2432 (struct r600_texture
*)sview
->base
.texture
;
2434 if (depth_needs_decompression(rtex
)) {
2435 util_dynarray_append(
2436 &sctx
->resident_tex_needs_depth_decompress
,
2437 struct si_texture_handle
*,
2441 if (color_needs_decompression(rtex
)) {
2442 util_dynarray_append(
2443 &sctx
->resident_tex_needs_color_decompress
,
2444 struct si_texture_handle
*,
2448 if (rtex
->dcc_offset
&&
2449 p_atomic_read(&rtex
->framebuffers_bound
))
2450 sctx
->need_check_render_feedback
= true;
2452 si_update_bindless_texture_descriptor(sctx
, tex_handle
);
2454 si_update_bindless_buffer_descriptor(sctx
,
2455 tex_handle
->desc_slot
,
2456 sview
->base
.texture
,
2457 sview
->base
.u
.buf
.offset
,
2458 &tex_handle
->desc_dirty
);
2461 /* Re-upload the descriptor if it has been updated while it
2464 if (tex_handle
->desc_dirty
)
2465 sctx
->bindless_descriptors_dirty
= true;
2467 /* Add the texture handle to the per-context list. */
2468 util_dynarray_append(&sctx
->resident_tex_handles
,
2469 struct si_texture_handle
*, tex_handle
);
2471 /* Add the buffers to the current CS in case si_begin_new_cs()
2472 * is not going to be called.
2474 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2476 sview
->is_stencil_sampler
, false);
2478 /* Remove the texture handle from the per-context list. */
2479 util_dynarray_delete_unordered(&sctx
->resident_tex_handles
,
2480 struct si_texture_handle
*,
2483 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2484 util_dynarray_delete_unordered(
2485 &sctx
->resident_tex_needs_depth_decompress
,
2486 struct si_texture_handle
*, tex_handle
);
2488 util_dynarray_delete_unordered(
2489 &sctx
->resident_tex_needs_color_decompress
,
2490 struct si_texture_handle
*, tex_handle
);
2495 static uint64_t si_create_image_handle(struct pipe_context
*ctx
,
2496 const struct pipe_image_view
*view
)
2498 struct si_context
*sctx
= (struct si_context
*)ctx
;
2499 struct si_image_handle
*img_handle
;
2500 uint32_t desc_list
[8];
2503 if (!view
|| !view
->resource
)
2506 img_handle
= CALLOC_STRUCT(si_image_handle
);
2510 memset(desc_list
, 0, sizeof(desc_list
));
2511 si_init_descriptor_list(&desc_list
[0], 8, 1, null_image_descriptor
);
2513 si_set_shader_image_desc(sctx
, view
, false, &desc_list
[0], NULL
);
2515 img_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2517 if (!img_handle
->desc_slot
) {
2522 handle
= img_handle
->desc_slot
;
2524 if (!_mesa_hash_table_insert(sctx
->img_handles
,
2525 (void *)(uintptr_t)handle
,
2531 util_copy_image_view(&img_handle
->view
, view
);
2533 r600_resource(view
->resource
)->image_handle_allocated
= true;
2538 static void si_delete_image_handle(struct pipe_context
*ctx
, uint64_t handle
)
2540 struct si_context
*sctx
= (struct si_context
*)ctx
;
2541 struct si_image_handle
*img_handle
;
2542 struct hash_entry
*entry
;
2544 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2545 (void *)(uintptr_t)handle
);
2549 img_handle
= (struct si_image_handle
*)entry
->data
;
2551 util_copy_image_view(&img_handle
->view
, NULL
);
2552 _mesa_hash_table_remove(sctx
->img_handles
, entry
);
2556 static void si_make_image_handle_resident(struct pipe_context
*ctx
,
2557 uint64_t handle
, unsigned access
,
2560 struct si_context
*sctx
= (struct si_context
*)ctx
;
2561 struct si_image_handle
*img_handle
;
2562 struct pipe_image_view
*view
;
2563 struct r600_resource
*res
;
2564 struct hash_entry
*entry
;
2566 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2567 (void *)(uintptr_t)handle
);
2571 img_handle
= (struct si_image_handle
*)entry
->data
;
2572 view
= &img_handle
->view
;
2573 res
= (struct r600_resource
*)view
->resource
;
2576 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2577 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
2578 unsigned level
= view
->u
.tex
.level
;
2580 if (color_needs_decompression(rtex
)) {
2581 util_dynarray_append(
2582 &sctx
->resident_img_needs_color_decompress
,
2583 struct si_image_handle
*,
2587 if (vi_dcc_enabled(rtex
, level
) &&
2588 p_atomic_read(&rtex
->framebuffers_bound
))
2589 sctx
->need_check_render_feedback
= true;
2591 si_update_bindless_image_descriptor(sctx
, img_handle
);
2593 si_update_bindless_buffer_descriptor(sctx
,
2594 img_handle
->desc_slot
,
2597 &img_handle
->desc_dirty
);
2600 /* Re-upload the descriptor if it has been updated while it
2603 if (img_handle
->desc_dirty
)
2604 sctx
->bindless_descriptors_dirty
= true;
2606 /* Add the image handle to the per-context list. */
2607 util_dynarray_append(&sctx
->resident_img_handles
,
2608 struct si_image_handle
*, img_handle
);
2610 /* Add the buffers to the current CS in case si_begin_new_cs()
2611 * is not going to be called.
2613 si_sampler_view_add_buffer(sctx
, view
->resource
,
2614 (access
& PIPE_IMAGE_ACCESS_WRITE
) ?
2615 RADEON_USAGE_READWRITE
:
2616 RADEON_USAGE_READ
, false, false);
2618 /* Remove the image handle from the per-context list. */
2619 util_dynarray_delete_unordered(&sctx
->resident_img_handles
,
2620 struct si_image_handle
*,
2623 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2624 util_dynarray_delete_unordered(
2625 &sctx
->resident_img_needs_color_decompress
,
2626 struct si_image_handle
*,
2633 void si_all_resident_buffers_begin_new_cs(struct si_context
*sctx
)
2635 unsigned num_resident_tex_handles
, num_resident_img_handles
;
2637 num_resident_tex_handles
= sctx
->resident_tex_handles
.size
/
2638 sizeof(struct si_texture_handle
*);
2639 num_resident_img_handles
= sctx
->resident_img_handles
.size
/
2640 sizeof(struct si_image_handle
*);
2642 /* Add all resident texture handles. */
2643 util_dynarray_foreach(&sctx
->resident_tex_handles
,
2644 struct si_texture_handle
*, tex_handle
) {
2645 struct si_sampler_view
*sview
=
2646 (struct si_sampler_view
*)(*tex_handle
)->view
;
2648 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2650 sview
->is_stencil_sampler
, false);
2653 /* Add all resident image handles. */
2654 util_dynarray_foreach(&sctx
->resident_img_handles
,
2655 struct si_image_handle
*, img_handle
) {
2656 struct pipe_image_view
*view
= &(*img_handle
)->view
;
2658 si_sampler_view_add_buffer(sctx
, view
->resource
,
2659 RADEON_USAGE_READWRITE
,
2663 sctx
->num_resident_handles
+= num_resident_tex_handles
+
2664 num_resident_img_handles
;
2667 /* INIT/DEINIT/UPLOAD */
2669 void si_init_all_descriptors(struct si_context
*sctx
)
2673 #if !HAVE_32BIT_POINTERS
2674 STATIC_ASSERT(GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES
% 2 == 0);
2677 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2678 bool is_2nd
= sctx
->chip_class
>= GFX9
&&
2679 (i
== PIPE_SHADER_TESS_CTRL
||
2680 i
== PIPE_SHADER_GEOMETRY
);
2681 unsigned num_sampler_slots
= SI_NUM_IMAGES
/ 2 + SI_NUM_SAMPLERS
;
2682 unsigned num_buffer_slots
= SI_NUM_SHADER_BUFFERS
+ SI_NUM_CONST_BUFFERS
;
2684 struct si_descriptors
*desc
;
2687 if (i
== PIPE_SHADER_TESS_CTRL
) {
2688 rel_dw_offset
= (R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
-
2689 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2690 } else { /* PIPE_SHADER_GEOMETRY */
2691 rel_dw_offset
= (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
-
2692 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2695 rel_dw_offset
= SI_SGPR_CONST_AND_SHADER_BUFFERS
;
2697 desc
= si_const_and_shader_buffer_descriptors(sctx
, i
);
2698 si_init_buffer_resources(&sctx
->const_and_shader_buffers
[i
], desc
,
2699 num_buffer_slots
, rel_dw_offset
,
2700 RADEON_USAGE_READWRITE
,
2702 RADEON_PRIO_SHADER_RW_BUFFER
,
2703 RADEON_PRIO_CONST_BUFFER
);
2704 desc
->slot_index_to_bind_directly
= si_get_constbuf_slot(0);
2707 #if HAVE_32BIT_POINTERS
2708 if (i
== PIPE_SHADER_TESS_CTRL
) {
2709 rel_dw_offset
= (R_00B40C_SPI_SHADER_USER_DATA_ADDR_HI_HS
-
2710 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2711 } else { /* PIPE_SHADER_GEOMETRY */
2712 rel_dw_offset
= (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS
-
2713 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2716 rel_dw_offset
= GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES
;
2719 rel_dw_offset
= SI_SGPR_SAMPLERS_AND_IMAGES
;
2722 desc
= si_sampler_and_image_descriptors(sctx
, i
);
2723 si_init_descriptors(desc
, rel_dw_offset
, 16, num_sampler_slots
);
2726 for (j
= 0; j
< SI_NUM_IMAGES
; j
++)
2727 memcpy(desc
->list
+ j
* 8, null_image_descriptor
, 8 * 4);
2728 for (; j
< SI_NUM_IMAGES
+ SI_NUM_SAMPLERS
* 2; j
++)
2729 memcpy(desc
->list
+ j
* 8, null_texture_descriptor
, 8 * 4);
2732 si_init_buffer_resources(&sctx
->rw_buffers
,
2733 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
2734 SI_NUM_RW_BUFFERS
, SI_SGPR_RW_BUFFERS
,
2735 /* The second set of usage/priority is used by
2736 * const buffers in RW buffer slots. */
2737 RADEON_USAGE_READWRITE
, RADEON_USAGE_READ
,
2738 RADEON_PRIO_SHADER_RINGS
, RADEON_PRIO_CONST_BUFFER
);
2739 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
= SI_NUM_RW_BUFFERS
;
2741 /* Initialize an array of 1024 bindless descriptors, when the limit is
2742 * reached, just make it larger and re-upload the whole array.
2744 si_init_bindless_descriptors(sctx
, &sctx
->bindless_descriptors
,
2745 SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
,
2748 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2750 /* Set pipe_context functions. */
2751 sctx
->b
.bind_sampler_states
= si_bind_sampler_states
;
2752 sctx
->b
.set_shader_images
= si_set_shader_images
;
2753 sctx
->b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
2754 sctx
->b
.set_polygon_stipple
= si_set_polygon_stipple
;
2755 sctx
->b
.set_shader_buffers
= si_set_shader_buffers
;
2756 sctx
->b
.set_sampler_views
= si_set_sampler_views
;
2757 sctx
->b
.create_texture_handle
= si_create_texture_handle
;
2758 sctx
->b
.delete_texture_handle
= si_delete_texture_handle
;
2759 sctx
->b
.make_texture_handle_resident
= si_make_texture_handle_resident
;
2760 sctx
->b
.create_image_handle
= si_create_image_handle
;
2761 sctx
->b
.delete_image_handle
= si_delete_image_handle
;
2762 sctx
->b
.make_image_handle_resident
= si_make_image_handle_resident
;
2764 /* Shader user data. */
2765 si_init_atom(sctx
, &sctx
->shader_pointers
.atom
, &sctx
->atoms
.s
.shader_pointers
,
2766 si_emit_graphics_shader_pointers
);
2768 /* Set default and immutable mappings. */
2769 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2771 if (sctx
->chip_class
>= GFX9
) {
2772 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2773 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2774 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2775 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2777 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2778 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2779 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2780 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2782 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2785 static bool si_upload_shader_descriptors(struct si_context
*sctx
, unsigned mask
)
2787 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2789 /* Assume nothing will go wrong: */
2790 sctx
->shader_pointers_dirty
|= dirty
;
2793 unsigned i
= u_bit_scan(&dirty
);
2795 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
]))
2799 sctx
->descriptors_dirty
&= ~mask
;
2801 si_upload_bindless_descriptors(sctx
);
2806 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
2808 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
2809 return si_upload_shader_descriptors(sctx
, mask
);
2812 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
2814 /* Does not update rw_buffers as that is not needed for compute shaders
2815 * and the input buffer is using the same SGPR's anyway.
2817 const unsigned mask
= u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
,
2818 SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
2819 return si_upload_shader_descriptors(sctx
, mask
);
2822 void si_release_all_descriptors(struct si_context
*sctx
)
2826 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2827 si_release_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2828 si_const_and_shader_buffer_descriptors(sctx
, i
));
2829 si_release_sampler_views(&sctx
->samplers
[i
]);
2830 si_release_image_views(&sctx
->images
[i
]);
2832 si_release_buffer_resources(&sctx
->rw_buffers
,
2833 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2834 for (i
= 0; i
< SI_NUM_VERTEX_BUFFERS
; i
++)
2835 pipe_vertex_buffer_unreference(&sctx
->vertex_buffer
[i
]);
2837 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2838 si_release_descriptors(&sctx
->descriptors
[i
]);
2840 r600_resource_reference(&sctx
->vb_descriptors_buffer
, NULL
);
2841 sctx
->vb_descriptors_gpu_list
= NULL
; /* points into a mapped buffer */
2843 si_release_bindless_descriptors(sctx
);
2846 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
2850 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2851 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2852 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
]);
2853 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
2855 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2856 si_vertex_buffers_begin_new_cs(sctx
);
2858 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2859 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
2860 si_descriptors_begin_new_cs(sctx
, &sctx
->bindless_descriptors
);
2862 si_shader_pointers_begin_new_cs(sctx
);
2865 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
2866 uint64_t new_active_mask
)
2868 struct si_descriptors
*desc
= &sctx
->descriptors
[desc_idx
];
2870 /* Ignore no-op updates and updates that disable all slots. */
2871 if (!new_active_mask
||
2872 new_active_mask
== u_bit_consecutive64(desc
->first_active_slot
,
2873 desc
->num_active_slots
))
2877 u_bit_scan_consecutive_range64(&new_active_mask
, &first
, &count
);
2878 assert(new_active_mask
== 0);
2880 /* Upload/dump descriptors if slots are being enabled. */
2881 if (first
< desc
->first_active_slot
||
2882 first
+ count
> desc
->first_active_slot
+ desc
->num_active_slots
)
2883 sctx
->descriptors_dirty
|= 1u << desc_idx
;
2885 desc
->first_active_slot
= first
;
2886 desc
->num_active_slots
= count
;
2889 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
2890 struct si_shader_selector
*sel
)
2895 si_set_active_descriptors(sctx
,
2896 si_const_and_shader_buffer_descriptors_idx(sel
->type
),
2897 sel
->active_const_and_shader_buffers
);
2898 si_set_active_descriptors(sctx
,
2899 si_sampler_and_image_descriptors_idx(sel
->type
),
2900 sel
->active_samplers_and_images
);