2 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 /* Resource binding slots and sampler states (each described with 8 or
26 * 4 dwords) are stored in lists in memory which is accessed by shaders
27 * using scalar load instructions.
29 * This file is responsible for managing such lists. It keeps a copy of all
30 * descriptors in CPU memory and re-uploads a whole list if some slots have
33 * This code is also reponsible for updating shader pointers to those lists.
35 * Note that CP DMA can't be used for updating the lists, because a GPU hang
36 * could leave the list in a mid-IB state and the next IB would get wrong
37 * descriptors and the whole context would be unusable at that point.
38 * (Note: The register shadowing can't be used due to the same reason)
40 * Also, uploading descriptors to newly allocated memory doesn't require
44 * Possible scenarios for one 16 dword image+sampler slot:
46 * | Image | w/ FMASK | Buffer | NULL
47 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
48 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
49 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
50 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
52 * FMASK implies MSAA, therefore no sampler state.
53 * Sampler states are never unbound except when FMASK is bound.
59 #include "util/hash_table.h"
60 #include "util/u_idalloc.h"
61 #include "util/format/u_format.h"
62 #include "util/u_memory.h"
63 #include "util/u_upload_mgr.h"
66 /* NULL image and buffer descriptor for textures (alpha = 1) and images
69 * For images, all fields must be zero except for the swizzle, which
70 * supports arbitrary combinations of 0s and 1s. The texture type must be
71 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
73 * For buffers, all fields must be zero. If they are not, the hw hangs.
75 * This is the only reason why the buffer descriptor must be in words [4:7].
77 static uint32_t null_texture_descriptor
[8] = {
81 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) |
82 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
83 /* the rest must contain zeros, which is also used by the buffer
87 static uint32_t null_image_descriptor
[8] = {
91 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
92 /* the rest must contain zeros, which is also used by the buffer
96 static uint64_t si_desc_extract_buffer_address(const uint32_t *desc
)
98 uint64_t va
= desc
[0] |
99 ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
101 /* Sign-extend the 48-bit address. */
103 va
= (int64_t)va
>> 16;
107 static void si_init_descriptor_list(uint32_t *desc_list
,
108 unsigned element_dw_size
,
109 unsigned num_elements
,
110 const uint32_t *null_descriptor
)
114 /* Initialize the array to NULL descriptors if the element size is 8. */
115 if (null_descriptor
) {
116 assert(element_dw_size
% 8 == 0);
117 for (i
= 0; i
< num_elements
* element_dw_size
/ 8; i
++)
118 memcpy(desc_list
+ i
* 8, null_descriptor
, 8 * 4);
122 static void si_init_descriptors(struct si_descriptors
*desc
,
123 short shader_userdata_rel_index
,
124 unsigned element_dw_size
,
125 unsigned num_elements
)
127 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
128 desc
->element_dw_size
= element_dw_size
;
129 desc
->num_elements
= num_elements
;
130 desc
->shader_userdata_offset
= shader_userdata_rel_index
* 4;
131 desc
->slot_index_to_bind_directly
= -1;
134 static void si_release_descriptors(struct si_descriptors
*desc
)
136 si_resource_reference(&desc
->buffer
, NULL
);
140 static bool si_upload_descriptors(struct si_context
*sctx
,
141 struct si_descriptors
*desc
)
143 unsigned slot_size
= desc
->element_dw_size
* 4;
144 unsigned first_slot_offset
= desc
->first_active_slot
* slot_size
;
145 unsigned upload_size
= desc
->num_active_slots
* slot_size
;
147 /* Skip the upload if no shader is using the descriptors. dirty_mask
148 * will stay dirty and the descriptors will be uploaded when there is
149 * a shader using them.
154 /* If there is just one active descriptor, bind it directly. */
155 if ((int)desc
->first_active_slot
== desc
->slot_index_to_bind_directly
&&
156 desc
->num_active_slots
== 1) {
157 uint32_t *descriptor
= &desc
->list
[desc
->slot_index_to_bind_directly
*
158 desc
->element_dw_size
];
160 /* The buffer is already in the buffer list. */
161 si_resource_reference(&desc
->buffer
, NULL
);
162 desc
->gpu_list
= NULL
;
163 desc
->gpu_address
= si_desc_extract_buffer_address(descriptor
);
164 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
169 unsigned buffer_offset
;
170 u_upload_alloc(sctx
->b
.const_uploader
, first_slot_offset
, upload_size
,
171 si_optimal_tcc_alignment(sctx
, upload_size
),
172 &buffer_offset
, (struct pipe_resource
**)&desc
->buffer
,
175 desc
->gpu_address
= 0;
176 return false; /* skip the draw call */
179 util_memcpy_cpu_to_le32(ptr
, (char*)desc
->list
+ first_slot_offset
,
181 desc
->gpu_list
= ptr
- first_slot_offset
/ 4;
183 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, desc
->buffer
,
184 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
186 /* The shader pointer should point to slot 0. */
187 buffer_offset
-= first_slot_offset
;
188 desc
->gpu_address
= desc
->buffer
->gpu_address
+ buffer_offset
;
190 assert(desc
->buffer
->flags
& RADEON_FLAG_32BIT
);
191 assert((desc
->buffer
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
192 assert((desc
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
194 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
199 si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
204 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, desc
->buffer
,
205 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
210 static inline enum radeon_bo_priority
211 si_get_sampler_view_priority(struct si_resource
*res
)
213 if (res
->b
.b
.target
== PIPE_BUFFER
)
214 return RADEON_PRIO_SAMPLER_BUFFER
;
216 if (res
->b
.b
.nr_samples
> 1)
217 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
219 return RADEON_PRIO_SAMPLER_TEXTURE
;
222 static struct si_descriptors
*
223 si_sampler_and_image_descriptors(struct si_context
*sctx
, unsigned shader
)
225 return &sctx
->descriptors
[si_sampler_and_image_descriptors_idx(shader
)];
228 static void si_release_sampler_views(struct si_samplers
*samplers
)
232 for (i
= 0; i
< ARRAY_SIZE(samplers
->views
); i
++) {
233 pipe_sampler_view_reference(&samplers
->views
[i
], NULL
);
237 static void si_sampler_view_add_buffer(struct si_context
*sctx
,
238 struct pipe_resource
*resource
,
239 enum radeon_bo_usage usage
,
240 bool is_stencil_sampler
,
243 struct si_texture
*tex
= (struct si_texture
*)resource
;
244 enum radeon_bo_priority priority
;
249 /* Use the flushed depth texture if direct sampling is unsupported. */
250 if (resource
->target
!= PIPE_BUFFER
&&
251 tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil_sampler
))
252 tex
= tex
->flushed_depth_texture
;
254 priority
= si_get_sampler_view_priority(&tex
->buffer
);
255 radeon_add_to_gfx_buffer_list_check_mem(sctx
, &tex
->buffer
, usage
, priority
,
258 if (resource
->target
== PIPE_BUFFER
)
261 /* Add separate DCC. */
262 if (tex
->dcc_separate_buffer
) {
263 radeon_add_to_gfx_buffer_list_check_mem(sctx
, tex
->dcc_separate_buffer
,
264 usage
, RADEON_PRIO_SEPARATE_META
, check_mem
);
268 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
,
269 struct si_samplers
*samplers
)
271 unsigned mask
= samplers
->enabled_mask
;
273 /* Add buffers to the CS. */
275 int i
= u_bit_scan(&mask
);
276 struct si_sampler_view
*sview
= (struct si_sampler_view
*)samplers
->views
[i
];
278 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
280 sview
->is_stencil_sampler
, false);
284 /* Set buffer descriptor fields that can be changed by reallocations. */
285 static void si_set_buf_desc_address(struct si_resource
*buf
,
286 uint64_t offset
, uint32_t *state
)
288 uint64_t va
= buf
->gpu_address
+ offset
;
291 state
[1] &= C_008F04_BASE_ADDRESS_HI
;
292 state
[1] |= S_008F04_BASE_ADDRESS_HI(va
>> 32);
295 /* Set texture descriptor fields that can be changed by reallocations.
298 * \param base_level_info information of the level of BASE_ADDRESS
299 * \param base_level the level of BASE_ADDRESS
300 * \param first_level pipe_sampler_view.u.tex.first_level
301 * \param block_width util_format_get_blockwidth()
302 * \param is_stencil select between separate Z & Stencil
303 * \param state descriptor to update
305 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
306 struct si_texture
*tex
,
307 const struct legacy_surf_level
*base_level_info
,
308 unsigned base_level
, unsigned first_level
,
309 unsigned block_width
, bool is_stencil
,
312 uint64_t va
, meta_va
= 0;
314 if (tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil
)) {
315 tex
= tex
->flushed_depth_texture
;
319 va
= tex
->buffer
.gpu_address
;
321 if (sscreen
->info
.chip_class
>= GFX9
) {
322 /* Only stencil_offset needs to be added here. */
324 va
+= tex
->surface
.u
.gfx9
.stencil_offset
;
326 va
+= tex
->surface
.u
.gfx9
.surf_offset
;
328 va
+= base_level_info
->offset
;
332 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
333 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
335 /* Only macrotiled modes can set tile swizzle.
336 * GFX9 doesn't use (legacy) base_level_info.
338 if (sscreen
->info
.chip_class
>= GFX9
||
339 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
340 state
[0] |= tex
->surface
.tile_swizzle
;
342 if (sscreen
->info
.chip_class
>= GFX8
) {
343 state
[6] &= C_008F28_COMPRESSION_EN
;
345 if (vi_dcc_enabled(tex
, first_level
)) {
346 meta_va
= (!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) +
347 tex
->surface
.dcc_offset
;
349 if (sscreen
->info
.chip_class
== GFX8
) {
350 meta_va
+= base_level_info
->dcc_offset
;
351 assert(base_level_info
->mode
== RADEON_SURF_MODE_2D
);
354 unsigned dcc_tile_swizzle
= tex
->surface
.tile_swizzle
<< 8;
355 dcc_tile_swizzle
&= tex
->surface
.dcc_alignment
- 1;
356 meta_va
|= dcc_tile_swizzle
;
357 } else if (vi_tc_compat_htile_enabled(tex
, first_level
,
358 is_stencil
? PIPE_MASK_S
: PIPE_MASK_Z
)) {
359 meta_va
= tex
->buffer
.gpu_address
+ tex
->surface
.htile_offset
;
363 state
[6] |= S_008F28_COMPRESSION_EN(1);
366 if (sscreen
->info
.chip_class
>= GFX8
&& sscreen
->info
.chip_class
<= GFX9
)
367 state
[7] = meta_va
>> 8;
369 if (sscreen
->info
.chip_class
>= GFX10
) {
370 state
[3] &= C_00A00C_SW_MODE
;
373 state
[3] |= S_00A00C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
375 state
[3] |= S_00A00C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
378 state
[6] &= C_00A018_META_DATA_ADDRESS_LO
&
379 C_00A018_META_PIPE_ALIGNED
;
382 struct gfx9_surf_meta_flags meta
;
384 if (tex
->surface
.dcc_offset
)
385 meta
= tex
->surface
.u
.gfx9
.dcc
;
387 meta
= tex
->surface
.u
.gfx9
.htile
;
389 state
[6] |= S_00A018_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
390 S_00A018_META_DATA_ADDRESS_LO(meta_va
>> 8);
393 state
[7] = meta_va
>> 16;
394 } else if (sscreen
->info
.chip_class
== GFX9
) {
395 state
[3] &= C_008F1C_SW_MODE
;
396 state
[4] &= C_008F20_PITCH
;
399 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
400 state
[4] |= S_008F20_PITCH(tex
->surface
.u
.gfx9
.stencil
.epitch
);
402 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
403 state
[4] |= S_008F20_PITCH(tex
->surface
.u
.gfx9
.surf
.epitch
);
406 state
[5] &= C_008F24_META_DATA_ADDRESS
&
407 C_008F24_META_PIPE_ALIGNED
&
408 C_008F24_META_RB_ALIGNED
;
410 struct gfx9_surf_meta_flags meta
;
412 if (tex
->surface
.dcc_offset
)
413 meta
= tex
->surface
.u
.gfx9
.dcc
;
415 meta
= tex
->surface
.u
.gfx9
.htile
;
417 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
418 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
419 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
423 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
424 unsigned index
= si_tile_mode_index(tex
, base_level
, is_stencil
);
426 state
[3] &= C_008F1C_TILING_INDEX
;
427 state
[3] |= S_008F1C_TILING_INDEX(index
);
428 state
[4] &= C_008F20_PITCH
;
429 state
[4] |= S_008F20_PITCH(pitch
- 1);
433 static void si_set_sampler_state_desc(struct si_sampler_state
*sstate
,
434 struct si_sampler_view
*sview
,
435 struct si_texture
*tex
,
438 if (sview
&& sview
->is_integer
)
439 memcpy(desc
, sstate
->integer_val
, 4*4);
440 else if (tex
&& tex
->upgraded_depth
&&
441 (!sview
|| !sview
->is_stencil_sampler
))
442 memcpy(desc
, sstate
->upgraded_depth_val
, 4*4);
444 memcpy(desc
, sstate
->val
, 4*4);
447 static void si_set_sampler_view_desc(struct si_context
*sctx
,
448 struct si_sampler_view
*sview
,
449 struct si_sampler_state
*sstate
,
452 struct pipe_sampler_view
*view
= &sview
->base
;
453 struct si_texture
*tex
= (struct si_texture
*)view
->texture
;
454 bool is_buffer
= tex
->buffer
.b
.b
.target
== PIPE_BUFFER
;
456 if (unlikely(!is_buffer
&& sview
->dcc_incompatible
)) {
457 if (vi_dcc_enabled(tex
, view
->u
.tex
.first_level
))
458 if (!si_texture_disable_dcc(sctx
, tex
))
459 si_decompress_dcc(sctx
, tex
);
461 sview
->dcc_incompatible
= false;
464 assert(tex
); /* views with texture == NULL aren't supported */
465 memcpy(desc
, sview
->state
, 8*4);
468 si_set_buf_desc_address(&tex
->buffer
,
469 sview
->base
.u
.buf
.offset
,
472 bool is_separate_stencil
= tex
->db_compatible
&&
473 sview
->is_stencil_sampler
;
475 si_set_mutable_tex_desc_fields(sctx
->screen
, tex
,
476 sview
->base_level_info
,
478 sview
->base
.u
.tex
.first_level
,
484 if (!is_buffer
&& tex
->surface
.fmask_size
) {
485 memcpy(desc
+ 8, sview
->fmask_state
, 8*4);
487 /* Disable FMASK and bind sampler state in [12:15]. */
488 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
491 si_set_sampler_state_desc(sstate
, sview
,
492 is_buffer
? NULL
: tex
,
497 static bool color_needs_decompression(struct si_texture
*tex
)
499 return tex
->surface
.fmask_size
||
500 (tex
->dirty_level_mask
&&
501 (tex
->cmask_buffer
|| tex
->surface
.dcc_offset
));
504 static bool depth_needs_decompression(struct si_texture
*tex
)
506 /* If the depth/stencil texture is TC-compatible, no decompression
507 * will be done. The decompression function will only flush DB caches
508 * to make it coherent with shaders. That's necessary because the driver
509 * doesn't flush DB caches in any other case.
511 return tex
->db_compatible
;
514 static void si_set_sampler_view(struct si_context
*sctx
,
516 unsigned slot
, struct pipe_sampler_view
*view
,
517 bool disallow_early_out
)
519 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
520 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
521 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
522 unsigned desc_slot
= si_get_sampler_slot(slot
);
523 uint32_t *desc
= descs
->list
+ desc_slot
* 16;
525 if (samplers
->views
[slot
] == view
&& !disallow_early_out
)
529 struct si_texture
*tex
= (struct si_texture
*)view
->texture
;
531 si_set_sampler_view_desc(sctx
, sview
,
532 samplers
->sampler_states
[slot
], desc
);
534 if (tex
->buffer
.b
.b
.target
== PIPE_BUFFER
) {
535 tex
->buffer
.bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
536 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
537 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
539 if (depth_needs_decompression(tex
)) {
540 samplers
->needs_depth_decompress_mask
|= 1u << slot
;
542 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
544 if (color_needs_decompression(tex
)) {
545 samplers
->needs_color_decompress_mask
|= 1u << slot
;
547 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
550 if (tex
->surface
.dcc_offset
&&
551 p_atomic_read(&tex
->framebuffers_bound
))
552 sctx
->need_check_render_feedback
= true;
555 pipe_sampler_view_reference(&samplers
->views
[slot
], view
);
556 samplers
->enabled_mask
|= 1u << slot
;
558 /* Since this can flush, it must be done after enabled_mask is
560 si_sampler_view_add_buffer(sctx
, view
->texture
,
562 sview
->is_stencil_sampler
, true);
564 pipe_sampler_view_reference(&samplers
->views
[slot
], NULL
);
565 memcpy(desc
, null_texture_descriptor
, 8*4);
566 /* Only clear the lower dwords of FMASK. */
567 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
568 /* Re-set the sampler state if we are transitioning from FMASK. */
569 if (samplers
->sampler_states
[slot
])
570 si_set_sampler_state_desc(samplers
->sampler_states
[slot
], NULL
, NULL
,
573 samplers
->enabled_mask
&= ~(1u << slot
);
574 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
575 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
578 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
581 static void si_update_shader_needs_decompress_mask(struct si_context
*sctx
,
584 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
585 unsigned shader_bit
= 1 << shader
;
587 if (samplers
->needs_depth_decompress_mask
||
588 samplers
->needs_color_decompress_mask
||
589 sctx
->images
[shader
].needs_color_decompress_mask
)
590 sctx
->shader_needs_decompress_mask
|= shader_bit
;
592 sctx
->shader_needs_decompress_mask
&= ~shader_bit
;
595 static void si_set_sampler_views(struct pipe_context
*ctx
,
596 enum pipe_shader_type shader
, unsigned start
,
598 struct pipe_sampler_view
**views
)
600 struct si_context
*sctx
= (struct si_context
*)ctx
;
603 if (!count
|| shader
>= SI_NUM_SHADERS
)
607 for (i
= 0; i
< count
; i
++)
608 si_set_sampler_view(sctx
, shader
, start
+ i
, views
[i
], false);
610 for (i
= 0; i
< count
; i
++)
611 si_set_sampler_view(sctx
, shader
, start
+ i
, NULL
, false);
614 si_update_shader_needs_decompress_mask(sctx
, shader
);
618 si_samplers_update_needs_color_decompress_mask(struct si_samplers
*samplers
)
620 unsigned mask
= samplers
->enabled_mask
;
623 int i
= u_bit_scan(&mask
);
624 struct pipe_resource
*res
= samplers
->views
[i
]->texture
;
626 if (res
&& res
->target
!= PIPE_BUFFER
) {
627 struct si_texture
*tex
= (struct si_texture
*)res
;
629 if (color_needs_decompression(tex
)) {
630 samplers
->needs_color_decompress_mask
|= 1u << i
;
632 samplers
->needs_color_decompress_mask
&= ~(1u << i
);
641 si_release_image_views(struct si_images
*images
)
645 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
646 struct pipe_image_view
*view
= &images
->views
[i
];
648 pipe_resource_reference(&view
->resource
, NULL
);
653 si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images
*images
)
655 uint mask
= images
->enabled_mask
;
657 /* Add buffers to the CS. */
659 int i
= u_bit_scan(&mask
);
660 struct pipe_image_view
*view
= &images
->views
[i
];
662 assert(view
->resource
);
664 si_sampler_view_add_buffer(sctx
, view
->resource
,
665 RADEON_USAGE_READWRITE
, false, false);
670 si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
672 struct si_images
*images
= &ctx
->images
[shader
];
674 if (images
->enabled_mask
& (1u << slot
)) {
675 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
676 unsigned desc_slot
= si_get_image_slot(slot
);
678 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
679 images
->needs_color_decompress_mask
&= ~(1 << slot
);
681 memcpy(descs
->list
+ desc_slot
*8, null_image_descriptor
, 8*4);
682 images
->enabled_mask
&= ~(1u << slot
);
683 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
688 si_mark_image_range_valid(const struct pipe_image_view
*view
)
690 struct si_resource
*res
= si_resource(view
->resource
);
692 if (res
->b
.b
.target
!= PIPE_BUFFER
)
695 util_range_add(&res
->b
.b
, &res
->valid_buffer_range
,
697 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
700 static void si_set_shader_image_desc(struct si_context
*ctx
,
701 const struct pipe_image_view
*view
,
702 bool skip_decompress
,
703 uint32_t *desc
, uint32_t *fmask_desc
)
705 struct si_screen
*screen
= ctx
->screen
;
706 struct si_resource
*res
;
708 res
= si_resource(view
->resource
);
710 if (res
->b
.b
.target
== PIPE_BUFFER
||
711 view
->shader_access
& SI_IMAGE_ACCESS_AS_BUFFER
) {
712 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
713 si_mark_image_range_valid(view
);
715 si_make_buffer_descriptor(screen
, res
,
718 view
->u
.buf
.size
, desc
);
719 si_set_buf_desc_address(res
, view
->u
.buf
.offset
, desc
+ 4);
721 static const unsigned char swizzle
[4] = { 0, 1, 2, 3 };
722 struct si_texture
*tex
= (struct si_texture
*)res
;
723 unsigned level
= view
->u
.tex
.level
;
724 unsigned width
, height
, depth
, hw_level
;
725 bool uses_dcc
= vi_dcc_enabled(tex
, level
);
726 unsigned access
= view
->access
;
728 assert(!tex
->is_depth
);
729 assert(fmask_desc
|| tex
->surface
.fmask_offset
== 0);
731 if (uses_dcc
&& !skip_decompress
&&
732 (access
& PIPE_IMAGE_ACCESS_WRITE
||
733 !vi_dcc_formats_compatible(screen
, res
->b
.b
.format
, view
->format
))) {
734 /* If DCC can't be disabled, at least decompress it.
735 * The decompression is relatively cheap if the surface
736 * has been decompressed already.
738 if (!si_texture_disable_dcc(ctx
, tex
))
739 si_decompress_dcc(ctx
, tex
);
742 if (ctx
->chip_class
>= GFX9
) {
743 /* Always set the base address. The swizzle modes don't
744 * allow setting mipmap level offsets as the base.
746 width
= res
->b
.b
.width0
;
747 height
= res
->b
.b
.height0
;
748 depth
= res
->b
.b
.depth0
;
751 /* Always force the base level to the selected level.
753 * This is required for 3D textures, where otherwise
754 * selecting a single slice for non-layered bindings
755 * fails. It doesn't hurt the other targets.
757 width
= u_minify(res
->b
.b
.width0
, level
);
758 height
= u_minify(res
->b
.b
.height0
, level
);
759 depth
= u_minify(res
->b
.b
.depth0
, level
);
763 screen
->make_texture_descriptor(screen
, tex
,
764 false, res
->b
.b
.target
,
765 view
->format
, swizzle
,
767 view
->u
.tex
.first_layer
,
768 view
->u
.tex
.last_layer
,
769 width
, height
, depth
,
771 si_set_mutable_tex_desc_fields(screen
, tex
,
772 &tex
->surface
.u
.legacy
.level
[level
],
774 util_format_get_blockwidth(view
->format
),
779 static void si_set_shader_image(struct si_context
*ctx
,
781 unsigned slot
, const struct pipe_image_view
*view
,
782 bool skip_decompress
)
784 struct si_images
*images
= &ctx
->images
[shader
];
785 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
786 struct si_resource
*res
;
788 if (!view
|| !view
->resource
) {
789 si_disable_shader_image(ctx
, shader
, slot
);
793 res
= si_resource(view
->resource
);
795 if (&images
->views
[slot
] != view
)
796 util_copy_image_view(&images
->views
[slot
], view
);
798 si_set_shader_image_desc(ctx
, view
, skip_decompress
,
799 descs
->list
+ si_get_image_slot(slot
) * 8,
800 descs
->list
+ si_get_image_slot(slot
+ SI_NUM_IMAGES
) * 8);
802 if (res
->b
.b
.target
== PIPE_BUFFER
||
803 view
->shader_access
& SI_IMAGE_ACCESS_AS_BUFFER
) {
804 images
->needs_color_decompress_mask
&= ~(1 << slot
);
805 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
807 struct si_texture
*tex
= (struct si_texture
*)res
;
808 unsigned level
= view
->u
.tex
.level
;
810 if (color_needs_decompression(tex
)) {
811 images
->needs_color_decompress_mask
|= 1 << slot
;
813 images
->needs_color_decompress_mask
&= ~(1 << slot
);
816 if (vi_dcc_enabled(tex
, level
) &&
817 p_atomic_read(&tex
->framebuffers_bound
))
818 ctx
->need_check_render_feedback
= true;
821 images
->enabled_mask
|= 1u << slot
;
822 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
824 /* Since this can flush, it must be done after enabled_mask is updated. */
825 si_sampler_view_add_buffer(ctx
, &res
->b
.b
,
826 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
) ?
827 RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
,
832 si_set_shader_images(struct pipe_context
*pipe
,
833 enum pipe_shader_type shader
,
834 unsigned start_slot
, unsigned count
,
835 const struct pipe_image_view
*views
)
837 struct si_context
*ctx
= (struct si_context
*)pipe
;
840 assert(shader
< SI_NUM_SHADERS
);
845 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
848 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
849 si_set_shader_image(ctx
, shader
, slot
, &views
[i
], false);
851 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
852 si_set_shader_image(ctx
, shader
, slot
, NULL
, false);
855 si_update_shader_needs_decompress_mask(ctx
, shader
);
859 si_images_update_needs_color_decompress_mask(struct si_images
*images
)
861 unsigned mask
= images
->enabled_mask
;
864 int i
= u_bit_scan(&mask
);
865 struct pipe_resource
*res
= images
->views
[i
].resource
;
867 if (res
&& res
->target
!= PIPE_BUFFER
) {
868 struct si_texture
*tex
= (struct si_texture
*)res
;
870 if (color_needs_decompression(tex
)) {
871 images
->needs_color_decompress_mask
|= 1 << i
;
873 images
->needs_color_decompress_mask
&= ~(1 << i
);
879 void si_update_ps_colorbuf0_slot(struct si_context
*sctx
)
881 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
882 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
883 unsigned slot
= SI_PS_IMAGE_COLORBUF0
;
884 struct pipe_surface
*surf
= NULL
;
886 /* si_texture_disable_dcc can get us here again. */
887 if (sctx
->blitter
->running
)
890 /* See whether FBFETCH is used and color buffer 0 is set. */
891 if (sctx
->ps_shader
.cso
&&
892 sctx
->ps_shader
.cso
->info
.uses_fbfetch
&&
893 sctx
->framebuffer
.state
.nr_cbufs
&&
894 sctx
->framebuffer
.state
.cbufs
[0])
895 surf
= sctx
->framebuffer
.state
.cbufs
[0];
897 /* Return if FBFETCH transitions from disabled to disabled. */
898 if (!buffers
->buffers
[slot
] && !surf
)
901 sctx
->ps_uses_fbfetch
= surf
!= NULL
;
902 si_update_ps_iter_samples(sctx
);
905 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
906 struct pipe_image_view view
;
909 assert(!tex
->is_depth
);
911 /* Disable DCC, because the texture is used as both a sampler
914 si_texture_disable_dcc(sctx
, tex
);
916 if (tex
->buffer
.b
.b
.nr_samples
<= 1 && tex
->cmask_buffer
) {
918 assert(tex
->cmask_buffer
!= &tex
->buffer
);
919 si_eliminate_fast_color_clear(sctx
, tex
);
920 si_texture_discard_cmask(sctx
->screen
, tex
);
923 view
.resource
= surf
->texture
;
924 view
.format
= surf
->format
;
925 view
.access
= PIPE_IMAGE_ACCESS_READ
;
926 view
.u
.tex
.first_layer
= surf
->u
.tex
.first_layer
;
927 view
.u
.tex
.last_layer
= surf
->u
.tex
.last_layer
;
928 view
.u
.tex
.level
= surf
->u
.tex
.level
;
930 /* Set the descriptor. */
931 uint32_t *desc
= descs
->list
+ slot
*4;
932 memset(desc
, 0, 16 * 4);
933 si_set_shader_image_desc(sctx
, &view
, true, desc
, desc
+ 8);
935 pipe_resource_reference(&buffers
->buffers
[slot
], &tex
->buffer
.b
.b
);
936 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
937 &tex
->buffer
, RADEON_USAGE_READ
,
938 RADEON_PRIO_SHADER_RW_IMAGE
);
939 buffers
->enabled_mask
|= 1u << slot
;
941 /* Clear the descriptor. */
942 memset(descs
->list
+ slot
*4, 0, 8*4);
943 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
944 buffers
->enabled_mask
&= ~(1u << slot
);
947 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
952 static void si_bind_sampler_states(struct pipe_context
*ctx
,
953 enum pipe_shader_type shader
,
954 unsigned start
, unsigned count
, void **states
)
956 struct si_context
*sctx
= (struct si_context
*)ctx
;
957 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
958 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, shader
);
959 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
962 if (!count
|| shader
>= SI_NUM_SHADERS
|| !sstates
)
965 for (i
= 0; i
< count
; i
++) {
966 unsigned slot
= start
+ i
;
967 unsigned desc_slot
= si_get_sampler_slot(slot
);
970 sstates
[i
] == samplers
->sampler_states
[slot
])
974 assert(sstates
[i
]->magic
== SI_SAMPLER_STATE_MAGIC
);
976 samplers
->sampler_states
[slot
] = sstates
[i
];
978 /* If FMASK is bound, don't overwrite it.
979 * The sampler state will be set after FMASK is unbound.
981 struct si_sampler_view
*sview
=
982 (struct si_sampler_view
*)samplers
->views
[slot
];
984 struct si_texture
*tex
= NULL
;
986 if (sview
&& sview
->base
.texture
&&
987 sview
->base
.texture
->target
!= PIPE_BUFFER
)
988 tex
= (struct si_texture
*)sview
->base
.texture
;
990 if (tex
&& tex
->surface
.fmask_size
)
993 si_set_sampler_state_desc(sstates
[i
], sview
, tex
,
994 desc
->list
+ desc_slot
* 16 + 12);
996 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
1000 /* BUFFER RESOURCES */
1002 static void si_init_buffer_resources(struct si_buffer_resources
*buffers
,
1003 struct si_descriptors
*descs
,
1004 unsigned num_buffers
,
1005 short shader_userdata_rel_index
,
1006 enum radeon_bo_priority priority
,
1007 enum radeon_bo_priority priority_constbuf
)
1009 buffers
->priority
= priority
;
1010 buffers
->priority_constbuf
= priority_constbuf
;
1011 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
1012 buffers
->offsets
= CALLOC(num_buffers
, sizeof(buffers
->offsets
[0]));
1014 si_init_descriptors(descs
, shader_userdata_rel_index
, 4, num_buffers
);
1017 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
1018 struct si_descriptors
*descs
)
1022 for (i
= 0; i
< descs
->num_elements
; i
++) {
1023 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
1026 FREE(buffers
->buffers
);
1027 FREE(buffers
->offsets
);
1030 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
1031 struct si_buffer_resources
*buffers
)
1033 unsigned mask
= buffers
->enabled_mask
;
1035 /* Add buffers to the CS. */
1037 int i
= u_bit_scan(&mask
);
1039 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1040 si_resource(buffers
->buffers
[i
]),
1041 buffers
->writable_mask
& (1u << i
) ? RADEON_USAGE_READWRITE
:
1043 i
< SI_NUM_SHADER_BUFFERS
? buffers
->priority
:
1044 buffers
->priority_constbuf
);
1048 static void si_get_buffer_from_descriptors(struct si_buffer_resources
*buffers
,
1049 struct si_descriptors
*descs
,
1050 unsigned idx
, struct pipe_resource
**buf
,
1051 unsigned *offset
, unsigned *size
)
1053 pipe_resource_reference(buf
, buffers
->buffers
[idx
]);
1055 struct si_resource
*res
= si_resource(*buf
);
1056 const uint32_t *desc
= descs
->list
+ idx
* 4;
1061 assert(G_008F04_STRIDE(desc
[1]) == 0);
1062 va
= si_desc_extract_buffer_address(desc
);
1064 assert(va
>= res
->gpu_address
&& va
+ *size
<= res
->gpu_address
+ res
->bo_size
);
1065 *offset
= va
- res
->gpu_address
;
1069 /* VERTEX BUFFERS */
1071 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
1073 int count
= sctx
->num_vertex_elements
;
1076 for (i
= 0; i
< count
; i
++) {
1077 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1079 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1081 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1084 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1085 si_resource(sctx
->vertex_buffer
[vb
].buffer
.resource
),
1086 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1089 if (!sctx
->vb_descriptors_buffer
)
1091 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1092 sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1093 RADEON_PRIO_DESCRIPTORS
);
1096 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
1098 unsigned i
, count
= sctx
->num_vertex_elements
;
1101 if (!sctx
->vertex_buffers_dirty
|| !count
)
1104 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
1105 unsigned alloc_size
= velems
->vb_desc_list_alloc_size
;
1106 unsigned first_vb_use_mask
= velems
->first_vb_use_mask
;
1108 /* Vertex buffer descriptors are the only ones which are uploaded
1109 * directly through a staging buffer and don't go through
1110 * the fine-grained upload path.
1112 u_upload_alloc(sctx
->b
.const_uploader
, 0,
1114 si_optimal_tcc_alignment(sctx
, alloc_size
),
1115 &sctx
->vb_descriptors_offset
,
1116 (struct pipe_resource
**)&sctx
->vb_descriptors_buffer
,
1118 if (!sctx
->vb_descriptors_buffer
) {
1119 sctx
->vb_descriptors_offset
= 0;
1120 sctx
->vb_descriptors_gpu_list
= NULL
;
1124 sctx
->vb_descriptors_gpu_list
= ptr
;
1125 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1126 sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1127 RADEON_PRIO_DESCRIPTORS
);
1129 assert(count
<= SI_MAX_ATTRIBS
);
1131 for (i
= 0; i
< count
; i
++) {
1132 struct pipe_vertex_buffer
*vb
;
1133 struct si_resource
*buf
;
1134 unsigned vbo_index
= velems
->vertex_buffer_index
[i
];
1135 uint32_t *desc
= &ptr
[i
*4];
1137 vb
= &sctx
->vertex_buffer
[vbo_index
];
1138 buf
= si_resource(vb
->buffer
.resource
);
1140 memset(desc
, 0, 16);
1144 int64_t offset
= (int64_t)((int)vb
->buffer_offset
) +
1145 velems
->src_offset
[i
];
1147 if (offset
>= buf
->b
.b
.width0
) {
1148 assert(offset
< buf
->b
.b
.width0
);
1149 memset(desc
, 0, 16);
1153 uint64_t va
= buf
->gpu_address
+ offset
;
1155 int64_t num_records
= (int64_t)buf
->b
.b
.width0
- offset
;
1156 if (sctx
->chip_class
!= GFX8
&& vb
->stride
) {
1157 /* Round up by rounding down and adding 1 */
1158 num_records
= (num_records
- velems
->format_size
[i
]) /
1161 assert(num_records
>= 0 && num_records
<= UINT_MAX
);
1163 uint32_t rsrc_word3
= velems
->rsrc_word3
[i
];
1165 /* OOB_SELECT chooses the out-of-bounds check:
1166 * - 1: index >= NUM_RECORDS (Structured)
1167 * - 3: offset >= NUM_RECORDS (Raw)
1169 if (sctx
->chip_class
>= GFX10
)
1170 rsrc_word3
|= S_008F0C_OOB_SELECT(vb
->stride
? V_008F0C_OOB_SELECT_STRUCTURED
: V_008F0C_OOB_SELECT_RAW
);
1173 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1174 S_008F04_STRIDE(vb
->stride
);
1175 desc
[2] = num_records
;
1176 desc
[3] = rsrc_word3
;
1178 if (first_vb_use_mask
& (1 << i
)) {
1179 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1180 si_resource(vb
->buffer
.resource
),
1181 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1185 /* Don't flush the const cache. It would have a very negative effect
1186 * on performance (confirmed by testing). New descriptors are always
1187 * uploaded to a fresh new buffer, so I don't think flushing the const
1188 * cache is needed. */
1189 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
1190 sctx
->vertex_buffers_dirty
= false;
1191 sctx
->vertex_buffer_pointer_dirty
= true;
1192 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VBO_DESCRIPTORS
;
1197 /* CONSTANT BUFFERS */
1199 static struct si_descriptors
*
1200 si_const_and_shader_buffer_descriptors(struct si_context
*sctx
, unsigned shader
)
1202 return &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(shader
)];
1205 void si_upload_const_buffer(struct si_context
*sctx
, struct si_resource
**buf
,
1206 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
)
1210 u_upload_alloc(sctx
->b
.const_uploader
, 0, size
,
1211 si_optimal_tcc_alignment(sctx
, size
),
1213 (struct pipe_resource
**)buf
, &tmp
);
1215 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
1218 static void si_set_constant_buffer(struct si_context
*sctx
,
1219 struct si_buffer_resources
*buffers
,
1220 unsigned descriptors_idx
,
1221 uint slot
, const struct pipe_constant_buffer
*input
)
1223 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1224 assert(slot
< descs
->num_elements
);
1225 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1227 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1228 * with a NULL buffer). We need to use a dummy buffer instead. */
1229 if (sctx
->chip_class
== GFX7
&&
1230 (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
1231 input
= &sctx
->null_const_buf
;
1233 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1234 struct pipe_resource
*buffer
= NULL
;
1236 unsigned buffer_offset
;
1238 /* Upload the user buffer if needed. */
1239 if (input
->user_buffer
) {
1240 si_upload_const_buffer(sctx
,
1241 (struct si_resource
**)&buffer
, input
->user_buffer
,
1242 input
->buffer_size
, &buffer_offset
);
1244 /* Just unbind on failure. */
1245 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1249 pipe_resource_reference(&buffer
, input
->buffer
);
1250 buffer_offset
= input
->buffer_offset
;
1253 va
= si_resource(buffer
)->gpu_address
+ buffer_offset
;
1255 /* Set the descriptor. */
1256 uint32_t *desc
= descs
->list
+ slot
*4;
1258 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1260 desc
[2] = input
->buffer_size
;
1261 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1262 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1263 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1264 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
1266 if (sctx
->chip_class
>= GFX10
) {
1267 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1268 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
1269 S_008F0C_RESOURCE_LEVEL(1);
1271 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1272 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1275 buffers
->buffers
[slot
] = buffer
;
1276 buffers
->offsets
[slot
] = buffer_offset
;
1277 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1278 si_resource(buffer
),
1280 buffers
->priority_constbuf
, true);
1281 buffers
->enabled_mask
|= 1u << slot
;
1283 /* Clear the descriptor. */
1284 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1285 buffers
->enabled_mask
&= ~(1u << slot
);
1288 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1291 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
,
1292 enum pipe_shader_type shader
, uint slot
,
1293 const struct pipe_constant_buffer
*input
)
1295 struct si_context
*sctx
= (struct si_context
*)ctx
;
1297 if (shader
>= SI_NUM_SHADERS
)
1300 if (slot
== 0 && input
&& input
->buffer
&&
1301 !(si_resource(input
->buffer
)->flags
& RADEON_FLAG_32BIT
)) {
1302 assert(!"constant buffer 0 must have a 32-bit VM address, use const_uploader");
1306 if (input
&& input
->buffer
)
1307 si_resource(input
->buffer
)->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
1309 slot
= si_get_constbuf_slot(slot
);
1310 si_set_constant_buffer(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1311 si_const_and_shader_buffer_descriptors_idx(shader
),
1315 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
1316 uint slot
, struct pipe_constant_buffer
*cbuf
)
1318 cbuf
->user_buffer
= NULL
;
1319 si_get_buffer_from_descriptors(
1320 &sctx
->const_and_shader_buffers
[shader
],
1321 si_const_and_shader_buffer_descriptors(sctx
, shader
),
1322 si_get_constbuf_slot(slot
),
1323 &cbuf
->buffer
, &cbuf
->buffer_offset
, &cbuf
->buffer_size
);
1326 /* SHADER BUFFERS */
1328 static void si_set_shader_buffer(struct si_context
*sctx
,
1329 struct si_buffer_resources
*buffers
,
1330 unsigned descriptors_idx
,
1331 uint slot
, const struct pipe_shader_buffer
*sbuffer
,
1332 bool writable
, enum radeon_bo_priority priority
)
1334 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1335 uint32_t *desc
= descs
->list
+ slot
* 4;
1337 if (!sbuffer
|| !sbuffer
->buffer
) {
1338 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1339 memset(desc
, 0, sizeof(uint32_t) * 4);
1340 buffers
->enabled_mask
&= ~(1u << slot
);
1341 buffers
->writable_mask
&= ~(1u << slot
);
1342 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1346 struct si_resource
*buf
= si_resource(sbuffer
->buffer
);
1347 uint64_t va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1350 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1352 desc
[2] = sbuffer
->buffer_size
;
1353 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1354 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1355 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1356 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
1358 if (sctx
->chip_class
>= GFX10
) {
1359 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1360 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
1361 S_008F0C_RESOURCE_LEVEL(1);
1363 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1364 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1367 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1368 buffers
->offsets
[slot
] = sbuffer
->buffer_offset
;
1369 radeon_add_to_gfx_buffer_list_check_mem(sctx
, buf
,
1370 writable
? RADEON_USAGE_READWRITE
:
1374 buffers
->writable_mask
|= 1u << slot
;
1376 buffers
->writable_mask
&= ~(1u << slot
);
1378 buffers
->enabled_mask
|= 1u << slot
;
1379 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1381 util_range_add(&buf
->b
.b
, &buf
->valid_buffer_range
, sbuffer
->buffer_offset
,
1382 sbuffer
->buffer_offset
+ sbuffer
->buffer_size
);
1385 static void si_set_shader_buffers(struct pipe_context
*ctx
,
1386 enum pipe_shader_type shader
,
1387 unsigned start_slot
, unsigned count
,
1388 const struct pipe_shader_buffer
*sbuffers
,
1389 unsigned writable_bitmask
)
1391 struct si_context
*sctx
= (struct si_context
*)ctx
;
1392 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1393 unsigned descriptors_idx
= si_const_and_shader_buffer_descriptors_idx(shader
);
1396 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1398 for (i
= 0; i
< count
; ++i
) {
1399 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1400 unsigned slot
= si_get_shaderbuf_slot(start_slot
+ i
);
1402 if (sbuffer
&& sbuffer
->buffer
)
1403 si_resource(sbuffer
->buffer
)->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1405 si_set_shader_buffer(sctx
, buffers
, descriptors_idx
, slot
, sbuffer
,
1406 !!(writable_bitmask
& (1u << i
)),
1411 void si_get_shader_buffers(struct si_context
*sctx
,
1412 enum pipe_shader_type shader
,
1413 uint start_slot
, uint count
,
1414 struct pipe_shader_buffer
*sbuf
)
1416 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1417 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1419 for (unsigned i
= 0; i
< count
; ++i
) {
1420 si_get_buffer_from_descriptors(
1422 si_get_shaderbuf_slot(start_slot
+ i
),
1423 &sbuf
[i
].buffer
, &sbuf
[i
].buffer_offset
,
1424 &sbuf
[i
].buffer_size
);
1430 void si_set_rw_buffer(struct si_context
*sctx
,
1431 uint slot
, const struct pipe_constant_buffer
*input
)
1433 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
, SI_DESCS_RW_BUFFERS
,
1437 void si_set_rw_shader_buffer(struct si_context
*sctx
, uint slot
,
1438 const struct pipe_shader_buffer
*sbuffer
)
1440 si_set_shader_buffer(sctx
, &sctx
->rw_buffers
, SI_DESCS_RW_BUFFERS
,
1441 slot
, sbuffer
, true, RADEON_PRIO_SHADER_RW_BUFFER
);
1444 void si_set_ring_buffer(struct si_context
*sctx
, uint slot
,
1445 struct pipe_resource
*buffer
,
1446 unsigned stride
, unsigned num_records
,
1447 bool add_tid
, bool swizzle
,
1448 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1450 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1451 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1453 /* The stride field in the resource descriptor has 14 bits */
1454 assert(stride
< (1 << 14));
1456 assert(slot
< descs
->num_elements
);
1457 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1462 va
= si_resource(buffer
)->gpu_address
+ offset
;
1464 switch (element_size
) {
1466 assert(!"Unsupported ring buffer element size");
1482 switch (index_stride
) {
1484 assert(!"Unsupported ring buffer index stride");
1500 if (sctx
->chip_class
>= GFX8
&& stride
)
1501 num_records
*= stride
;
1503 /* Set the descriptor. */
1504 uint32_t *desc
= descs
->list
+ slot
*4;
1506 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1507 S_008F04_STRIDE(stride
) |
1508 S_008F04_SWIZZLE_ENABLE(swizzle
);
1509 desc
[2] = num_records
;
1510 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1511 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1512 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1513 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1514 S_008F0C_INDEX_STRIDE(index_stride
) |
1515 S_008F0C_ADD_TID_ENABLE(add_tid
);
1517 if (sctx
->chip_class
>= GFX9
)
1518 assert(!swizzle
|| element_size
== 1); /* always 4 bytes on GFX9 */
1520 desc
[3] |= S_008F0C_ELEMENT_SIZE(element_size
);
1522 if (sctx
->chip_class
>= GFX10
) {
1523 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1524 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
1525 S_008F0C_RESOURCE_LEVEL(1);
1527 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1528 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1531 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1532 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1533 si_resource(buffer
),
1534 RADEON_USAGE_READWRITE
, buffers
->priority
);
1535 buffers
->enabled_mask
|= 1u << slot
;
1537 /* Clear the descriptor. */
1538 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1539 buffers
->enabled_mask
&= ~(1u << slot
);
1542 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1545 /* INTERNAL CONST BUFFERS */
1547 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
1548 const struct pipe_poly_stipple
*state
)
1550 struct si_context
*sctx
= (struct si_context
*)ctx
;
1551 struct pipe_constant_buffer cb
= {};
1552 unsigned stipple
[32];
1555 for (i
= 0; i
< 32; i
++)
1556 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1558 cb
.user_buffer
= stipple
;
1559 cb
.buffer_size
= sizeof(stipple
);
1561 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1564 /* TEXTURE METADATA ENABLE/DISABLE */
1567 si_resident_handles_update_needs_color_decompress(struct si_context
*sctx
)
1569 util_dynarray_clear(&sctx
->resident_tex_needs_color_decompress
);
1570 util_dynarray_clear(&sctx
->resident_img_needs_color_decompress
);
1572 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1573 struct si_texture_handle
*, tex_handle
) {
1574 struct pipe_resource
*res
= (*tex_handle
)->view
->texture
;
1575 struct si_texture
*tex
;
1577 if (!res
|| res
->target
== PIPE_BUFFER
)
1580 tex
= (struct si_texture
*)res
;
1581 if (!color_needs_decompression(tex
))
1584 util_dynarray_append(&sctx
->resident_tex_needs_color_decompress
,
1585 struct si_texture_handle
*, *tex_handle
);
1588 util_dynarray_foreach(&sctx
->resident_img_handles
,
1589 struct si_image_handle
*, img_handle
) {
1590 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1591 struct pipe_resource
*res
= view
->resource
;
1592 struct si_texture
*tex
;
1594 if (!res
|| res
->target
== PIPE_BUFFER
)
1597 tex
= (struct si_texture
*)res
;
1598 if (!color_needs_decompression(tex
))
1601 util_dynarray_append(&sctx
->resident_img_needs_color_decompress
,
1602 struct si_image_handle
*, *img_handle
);
1606 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1607 * while the texture is bound, possibly by a different context. In that case,
1608 * call this function to update needs_*_decompress_masks.
1610 void si_update_needs_color_decompress_masks(struct si_context
*sctx
)
1612 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1613 si_samplers_update_needs_color_decompress_mask(&sctx
->samplers
[i
]);
1614 si_images_update_needs_color_decompress_mask(&sctx
->images
[i
]);
1615 si_update_shader_needs_decompress_mask(sctx
, i
);
1618 si_resident_handles_update_needs_color_decompress(sctx
);
1621 /* BUFFER DISCARD/INVALIDATION */
1623 /* Reset descriptors of buffer resources after \p buf has been invalidated.
1624 * If buf == NULL, reset all descriptors.
1626 static void si_reset_buffer_resources(struct si_context
*sctx
,
1627 struct si_buffer_resources
*buffers
,
1628 unsigned descriptors_idx
,
1630 struct pipe_resource
*buf
,
1631 enum radeon_bo_priority priority
)
1633 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1634 unsigned mask
= buffers
->enabled_mask
& slot_mask
;
1637 unsigned i
= u_bit_scan(&mask
);
1638 struct pipe_resource
*buffer
= buffers
->buffers
[i
];
1640 if (buffer
&& (!buf
|| buffer
== buf
)) {
1641 si_set_buf_desc_address(si_resource(buffer
), buffers
->offsets
[i
],
1643 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1645 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1646 si_resource(buffer
),
1647 buffers
->writable_mask
& (1u << i
) ?
1648 RADEON_USAGE_READWRITE
:
1655 /* Update all buffer bindings where the buffer is bound, including
1656 * all resource descriptors. This is invalidate_buffer without
1659 * If buf == NULL, update all buffer bindings.
1661 void si_rebind_buffer(struct si_context
*sctx
, struct pipe_resource
*buf
)
1663 struct si_resource
*buffer
= si_resource(buf
);
1665 unsigned num_elems
= sctx
->num_vertex_elements
;
1667 /* We changed the buffer, now we need to bind it where the old one
1668 * was bound. This consists of 2 things:
1669 * 1) Updating the resource descriptor and dirtying it.
1670 * 2) Adding a relocation to the CS, so that it's usable.
1673 /* Vertex buffers. */
1676 sctx
->vertex_buffers_dirty
= true;
1677 } else if (buffer
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
1678 for (i
= 0; i
< num_elems
; i
++) {
1679 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1681 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1683 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1686 if (sctx
->vertex_buffer
[vb
].buffer
.resource
== buf
) {
1687 sctx
->vertex_buffers_dirty
= true;
1693 /* Streamout buffers. (other internal buffers can't be invalidated) */
1694 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
1695 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1696 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1697 struct si_descriptors
*descs
=
1698 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1699 struct pipe_resource
*buffer
= buffers
->buffers
[i
];
1701 if (!buffer
|| (buf
&& buffer
!= buf
))
1704 si_set_buf_desc_address(si_resource(buffer
), buffers
->offsets
[i
],
1706 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1708 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1709 si_resource(buffer
),
1711 RADEON_PRIO_SHADER_RW_BUFFER
,
1714 /* Update the streamout state. */
1715 if (sctx
->streamout
.begin_emitted
)
1716 si_emit_streamout_end(sctx
);
1717 sctx
->streamout
.append_bitmask
=
1718 sctx
->streamout
.enabled_mask
;
1719 si_streamout_buffers_dirty(sctx
);
1723 /* Constant and shader buffers. */
1724 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1725 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1726 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1727 si_const_and_shader_buffer_descriptors_idx(shader
),
1728 u_bit_consecutive(SI_NUM_SHADER_BUFFERS
, SI_NUM_CONST_BUFFERS
),
1730 sctx
->const_and_shader_buffers
[shader
].priority_constbuf
);
1733 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
1734 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1735 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1736 si_const_and_shader_buffer_descriptors_idx(shader
),
1737 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
),
1739 sctx
->const_and_shader_buffers
[shader
].priority
);
1742 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
1743 /* Texture buffers - update bindings. */
1744 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1745 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1746 struct si_descriptors
*descs
=
1747 si_sampler_and_image_descriptors(sctx
, shader
);
1748 unsigned mask
= samplers
->enabled_mask
;
1751 unsigned i
= u_bit_scan(&mask
);
1752 struct pipe_resource
*buffer
= samplers
->views
[i
]->texture
;
1754 if (buffer
&& buffer
->target
== PIPE_BUFFER
&&
1755 (!buf
|| buffer
== buf
)) {
1756 unsigned desc_slot
= si_get_sampler_slot(i
);
1758 si_set_buf_desc_address(si_resource(buffer
),
1759 samplers
->views
[i
]->u
.buf
.offset
,
1760 descs
->list
+ desc_slot
* 16 + 4);
1761 sctx
->descriptors_dirty
|=
1762 1u << si_sampler_and_image_descriptors_idx(shader
);
1764 radeon_add_to_gfx_buffer_list_check_mem(
1765 sctx
, si_resource(buffer
),
1767 RADEON_PRIO_SAMPLER_BUFFER
, true);
1774 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
1775 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1776 struct si_images
*images
= &sctx
->images
[shader
];
1777 struct si_descriptors
*descs
=
1778 si_sampler_and_image_descriptors(sctx
, shader
);
1779 unsigned mask
= images
->enabled_mask
;
1782 unsigned i
= u_bit_scan(&mask
);
1783 struct pipe_resource
*buffer
= images
->views
[i
].resource
;
1785 if (buffer
&& buffer
->target
== PIPE_BUFFER
&&
1786 (!buf
|| buffer
== buf
)) {
1787 unsigned desc_slot
= si_get_image_slot(i
);
1789 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1790 si_mark_image_range_valid(&images
->views
[i
]);
1792 si_set_buf_desc_address(si_resource(buffer
),
1793 images
->views
[i
].u
.buf
.offset
,
1794 descs
->list
+ desc_slot
* 8 + 4);
1795 sctx
->descriptors_dirty
|=
1796 1u << si_sampler_and_image_descriptors_idx(shader
);
1798 radeon_add_to_gfx_buffer_list_check_mem(
1799 sctx
, si_resource(buffer
),
1800 RADEON_USAGE_READWRITE
,
1801 RADEON_PRIO_SAMPLER_BUFFER
, true);
1807 /* Bindless texture handles */
1808 if (!buffer
|| buffer
->texture_handle_allocated
) {
1809 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1811 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1812 struct si_texture_handle
*, tex_handle
) {
1813 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
1814 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1815 struct pipe_resource
*buffer
= view
->texture
;
1817 if (buffer
&& buffer
->target
== PIPE_BUFFER
&&
1818 (!buf
|| buffer
== buf
)) {
1819 si_set_buf_desc_address(si_resource(buffer
),
1822 desc_slot
* 16 + 4);
1824 (*tex_handle
)->desc_dirty
= true;
1825 sctx
->bindless_descriptors_dirty
= true;
1827 radeon_add_to_gfx_buffer_list_check_mem(
1828 sctx
, si_resource(buffer
),
1830 RADEON_PRIO_SAMPLER_BUFFER
, true);
1835 /* Bindless image handles */
1836 if (!buffer
|| buffer
->image_handle_allocated
) {
1837 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1839 util_dynarray_foreach(&sctx
->resident_img_handles
,
1840 struct si_image_handle
*, img_handle
) {
1841 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1842 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1843 struct pipe_resource
*buffer
= view
->resource
;
1845 if (buffer
&& buffer
->target
== PIPE_BUFFER
&&
1846 (!buf
|| buffer
== buf
)) {
1847 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
1848 si_mark_image_range_valid(view
);
1850 si_set_buf_desc_address(si_resource(buffer
),
1853 desc_slot
* 16 + 4);
1855 (*img_handle
)->desc_dirty
= true;
1856 sctx
->bindless_descriptors_dirty
= true;
1858 radeon_add_to_gfx_buffer_list_check_mem(
1859 sctx
, si_resource(buffer
),
1860 RADEON_USAGE_READWRITE
,
1861 RADEON_PRIO_SAMPLER_BUFFER
, true);
1867 /* Do the same for other contexts. They will invoke this function
1868 * with buffer == NULL.
1870 unsigned new_counter
= p_atomic_inc_return(&sctx
->screen
->dirty_buf_counter
);
1872 /* Skip the update for the current context, because we have already updated
1873 * the buffer bindings.
1875 if (new_counter
== sctx
->last_dirty_buf_counter
+ 1)
1876 sctx
->last_dirty_buf_counter
= new_counter
;
1880 static void si_upload_bindless_descriptor(struct si_context
*sctx
,
1882 unsigned num_dwords
)
1884 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1885 unsigned desc_slot_offset
= desc_slot
* 16;
1889 data
= desc
->list
+ desc_slot_offset
;
1890 va
= desc
->gpu_address
+ desc_slot_offset
* 4;
1892 si_cp_write_data(sctx
, desc
->buffer
, va
- desc
->buffer
->gpu_address
,
1893 num_dwords
* 4, V_370_TC_L2
, V_370_ME
, data
);
1896 static void si_upload_bindless_descriptors(struct si_context
*sctx
)
1898 if (!sctx
->bindless_descriptors_dirty
)
1901 /* Wait for graphics/compute to be idle before updating the resident
1902 * descriptors directly in memory, in case the GPU is using them.
1904 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
1905 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1906 sctx
->emit_cache_flush(sctx
);
1908 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1909 struct si_texture_handle
*, tex_handle
) {
1910 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1912 if (!(*tex_handle
)->desc_dirty
)
1915 si_upload_bindless_descriptor(sctx
, desc_slot
, 16);
1916 (*tex_handle
)->desc_dirty
= false;
1919 util_dynarray_foreach(&sctx
->resident_img_handles
,
1920 struct si_image_handle
*, img_handle
) {
1921 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1923 if (!(*img_handle
)->desc_dirty
)
1926 si_upload_bindless_descriptor(sctx
, desc_slot
, 8);
1927 (*img_handle
)->desc_dirty
= false;
1930 /* Invalidate L1 because it doesn't know that L2 changed. */
1931 sctx
->flags
|= SI_CONTEXT_INV_SCACHE
;
1932 sctx
->emit_cache_flush(sctx
);
1934 sctx
->bindless_descriptors_dirty
= false;
1937 /* Update mutable image descriptor fields of all resident textures. */
1938 static void si_update_bindless_texture_descriptor(struct si_context
*sctx
,
1939 struct si_texture_handle
*tex_handle
)
1941 struct si_sampler_view
*sview
= (struct si_sampler_view
*)tex_handle
->view
;
1942 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1943 unsigned desc_slot_offset
= tex_handle
->desc_slot
* 16;
1944 uint32_t desc_list
[16];
1946 if (sview
->base
.texture
->target
== PIPE_BUFFER
)
1949 memcpy(desc_list
, desc
->list
+ desc_slot_offset
, sizeof(desc_list
));
1950 si_set_sampler_view_desc(sctx
, sview
, &tex_handle
->sstate
,
1951 desc
->list
+ desc_slot_offset
);
1953 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1954 sizeof(desc_list
))) {
1955 tex_handle
->desc_dirty
= true;
1956 sctx
->bindless_descriptors_dirty
= true;
1960 static void si_update_bindless_image_descriptor(struct si_context
*sctx
,
1961 struct si_image_handle
*img_handle
)
1963 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1964 unsigned desc_slot_offset
= img_handle
->desc_slot
* 16;
1965 struct pipe_image_view
*view
= &img_handle
->view
;
1966 struct pipe_resource
*res
= view
->resource
;
1967 uint32_t image_desc
[16];
1968 unsigned desc_size
= (res
->nr_samples
>= 2 ? 16 : 8) * 4;
1970 if (res
->target
== PIPE_BUFFER
)
1973 memcpy(image_desc
, desc
->list
+ desc_slot_offset
, desc_size
);
1974 si_set_shader_image_desc(sctx
, view
, true,
1975 desc
->list
+ desc_slot_offset
,
1976 desc
->list
+ desc_slot_offset
+ 8);
1978 if (memcmp(image_desc
, desc
->list
+ desc_slot_offset
, desc_size
)) {
1979 img_handle
->desc_dirty
= true;
1980 sctx
->bindless_descriptors_dirty
= true;
1984 static void si_update_all_resident_texture_descriptors(struct si_context
*sctx
)
1986 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1987 struct si_texture_handle
*, tex_handle
) {
1988 si_update_bindless_texture_descriptor(sctx
, *tex_handle
);
1991 util_dynarray_foreach(&sctx
->resident_img_handles
,
1992 struct si_image_handle
*, img_handle
) {
1993 si_update_bindless_image_descriptor(sctx
, *img_handle
);
1996 si_upload_bindless_descriptors(sctx
);
1999 /* Update mutable image descriptor fields of all bound textures. */
2000 void si_update_all_texture_descriptors(struct si_context
*sctx
)
2004 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
2005 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
2006 struct si_images
*images
= &sctx
->images
[shader
];
2010 mask
= images
->enabled_mask
;
2012 unsigned i
= u_bit_scan(&mask
);
2013 struct pipe_image_view
*view
= &images
->views
[i
];
2015 if (!view
->resource
||
2016 view
->resource
->target
== PIPE_BUFFER
)
2019 si_set_shader_image(sctx
, shader
, i
, view
, true);
2022 /* Sampler views. */
2023 mask
= samplers
->enabled_mask
;
2025 unsigned i
= u_bit_scan(&mask
);
2026 struct pipe_sampler_view
*view
= samplers
->views
[i
];
2030 view
->texture
->target
== PIPE_BUFFER
)
2033 si_set_sampler_view(sctx
, shader
, i
,
2034 samplers
->views
[i
], true);
2037 si_update_shader_needs_decompress_mask(sctx
, shader
);
2040 si_update_all_resident_texture_descriptors(sctx
);
2041 si_update_ps_colorbuf0_slot(sctx
);
2044 /* SHADER USER DATA */
2046 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
,
2049 sctx
->shader_pointers_dirty
|=
2050 u_bit_consecutive(SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
,
2051 SI_NUM_SHADER_DESCS
);
2053 if (shader
== PIPE_SHADER_VERTEX
)
2054 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
2056 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
2059 static void si_shader_pointers_begin_new_cs(struct si_context
*sctx
)
2061 sctx
->shader_pointers_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2062 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
2063 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
2064 sctx
->graphics_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
2065 sctx
->compute_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
2068 /* Set a base register address for user data constants in the given shader.
2069 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
2071 static void si_set_user_data_base(struct si_context
*sctx
,
2072 unsigned shader
, uint32_t new_base
)
2074 uint32_t *base
= &sctx
->shader_pointers
.sh_base
[shader
];
2076 if (*base
!= new_base
) {
2080 si_mark_shader_pointers_dirty(sctx
, shader
);
2082 /* Any change in enabled shader stages requires re-emitting
2083 * the VS state SGPR, because it contains the clamp_vertex_color
2084 * state, which can be done in VS, TES, and GS.
2086 sctx
->last_vs_state
= ~0;
2090 /* This must be called when these are changed between enabled and disabled
2092 * - tessellation evaluation shader
2095 void si_shader_change_notify(struct si_context
*sctx
)
2097 /* VS can be bound as VS, ES, or LS. */
2098 if (sctx
->tes_shader
.cso
) {
2099 if (sctx
->chip_class
>= GFX10
) {
2100 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2101 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2102 } else if (sctx
->chip_class
== GFX9
) {
2103 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2104 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2106 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2107 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2109 } else if (sctx
->chip_class
>= GFX10
) {
2110 if (sctx
->ngg
|| sctx
->gs_shader
.cso
) {
2111 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2112 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2114 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2115 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2117 } else if (sctx
->gs_shader
.cso
) {
2118 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2119 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2121 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2122 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2125 /* TES can be bound as ES, VS, or not bound. */
2126 if (sctx
->tes_shader
.cso
) {
2127 if (sctx
->chip_class
>= GFX10
) {
2128 if (sctx
->ngg
|| sctx
->gs_shader
.cso
) {
2129 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2130 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2132 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2133 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2135 } else if (sctx
->gs_shader
.cso
) {
2136 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2137 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2139 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2140 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2143 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
2147 static void si_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
2149 unsigned pointer_count
)
2151 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
, 0));
2152 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
2155 static void si_emit_shader_pointer_body(struct si_screen
*sscreen
,
2156 struct radeon_cmdbuf
*cs
,
2159 radeon_emit(cs
, va
);
2161 assert(va
== 0 || (va
>> 32) == sscreen
->info
.address32_hi
);
2164 static void si_emit_shader_pointer(struct si_context
*sctx
,
2165 struct si_descriptors
*desc
,
2168 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2169 unsigned sh_offset
= sh_base
+ desc
->shader_userdata_offset
;
2171 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2172 si_emit_shader_pointer_body(sctx
->screen
, cs
, desc
->gpu_address
);
2175 static void si_emit_consecutive_shader_pointers(struct si_context
*sctx
,
2176 unsigned pointer_mask
,
2182 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2183 unsigned mask
= sctx
->shader_pointers_dirty
& pointer_mask
;
2187 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
2189 struct si_descriptors
*descs
= &sctx
->descriptors
[start
];
2190 unsigned sh_offset
= sh_base
+ descs
->shader_userdata_offset
;
2192 si_emit_shader_pointer_head(cs
, sh_offset
, count
);
2193 for (int i
= 0; i
< count
; i
++)
2194 si_emit_shader_pointer_body(sctx
->screen
, cs
,
2195 descs
[i
].gpu_address
);
2199 static void si_emit_global_shader_pointers(struct si_context
*sctx
,
2200 struct si_descriptors
*descs
)
2202 if (sctx
->chip_class
>= GFX10
) {
2203 si_emit_shader_pointer(sctx
, descs
,
2204 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2205 /* HW VS stage only used in non-NGG mode. */
2206 si_emit_shader_pointer(sctx
, descs
,
2207 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2208 si_emit_shader_pointer(sctx
, descs
,
2209 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2210 si_emit_shader_pointer(sctx
, descs
,
2211 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2213 } else if (sctx
->chip_class
== GFX9
) {
2214 /* Broadcast it to all shader stages. */
2215 si_emit_shader_pointer(sctx
, descs
,
2216 R_00B530_SPI_SHADER_USER_DATA_COMMON_0
);
2220 si_emit_shader_pointer(sctx
, descs
,
2221 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2222 si_emit_shader_pointer(sctx
, descs
,
2223 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2224 si_emit_shader_pointer(sctx
, descs
,
2225 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2226 si_emit_shader_pointer(sctx
, descs
,
2227 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2228 si_emit_shader_pointer(sctx
, descs
,
2229 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2230 si_emit_shader_pointer(sctx
, descs
,
2231 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2234 void si_emit_graphics_shader_pointers(struct si_context
*sctx
)
2236 uint32_t *sh_base
= sctx
->shader_pointers
.sh_base
;
2238 if (sctx
->shader_pointers_dirty
& (1 << SI_DESCS_RW_BUFFERS
)) {
2239 si_emit_global_shader_pointers(sctx
,
2240 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2243 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(VERTEX
),
2244 sh_base
[PIPE_SHADER_VERTEX
]);
2245 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_EVAL
),
2246 sh_base
[PIPE_SHADER_TESS_EVAL
]);
2247 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(FRAGMENT
),
2248 sh_base
[PIPE_SHADER_FRAGMENT
]);
2249 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_CTRL
),
2250 sh_base
[PIPE_SHADER_TESS_CTRL
]);
2251 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(GEOMETRY
),
2252 sh_base
[PIPE_SHADER_GEOMETRY
]);
2254 sctx
->shader_pointers_dirty
&=
2255 ~u_bit_consecutive(SI_DESCS_RW_BUFFERS
, SI_DESCS_FIRST_COMPUTE
);
2257 if (sctx
->vertex_buffer_pointer_dirty
) {
2258 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2260 /* Find the location of the VB descriptor pointer. */
2261 /* TODO: In the future, the pointer will be packed in unused
2262 * bits of the first 2 VB descriptors. */
2263 unsigned sh_dw_offset
= SI_VS_NUM_USER_SGPR
;
2264 if (sctx
->chip_class
>= GFX9
) {
2265 if (sctx
->tes_shader
.cso
)
2266 sh_dw_offset
= GFX9_TCS_NUM_USER_SGPR
;
2267 else if (sctx
->gs_shader
.cso
)
2268 sh_dw_offset
= GFX9_VSGS_NUM_USER_SGPR
;
2271 unsigned sh_offset
= sh_base
[PIPE_SHADER_VERTEX
] + sh_dw_offset
* 4;
2272 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2273 si_emit_shader_pointer_body(sctx
->screen
, cs
,
2274 sctx
->vb_descriptors_buffer
->gpu_address
+
2275 sctx
->vb_descriptors_offset
);
2276 sctx
->vertex_buffer_pointer_dirty
= false;
2279 if (sctx
->graphics_bindless_pointer_dirty
) {
2280 si_emit_global_shader_pointers(sctx
,
2281 &sctx
->bindless_descriptors
);
2282 sctx
->graphics_bindless_pointer_dirty
= false;
2286 void si_emit_compute_shader_pointers(struct si_context
*sctx
)
2288 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
2290 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(COMPUTE
),
2291 R_00B900_COMPUTE_USER_DATA_0
);
2292 sctx
->shader_pointers_dirty
&= ~SI_DESCS_SHADER_MASK(COMPUTE
);
2294 if (sctx
->compute_bindless_pointer_dirty
) {
2295 si_emit_shader_pointer(sctx
, &sctx
->bindless_descriptors
, base
);
2296 sctx
->compute_bindless_pointer_dirty
= false;
2302 static void si_init_bindless_descriptors(struct si_context
*sctx
,
2303 struct si_descriptors
*desc
,
2304 short shader_userdata_rel_index
,
2305 unsigned num_elements
)
2307 ASSERTED
unsigned desc_slot
;
2309 si_init_descriptors(desc
, shader_userdata_rel_index
, 16, num_elements
);
2310 sctx
->bindless_descriptors
.num_active_slots
= num_elements
;
2312 /* The first bindless descriptor is stored at slot 1, because 0 is not
2313 * considered to be a valid handle.
2315 sctx
->num_bindless_descriptors
= 1;
2317 /* Track which bindless slots are used (or not). */
2318 util_idalloc_init(&sctx
->bindless_used_slots
);
2319 util_idalloc_resize(&sctx
->bindless_used_slots
, num_elements
);
2321 /* Reserve slot 0 because it's an invalid handle for bindless. */
2322 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2323 assert(desc_slot
== 0);
2326 static void si_release_bindless_descriptors(struct si_context
*sctx
)
2328 si_release_descriptors(&sctx
->bindless_descriptors
);
2329 util_idalloc_fini(&sctx
->bindless_used_slots
);
2332 static unsigned si_get_first_free_bindless_slot(struct si_context
*sctx
)
2334 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2337 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2338 if (desc_slot
>= desc
->num_elements
) {
2339 /* The array of bindless descriptors is full, resize it. */
2340 unsigned slot_size
= desc
->element_dw_size
* 4;
2341 unsigned new_num_elements
= desc
->num_elements
* 2;
2343 desc
->list
= REALLOC(desc
->list
, desc
->num_elements
* slot_size
,
2344 new_num_elements
* slot_size
);
2345 desc
->num_elements
= new_num_elements
;
2346 desc
->num_active_slots
= new_num_elements
;
2354 si_create_bindless_descriptor(struct si_context
*sctx
, uint32_t *desc_list
,
2357 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2358 unsigned desc_slot
, desc_slot_offset
;
2360 /* Find a free slot. */
2361 desc_slot
= si_get_first_free_bindless_slot(sctx
);
2363 /* For simplicity, sampler and image bindless descriptors use fixed
2364 * 16-dword slots for now. Image descriptors only need 8-dword but this
2365 * doesn't really matter because no real apps use image handles.
2367 desc_slot_offset
= desc_slot
* 16;
2369 /* Copy the descriptor into the array. */
2370 memcpy(desc
->list
+ desc_slot_offset
, desc_list
, size
);
2372 /* Re-upload the whole array of bindless descriptors into a new buffer.
2374 if (!si_upload_descriptors(sctx
, desc
))
2377 /* Make sure to re-emit the shader pointers for all stages. */
2378 sctx
->graphics_bindless_pointer_dirty
= true;
2379 sctx
->compute_bindless_pointer_dirty
= true;
2384 static void si_update_bindless_buffer_descriptor(struct si_context
*sctx
,
2386 struct pipe_resource
*resource
,
2390 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2391 struct si_resource
*buf
= si_resource(resource
);
2392 unsigned desc_slot_offset
= desc_slot
* 16;
2393 uint32_t *desc_list
= desc
->list
+ desc_slot_offset
+ 4;
2394 uint64_t old_desc_va
;
2396 assert(resource
->target
== PIPE_BUFFER
);
2398 /* Retrieve the old buffer addr from the descriptor. */
2399 old_desc_va
= si_desc_extract_buffer_address(desc_list
);
2401 if (old_desc_va
!= buf
->gpu_address
+ offset
) {
2402 /* The buffer has been invalidated when the handle wasn't
2403 * resident, update the descriptor and the dirty flag.
2405 si_set_buf_desc_address(buf
, offset
, &desc_list
[0]);
2411 static uint64_t si_create_texture_handle(struct pipe_context
*ctx
,
2412 struct pipe_sampler_view
*view
,
2413 const struct pipe_sampler_state
*state
)
2415 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
2416 struct si_context
*sctx
= (struct si_context
*)ctx
;
2417 struct si_texture_handle
*tex_handle
;
2418 struct si_sampler_state
*sstate
;
2419 uint32_t desc_list
[16];
2422 tex_handle
= CALLOC_STRUCT(si_texture_handle
);
2426 memset(desc_list
, 0, sizeof(desc_list
));
2427 si_init_descriptor_list(&desc_list
[0], 16, 1, null_texture_descriptor
);
2429 sstate
= ctx
->create_sampler_state(ctx
, state
);
2435 si_set_sampler_view_desc(sctx
, sview
, sstate
, &desc_list
[0]);
2436 memcpy(&tex_handle
->sstate
, sstate
, sizeof(*sstate
));
2437 ctx
->delete_sampler_state(ctx
, sstate
);
2439 tex_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2441 if (!tex_handle
->desc_slot
) {
2446 handle
= tex_handle
->desc_slot
;
2448 if (!_mesa_hash_table_insert(sctx
->tex_handles
,
2449 (void *)(uintptr_t)handle
,
2455 pipe_sampler_view_reference(&tex_handle
->view
, view
);
2457 si_resource(sview
->base
.texture
)->texture_handle_allocated
= true;
2462 static void si_delete_texture_handle(struct pipe_context
*ctx
, uint64_t handle
)
2464 struct si_context
*sctx
= (struct si_context
*)ctx
;
2465 struct si_texture_handle
*tex_handle
;
2466 struct hash_entry
*entry
;
2468 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2469 (void *)(uintptr_t)handle
);
2473 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2475 /* Allow this descriptor slot to be re-used. */
2476 util_idalloc_free(&sctx
->bindless_used_slots
, tex_handle
->desc_slot
);
2478 pipe_sampler_view_reference(&tex_handle
->view
, NULL
);
2479 _mesa_hash_table_remove(sctx
->tex_handles
, entry
);
2483 static void si_make_texture_handle_resident(struct pipe_context
*ctx
,
2484 uint64_t handle
, bool resident
)
2486 struct si_context
*sctx
= (struct si_context
*)ctx
;
2487 struct si_texture_handle
*tex_handle
;
2488 struct si_sampler_view
*sview
;
2489 struct hash_entry
*entry
;
2491 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2492 (void *)(uintptr_t)handle
);
2496 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2497 sview
= (struct si_sampler_view
*)tex_handle
->view
;
2500 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2501 struct si_texture
*tex
=
2502 (struct si_texture
*)sview
->base
.texture
;
2504 if (depth_needs_decompression(tex
)) {
2505 util_dynarray_append(
2506 &sctx
->resident_tex_needs_depth_decompress
,
2507 struct si_texture_handle
*,
2511 if (color_needs_decompression(tex
)) {
2512 util_dynarray_append(
2513 &sctx
->resident_tex_needs_color_decompress
,
2514 struct si_texture_handle
*,
2518 if (tex
->surface
.dcc_offset
&&
2519 p_atomic_read(&tex
->framebuffers_bound
))
2520 sctx
->need_check_render_feedback
= true;
2522 si_update_bindless_texture_descriptor(sctx
, tex_handle
);
2524 si_update_bindless_buffer_descriptor(sctx
,
2525 tex_handle
->desc_slot
,
2526 sview
->base
.texture
,
2527 sview
->base
.u
.buf
.offset
,
2528 &tex_handle
->desc_dirty
);
2531 /* Re-upload the descriptor if it has been updated while it
2534 if (tex_handle
->desc_dirty
)
2535 sctx
->bindless_descriptors_dirty
= true;
2537 /* Add the texture handle to the per-context list. */
2538 util_dynarray_append(&sctx
->resident_tex_handles
,
2539 struct si_texture_handle
*, tex_handle
);
2541 /* Add the buffers to the current CS in case si_begin_new_cs()
2542 * is not going to be called.
2544 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2546 sview
->is_stencil_sampler
, false);
2548 /* Remove the texture handle from the per-context list. */
2549 util_dynarray_delete_unordered(&sctx
->resident_tex_handles
,
2550 struct si_texture_handle
*,
2553 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2554 util_dynarray_delete_unordered(
2555 &sctx
->resident_tex_needs_depth_decompress
,
2556 struct si_texture_handle
*, tex_handle
);
2558 util_dynarray_delete_unordered(
2559 &sctx
->resident_tex_needs_color_decompress
,
2560 struct si_texture_handle
*, tex_handle
);
2565 static uint64_t si_create_image_handle(struct pipe_context
*ctx
,
2566 const struct pipe_image_view
*view
)
2568 struct si_context
*sctx
= (struct si_context
*)ctx
;
2569 struct si_image_handle
*img_handle
;
2570 uint32_t desc_list
[16];
2573 if (!view
|| !view
->resource
)
2576 img_handle
= CALLOC_STRUCT(si_image_handle
);
2580 memset(desc_list
, 0, sizeof(desc_list
));
2581 si_init_descriptor_list(&desc_list
[0], 8, 2, null_image_descriptor
);
2583 si_set_shader_image_desc(sctx
, view
, false, &desc_list
[0], &desc_list
[8]);
2585 img_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2587 if (!img_handle
->desc_slot
) {
2592 handle
= img_handle
->desc_slot
;
2594 if (!_mesa_hash_table_insert(sctx
->img_handles
,
2595 (void *)(uintptr_t)handle
,
2601 util_copy_image_view(&img_handle
->view
, view
);
2603 si_resource(view
->resource
)->image_handle_allocated
= true;
2608 static void si_delete_image_handle(struct pipe_context
*ctx
, uint64_t handle
)
2610 struct si_context
*sctx
= (struct si_context
*)ctx
;
2611 struct si_image_handle
*img_handle
;
2612 struct hash_entry
*entry
;
2614 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2615 (void *)(uintptr_t)handle
);
2619 img_handle
= (struct si_image_handle
*)entry
->data
;
2621 util_copy_image_view(&img_handle
->view
, NULL
);
2622 _mesa_hash_table_remove(sctx
->img_handles
, entry
);
2626 static void si_make_image_handle_resident(struct pipe_context
*ctx
,
2627 uint64_t handle
, unsigned access
,
2630 struct si_context
*sctx
= (struct si_context
*)ctx
;
2631 struct si_image_handle
*img_handle
;
2632 struct pipe_image_view
*view
;
2633 struct si_resource
*res
;
2634 struct hash_entry
*entry
;
2636 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2637 (void *)(uintptr_t)handle
);
2641 img_handle
= (struct si_image_handle
*)entry
->data
;
2642 view
= &img_handle
->view
;
2643 res
= si_resource(view
->resource
);
2646 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2647 struct si_texture
*tex
= (struct si_texture
*)res
;
2648 unsigned level
= view
->u
.tex
.level
;
2650 if (color_needs_decompression(tex
)) {
2651 util_dynarray_append(
2652 &sctx
->resident_img_needs_color_decompress
,
2653 struct si_image_handle
*,
2657 if (vi_dcc_enabled(tex
, level
) &&
2658 p_atomic_read(&tex
->framebuffers_bound
))
2659 sctx
->need_check_render_feedback
= true;
2661 si_update_bindless_image_descriptor(sctx
, img_handle
);
2663 si_update_bindless_buffer_descriptor(sctx
,
2664 img_handle
->desc_slot
,
2667 &img_handle
->desc_dirty
);
2670 /* Re-upload the descriptor if it has been updated while it
2673 if (img_handle
->desc_dirty
)
2674 sctx
->bindless_descriptors_dirty
= true;
2676 /* Add the image handle to the per-context list. */
2677 util_dynarray_append(&sctx
->resident_img_handles
,
2678 struct si_image_handle
*, img_handle
);
2680 /* Add the buffers to the current CS in case si_begin_new_cs()
2681 * is not going to be called.
2683 si_sampler_view_add_buffer(sctx
, view
->resource
,
2684 (access
& PIPE_IMAGE_ACCESS_WRITE
) ?
2685 RADEON_USAGE_READWRITE
:
2686 RADEON_USAGE_READ
, false, false);
2688 /* Remove the image handle from the per-context list. */
2689 util_dynarray_delete_unordered(&sctx
->resident_img_handles
,
2690 struct si_image_handle
*,
2693 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2694 util_dynarray_delete_unordered(
2695 &sctx
->resident_img_needs_color_decompress
,
2696 struct si_image_handle
*,
2702 static void si_resident_buffers_add_all_to_bo_list(struct si_context
*sctx
)
2704 unsigned num_resident_tex_handles
, num_resident_img_handles
;
2706 num_resident_tex_handles
= sctx
->resident_tex_handles
.size
/
2707 sizeof(struct si_texture_handle
*);
2708 num_resident_img_handles
= sctx
->resident_img_handles
.size
/
2709 sizeof(struct si_image_handle
*);
2711 /* Add all resident texture handles. */
2712 util_dynarray_foreach(&sctx
->resident_tex_handles
,
2713 struct si_texture_handle
*, tex_handle
) {
2714 struct si_sampler_view
*sview
=
2715 (struct si_sampler_view
*)(*tex_handle
)->view
;
2717 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2719 sview
->is_stencil_sampler
, false);
2722 /* Add all resident image handles. */
2723 util_dynarray_foreach(&sctx
->resident_img_handles
,
2724 struct si_image_handle
*, img_handle
) {
2725 struct pipe_image_view
*view
= &(*img_handle
)->view
;
2727 si_sampler_view_add_buffer(sctx
, view
->resource
,
2728 RADEON_USAGE_READWRITE
,
2732 sctx
->num_resident_handles
+= num_resident_tex_handles
+
2733 num_resident_img_handles
;
2734 assert(sctx
->bo_list_add_all_resident_resources
);
2735 sctx
->bo_list_add_all_resident_resources
= false;
2738 /* INIT/DEINIT/UPLOAD */
2740 void si_init_all_descriptors(struct si_context
*sctx
)
2743 unsigned first_shader
=
2744 sctx
->has_graphics
? 0 : PIPE_SHADER_COMPUTE
;
2746 for (i
= first_shader
; i
< SI_NUM_SHADERS
; i
++) {
2747 bool is_2nd
= sctx
->chip_class
>= GFX9
&&
2748 (i
== PIPE_SHADER_TESS_CTRL
||
2749 i
== PIPE_SHADER_GEOMETRY
);
2750 unsigned num_sampler_slots
= SI_NUM_IMAGE_SLOTS
/ 2 + SI_NUM_SAMPLERS
;
2751 unsigned num_buffer_slots
= SI_NUM_SHADER_BUFFERS
+ SI_NUM_CONST_BUFFERS
;
2753 struct si_descriptors
*desc
;
2756 if (i
== PIPE_SHADER_TESS_CTRL
) {
2757 rel_dw_offset
= (R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
-
2758 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2759 } else if (sctx
->chip_class
>= GFX10
) { /* PIPE_SHADER_GEOMETRY */
2760 rel_dw_offset
= (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
-
2761 R_00B230_SPI_SHADER_USER_DATA_GS_0
) / 4;
2763 rel_dw_offset
= (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
-
2764 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2767 rel_dw_offset
= SI_SGPR_CONST_AND_SHADER_BUFFERS
;
2769 desc
= si_const_and_shader_buffer_descriptors(sctx
, i
);
2770 si_init_buffer_resources(&sctx
->const_and_shader_buffers
[i
], desc
,
2771 num_buffer_slots
, rel_dw_offset
,
2772 RADEON_PRIO_SHADER_RW_BUFFER
,
2773 RADEON_PRIO_CONST_BUFFER
);
2774 desc
->slot_index_to_bind_directly
= si_get_constbuf_slot(0);
2777 if (i
== PIPE_SHADER_TESS_CTRL
) {
2778 rel_dw_offset
= (R_00B40C_SPI_SHADER_USER_DATA_ADDR_HI_HS
-
2779 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2780 } else if (sctx
->chip_class
>= GFX10
) { /* PIPE_SHADER_GEOMETRY */
2781 rel_dw_offset
= (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS
-
2782 R_00B230_SPI_SHADER_USER_DATA_GS_0
) / 4;
2784 rel_dw_offset
= (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS
-
2785 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2788 rel_dw_offset
= SI_SGPR_SAMPLERS_AND_IMAGES
;
2791 desc
= si_sampler_and_image_descriptors(sctx
, i
);
2792 si_init_descriptors(desc
, rel_dw_offset
, 16, num_sampler_slots
);
2795 for (j
= 0; j
< SI_NUM_IMAGE_SLOTS
; j
++)
2796 memcpy(desc
->list
+ j
* 8, null_image_descriptor
, 8 * 4);
2797 for (; j
< SI_NUM_IMAGE_SLOTS
+ SI_NUM_SAMPLERS
* 2; j
++)
2798 memcpy(desc
->list
+ j
* 8, null_texture_descriptor
, 8 * 4);
2801 si_init_buffer_resources(&sctx
->rw_buffers
,
2802 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
2803 SI_NUM_RW_BUFFERS
, SI_SGPR_RW_BUFFERS
,
2804 /* The second priority is used by
2805 * const buffers in RW buffer slots. */
2806 RADEON_PRIO_SHADER_RINGS
, RADEON_PRIO_CONST_BUFFER
);
2807 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
= SI_NUM_RW_BUFFERS
;
2809 /* Initialize an array of 1024 bindless descriptors, when the limit is
2810 * reached, just make it larger and re-upload the whole array.
2812 si_init_bindless_descriptors(sctx
, &sctx
->bindless_descriptors
,
2813 SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
,
2816 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2818 /* Set pipe_context functions. */
2819 sctx
->b
.bind_sampler_states
= si_bind_sampler_states
;
2820 sctx
->b
.set_shader_images
= si_set_shader_images
;
2821 sctx
->b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
2822 sctx
->b
.set_shader_buffers
= si_set_shader_buffers
;
2823 sctx
->b
.set_sampler_views
= si_set_sampler_views
;
2824 sctx
->b
.create_texture_handle
= si_create_texture_handle
;
2825 sctx
->b
.delete_texture_handle
= si_delete_texture_handle
;
2826 sctx
->b
.make_texture_handle_resident
= si_make_texture_handle_resident
;
2827 sctx
->b
.create_image_handle
= si_create_image_handle
;
2828 sctx
->b
.delete_image_handle
= si_delete_image_handle
;
2829 sctx
->b
.make_image_handle_resident
= si_make_image_handle_resident
;
2831 if (!sctx
->has_graphics
)
2834 sctx
->b
.set_polygon_stipple
= si_set_polygon_stipple
;
2836 /* Shader user data. */
2837 sctx
->atoms
.s
.shader_pointers
.emit
= si_emit_graphics_shader_pointers
;
2839 /* Set default and immutable mappings. */
2841 assert(sctx
->chip_class
>= GFX10
);
2842 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2844 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2847 if (sctx
->chip_class
== GFX9
) {
2848 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2849 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2850 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2851 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2853 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2854 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2855 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2856 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2858 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2861 static bool si_upload_shader_descriptors(struct si_context
*sctx
, unsigned mask
)
2863 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2865 /* Assume nothing will go wrong: */
2866 sctx
->shader_pointers_dirty
|= dirty
;
2869 unsigned i
= u_bit_scan(&dirty
);
2871 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
]))
2875 sctx
->descriptors_dirty
&= ~mask
;
2877 si_upload_bindless_descriptors(sctx
);
2882 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
2884 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
2885 return si_upload_shader_descriptors(sctx
, mask
);
2888 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
2890 /* Does not update rw_buffers as that is not needed for compute shaders
2891 * and the input buffer is using the same SGPR's anyway.
2893 const unsigned mask
= u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
,
2894 SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
2895 return si_upload_shader_descriptors(sctx
, mask
);
2898 void si_release_all_descriptors(struct si_context
*sctx
)
2902 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2903 si_release_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2904 si_const_and_shader_buffer_descriptors(sctx
, i
));
2905 si_release_sampler_views(&sctx
->samplers
[i
]);
2906 si_release_image_views(&sctx
->images
[i
]);
2908 si_release_buffer_resources(&sctx
->rw_buffers
,
2909 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2910 for (i
= 0; i
< SI_NUM_VERTEX_BUFFERS
; i
++)
2911 pipe_vertex_buffer_unreference(&sctx
->vertex_buffer
[i
]);
2913 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2914 si_release_descriptors(&sctx
->descriptors
[i
]);
2916 si_resource_reference(&sctx
->vb_descriptors_buffer
, NULL
);
2917 sctx
->vb_descriptors_gpu_list
= NULL
; /* points into a mapped buffer */
2919 si_release_bindless_descriptors(sctx
);
2922 void si_gfx_resources_add_all_to_bo_list(struct si_context
*sctx
)
2924 for (unsigned i
= 0; i
< SI_NUM_GRAPHICS_SHADERS
; i
++) {
2925 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2926 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
]);
2927 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
2929 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2930 si_vertex_buffers_begin_new_cs(sctx
);
2932 if (sctx
->bo_list_add_all_resident_resources
)
2933 si_resident_buffers_add_all_to_bo_list(sctx
);
2935 assert(sctx
->bo_list_add_all_gfx_resources
);
2936 sctx
->bo_list_add_all_gfx_resources
= false;
2939 void si_compute_resources_add_all_to_bo_list(struct si_context
*sctx
)
2941 unsigned sh
= PIPE_SHADER_COMPUTE
;
2943 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[sh
]);
2944 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[sh
]);
2945 si_image_views_begin_new_cs(sctx
, &sctx
->images
[sh
]);
2946 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2948 if (sctx
->bo_list_add_all_resident_resources
)
2949 si_resident_buffers_add_all_to_bo_list(sctx
);
2951 assert(sctx
->bo_list_add_all_compute_resources
);
2952 sctx
->bo_list_add_all_compute_resources
= false;
2955 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
2957 for (unsigned i
= 0; i
< SI_NUM_DESCS
; ++i
)
2958 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
2959 si_descriptors_begin_new_cs(sctx
, &sctx
->bindless_descriptors
);
2961 si_shader_pointers_begin_new_cs(sctx
);
2963 sctx
->bo_list_add_all_resident_resources
= true;
2964 sctx
->bo_list_add_all_gfx_resources
= true;
2965 sctx
->bo_list_add_all_compute_resources
= true;
2968 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
2969 uint64_t new_active_mask
)
2971 struct si_descriptors
*desc
= &sctx
->descriptors
[desc_idx
];
2973 /* Ignore no-op updates and updates that disable all slots. */
2974 if (!new_active_mask
||
2975 new_active_mask
== u_bit_consecutive64(desc
->first_active_slot
,
2976 desc
->num_active_slots
))
2980 u_bit_scan_consecutive_range64(&new_active_mask
, &first
, &count
);
2981 assert(new_active_mask
== 0);
2983 /* Upload/dump descriptors if slots are being enabled. */
2984 if (first
< desc
->first_active_slot
||
2985 first
+ count
> desc
->first_active_slot
+ desc
->num_active_slots
)
2986 sctx
->descriptors_dirty
|= 1u << desc_idx
;
2988 desc
->first_active_slot
= first
;
2989 desc
->num_active_slots
= count
;
2992 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
2993 struct si_shader_selector
*sel
)
2998 si_set_active_descriptors(sctx
,
2999 si_const_and_shader_buffer_descriptors_idx(sel
->type
),
3000 sel
->active_const_and_shader_buffers
);
3001 si_set_active_descriptors(sctx
,
3002 si_sampler_and_image_descriptors_idx(sel
->type
),
3003 sel
->active_samplers_and_images
);