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gallium: add render_condition_enable param to clear_render_target/depth_stencil
[mesa.git] / src / gallium / drivers / radeonsi / si_descriptors.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Marek Olšák <marek.olsak@amd.com>
25 */
26
27 /* Resource binding slots and sampler states (each described with 8 or
28 * 4 dwords) are stored in lists in memory which is accessed by shaders
29 * using scalar load instructions.
30 *
31 * This file is responsible for managing such lists. It keeps a copy of all
32 * descriptors in CPU memory and re-uploads a whole list if some slots have
33 * been changed.
34 *
35 * This code is also reponsible for updating shader pointers to those lists.
36 *
37 * Note that CP DMA can't be used for updating the lists, because a GPU hang
38 * could leave the list in a mid-IB state and the next IB would get wrong
39 * descriptors and the whole context would be unusable at that point.
40 * (Note: The register shadowing can't be used due to the same reason)
41 *
42 * Also, uploading descriptors to newly allocated memory doesn't require
43 * a KCACHE flush.
44 *
45 *
46 * Possible scenarios for one 16 dword image+sampler slot:
47 *
48 * | Image | w/ FMASK | Buffer | NULL
49 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
50 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
51 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
52 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
53 *
54 * FMASK implies MSAA, therefore no sampler state.
55 * Sampler states are never unbound except when FMASK is bound.
56 */
57
58 #include "radeon/r600_cs.h"
59 #include "si_pipe.h"
60 #include "si_shader.h"
61 #include "sid.h"
62
63 #include "util/u_format.h"
64 #include "util/u_math.h"
65 #include "util/u_memory.h"
66 #include "util/u_suballoc.h"
67 #include "util/u_upload_mgr.h"
68
69
70 /* NULL image and buffer descriptor for textures (alpha = 1) and images
71 * (alpha = 0).
72 *
73 * For images, all fields must be zero except for the swizzle, which
74 * supports arbitrary combinations of 0s and 1s. The texture type must be
75 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
76 *
77 * For buffers, all fields must be zero. If they are not, the hw hangs.
78 *
79 * This is the only reason why the buffer descriptor must be in words [4:7].
80 */
81 static uint32_t null_texture_descriptor[8] = {
82 0,
83 0,
84 0,
85 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1) |
86 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
87 /* the rest must contain zeros, which is also used by the buffer
88 * descriptor */
89 };
90
91 static uint32_t null_image_descriptor[8] = {
92 0,
93 0,
94 0,
95 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
96 /* the rest must contain zeros, which is also used by the buffer
97 * descriptor */
98 };
99
100 static void si_init_descriptors(struct si_descriptors *desc,
101 unsigned shader_userdata_index,
102 unsigned element_dw_size,
103 unsigned num_elements,
104 const uint32_t *null_descriptor,
105 unsigned *ce_offset)
106 {
107 int i;
108
109 assert(num_elements <= sizeof(desc->dirty_mask)*8);
110
111 desc->list = CALLOC(num_elements, element_dw_size * 4);
112 desc->element_dw_size = element_dw_size;
113 desc->num_elements = num_elements;
114 desc->dirty_mask = num_elements == 32 ? ~0u : (1u << num_elements) - 1;
115 desc->shader_userdata_offset = shader_userdata_index * 4;
116
117 if (ce_offset) {
118 desc->ce_offset = *ce_offset;
119
120 /* make sure that ce_offset stays 32 byte aligned */
121 *ce_offset += align(element_dw_size * num_elements * 4, 32);
122 }
123
124 /* Initialize the array to NULL descriptors if the element size is 8. */
125 if (null_descriptor) {
126 assert(element_dw_size % 8 == 0);
127 for (i = 0; i < num_elements * element_dw_size / 8; i++)
128 memcpy(desc->list + i * 8, null_descriptor,
129 8 * 4);
130 }
131 }
132
133 static void si_release_descriptors(struct si_descriptors *desc)
134 {
135 r600_resource_reference(&desc->buffer, NULL);
136 FREE(desc->list);
137 }
138
139 static bool si_ce_upload(struct si_context *sctx, unsigned ce_offset, unsigned size,
140 unsigned *out_offset, struct r600_resource **out_buf) {
141 uint64_t va;
142
143 u_suballocator_alloc(sctx->ce_suballocator, size, 64, out_offset,
144 (struct pipe_resource**)out_buf);
145 if (!out_buf)
146 return false;
147
148 va = (*out_buf)->gpu_address + *out_offset;
149
150 radeon_emit(sctx->ce_ib, PKT3(PKT3_DUMP_CONST_RAM, 3, 0));
151 radeon_emit(sctx->ce_ib, ce_offset);
152 radeon_emit(sctx->ce_ib, size / 4);
153 radeon_emit(sctx->ce_ib, va);
154 radeon_emit(sctx->ce_ib, va >> 32);
155
156 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, *out_buf,
157 RADEON_USAGE_READWRITE, RADEON_PRIO_DESCRIPTORS);
158
159 sctx->ce_need_synchronization = true;
160 return true;
161 }
162
163 static void si_ce_reinitialize_descriptors(struct si_context *sctx,
164 struct si_descriptors *desc)
165 {
166 if (desc->buffer) {
167 struct r600_resource *buffer = (struct r600_resource*)desc->buffer;
168 unsigned list_size = desc->num_elements * desc->element_dw_size * 4;
169 uint64_t va = buffer->gpu_address + desc->buffer_offset;
170 struct radeon_winsys_cs *ib = sctx->ce_preamble_ib;
171
172 if (!ib)
173 ib = sctx->ce_ib;
174
175 list_size = align(list_size, 32);
176
177 radeon_emit(ib, PKT3(PKT3_LOAD_CONST_RAM, 3, 0));
178 radeon_emit(ib, va);
179 radeon_emit(ib, va >> 32);
180 radeon_emit(ib, list_size / 4);
181 radeon_emit(ib, desc->ce_offset);
182
183 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
184 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
185 }
186 desc->ce_ram_dirty = false;
187 }
188
189 void si_ce_reinitialize_all_descriptors(struct si_context *sctx)
190 {
191 int i;
192
193 for (i = 0; i < SI_NUM_DESCS; ++i)
194 si_ce_reinitialize_descriptors(sctx, &sctx->descriptors[i]);
195 }
196
197 void si_ce_enable_loads(struct radeon_winsys_cs *ib)
198 {
199 radeon_emit(ib, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
200 radeon_emit(ib, CONTEXT_CONTROL_LOAD_ENABLE(1) |
201 CONTEXT_CONTROL_LOAD_CE_RAM(1));
202 radeon_emit(ib, CONTEXT_CONTROL_SHADOW_ENABLE(1));
203 }
204
205 static bool si_upload_descriptors(struct si_context *sctx,
206 struct si_descriptors *desc,
207 struct r600_atom * atom)
208 {
209 unsigned list_size = desc->num_elements * desc->element_dw_size * 4;
210
211 if (!desc->dirty_mask)
212 return true;
213
214 if (sctx->ce_ib) {
215 uint32_t const* list = (uint32_t const*)desc->list;
216
217 if (desc->ce_ram_dirty)
218 si_ce_reinitialize_descriptors(sctx, desc);
219
220 while(desc->dirty_mask) {
221 int begin, count;
222 u_bit_scan_consecutive_range(&desc->dirty_mask, &begin,
223 &count);
224
225 begin *= desc->element_dw_size;
226 count *= desc->element_dw_size;
227
228 radeon_emit(sctx->ce_ib,
229 PKT3(PKT3_WRITE_CONST_RAM, count, 0));
230 radeon_emit(sctx->ce_ib, desc->ce_offset + begin * 4);
231 radeon_emit_array(sctx->ce_ib, list + begin, count);
232 }
233
234 if (!si_ce_upload(sctx, desc->ce_offset, list_size,
235 &desc->buffer_offset, &desc->buffer))
236 return false;
237 } else {
238 void *ptr;
239
240 u_upload_alloc(sctx->b.uploader, 0, list_size, 256,
241 &desc->buffer_offset,
242 (struct pipe_resource**)&desc->buffer, &ptr);
243 if (!desc->buffer)
244 return false; /* skip the draw call */
245
246 util_memcpy_cpu_to_le32(ptr, desc->list, list_size);
247
248 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
249 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
250 }
251 desc->pointer_dirty = true;
252 desc->dirty_mask = 0;
253
254 if (atom)
255 si_mark_atom_dirty(sctx, atom);
256
257 return true;
258 }
259
260 static void
261 si_descriptors_begin_new_cs(struct si_context *sctx, struct si_descriptors *desc)
262 {
263 desc->ce_ram_dirty = true;
264
265 if (!desc->buffer)
266 return;
267
268 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
269 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
270 }
271
272 /* SAMPLER VIEWS */
273
274 static unsigned
275 si_sampler_descriptors_idx(unsigned shader)
276 {
277 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
278 SI_SHADER_DESCS_SAMPLERS;
279 }
280
281 static struct si_descriptors *
282 si_sampler_descriptors(struct si_context *sctx, unsigned shader)
283 {
284 return &sctx->descriptors[si_sampler_descriptors_idx(shader)];
285 }
286
287 static void si_release_sampler_views(struct si_sampler_views *views)
288 {
289 int i;
290
291 for (i = 0; i < ARRAY_SIZE(views->views); i++) {
292 pipe_sampler_view_reference(&views->views[i], NULL);
293 }
294 }
295
296 static void si_sampler_view_add_buffer(struct si_context *sctx,
297 struct pipe_resource *resource,
298 enum radeon_bo_usage usage,
299 bool is_stencil_sampler,
300 bool check_mem)
301 {
302 struct r600_resource *rres;
303 struct r600_texture *rtex;
304 enum radeon_bo_priority priority;
305
306 if (!resource)
307 return;
308
309 if (resource->target != PIPE_BUFFER) {
310 struct r600_texture *tex = (struct r600_texture*)resource;
311
312 if (tex->is_depth && !r600_can_sample_zs(tex, is_stencil_sampler))
313 resource = &tex->flushed_depth_texture->resource.b.b;
314 }
315
316 rres = (struct r600_resource*)resource;
317 priority = r600_get_sampler_view_priority(rres);
318
319 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
320 rres, usage, priority,
321 check_mem);
322
323 if (resource->target == PIPE_BUFFER)
324 return;
325
326 /* Now add separate DCC if it's present. */
327 rtex = (struct r600_texture*)resource;
328 if (!rtex->dcc_separate_buffer)
329 return;
330
331 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
332 rtex->dcc_separate_buffer, usage,
333 RADEON_PRIO_DCC, check_mem);
334 }
335
336 static void si_sampler_views_begin_new_cs(struct si_context *sctx,
337 struct si_sampler_views *views)
338 {
339 unsigned mask = views->enabled_mask;
340
341 /* Add buffers to the CS. */
342 while (mask) {
343 int i = u_bit_scan(&mask);
344 struct si_sampler_view *sview = (struct si_sampler_view *)views->views[i];
345
346 si_sampler_view_add_buffer(sctx, sview->base.texture,
347 RADEON_USAGE_READ,
348 sview->is_stencil_sampler, false);
349 }
350 }
351
352 /* Set texture descriptor fields that can be changed by reallocations.
353 *
354 * \param tex texture
355 * \param base_level_info information of the level of BASE_ADDRESS
356 * \param base_level the level of BASE_ADDRESS
357 * \param first_level pipe_sampler_view.u.tex.first_level
358 * \param block_width util_format_get_blockwidth()
359 * \param is_stencil select between separate Z & Stencil
360 * \param state descriptor to update
361 */
362 void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
363 const struct radeon_surf_level *base_level_info,
364 unsigned base_level, unsigned first_level,
365 unsigned block_width, bool is_stencil,
366 uint32_t *state)
367 {
368 uint64_t va;
369 unsigned pitch = base_level_info->nblk_x * block_width;
370
371 if (tex->is_depth && !r600_can_sample_zs(tex, is_stencil)) {
372 tex = tex->flushed_depth_texture;
373 is_stencil = false;
374 }
375
376 va = tex->resource.gpu_address + base_level_info->offset;
377
378 state[1] &= C_008F14_BASE_ADDRESS_HI;
379 state[3] &= C_008F1C_TILING_INDEX;
380 state[4] &= C_008F20_PITCH;
381 state[6] &= C_008F28_COMPRESSION_EN;
382
383 state[0] = va >> 8;
384 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
385 state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(tex, base_level,
386 is_stencil));
387 state[4] |= S_008F20_PITCH(pitch - 1);
388
389 if (tex->dcc_offset && tex->surface.level[first_level].dcc_enabled) {
390 state[6] |= S_008F28_COMPRESSION_EN(1);
391 state[7] = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
392 tex->dcc_offset +
393 base_level_info->dcc_offset) >> 8;
394 }
395 }
396
397 static void si_set_sampler_view(struct si_context *sctx,
398 unsigned shader,
399 unsigned slot, struct pipe_sampler_view *view,
400 bool disallow_early_out)
401 {
402 struct si_sampler_views *views = &sctx->samplers[shader].views;
403 struct si_sampler_view *rview = (struct si_sampler_view*)view;
404 struct si_descriptors *descs = si_sampler_descriptors(sctx, shader);
405
406 if (views->views[slot] == view && !disallow_early_out)
407 return;
408
409 if (view) {
410 struct r600_texture *rtex = (struct r600_texture *)view->texture;
411 uint32_t *desc = descs->list + slot * 16;
412
413 si_sampler_view_add_buffer(sctx, view->texture,
414 RADEON_USAGE_READ,
415 rview->is_stencil_sampler, true);
416
417 pipe_sampler_view_reference(&views->views[slot], view);
418 memcpy(desc, rview->state, 8*4);
419
420 if (view->texture && view->texture->target != PIPE_BUFFER) {
421 bool is_separate_stencil =
422 rtex->db_compatible &&
423 rview->is_stencil_sampler;
424
425 si_set_mutable_tex_desc_fields(rtex,
426 rview->base_level_info,
427 rview->base_level,
428 rview->base.u.tex.first_level,
429 rview->block_width,
430 is_separate_stencil,
431 desc);
432 }
433
434 if (view->texture && view->texture->target != PIPE_BUFFER &&
435 rtex->fmask.size) {
436 memcpy(desc + 8,
437 rview->fmask_state, 8*4);
438 } else {
439 /* Disable FMASK and bind sampler state in [12:15]. */
440 memcpy(desc + 8,
441 null_texture_descriptor, 4*4);
442
443 if (views->sampler_states[slot])
444 memcpy(desc + 12,
445 views->sampler_states[slot], 4*4);
446 }
447
448 views->enabled_mask |= 1u << slot;
449 } else {
450 pipe_sampler_view_reference(&views->views[slot], NULL);
451 memcpy(descs->list + slot*16, null_texture_descriptor, 8*4);
452 /* Only clear the lower dwords of FMASK. */
453 memcpy(descs->list + slot*16 + 8, null_texture_descriptor, 4*4);
454 views->enabled_mask &= ~(1u << slot);
455 }
456
457 descs->dirty_mask |= 1u << slot;
458 sctx->descriptors_dirty |= 1u << si_sampler_descriptors_idx(shader);
459 }
460
461 static bool is_compressed_colortex(struct r600_texture *rtex)
462 {
463 return rtex->cmask.size || rtex->fmask.size ||
464 (rtex->dcc_offset && rtex->dirty_level_mask);
465 }
466
467 static void si_set_sampler_views(struct pipe_context *ctx,
468 unsigned shader, unsigned start,
469 unsigned count,
470 struct pipe_sampler_view **views)
471 {
472 struct si_context *sctx = (struct si_context *)ctx;
473 struct si_textures_info *samplers = &sctx->samplers[shader];
474 int i;
475
476 if (!count || shader >= SI_NUM_SHADERS)
477 return;
478
479 for (i = 0; i < count; i++) {
480 unsigned slot = start + i;
481
482 if (!views || !views[i]) {
483 samplers->depth_texture_mask &= ~(1u << slot);
484 samplers->compressed_colortex_mask &= ~(1u << slot);
485 si_set_sampler_view(sctx, shader, slot, NULL, false);
486 continue;
487 }
488
489 si_set_sampler_view(sctx, shader, slot, views[i], false);
490
491 if (views[i]->texture && views[i]->texture->target != PIPE_BUFFER) {
492 struct r600_texture *rtex =
493 (struct r600_texture*)views[i]->texture;
494
495 if (rtex->db_compatible) {
496 samplers->depth_texture_mask |= 1u << slot;
497 } else {
498 samplers->depth_texture_mask &= ~(1u << slot);
499 }
500 if (is_compressed_colortex(rtex)) {
501 samplers->compressed_colortex_mask |= 1u << slot;
502 } else {
503 samplers->compressed_colortex_mask &= ~(1u << slot);
504 }
505
506 if (rtex->dcc_offset &&
507 p_atomic_read(&rtex->framebuffers_bound))
508 sctx->need_check_render_feedback = true;
509 } else {
510 samplers->depth_texture_mask &= ~(1u << slot);
511 samplers->compressed_colortex_mask &= ~(1u << slot);
512 }
513 }
514 }
515
516 static void
517 si_samplers_update_compressed_colortex_mask(struct si_textures_info *samplers)
518 {
519 unsigned mask = samplers->views.enabled_mask;
520
521 while (mask) {
522 int i = u_bit_scan(&mask);
523 struct pipe_resource *res = samplers->views.views[i]->texture;
524
525 if (res && res->target != PIPE_BUFFER) {
526 struct r600_texture *rtex = (struct r600_texture *)res;
527
528 if (is_compressed_colortex(rtex)) {
529 samplers->compressed_colortex_mask |= 1u << i;
530 } else {
531 samplers->compressed_colortex_mask &= ~(1u << i);
532 }
533 }
534 }
535 }
536
537 /* IMAGE VIEWS */
538
539 static unsigned
540 si_image_descriptors_idx(unsigned shader)
541 {
542 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
543 SI_SHADER_DESCS_IMAGES;
544 }
545
546 static struct si_descriptors*
547 si_image_descriptors(struct si_context *sctx, unsigned shader)
548 {
549 return &sctx->descriptors[si_image_descriptors_idx(shader)];
550 }
551
552 static void
553 si_release_image_views(struct si_images_info *images)
554 {
555 unsigned i;
556
557 for (i = 0; i < SI_NUM_IMAGES; ++i) {
558 struct pipe_image_view *view = &images->views[i];
559
560 pipe_resource_reference(&view->resource, NULL);
561 }
562 }
563
564 static void
565 si_image_views_begin_new_cs(struct si_context *sctx, struct si_images_info *images)
566 {
567 uint mask = images->enabled_mask;
568
569 /* Add buffers to the CS. */
570 while (mask) {
571 int i = u_bit_scan(&mask);
572 struct pipe_image_view *view = &images->views[i];
573
574 assert(view->resource);
575
576 si_sampler_view_add_buffer(sctx, view->resource,
577 RADEON_USAGE_READWRITE, false, false);
578 }
579 }
580
581 static void
582 si_disable_shader_image(struct si_context *ctx, unsigned shader, unsigned slot)
583 {
584 struct si_images_info *images = &ctx->images[shader];
585
586 if (images->enabled_mask & (1u << slot)) {
587 struct si_descriptors *descs = si_image_descriptors(ctx, shader);
588
589 pipe_resource_reference(&images->views[slot].resource, NULL);
590 images->compressed_colortex_mask &= ~(1 << slot);
591
592 memcpy(descs->list + slot*8, null_image_descriptor, 8*4);
593 images->enabled_mask &= ~(1u << slot);
594 descs->dirty_mask |= 1u << slot;
595 ctx->descriptors_dirty |= 1u << si_image_descriptors_idx(shader);
596 }
597 }
598
599 static void
600 si_mark_image_range_valid(const struct pipe_image_view *view)
601 {
602 struct r600_resource *res = (struct r600_resource *)view->resource;
603 const struct util_format_description *desc;
604 unsigned stride;
605
606 assert(res && res->b.b.target == PIPE_BUFFER);
607
608 desc = util_format_description(view->format);
609 stride = desc->block.bits / 8;
610
611 util_range_add(&res->valid_buffer_range,
612 stride * (view->u.buf.first_element),
613 stride * (view->u.buf.last_element + 1));
614 }
615
616 static void si_set_shader_image(struct si_context *ctx,
617 unsigned shader,
618 unsigned slot, const struct pipe_image_view *view)
619 {
620 struct si_screen *screen = ctx->screen;
621 struct si_images_info *images = &ctx->images[shader];
622 struct si_descriptors *descs = si_image_descriptors(ctx, shader);
623 struct r600_resource *res;
624
625 if (!view || !view->resource) {
626 si_disable_shader_image(ctx, shader, slot);
627 return;
628 }
629
630 res = (struct r600_resource *)view->resource;
631
632 if (&images->views[slot] != view)
633 util_copy_image_view(&images->views[slot], view);
634
635 si_sampler_view_add_buffer(ctx, &res->b.b,
636 RADEON_USAGE_READWRITE, false, true);
637
638 if (res->b.b.target == PIPE_BUFFER) {
639 if (view->access & PIPE_IMAGE_ACCESS_WRITE)
640 si_mark_image_range_valid(view);
641
642 si_make_buffer_descriptor(screen, res,
643 view->format,
644 view->u.buf.first_element,
645 view->u.buf.last_element,
646 descs->list + slot * 8);
647 images->compressed_colortex_mask &= ~(1 << slot);
648 } else {
649 static const unsigned char swizzle[4] = { 0, 1, 2, 3 };
650 struct r600_texture *tex = (struct r600_texture *)res;
651 unsigned level = view->u.tex.level;
652 unsigned width, height, depth;
653 uint32_t *desc = descs->list + slot * 8;
654 bool uses_dcc = tex->dcc_offset &&
655 tex->surface.level[level].dcc_enabled;
656
657 assert(!tex->is_depth);
658 assert(tex->fmask.size == 0);
659
660 if (uses_dcc &&
661 view->access & PIPE_IMAGE_ACCESS_WRITE) {
662 /* If DCC can't be disabled, at least decompress it.
663 * The decompression is relatively cheap if the surface
664 * has been decompressed already.
665 */
666 if (r600_texture_disable_dcc(&screen->b, tex))
667 uses_dcc = false;
668 else
669 ctx->b.decompress_dcc(&ctx->b.b, tex);
670 }
671
672 if (is_compressed_colortex(tex)) {
673 images->compressed_colortex_mask |= 1 << slot;
674 } else {
675 images->compressed_colortex_mask &= ~(1 << slot);
676 }
677
678 if (uses_dcc &&
679 p_atomic_read(&tex->framebuffers_bound))
680 ctx->need_check_render_feedback = true;
681
682 /* Always force the base level to the selected level.
683 *
684 * This is required for 3D textures, where otherwise
685 * selecting a single slice for non-layered bindings
686 * fails. It doesn't hurt the other targets.
687 */
688 width = u_minify(res->b.b.width0, level);
689 height = u_minify(res->b.b.height0, level);
690 depth = u_minify(res->b.b.depth0, level);
691
692 si_make_texture_descriptor(screen, tex,
693 false, res->b.b.target,
694 view->format, swizzle,
695 0, 0,
696 view->u.tex.first_layer,
697 view->u.tex.last_layer,
698 width, height, depth,
699 desc, NULL);
700 si_set_mutable_tex_desc_fields(tex, &tex->surface.level[level],
701 level, level,
702 util_format_get_blockwidth(view->format),
703 false, desc);
704 }
705
706 images->enabled_mask |= 1u << slot;
707 descs->dirty_mask |= 1u << slot;
708 ctx->descriptors_dirty |= 1u << si_image_descriptors_idx(shader);
709 }
710
711 static void
712 si_set_shader_images(struct pipe_context *pipe, unsigned shader,
713 unsigned start_slot, unsigned count,
714 const struct pipe_image_view *views)
715 {
716 struct si_context *ctx = (struct si_context *)pipe;
717 unsigned i, slot;
718
719 assert(shader < SI_NUM_SHADERS);
720
721 if (!count)
722 return;
723
724 assert(start_slot + count <= SI_NUM_IMAGES);
725
726 if (views) {
727 for (i = 0, slot = start_slot; i < count; ++i, ++slot)
728 si_set_shader_image(ctx, shader, slot, &views[i]);
729 } else {
730 for (i = 0, slot = start_slot; i < count; ++i, ++slot)
731 si_set_shader_image(ctx, shader, slot, NULL);
732 }
733 }
734
735 static void
736 si_images_update_compressed_colortex_mask(struct si_images_info *images)
737 {
738 unsigned mask = images->enabled_mask;
739
740 while (mask) {
741 int i = u_bit_scan(&mask);
742 struct pipe_resource *res = images->views[i].resource;
743
744 if (res && res->target != PIPE_BUFFER) {
745 struct r600_texture *rtex = (struct r600_texture *)res;
746
747 if (is_compressed_colortex(rtex)) {
748 images->compressed_colortex_mask |= 1 << i;
749 } else {
750 images->compressed_colortex_mask &= ~(1 << i);
751 }
752 }
753 }
754 }
755
756 /* SAMPLER STATES */
757
758 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
759 unsigned start, unsigned count, void **states)
760 {
761 struct si_context *sctx = (struct si_context *)ctx;
762 struct si_textures_info *samplers = &sctx->samplers[shader];
763 struct si_descriptors *desc = si_sampler_descriptors(sctx, shader);
764 struct si_sampler_state **sstates = (struct si_sampler_state**)states;
765 int i;
766
767 if (!count || shader >= SI_NUM_SHADERS)
768 return;
769
770 for (i = 0; i < count; i++) {
771 unsigned slot = start + i;
772
773 if (!sstates[i] ||
774 sstates[i] == samplers->views.sampler_states[slot])
775 continue;
776
777 samplers->views.sampler_states[slot] = sstates[i];
778
779 /* If FMASK is bound, don't overwrite it.
780 * The sampler state will be set after FMASK is unbound.
781 */
782 if (samplers->views.views[i] &&
783 samplers->views.views[i]->texture &&
784 samplers->views.views[i]->texture->target != PIPE_BUFFER &&
785 ((struct r600_texture*)samplers->views.views[i]->texture)->fmask.size)
786 continue;
787
788 memcpy(desc->list + slot * 16 + 12, sstates[i]->val, 4*4);
789 desc->dirty_mask |= 1u << slot;
790 sctx->descriptors_dirty |= 1u << si_sampler_descriptors_idx(shader);
791 }
792 }
793
794 /* BUFFER RESOURCES */
795
796 static void si_init_buffer_resources(struct si_buffer_resources *buffers,
797 struct si_descriptors *descs,
798 unsigned num_buffers,
799 unsigned shader_userdata_index,
800 enum radeon_bo_usage shader_usage,
801 enum radeon_bo_priority priority,
802 unsigned *ce_offset)
803 {
804 buffers->shader_usage = shader_usage;
805 buffers->priority = priority;
806 buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource*));
807
808 si_init_descriptors(descs, shader_userdata_index, 4,
809 num_buffers, NULL, ce_offset);
810 }
811
812 static void si_release_buffer_resources(struct si_buffer_resources *buffers,
813 struct si_descriptors *descs)
814 {
815 int i;
816
817 for (i = 0; i < descs->num_elements; i++) {
818 pipe_resource_reference(&buffers->buffers[i], NULL);
819 }
820
821 FREE(buffers->buffers);
822 }
823
824 static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
825 struct si_buffer_resources *buffers)
826 {
827 unsigned mask = buffers->enabled_mask;
828
829 /* Add buffers to the CS. */
830 while (mask) {
831 int i = u_bit_scan(&mask);
832
833 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
834 (struct r600_resource*)buffers->buffers[i],
835 buffers->shader_usage, buffers->priority);
836 }
837 }
838
839 /* VERTEX BUFFERS */
840
841 static void si_vertex_buffers_begin_new_cs(struct si_context *sctx)
842 {
843 struct si_descriptors *desc = &sctx->vertex_buffers;
844 int count = sctx->vertex_elements ? sctx->vertex_elements->count : 0;
845 int i;
846
847 for (i = 0; i < count; i++) {
848 int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
849
850 if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
851 continue;
852 if (!sctx->vertex_buffer[vb].buffer)
853 continue;
854
855 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
856 (struct r600_resource*)sctx->vertex_buffer[vb].buffer,
857 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
858 }
859
860 if (!desc->buffer)
861 return;
862 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
863 desc->buffer, RADEON_USAGE_READ,
864 RADEON_PRIO_DESCRIPTORS);
865 }
866
867 bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
868 {
869 struct si_descriptors *desc = &sctx->vertex_buffers;
870 bool bound[SI_NUM_VERTEX_BUFFERS] = {};
871 unsigned i, count = sctx->vertex_elements->count;
872 uint64_t va;
873 uint32_t *ptr;
874
875 if (!sctx->vertex_buffers_dirty)
876 return true;
877 if (!count || !sctx->vertex_elements)
878 return true;
879
880 /* Vertex buffer descriptors are the only ones which are uploaded
881 * directly through a staging buffer and don't go through
882 * the fine-grained upload path.
883 */
884 u_upload_alloc(sctx->b.uploader, 0, count * 16, 256, &desc->buffer_offset,
885 (struct pipe_resource**)&desc->buffer, (void**)&ptr);
886 if (!desc->buffer)
887 return false;
888
889 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
890 desc->buffer, RADEON_USAGE_READ,
891 RADEON_PRIO_DESCRIPTORS);
892
893 assert(count <= SI_NUM_VERTEX_BUFFERS);
894
895 for (i = 0; i < count; i++) {
896 struct pipe_vertex_element *ve = &sctx->vertex_elements->elements[i];
897 struct pipe_vertex_buffer *vb;
898 struct r600_resource *rbuffer;
899 unsigned offset;
900 uint32_t *desc = &ptr[i*4];
901
902 if (ve->vertex_buffer_index >= ARRAY_SIZE(sctx->vertex_buffer)) {
903 memset(desc, 0, 16);
904 continue;
905 }
906
907 vb = &sctx->vertex_buffer[ve->vertex_buffer_index];
908 rbuffer = (struct r600_resource*)vb->buffer;
909 if (!rbuffer) {
910 memset(desc, 0, 16);
911 continue;
912 }
913
914 offset = vb->buffer_offset + ve->src_offset;
915 va = rbuffer->gpu_address + offset;
916
917 /* Fill in T# buffer resource description */
918 desc[0] = va;
919 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
920 S_008F04_STRIDE(vb->stride);
921
922 if (sctx->b.chip_class <= CIK && vb->stride)
923 /* Round up by rounding down and adding 1 */
924 desc[2] = (vb->buffer->width0 - offset -
925 sctx->vertex_elements->format_size[i]) /
926 vb->stride + 1;
927 else
928 desc[2] = vb->buffer->width0 - offset;
929
930 desc[3] = sctx->vertex_elements->rsrc_word3[i];
931
932 if (!bound[ve->vertex_buffer_index]) {
933 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
934 (struct r600_resource*)vb->buffer,
935 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
936 bound[ve->vertex_buffer_index] = true;
937 }
938 }
939
940 /* Don't flush the const cache. It would have a very negative effect
941 * on performance (confirmed by testing). New descriptors are always
942 * uploaded to a fresh new buffer, so I don't think flushing the const
943 * cache is needed. */
944 desc->pointer_dirty = true;
945 si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
946 sctx->vertex_buffers_dirty = false;
947 return true;
948 }
949
950
951 /* CONSTANT BUFFERS */
952
953 static unsigned
954 si_const_buffer_descriptors_idx(unsigned shader)
955 {
956 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
957 SI_SHADER_DESCS_CONST_BUFFERS;
958 }
959
960 static struct si_descriptors *
961 si_const_buffer_descriptors(struct si_context *sctx, unsigned shader)
962 {
963 return &sctx->descriptors[si_const_buffer_descriptors_idx(shader)];
964 }
965
966 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
967 const uint8_t *ptr, unsigned size, uint32_t *const_offset)
968 {
969 void *tmp;
970
971 u_upload_alloc(sctx->b.uploader, 0, size, 256, const_offset,
972 (struct pipe_resource**)rbuffer, &tmp);
973 if (*rbuffer)
974 util_memcpy_cpu_to_le32(tmp, ptr, size);
975 }
976
977 static void si_set_constant_buffer(struct si_context *sctx,
978 struct si_buffer_resources *buffers,
979 unsigned descriptors_idx,
980 uint slot, const struct pipe_constant_buffer *input)
981 {
982 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
983 assert(slot < descs->num_elements);
984 pipe_resource_reference(&buffers->buffers[slot], NULL);
985
986 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
987 * with a NULL buffer). We need to use a dummy buffer instead. */
988 if (sctx->b.chip_class == CIK &&
989 (!input || (!input->buffer && !input->user_buffer)))
990 input = &sctx->null_const_buf;
991
992 if (input && (input->buffer || input->user_buffer)) {
993 struct pipe_resource *buffer = NULL;
994 uint64_t va;
995
996 /* Upload the user buffer if needed. */
997 if (input->user_buffer) {
998 unsigned buffer_offset;
999
1000 si_upload_const_buffer(sctx,
1001 (struct r600_resource**)&buffer, input->user_buffer,
1002 input->buffer_size, &buffer_offset);
1003 if (!buffer) {
1004 /* Just unbind on failure. */
1005 si_set_constant_buffer(sctx, buffers, descriptors_idx, slot, NULL);
1006 return;
1007 }
1008 va = r600_resource(buffer)->gpu_address + buffer_offset;
1009 } else {
1010 pipe_resource_reference(&buffer, input->buffer);
1011 va = r600_resource(buffer)->gpu_address + input->buffer_offset;
1012 }
1013
1014 /* Set the descriptor. */
1015 uint32_t *desc = descs->list + slot*4;
1016 desc[0] = va;
1017 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1018 S_008F04_STRIDE(0);
1019 desc[2] = input->buffer_size;
1020 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1021 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1022 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1023 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1024 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1025 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1026
1027 buffers->buffers[slot] = buffer;
1028 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1029 (struct r600_resource*)buffer,
1030 buffers->shader_usage,
1031 buffers->priority, true);
1032 buffers->enabled_mask |= 1u << slot;
1033 } else {
1034 /* Clear the descriptor. */
1035 memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4);
1036 buffers->enabled_mask &= ~(1u << slot);
1037 }
1038
1039 descs->dirty_mask |= 1u << slot;
1040 sctx->descriptors_dirty |= 1u << descriptors_idx;
1041 }
1042
1043 void si_set_rw_buffer(struct si_context *sctx,
1044 uint slot, const struct pipe_constant_buffer *input)
1045 {
1046 si_set_constant_buffer(sctx, &sctx->rw_buffers,
1047 SI_DESCS_RW_BUFFERS, slot, input);
1048 }
1049
1050 static void si_pipe_set_constant_buffer(struct pipe_context *ctx,
1051 uint shader, uint slot,
1052 const struct pipe_constant_buffer *input)
1053 {
1054 struct si_context *sctx = (struct si_context *)ctx;
1055
1056 if (shader >= SI_NUM_SHADERS)
1057 return;
1058
1059 si_set_constant_buffer(sctx, &sctx->const_buffers[shader],
1060 si_const_buffer_descriptors_idx(shader),
1061 slot, input);
1062 }
1063
1064 /* SHADER BUFFERS */
1065
1066 static unsigned
1067 si_shader_buffer_descriptors_idx(unsigned shader)
1068 {
1069 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
1070 SI_SHADER_DESCS_SHADER_BUFFERS;
1071 }
1072
1073 static struct si_descriptors *
1074 si_shader_buffer_descriptors(struct si_context *sctx, unsigned shader)
1075 {
1076 return &sctx->descriptors[si_shader_buffer_descriptors_idx(shader)];
1077 }
1078
1079 static void si_set_shader_buffers(struct pipe_context *ctx, unsigned shader,
1080 unsigned start_slot, unsigned count,
1081 const struct pipe_shader_buffer *sbuffers)
1082 {
1083 struct si_context *sctx = (struct si_context *)ctx;
1084 struct si_buffer_resources *buffers = &sctx->shader_buffers[shader];
1085 struct si_descriptors *descs = si_shader_buffer_descriptors(sctx, shader);
1086 unsigned i;
1087
1088 assert(start_slot + count <= SI_NUM_SHADER_BUFFERS);
1089
1090 for (i = 0; i < count; ++i) {
1091 const struct pipe_shader_buffer *sbuffer = sbuffers ? &sbuffers[i] : NULL;
1092 struct r600_resource *buf;
1093 unsigned slot = start_slot + i;
1094 uint32_t *desc = descs->list + slot * 4;
1095 uint64_t va;
1096
1097 if (!sbuffer || !sbuffer->buffer) {
1098 pipe_resource_reference(&buffers->buffers[slot], NULL);
1099 memset(desc, 0, sizeof(uint32_t) * 4);
1100 buffers->enabled_mask &= ~(1u << slot);
1101 descs->dirty_mask |= 1u << slot;
1102 sctx->descriptors_dirty |=
1103 1u << si_shader_buffer_descriptors_idx(shader);
1104 continue;
1105 }
1106
1107 buf = (struct r600_resource *)sbuffer->buffer;
1108 va = buf->gpu_address + sbuffer->buffer_offset;
1109
1110 desc[0] = va;
1111 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1112 S_008F04_STRIDE(0);
1113 desc[2] = sbuffer->buffer_size;
1114 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1115 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1116 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1117 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1118 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1119 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1120
1121 pipe_resource_reference(&buffers->buffers[slot], &buf->b.b);
1122 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx, buf,
1123 buffers->shader_usage,
1124 buffers->priority, true);
1125 buffers->enabled_mask |= 1u << slot;
1126 descs->dirty_mask |= 1u << slot;
1127 sctx->descriptors_dirty |=
1128 1u << si_shader_buffer_descriptors_idx(shader);
1129 }
1130 }
1131
1132 /* RING BUFFERS */
1133
1134 void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
1135 struct pipe_resource *buffer,
1136 unsigned stride, unsigned num_records,
1137 bool add_tid, bool swizzle,
1138 unsigned element_size, unsigned index_stride, uint64_t offset)
1139 {
1140 struct si_context *sctx = (struct si_context *)ctx;
1141 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1142 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1143
1144 /* The stride field in the resource descriptor has 14 bits */
1145 assert(stride < (1 << 14));
1146
1147 assert(slot < descs->num_elements);
1148 pipe_resource_reference(&buffers->buffers[slot], NULL);
1149
1150 if (buffer) {
1151 uint64_t va;
1152
1153 va = r600_resource(buffer)->gpu_address + offset;
1154
1155 switch (element_size) {
1156 default:
1157 assert(!"Unsupported ring buffer element size");
1158 case 0:
1159 case 2:
1160 element_size = 0;
1161 break;
1162 case 4:
1163 element_size = 1;
1164 break;
1165 case 8:
1166 element_size = 2;
1167 break;
1168 case 16:
1169 element_size = 3;
1170 break;
1171 }
1172
1173 switch (index_stride) {
1174 default:
1175 assert(!"Unsupported ring buffer index stride");
1176 case 0:
1177 case 8:
1178 index_stride = 0;
1179 break;
1180 case 16:
1181 index_stride = 1;
1182 break;
1183 case 32:
1184 index_stride = 2;
1185 break;
1186 case 64:
1187 index_stride = 3;
1188 break;
1189 }
1190
1191 if (sctx->b.chip_class >= VI && stride)
1192 num_records *= stride;
1193
1194 /* Set the descriptor. */
1195 uint32_t *desc = descs->list + slot*4;
1196 desc[0] = va;
1197 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1198 S_008F04_STRIDE(stride) |
1199 S_008F04_SWIZZLE_ENABLE(swizzle);
1200 desc[2] = num_records;
1201 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1202 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1203 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1204 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1205 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1206 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1207 S_008F0C_ELEMENT_SIZE(element_size) |
1208 S_008F0C_INDEX_STRIDE(index_stride) |
1209 S_008F0C_ADD_TID_ENABLE(add_tid);
1210
1211 pipe_resource_reference(&buffers->buffers[slot], buffer);
1212 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1213 (struct r600_resource*)buffer,
1214 buffers->shader_usage, buffers->priority);
1215 buffers->enabled_mask |= 1u << slot;
1216 } else {
1217 /* Clear the descriptor. */
1218 memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4);
1219 buffers->enabled_mask &= ~(1u << slot);
1220 }
1221
1222 descs->dirty_mask |= 1u << slot;
1223 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1224 }
1225
1226 /* STREAMOUT BUFFERS */
1227
1228 static void si_set_streamout_targets(struct pipe_context *ctx,
1229 unsigned num_targets,
1230 struct pipe_stream_output_target **targets,
1231 const unsigned *offsets)
1232 {
1233 struct si_context *sctx = (struct si_context *)ctx;
1234 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1235 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1236 unsigned old_num_targets = sctx->b.streamout.num_targets;
1237 unsigned i, bufidx;
1238
1239 /* We are going to unbind the buffers. Mark which caches need to be flushed. */
1240 if (sctx->b.streamout.num_targets && sctx->b.streamout.begin_emitted) {
1241 /* Since streamout uses vector writes which go through TC L2
1242 * and most other clients can use TC L2 as well, we don't need
1243 * to flush it.
1244 *
1245 * The only cases which requires flushing it is VGT DMA index
1246 * fetching (on <= CIK) and indirect draw data, which are rare
1247 * cases. Thus, flag the TC L2 dirtiness in the resource and
1248 * handle it at draw call time.
1249 */
1250 for (i = 0; i < sctx->b.streamout.num_targets; i++)
1251 if (sctx->b.streamout.targets[i])
1252 r600_resource(sctx->b.streamout.targets[i]->b.buffer)->TC_L2_dirty = true;
1253
1254 /* Invalidate the scalar cache in case a streamout buffer is
1255 * going to be used as a constant buffer.
1256 *
1257 * Invalidate TC L1, because streamout bypasses it (done by
1258 * setting GLC=1 in the store instruction), but it can contain
1259 * outdated data of streamout buffers.
1260 *
1261 * VS_PARTIAL_FLUSH is required if the buffers are going to be
1262 * used as an input immediately.
1263 */
1264 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
1265 SI_CONTEXT_INV_VMEM_L1 |
1266 SI_CONTEXT_VS_PARTIAL_FLUSH;
1267 }
1268
1269 /* All readers of the streamout targets need to be finished before we can
1270 * start writing to the targets.
1271 */
1272 if (num_targets)
1273 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
1274 SI_CONTEXT_CS_PARTIAL_FLUSH;
1275
1276 /* Streamout buffers must be bound in 2 places:
1277 * 1) in VGT by setting the VGT_STRMOUT registers
1278 * 2) as shader resources
1279 */
1280
1281 /* Set the VGT regs. */
1282 r600_set_streamout_targets(ctx, num_targets, targets, offsets);
1283
1284 /* Set the shader resources.*/
1285 for (i = 0; i < num_targets; i++) {
1286 bufidx = SI_VS_STREAMOUT_BUF0 + i;
1287
1288 if (targets[i]) {
1289 struct pipe_resource *buffer = targets[i]->buffer;
1290 uint64_t va = r600_resource(buffer)->gpu_address;
1291
1292 /* Set the descriptor.
1293 *
1294 * On VI, the format must be non-INVALID, otherwise
1295 * the buffer will be considered not bound and store
1296 * instructions will be no-ops.
1297 */
1298 uint32_t *desc = descs->list + bufidx*4;
1299 desc[0] = va;
1300 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1301 desc[2] = 0xffffffff;
1302 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1303 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1304 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1305 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1306 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1307
1308 /* Set the resource. */
1309 pipe_resource_reference(&buffers->buffers[bufidx],
1310 buffer);
1311 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1312 (struct r600_resource*)buffer,
1313 buffers->shader_usage,
1314 buffers->priority, true);
1315 buffers->enabled_mask |= 1u << bufidx;
1316 } else {
1317 /* Clear the descriptor and unset the resource. */
1318 memset(descs->list + bufidx*4, 0,
1319 sizeof(uint32_t) * 4);
1320 pipe_resource_reference(&buffers->buffers[bufidx],
1321 NULL);
1322 buffers->enabled_mask &= ~(1u << bufidx);
1323 }
1324 descs->dirty_mask |= 1u << bufidx;
1325 }
1326 for (; i < old_num_targets; i++) {
1327 bufidx = SI_VS_STREAMOUT_BUF0 + i;
1328 /* Clear the descriptor and unset the resource. */
1329 memset(descs->list + bufidx*4, 0, sizeof(uint32_t) * 4);
1330 pipe_resource_reference(&buffers->buffers[bufidx], NULL);
1331 buffers->enabled_mask &= ~(1u << bufidx);
1332 descs->dirty_mask |= 1u << bufidx;
1333 }
1334
1335 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1336 }
1337
1338 static void si_desc_reset_buffer_offset(struct pipe_context *ctx,
1339 uint32_t *desc, uint64_t old_buf_va,
1340 struct pipe_resource *new_buf)
1341 {
1342 /* Retrieve the buffer offset from the descriptor. */
1343 uint64_t old_desc_va =
1344 desc[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc[1]) << 32);
1345
1346 assert(old_buf_va <= old_desc_va);
1347 uint64_t offset_within_buffer = old_desc_va - old_buf_va;
1348
1349 /* Update the descriptor. */
1350 uint64_t va = r600_resource(new_buf)->gpu_address + offset_within_buffer;
1351
1352 desc[0] = va;
1353 desc[1] = (desc[1] & C_008F04_BASE_ADDRESS_HI) |
1354 S_008F04_BASE_ADDRESS_HI(va >> 32);
1355 }
1356
1357 /* INTERNAL CONST BUFFERS */
1358
1359 static void si_set_polygon_stipple(struct pipe_context *ctx,
1360 const struct pipe_poly_stipple *state)
1361 {
1362 struct si_context *sctx = (struct si_context *)ctx;
1363 struct pipe_constant_buffer cb = {};
1364 unsigned stipple[32];
1365 int i;
1366
1367 for (i = 0; i < 32; i++)
1368 stipple[i] = util_bitreverse(state->stipple[i]);
1369
1370 cb.user_buffer = stipple;
1371 cb.buffer_size = sizeof(stipple);
1372
1373 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE, &cb);
1374 }
1375
1376 /* TEXTURE METADATA ENABLE/DISABLE */
1377
1378 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1379 * while the texture is bound, possibly by a different context. In that case,
1380 * call this function to update compressed_colortex_masks.
1381 */
1382 void si_update_compressed_colortex_masks(struct si_context *sctx)
1383 {
1384 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
1385 si_samplers_update_compressed_colortex_mask(&sctx->samplers[i]);
1386 si_images_update_compressed_colortex_mask(&sctx->images[i]);
1387 }
1388 }
1389
1390 /* BUFFER DISCARD/INVALIDATION */
1391
1392 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1393 static void si_reset_buffer_resources(struct si_context *sctx,
1394 struct si_buffer_resources *buffers,
1395 unsigned descriptors_idx,
1396 struct pipe_resource *buf,
1397 uint64_t old_va)
1398 {
1399 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
1400 unsigned mask = buffers->enabled_mask;
1401
1402 while (mask) {
1403 unsigned i = u_bit_scan(&mask);
1404 if (buffers->buffers[i] == buf) {
1405 si_desc_reset_buffer_offset(&sctx->b.b,
1406 descs->list + i*4,
1407 old_va, buf);
1408 descs->dirty_mask |= 1u << i;
1409 sctx->descriptors_dirty |= 1u << descriptors_idx;
1410
1411 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1412 (struct r600_resource *)buf,
1413 buffers->shader_usage,
1414 buffers->priority, true);
1415 }
1416 }
1417 }
1418
1419 /* Reallocate a buffer a update all resource bindings where the buffer is
1420 * bound.
1421 *
1422 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
1423 * idle by discarding its contents. Apps usually tell us when to do this using
1424 * map_buffer flags, for example.
1425 */
1426 static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
1427 {
1428 struct si_context *sctx = (struct si_context*)ctx;
1429 struct r600_resource *rbuffer = r600_resource(buf);
1430 unsigned i, shader, alignment = rbuffer->buf->alignment;
1431 uint64_t old_va = rbuffer->gpu_address;
1432 unsigned num_elems = sctx->vertex_elements ?
1433 sctx->vertex_elements->count : 0;
1434 struct si_sampler_view *view;
1435
1436 /* Reallocate the buffer in the same pipe_resource. */
1437 r600_init_resource(&sctx->screen->b, rbuffer, rbuffer->b.b.width0,
1438 alignment);
1439
1440 /* We changed the buffer, now we need to bind it where the old one
1441 * was bound. This consists of 2 things:
1442 * 1) Updating the resource descriptor and dirtying it.
1443 * 2) Adding a relocation to the CS, so that it's usable.
1444 */
1445
1446 /* Vertex buffers. */
1447 for (i = 0; i < num_elems; i++) {
1448 int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
1449
1450 if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
1451 continue;
1452 if (!sctx->vertex_buffer[vb].buffer)
1453 continue;
1454
1455 if (sctx->vertex_buffer[vb].buffer == buf) {
1456 sctx->vertex_buffers_dirty = true;
1457 break;
1458 }
1459 }
1460
1461 /* Streamout buffers. (other internal buffers can't be invalidated) */
1462 for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) {
1463 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1464 struct si_descriptors *descs =
1465 &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1466
1467 if (buffers->buffers[i] != buf)
1468 continue;
1469
1470 si_desc_reset_buffer_offset(ctx, descs->list + i*4,
1471 old_va, buf);
1472 descs->dirty_mask |= 1u << i;
1473 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1474
1475 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1476 rbuffer, buffers->shader_usage,
1477 buffers->priority, true);
1478
1479 /* Update the streamout state. */
1480 if (sctx->b.streamout.begin_emitted)
1481 r600_emit_streamout_end(&sctx->b);
1482 sctx->b.streamout.append_bitmask =
1483 sctx->b.streamout.enabled_mask;
1484 r600_streamout_buffers_dirty(&sctx->b);
1485 }
1486
1487 /* Constant and shader buffers. */
1488 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1489 si_reset_buffer_resources(sctx, &sctx->const_buffers[shader],
1490 si_const_buffer_descriptors_idx(shader),
1491 buf, old_va);
1492 si_reset_buffer_resources(sctx, &sctx->shader_buffers[shader],
1493 si_shader_buffer_descriptors_idx(shader),
1494 buf, old_va);
1495 }
1496
1497 /* Texture buffers - update virtual addresses in sampler view descriptors. */
1498 LIST_FOR_EACH_ENTRY(view, &sctx->b.texture_buffers, list) {
1499 if (view->base.texture == buf) {
1500 si_desc_reset_buffer_offset(ctx, &view->state[4], old_va, buf);
1501 }
1502 }
1503 /* Texture buffers - update bindings. */
1504 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1505 struct si_sampler_views *views = &sctx->samplers[shader].views;
1506 struct si_descriptors *descs =
1507 si_sampler_descriptors(sctx, shader);
1508 unsigned mask = views->enabled_mask;
1509
1510 while (mask) {
1511 unsigned i = u_bit_scan(&mask);
1512 if (views->views[i]->texture == buf) {
1513 si_desc_reset_buffer_offset(ctx,
1514 descs->list +
1515 i * 16 + 4,
1516 old_va, buf);
1517 descs->dirty_mask |= 1u << i;
1518 sctx->descriptors_dirty |=
1519 1u << si_sampler_descriptors_idx(shader);
1520
1521 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1522 rbuffer, RADEON_USAGE_READ,
1523 RADEON_PRIO_SAMPLER_BUFFER,
1524 true);
1525 }
1526 }
1527 }
1528
1529 /* Shader images */
1530 for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
1531 struct si_images_info *images = &sctx->images[shader];
1532 struct si_descriptors *descs =
1533 si_image_descriptors(sctx, shader);
1534 unsigned mask = images->enabled_mask;
1535
1536 while (mask) {
1537 unsigned i = u_bit_scan(&mask);
1538
1539 if (images->views[i].resource == buf) {
1540 if (images->views[i].access & PIPE_IMAGE_ACCESS_WRITE)
1541 si_mark_image_range_valid(&images->views[i]);
1542
1543 si_desc_reset_buffer_offset(
1544 ctx, descs->list + i * 8 + 4,
1545 old_va, buf);
1546 descs->dirty_mask |= 1u << i;
1547 sctx->descriptors_dirty |=
1548 1u << si_image_descriptors_idx(shader);
1549
1550 radeon_add_to_buffer_list_check_mem(
1551 &sctx->b, &sctx->b.gfx, rbuffer,
1552 RADEON_USAGE_READWRITE,
1553 RADEON_PRIO_SAMPLER_BUFFER, true);
1554 }
1555 }
1556 }
1557 }
1558
1559 /* Update mutable image descriptor fields of all bound textures. */
1560 void si_update_all_texture_descriptors(struct si_context *sctx)
1561 {
1562 unsigned shader;
1563
1564 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1565 struct si_sampler_views *samplers = &sctx->samplers[shader].views;
1566 struct si_images_info *images = &sctx->images[shader];
1567 unsigned mask;
1568
1569 /* Images. */
1570 mask = images->enabled_mask;
1571 while (mask) {
1572 unsigned i = u_bit_scan(&mask);
1573 struct pipe_image_view *view = &images->views[i];
1574
1575 if (!view->resource ||
1576 view->resource->target == PIPE_BUFFER)
1577 continue;
1578
1579 si_set_shader_image(sctx, shader, i, view);
1580 }
1581
1582 /* Sampler views. */
1583 mask = samplers->enabled_mask;
1584 while (mask) {
1585 unsigned i = u_bit_scan(&mask);
1586 struct pipe_sampler_view *view = samplers->views[i];
1587
1588 if (!view ||
1589 !view->texture ||
1590 view->texture->target == PIPE_BUFFER)
1591 continue;
1592
1593 si_set_sampler_view(sctx, shader, i,
1594 samplers->views[i], true);
1595 }
1596 }
1597 }
1598
1599 /* SHADER USER DATA */
1600
1601 static void si_mark_shader_pointers_dirty(struct si_context *sctx,
1602 unsigned shader)
1603 {
1604 struct si_descriptors *descs =
1605 &sctx->descriptors[SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS];
1606
1607 for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs)
1608 descs->pointer_dirty = true;
1609
1610 if (shader == PIPE_SHADER_VERTEX)
1611 sctx->vertex_buffers.pointer_dirty = true;
1612
1613 si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
1614 }
1615
1616 static void si_shader_userdata_begin_new_cs(struct si_context *sctx)
1617 {
1618 int i;
1619
1620 for (i = 0; i < SI_NUM_SHADERS; i++) {
1621 si_mark_shader_pointers_dirty(sctx, i);
1622 }
1623 sctx->descriptors[SI_DESCS_RW_BUFFERS].pointer_dirty = true;
1624 }
1625
1626 /* Set a base register address for user data constants in the given shader.
1627 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1628 */
1629 static void si_set_user_data_base(struct si_context *sctx,
1630 unsigned shader, uint32_t new_base)
1631 {
1632 uint32_t *base = &sctx->shader_userdata.sh_base[shader];
1633
1634 if (*base != new_base) {
1635 *base = new_base;
1636
1637 if (new_base)
1638 si_mark_shader_pointers_dirty(sctx, shader);
1639 }
1640 }
1641
1642 /* This must be called when these shaders are changed from non-NULL to NULL
1643 * and vice versa:
1644 * - geometry shader
1645 * - tessellation control shader
1646 * - tessellation evaluation shader
1647 */
1648 void si_shader_change_notify(struct si_context *sctx)
1649 {
1650 /* VS can be bound as VS, ES, or LS. */
1651 if (sctx->tes_shader.cso)
1652 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1653 R_00B530_SPI_SHADER_USER_DATA_LS_0);
1654 else if (sctx->gs_shader.cso)
1655 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1656 R_00B330_SPI_SHADER_USER_DATA_ES_0);
1657 else
1658 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1659 R_00B130_SPI_SHADER_USER_DATA_VS_0);
1660
1661 /* TES can be bound as ES, VS, or not bound. */
1662 if (sctx->tes_shader.cso) {
1663 if (sctx->gs_shader.cso)
1664 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
1665 R_00B330_SPI_SHADER_USER_DATA_ES_0);
1666 else
1667 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
1668 R_00B130_SPI_SHADER_USER_DATA_VS_0);
1669 } else {
1670 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, 0);
1671 }
1672 }
1673
1674 static void si_emit_shader_pointer(struct si_context *sctx,
1675 struct si_descriptors *desc,
1676 unsigned sh_base, bool keep_dirty)
1677 {
1678 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1679 uint64_t va;
1680
1681 if (!desc->pointer_dirty || !desc->buffer)
1682 return;
1683
1684 va = desc->buffer->gpu_address +
1685 desc->buffer_offset;
1686
1687 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0));
1688 radeon_emit(cs, (sh_base + desc->shader_userdata_offset - SI_SH_REG_OFFSET) >> 2);
1689 radeon_emit(cs, va);
1690 radeon_emit(cs, va >> 32);
1691
1692 desc->pointer_dirty = keep_dirty;
1693 }
1694
1695 void si_emit_graphics_shader_userdata(struct si_context *sctx,
1696 struct r600_atom *atom)
1697 {
1698 unsigned shader;
1699 uint32_t *sh_base = sctx->shader_userdata.sh_base;
1700 struct si_descriptors *descs;
1701
1702 descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1703
1704 if (descs->pointer_dirty) {
1705 si_emit_shader_pointer(sctx, descs,
1706 R_00B030_SPI_SHADER_USER_DATA_PS_0, true);
1707 si_emit_shader_pointer(sctx, descs,
1708 R_00B130_SPI_SHADER_USER_DATA_VS_0, true);
1709 si_emit_shader_pointer(sctx, descs,
1710 R_00B230_SPI_SHADER_USER_DATA_GS_0, true);
1711 si_emit_shader_pointer(sctx, descs,
1712 R_00B330_SPI_SHADER_USER_DATA_ES_0, true);
1713 si_emit_shader_pointer(sctx, descs,
1714 R_00B430_SPI_SHADER_USER_DATA_HS_0, true);
1715 descs->pointer_dirty = false;
1716 }
1717
1718 descs = &sctx->descriptors[SI_DESCS_FIRST_SHADER];
1719
1720 for (shader = 0; shader < SI_NUM_GRAPHICS_SHADERS; shader++) {
1721 unsigned base = sh_base[shader];
1722 unsigned i;
1723
1724 if (!base)
1725 continue;
1726
1727 for (i = 0; i < SI_NUM_SHADER_DESCS; i++, descs++)
1728 si_emit_shader_pointer(sctx, descs, base, false);
1729 }
1730 si_emit_shader_pointer(sctx, &sctx->vertex_buffers, sh_base[PIPE_SHADER_VERTEX], false);
1731 }
1732
1733 void si_emit_compute_shader_userdata(struct si_context *sctx)
1734 {
1735 unsigned base = R_00B900_COMPUTE_USER_DATA_0;
1736 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_FIRST_COMPUTE];
1737
1738 for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs)
1739 si_emit_shader_pointer(sctx, descs, base, false);
1740 }
1741
1742 /* INIT/DEINIT/UPLOAD */
1743
1744 void si_init_all_descriptors(struct si_context *sctx)
1745 {
1746 int i;
1747 unsigned ce_offset = 0;
1748
1749 for (i = 0; i < SI_NUM_SHADERS; i++) {
1750 si_init_buffer_resources(&sctx->const_buffers[i],
1751 si_const_buffer_descriptors(sctx, i),
1752 SI_NUM_CONST_BUFFERS, SI_SGPR_CONST_BUFFERS,
1753 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER,
1754 &ce_offset);
1755 si_init_buffer_resources(&sctx->shader_buffers[i],
1756 si_shader_buffer_descriptors(sctx, i),
1757 SI_NUM_SHADER_BUFFERS, SI_SGPR_SHADER_BUFFERS,
1758 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RW_BUFFER,
1759 &ce_offset);
1760
1761 si_init_descriptors(si_sampler_descriptors(sctx, i),
1762 SI_SGPR_SAMPLERS, 16, SI_NUM_SAMPLERS,
1763 null_texture_descriptor, &ce_offset);
1764
1765 si_init_descriptors(si_image_descriptors(sctx, i),
1766 SI_SGPR_IMAGES, 8, SI_NUM_IMAGES,
1767 null_image_descriptor, &ce_offset);
1768 }
1769
1770 si_init_buffer_resources(&sctx->rw_buffers,
1771 &sctx->descriptors[SI_DESCS_RW_BUFFERS],
1772 SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS,
1773 RADEON_USAGE_READWRITE, RADEON_PRIO_RINGS_STREAMOUT,
1774 &ce_offset);
1775 si_init_descriptors(&sctx->vertex_buffers, SI_SGPR_VERTEX_BUFFERS,
1776 4, SI_NUM_VERTEX_BUFFERS, NULL, NULL);
1777
1778 sctx->descriptors_dirty = u_bit_consecutive(0, SI_NUM_DESCS);
1779
1780 assert(ce_offset <= 32768);
1781
1782 /* Set pipe_context functions. */
1783 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
1784 sctx->b.b.set_shader_images = si_set_shader_images;
1785 sctx->b.b.set_constant_buffer = si_pipe_set_constant_buffer;
1786 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
1787 sctx->b.b.set_shader_buffers = si_set_shader_buffers;
1788 sctx->b.b.set_sampler_views = si_set_sampler_views;
1789 sctx->b.b.set_stream_output_targets = si_set_streamout_targets;
1790 sctx->b.invalidate_buffer = si_invalidate_buffer;
1791
1792 /* Shader user data. */
1793 si_init_atom(sctx, &sctx->shader_userdata.atom, &sctx->atoms.s.shader_userdata,
1794 si_emit_graphics_shader_userdata);
1795
1796 /* Set default and immutable mappings. */
1797 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
1798 si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, R_00B430_SPI_SHADER_USER_DATA_HS_0);
1799 si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, R_00B230_SPI_SHADER_USER_DATA_GS_0);
1800 si_set_user_data_base(sctx, PIPE_SHADER_FRAGMENT, R_00B030_SPI_SHADER_USER_DATA_PS_0);
1801 }
1802
1803 bool si_upload_graphics_shader_descriptors(struct si_context *sctx)
1804 {
1805 const unsigned mask = u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE);
1806 unsigned dirty = sctx->descriptors_dirty & mask;
1807
1808 while (dirty) {
1809 unsigned i = u_bit_scan(&dirty);
1810
1811 if (!si_upload_descriptors(sctx, &sctx->descriptors[i],
1812 &sctx->shader_userdata.atom))
1813 return false;
1814 }
1815
1816 sctx->descriptors_dirty &= ~mask;
1817 return true;
1818 }
1819
1820 bool si_upload_compute_shader_descriptors(struct si_context *sctx)
1821 {
1822 /* Does not update rw_buffers as that is not needed for compute shaders
1823 * and the input buffer is using the same SGPR's anyway.
1824 */
1825 const unsigned mask = u_bit_consecutive(SI_DESCS_FIRST_COMPUTE,
1826 SI_NUM_DESCS - SI_DESCS_FIRST_COMPUTE);
1827 unsigned dirty = sctx->descriptors_dirty & mask;
1828
1829 while (dirty) {
1830 unsigned i = u_bit_scan(&dirty);
1831
1832 if (!si_upload_descriptors(sctx, &sctx->descriptors[i], NULL))
1833 return false;
1834 }
1835
1836 sctx->descriptors_dirty &= ~mask;
1837
1838 return true;
1839 }
1840
1841 void si_release_all_descriptors(struct si_context *sctx)
1842 {
1843 int i;
1844
1845 for (i = 0; i < SI_NUM_SHADERS; i++) {
1846 si_release_buffer_resources(&sctx->const_buffers[i],
1847 si_const_buffer_descriptors(sctx, i));
1848 si_release_buffer_resources(&sctx->shader_buffers[i],
1849 si_shader_buffer_descriptors(sctx, i));
1850 si_release_sampler_views(&sctx->samplers[i].views);
1851 si_release_image_views(&sctx->images[i]);
1852 }
1853 si_release_buffer_resources(&sctx->rw_buffers,
1854 &sctx->descriptors[SI_DESCS_RW_BUFFERS]);
1855
1856 for (i = 0; i < SI_NUM_DESCS; ++i)
1857 si_release_descriptors(&sctx->descriptors[i]);
1858 si_release_descriptors(&sctx->vertex_buffers);
1859 }
1860
1861 void si_all_descriptors_begin_new_cs(struct si_context *sctx)
1862 {
1863 int i;
1864
1865 for (i = 0; i < SI_NUM_SHADERS; i++) {
1866 si_buffer_resources_begin_new_cs(sctx, &sctx->const_buffers[i]);
1867 si_buffer_resources_begin_new_cs(sctx, &sctx->shader_buffers[i]);
1868 si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i].views);
1869 si_image_views_begin_new_cs(sctx, &sctx->images[i]);
1870 }
1871 si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers);
1872 si_vertex_buffers_begin_new_cs(sctx);
1873
1874 for (i = 0; i < SI_NUM_DESCS; ++i)
1875 si_descriptors_begin_new_cs(sctx, &sctx->descriptors[i]);
1876
1877 si_shader_userdata_begin_new_cs(sctx);
1878 }