2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 /* Resource binding slots and sampler states (each described with 8 or
25 * 4 dwords) are stored in lists in memory which is accessed by shaders
26 * using scalar load instructions.
28 * This file is responsible for managing such lists. It keeps a copy of all
29 * descriptors in CPU memory and re-uploads a whole list if some slots have
32 * This code is also reponsible for updating shader pointers to those lists.
34 * Note that CP DMA can't be used for updating the lists, because a GPU hang
35 * could leave the list in a mid-IB state and the next IB would get wrong
36 * descriptors and the whole context would be unusable at that point.
37 * (Note: The register shadowing can't be used due to the same reason)
39 * Also, uploading descriptors to newly allocated memory doesn't require
43 * Possible scenarios for one 16 dword image+sampler slot:
45 * | Image | w/ FMASK | Buffer | NULL
46 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
47 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
48 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
49 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
51 * FMASK implies MSAA, therefore no sampler state.
52 * Sampler states are never unbound except when FMASK is bound.
55 #include "radeon/r600_cs.h"
60 #include "util/hash_table.h"
61 #include "util/u_idalloc.h"
62 #include "util/u_format.h"
63 #include "util/u_memory.h"
64 #include "util/u_upload_mgr.h"
67 /* NULL image and buffer descriptor for textures (alpha = 1) and images
70 * For images, all fields must be zero except for the swizzle, which
71 * supports arbitrary combinations of 0s and 1s. The texture type must be
72 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
74 * For buffers, all fields must be zero. If they are not, the hw hangs.
76 * This is the only reason why the buffer descriptor must be in words [4:7].
78 static uint32_t null_texture_descriptor
[8] = {
82 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) |
83 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
84 /* the rest must contain zeros, which is also used by the buffer
88 static uint32_t null_image_descriptor
[8] = {
92 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
93 /* the rest must contain zeros, which is also used by the buffer
97 static uint64_t si_desc_extract_buffer_address(uint32_t *desc
)
99 return desc
[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
102 static void si_init_descriptor_list(uint32_t *desc_list
,
103 unsigned element_dw_size
,
104 unsigned num_elements
,
105 const uint32_t *null_descriptor
)
109 /* Initialize the array to NULL descriptors if the element size is 8. */
110 if (null_descriptor
) {
111 assert(element_dw_size
% 8 == 0);
112 for (i
= 0; i
< num_elements
* element_dw_size
/ 8; i
++)
113 memcpy(desc_list
+ i
* 8, null_descriptor
, 8 * 4);
117 static void si_init_descriptors(struct si_descriptors
*desc
,
118 unsigned shader_userdata_index
,
119 unsigned element_dw_size
,
120 unsigned num_elements
)
122 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
123 desc
->element_dw_size
= element_dw_size
;
124 desc
->num_elements
= num_elements
;
125 desc
->shader_userdata_offset
= shader_userdata_index
* 4;
126 desc
->slot_index_to_bind_directly
= -1;
129 static void si_release_descriptors(struct si_descriptors
*desc
)
131 r600_resource_reference(&desc
->buffer
, NULL
);
135 static bool si_upload_descriptors(struct si_context
*sctx
,
136 struct si_descriptors
*desc
)
138 unsigned slot_size
= desc
->element_dw_size
* 4;
139 unsigned first_slot_offset
= desc
->first_active_slot
* slot_size
;
140 unsigned upload_size
= desc
->num_active_slots
* slot_size
;
142 /* Skip the upload if no shader is using the descriptors. dirty_mask
143 * will stay dirty and the descriptors will be uploaded when there is
144 * a shader using them.
149 /* If there is just one active descriptor, bind it directly. */
150 if ((int)desc
->first_active_slot
== desc
->slot_index_to_bind_directly
&&
151 desc
->num_active_slots
== 1) {
152 uint32_t *descriptor
= &desc
->list
[desc
->slot_index_to_bind_directly
*
153 desc
->element_dw_size
];
155 /* The buffer is already in the buffer list. */
156 r600_resource_reference(&desc
->buffer
, NULL
);
157 desc
->gpu_list
= NULL
;
158 desc
->gpu_address
= si_desc_extract_buffer_address(descriptor
);
159 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
165 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, upload_size
,
166 si_optimal_tcc_alignment(sctx
, upload_size
),
167 (unsigned*)&buffer_offset
,
168 (struct pipe_resource
**)&desc
->buffer
,
171 desc
->gpu_address
= 0;
172 return false; /* skip the draw call */
175 util_memcpy_cpu_to_le32(ptr
, (char*)desc
->list
+ first_slot_offset
,
177 desc
->gpu_list
= ptr
- first_slot_offset
/ 4;
179 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
180 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
182 /* The shader pointer should point to slot 0. */
183 buffer_offset
-= first_slot_offset
;
184 desc
->gpu_address
= desc
->buffer
->gpu_address
+ buffer_offset
;
186 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
191 si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
196 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
197 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
203 si_sampler_and_image_descriptors_idx(unsigned shader
)
205 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
206 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
;
209 static struct si_descriptors
*
210 si_sampler_and_image_descriptors(struct si_context
*sctx
, unsigned shader
)
212 return &sctx
->descriptors
[si_sampler_and_image_descriptors_idx(shader
)];
215 static void si_release_sampler_views(struct si_samplers
*samplers
)
219 for (i
= 0; i
< ARRAY_SIZE(samplers
->views
); i
++) {
220 pipe_sampler_view_reference(&samplers
->views
[i
], NULL
);
224 static void si_sampler_view_add_buffer(struct si_context
*sctx
,
225 struct pipe_resource
*resource
,
226 enum radeon_bo_usage usage
,
227 bool is_stencil_sampler
,
230 struct r600_resource
*rres
;
231 struct r600_texture
*rtex
;
232 enum radeon_bo_priority priority
;
237 if (resource
->target
!= PIPE_BUFFER
) {
238 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
240 if (tex
->is_depth
&& !r600_can_sample_zs(tex
, is_stencil_sampler
))
241 resource
= &tex
->flushed_depth_texture
->resource
.b
.b
;
244 rres
= (struct r600_resource
*)resource
;
245 priority
= r600_get_sampler_view_priority(rres
);
247 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
248 rres
, usage
, priority
,
251 if (resource
->target
== PIPE_BUFFER
)
254 /* Now add separate DCC or HTILE. */
255 rtex
= (struct r600_texture
*)resource
;
256 if (rtex
->dcc_separate_buffer
) {
257 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
258 rtex
->dcc_separate_buffer
, usage
,
259 RADEON_PRIO_DCC
, check_mem
);
263 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
,
264 struct si_samplers
*samplers
)
266 unsigned mask
= samplers
->enabled_mask
;
268 /* Add buffers to the CS. */
270 int i
= u_bit_scan(&mask
);
271 struct si_sampler_view
*sview
= (struct si_sampler_view
*)samplers
->views
[i
];
273 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
275 sview
->is_stencil_sampler
, false);
279 /* Set buffer descriptor fields that can be changed by reallocations. */
280 static void si_set_buf_desc_address(struct r600_resource
*buf
,
281 uint64_t offset
, uint32_t *state
)
283 uint64_t va
= buf
->gpu_address
+ offset
;
286 state
[1] &= C_008F04_BASE_ADDRESS_HI
;
287 state
[1] |= S_008F04_BASE_ADDRESS_HI(va
>> 32);
290 /* Set texture descriptor fields that can be changed by reallocations.
293 * \param base_level_info information of the level of BASE_ADDRESS
294 * \param base_level the level of BASE_ADDRESS
295 * \param first_level pipe_sampler_view.u.tex.first_level
296 * \param block_width util_format_get_blockwidth()
297 * \param is_stencil select between separate Z & Stencil
298 * \param state descriptor to update
300 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
301 struct r600_texture
*tex
,
302 const struct legacy_surf_level
*base_level_info
,
303 unsigned base_level
, unsigned first_level
,
304 unsigned block_width
, bool is_stencil
,
307 uint64_t va
, meta_va
= 0;
309 if (tex
->is_depth
&& !r600_can_sample_zs(tex
, is_stencil
)) {
310 tex
= tex
->flushed_depth_texture
;
314 va
= tex
->resource
.gpu_address
;
316 if (sscreen
->b
.chip_class
>= GFX9
) {
317 /* Only stencil_offset needs to be added here. */
319 va
+= tex
->surface
.u
.gfx9
.stencil_offset
;
321 va
+= tex
->surface
.u
.gfx9
.surf_offset
;
323 va
+= base_level_info
->offset
;
327 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
328 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
330 /* Only macrotiled modes can set tile swizzle.
331 * GFX9 doesn't use (legacy) base_level_info.
333 if (sscreen
->b
.chip_class
>= GFX9
||
334 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
335 state
[0] |= tex
->surface
.tile_swizzle
;
337 if (sscreen
->b
.chip_class
>= VI
) {
338 state
[6] &= C_008F28_COMPRESSION_EN
;
341 if (vi_dcc_enabled(tex
, first_level
)) {
342 meta_va
= (!tex
->dcc_separate_buffer
? tex
->resource
.gpu_address
: 0) +
345 if (sscreen
->b
.chip_class
== VI
) {
346 meta_va
+= base_level_info
->dcc_offset
;
347 assert(base_level_info
->mode
== RADEON_SURF_MODE_2D
);
350 meta_va
|= (uint32_t)tex
->surface
.tile_swizzle
<< 8;
351 } else if (vi_tc_compat_htile_enabled(tex
, first_level
)) {
352 meta_va
= tex
->resource
.gpu_address
+ tex
->htile_offset
;
356 state
[6] |= S_008F28_COMPRESSION_EN(1);
357 state
[7] = meta_va
>> 8;
361 if (sscreen
->b
.chip_class
>= GFX9
) {
362 state
[3] &= C_008F1C_SW_MODE
;
363 state
[4] &= C_008F20_PITCH_GFX9
;
366 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
367 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.stencil
.epitch
);
369 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
370 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.surf
.epitch
);
373 state
[5] &= C_008F24_META_DATA_ADDRESS
&
374 C_008F24_META_PIPE_ALIGNED
&
375 C_008F24_META_RB_ALIGNED
;
377 struct gfx9_surf_meta_flags meta
;
380 meta
= tex
->surface
.u
.gfx9
.dcc
;
382 meta
= tex
->surface
.u
.gfx9
.htile
;
384 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
385 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
386 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
390 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
391 unsigned index
= si_tile_mode_index(tex
, base_level
, is_stencil
);
393 state
[3] &= C_008F1C_TILING_INDEX
;
394 state
[3] |= S_008F1C_TILING_INDEX(index
);
395 state
[4] &= C_008F20_PITCH_GFX6
;
396 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
400 static void si_set_sampler_state_desc(struct si_sampler_state
*sstate
,
401 struct si_sampler_view
*sview
,
402 struct r600_texture
*tex
,
405 if (sview
&& sview
->is_integer
)
406 memcpy(desc
, sstate
->integer_val
, 4*4);
407 else if (tex
&& tex
->upgraded_depth
&&
408 (!sview
|| !sview
->is_stencil_sampler
))
409 memcpy(desc
, sstate
->upgraded_depth_val
, 4*4);
411 memcpy(desc
, sstate
->val
, 4*4);
414 static void si_set_sampler_view_desc(struct si_context
*sctx
,
415 struct si_sampler_view
*sview
,
416 struct si_sampler_state
*sstate
,
419 struct pipe_sampler_view
*view
= &sview
->base
;
420 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
421 bool is_buffer
= rtex
->resource
.b
.b
.target
== PIPE_BUFFER
;
423 if (unlikely(!is_buffer
&& sview
->dcc_incompatible
)) {
424 if (vi_dcc_enabled(rtex
, view
->u
.tex
.first_level
))
425 if (!si_texture_disable_dcc(&sctx
->b
, rtex
))
426 sctx
->b
.decompress_dcc(&sctx
->b
.b
, rtex
);
428 sview
->dcc_incompatible
= false;
431 assert(rtex
); /* views with texture == NULL aren't supported */
432 memcpy(desc
, sview
->state
, 8*4);
435 si_set_buf_desc_address(&rtex
->resource
,
436 sview
->base
.u
.buf
.offset
,
439 bool is_separate_stencil
= rtex
->db_compatible
&&
440 sview
->is_stencil_sampler
;
442 si_set_mutable_tex_desc_fields(sctx
->screen
, rtex
,
443 sview
->base_level_info
,
445 sview
->base
.u
.tex
.first_level
,
451 if (!is_buffer
&& rtex
->fmask
.size
) {
452 memcpy(desc
+ 8, sview
->fmask_state
, 8*4);
454 /* Disable FMASK and bind sampler state in [12:15]. */
455 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
458 si_set_sampler_state_desc(sstate
, sview
,
459 is_buffer
? NULL
: rtex
,
464 static bool color_needs_decompression(struct r600_texture
*rtex
)
466 return rtex
->fmask
.size
||
467 (rtex
->dirty_level_mask
&&
468 (rtex
->cmask
.size
|| rtex
->dcc_offset
));
471 static bool depth_needs_decompression(struct r600_texture
*rtex
)
473 /* If the depth/stencil texture is TC-compatible, no decompression
474 * will be done. The decompression function will only flush DB caches
475 * to make it coherent with shaders. That's necessary because the driver
476 * doesn't flush DB caches in any other case.
478 return rtex
->db_compatible
;
481 static void si_set_sampler_view(struct si_context
*sctx
,
483 unsigned slot
, struct pipe_sampler_view
*view
,
484 bool disallow_early_out
)
486 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
487 struct si_sampler_view
*rview
= (struct si_sampler_view
*)view
;
488 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
489 unsigned desc_slot
= si_get_sampler_slot(slot
);
490 uint32_t *desc
= descs
->list
+ desc_slot
* 16;
492 if (samplers
->views
[slot
] == view
&& !disallow_early_out
)
496 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
498 si_set_sampler_view_desc(sctx
, rview
,
499 samplers
->sampler_states
[slot
], desc
);
501 if (rtex
->resource
.b
.b
.target
== PIPE_BUFFER
) {
502 rtex
->resource
.bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
503 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
504 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
506 if (depth_needs_decompression(rtex
)) {
507 samplers
->needs_depth_decompress_mask
|= 1u << slot
;
509 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
511 if (color_needs_decompression(rtex
)) {
512 samplers
->needs_color_decompress_mask
|= 1u << slot
;
514 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
517 if (rtex
->dcc_offset
&&
518 p_atomic_read(&rtex
->framebuffers_bound
))
519 sctx
->need_check_render_feedback
= true;
522 pipe_sampler_view_reference(&samplers
->views
[slot
], view
);
523 samplers
->enabled_mask
|= 1u << slot
;
525 /* Since this can flush, it must be done after enabled_mask is
527 si_sampler_view_add_buffer(sctx
, view
->texture
,
529 rview
->is_stencil_sampler
, true);
531 pipe_sampler_view_reference(&samplers
->views
[slot
], NULL
);
532 memcpy(desc
, null_texture_descriptor
, 8*4);
533 /* Only clear the lower dwords of FMASK. */
534 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
535 /* Re-set the sampler state if we are transitioning from FMASK. */
536 if (samplers
->sampler_states
[slot
])
537 si_set_sampler_state_desc(samplers
->sampler_states
[slot
], NULL
, NULL
,
540 samplers
->enabled_mask
&= ~(1u << slot
);
541 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
542 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
545 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
548 static void si_update_shader_needs_decompress_mask(struct si_context
*sctx
,
551 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
552 unsigned shader_bit
= 1 << shader
;
554 if (samplers
->needs_depth_decompress_mask
||
555 samplers
->needs_color_decompress_mask
||
556 sctx
->images
[shader
].needs_color_decompress_mask
)
557 sctx
->shader_needs_decompress_mask
|= shader_bit
;
559 sctx
->shader_needs_decompress_mask
&= ~shader_bit
;
562 static void si_set_sampler_views(struct pipe_context
*ctx
,
563 enum pipe_shader_type shader
, unsigned start
,
565 struct pipe_sampler_view
**views
)
567 struct si_context
*sctx
= (struct si_context
*)ctx
;
570 if (!count
|| shader
>= SI_NUM_SHADERS
)
574 for (i
= 0; i
< count
; i
++)
575 si_set_sampler_view(sctx
, shader
, start
+ i
, views
[i
], false);
577 for (i
= 0; i
< count
; i
++)
578 si_set_sampler_view(sctx
, shader
, start
+ i
, NULL
, false);
581 si_update_shader_needs_decompress_mask(sctx
, shader
);
585 si_samplers_update_needs_color_decompress_mask(struct si_samplers
*samplers
)
587 unsigned mask
= samplers
->enabled_mask
;
590 int i
= u_bit_scan(&mask
);
591 struct pipe_resource
*res
= samplers
->views
[i
]->texture
;
593 if (res
&& res
->target
!= PIPE_BUFFER
) {
594 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
596 if (color_needs_decompression(rtex
)) {
597 samplers
->needs_color_decompress_mask
|= 1u << i
;
599 samplers
->needs_color_decompress_mask
&= ~(1u << i
);
608 si_release_image_views(struct si_images
*images
)
612 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
613 struct pipe_image_view
*view
= &images
->views
[i
];
615 pipe_resource_reference(&view
->resource
, NULL
);
620 si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images
*images
)
622 uint mask
= images
->enabled_mask
;
624 /* Add buffers to the CS. */
626 int i
= u_bit_scan(&mask
);
627 struct pipe_image_view
*view
= &images
->views
[i
];
629 assert(view
->resource
);
631 si_sampler_view_add_buffer(sctx
, view
->resource
,
632 RADEON_USAGE_READWRITE
, false, false);
637 si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
639 struct si_images
*images
= &ctx
->images
[shader
];
641 if (images
->enabled_mask
& (1u << slot
)) {
642 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
643 unsigned desc_slot
= si_get_image_slot(slot
);
645 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
646 images
->needs_color_decompress_mask
&= ~(1 << slot
);
648 memcpy(descs
->list
+ desc_slot
*8, null_image_descriptor
, 8*4);
649 images
->enabled_mask
&= ~(1u << slot
);
650 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
655 si_mark_image_range_valid(const struct pipe_image_view
*view
)
657 struct r600_resource
*res
= (struct r600_resource
*)view
->resource
;
659 assert(res
&& res
->b
.b
.target
== PIPE_BUFFER
);
661 util_range_add(&res
->valid_buffer_range
,
663 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
666 static void si_set_shader_image_desc(struct si_context
*ctx
,
667 const struct pipe_image_view
*view
,
668 bool skip_decompress
,
671 struct si_screen
*screen
= ctx
->screen
;
672 struct r600_resource
*res
;
674 res
= (struct r600_resource
*)view
->resource
;
676 if (res
->b
.b
.target
== PIPE_BUFFER
) {
677 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
678 si_mark_image_range_valid(view
);
680 si_make_buffer_descriptor(screen
, res
,
683 view
->u
.buf
.size
, desc
);
684 si_set_buf_desc_address(res
, view
->u
.buf
.offset
, desc
+ 4);
686 static const unsigned char swizzle
[4] = { 0, 1, 2, 3 };
687 struct r600_texture
*tex
= (struct r600_texture
*)res
;
688 unsigned level
= view
->u
.tex
.level
;
689 unsigned width
, height
, depth
, hw_level
;
690 bool uses_dcc
= vi_dcc_enabled(tex
, level
);
692 assert(!tex
->is_depth
);
693 assert(tex
->fmask
.size
== 0);
695 if (uses_dcc
&& !skip_decompress
&&
696 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
||
697 !vi_dcc_formats_compatible(res
->b
.b
.format
, view
->format
))) {
698 /* If DCC can't be disabled, at least decompress it.
699 * The decompression is relatively cheap if the surface
700 * has been decompressed already.
702 if (!si_texture_disable_dcc(&ctx
->b
, tex
))
703 ctx
->b
.decompress_dcc(&ctx
->b
.b
, tex
);
706 if (ctx
->b
.chip_class
>= GFX9
) {
707 /* Always set the base address. The swizzle modes don't
708 * allow setting mipmap level offsets as the base.
710 width
= res
->b
.b
.width0
;
711 height
= res
->b
.b
.height0
;
712 depth
= res
->b
.b
.depth0
;
715 /* Always force the base level to the selected level.
717 * This is required for 3D textures, where otherwise
718 * selecting a single slice for non-layered bindings
719 * fails. It doesn't hurt the other targets.
721 width
= u_minify(res
->b
.b
.width0
, level
);
722 height
= u_minify(res
->b
.b
.height0
, level
);
723 depth
= u_minify(res
->b
.b
.depth0
, level
);
727 si_make_texture_descriptor(screen
, tex
,
728 false, res
->b
.b
.target
,
729 view
->format
, swizzle
,
731 view
->u
.tex
.first_layer
,
732 view
->u
.tex
.last_layer
,
733 width
, height
, depth
,
735 si_set_mutable_tex_desc_fields(screen
, tex
,
736 &tex
->surface
.u
.legacy
.level
[level
],
738 util_format_get_blockwidth(view
->format
),
743 static void si_set_shader_image(struct si_context
*ctx
,
745 unsigned slot
, const struct pipe_image_view
*view
,
746 bool skip_decompress
)
748 struct si_images
*images
= &ctx
->images
[shader
];
749 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
750 struct r600_resource
*res
;
751 unsigned desc_slot
= si_get_image_slot(slot
);
752 uint32_t *desc
= descs
->list
+ desc_slot
* 8;
754 if (!view
|| !view
->resource
) {
755 si_disable_shader_image(ctx
, shader
, slot
);
759 res
= (struct r600_resource
*)view
->resource
;
761 if (&images
->views
[slot
] != view
)
762 util_copy_image_view(&images
->views
[slot
], view
);
764 si_set_shader_image_desc(ctx
, view
, skip_decompress
, desc
);
766 if (res
->b
.b
.target
== PIPE_BUFFER
) {
767 images
->needs_color_decompress_mask
&= ~(1 << slot
);
768 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
770 struct r600_texture
*tex
= (struct r600_texture
*)res
;
771 unsigned level
= view
->u
.tex
.level
;
773 if (color_needs_decompression(tex
)) {
774 images
->needs_color_decompress_mask
|= 1 << slot
;
776 images
->needs_color_decompress_mask
&= ~(1 << slot
);
779 if (vi_dcc_enabled(tex
, level
) &&
780 p_atomic_read(&tex
->framebuffers_bound
))
781 ctx
->need_check_render_feedback
= true;
784 images
->enabled_mask
|= 1u << slot
;
785 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
787 /* Since this can flush, it must be done after enabled_mask is updated. */
788 si_sampler_view_add_buffer(ctx
, &res
->b
.b
,
789 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
) ?
790 RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
,
795 si_set_shader_images(struct pipe_context
*pipe
,
796 enum pipe_shader_type shader
,
797 unsigned start_slot
, unsigned count
,
798 const struct pipe_image_view
*views
)
800 struct si_context
*ctx
= (struct si_context
*)pipe
;
803 assert(shader
< SI_NUM_SHADERS
);
808 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
811 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
812 si_set_shader_image(ctx
, shader
, slot
, &views
[i
], false);
814 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
815 si_set_shader_image(ctx
, shader
, slot
, NULL
, false);
818 si_update_shader_needs_decompress_mask(ctx
, shader
);
822 si_images_update_needs_color_decompress_mask(struct si_images
*images
)
824 unsigned mask
= images
->enabled_mask
;
827 int i
= u_bit_scan(&mask
);
828 struct pipe_resource
*res
= images
->views
[i
].resource
;
830 if (res
&& res
->target
!= PIPE_BUFFER
) {
831 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
833 if (color_needs_decompression(rtex
)) {
834 images
->needs_color_decompress_mask
|= 1 << i
;
836 images
->needs_color_decompress_mask
&= ~(1 << i
);
844 static void si_bind_sampler_states(struct pipe_context
*ctx
,
845 enum pipe_shader_type shader
,
846 unsigned start
, unsigned count
, void **states
)
848 struct si_context
*sctx
= (struct si_context
*)ctx
;
849 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
850 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, shader
);
851 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
854 if (!count
|| shader
>= SI_NUM_SHADERS
)
857 for (i
= 0; i
< count
; i
++) {
858 unsigned slot
= start
+ i
;
859 unsigned desc_slot
= si_get_sampler_slot(slot
);
862 sstates
[i
] == samplers
->sampler_states
[slot
])
866 assert(sstates
[i
]->magic
== SI_SAMPLER_STATE_MAGIC
);
868 samplers
->sampler_states
[slot
] = sstates
[i
];
870 /* If FMASK is bound, don't overwrite it.
871 * The sampler state will be set after FMASK is unbound.
873 struct si_sampler_view
*sview
=
874 (struct si_sampler_view
*)samplers
->views
[slot
];
876 struct r600_texture
*tex
= NULL
;
878 if (sview
&& sview
->base
.texture
&&
879 sview
->base
.texture
->target
!= PIPE_BUFFER
)
880 tex
= (struct r600_texture
*)sview
->base
.texture
;
882 if (tex
&& tex
->fmask
.size
)
885 si_set_sampler_state_desc(sstates
[i
], sview
, tex
,
886 desc
->list
+ desc_slot
* 16 + 12);
888 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
892 /* BUFFER RESOURCES */
894 static void si_init_buffer_resources(struct si_buffer_resources
*buffers
,
895 struct si_descriptors
*descs
,
896 unsigned num_buffers
,
897 unsigned shader_userdata_index
,
898 enum radeon_bo_usage shader_usage
,
899 enum radeon_bo_usage shader_usage_constbuf
,
900 enum radeon_bo_priority priority
,
901 enum radeon_bo_priority priority_constbuf
)
903 buffers
->shader_usage
= shader_usage
;
904 buffers
->shader_usage_constbuf
= shader_usage_constbuf
;
905 buffers
->priority
= priority
;
906 buffers
->priority_constbuf
= priority_constbuf
;
907 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
909 si_init_descriptors(descs
, shader_userdata_index
, 4, num_buffers
);
912 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
913 struct si_descriptors
*descs
)
917 for (i
= 0; i
< descs
->num_elements
; i
++) {
918 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
921 FREE(buffers
->buffers
);
924 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
925 struct si_buffer_resources
*buffers
)
927 unsigned mask
= buffers
->enabled_mask
;
929 /* Add buffers to the CS. */
931 int i
= u_bit_scan(&mask
);
933 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
934 r600_resource(buffers
->buffers
[i
]),
935 i
< SI_NUM_SHADER_BUFFERS
? buffers
->shader_usage
:
936 buffers
->shader_usage_constbuf
,
937 i
< SI_NUM_SHADER_BUFFERS
? buffers
->priority
:
938 buffers
->priority_constbuf
);
942 static void si_get_buffer_from_descriptors(struct si_buffer_resources
*buffers
,
943 struct si_descriptors
*descs
,
944 unsigned idx
, struct pipe_resource
**buf
,
945 unsigned *offset
, unsigned *size
)
947 pipe_resource_reference(buf
, buffers
->buffers
[idx
]);
949 struct r600_resource
*res
= r600_resource(*buf
);
950 const uint32_t *desc
= descs
->list
+ idx
* 4;
955 assert(G_008F04_STRIDE(desc
[1]) == 0);
956 va
= ((uint64_t)desc
[1] << 32) | desc
[0];
958 assert(va
>= res
->gpu_address
&& va
+ *size
<= res
->gpu_address
+ res
->bo_size
);
959 *offset
= va
- res
->gpu_address
;
965 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
967 struct si_descriptors
*desc
= &sctx
->vertex_buffers
;
968 int count
= sctx
->vertex_elements
? sctx
->vertex_elements
->count
: 0;
971 for (i
= 0; i
< count
; i
++) {
972 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
974 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
976 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
979 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
980 (struct r600_resource
*)sctx
->vertex_buffer
[vb
].buffer
.resource
,
981 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
986 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
987 desc
->buffer
, RADEON_USAGE_READ
,
988 RADEON_PRIO_DESCRIPTORS
);
991 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
993 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
994 struct si_descriptors
*desc
= &sctx
->vertex_buffers
;
996 unsigned desc_list_byte_size
;
997 unsigned first_vb_use_mask
;
1001 if (!sctx
->vertex_buffers_dirty
|| !velems
)
1004 count
= velems
->count
;
1009 desc_list_byte_size
= velems
->desc_list_byte_size
;
1010 first_vb_use_mask
= velems
->first_vb_use_mask
;
1012 /* Vertex buffer descriptors are the only ones which are uploaded
1013 * directly through a staging buffer and don't go through
1014 * the fine-grained upload path.
1016 unsigned buffer_offset
= 0;
1017 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0,
1018 desc_list_byte_size
,
1019 si_optimal_tcc_alignment(sctx
, desc_list_byte_size
),
1021 (struct pipe_resource
**)&desc
->buffer
, (void**)&ptr
);
1022 if (!desc
->buffer
) {
1023 desc
->gpu_address
= 0;
1027 desc
->gpu_address
= desc
->buffer
->gpu_address
+ buffer_offset
;
1029 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1030 desc
->buffer
, RADEON_USAGE_READ
,
1031 RADEON_PRIO_DESCRIPTORS
);
1033 assert(count
<= SI_MAX_ATTRIBS
);
1035 for (i
= 0; i
< count
; i
++) {
1036 struct pipe_vertex_buffer
*vb
;
1037 struct r600_resource
*rbuffer
;
1039 unsigned vbo_index
= velems
->vertex_buffer_index
[i
];
1040 uint32_t *desc
= &ptr
[i
*4];
1042 vb
= &sctx
->vertex_buffer
[vbo_index
];
1043 rbuffer
= (struct r600_resource
*)vb
->buffer
.resource
;
1045 memset(desc
, 0, 16);
1049 offset
= vb
->buffer_offset
+ velems
->src_offset
[i
];
1050 va
= rbuffer
->gpu_address
+ offset
;
1052 /* Fill in T# buffer resource description */
1054 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1055 S_008F04_STRIDE(vb
->stride
);
1057 if (sctx
->b
.chip_class
!= VI
&& vb
->stride
) {
1058 /* Round up by rounding down and adding 1 */
1059 desc
[2] = (vb
->buffer
.resource
->width0
- offset
-
1060 velems
->format_size
[i
]) /
1063 desc
[2] = vb
->buffer
.resource
->width0
- offset
;
1066 desc
[3] = velems
->rsrc_word3
[i
];
1068 if (first_vb_use_mask
& (1 << i
)) {
1069 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1070 (struct r600_resource
*)vb
->buffer
.resource
,
1071 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1075 /* Don't flush the const cache. It would have a very negative effect
1076 * on performance (confirmed by testing). New descriptors are always
1077 * uploaded to a fresh new buffer, so I don't think flushing the const
1078 * cache is needed. */
1079 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1080 sctx
->vertex_buffers_dirty
= false;
1081 sctx
->vertex_buffer_pointer_dirty
= true;
1082 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VBO_DESCRIPTORS
;
1087 /* CONSTANT BUFFERS */
1090 si_const_and_shader_buffer_descriptors_idx(unsigned shader
)
1092 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
1093 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
;
1096 static struct si_descriptors
*
1097 si_const_and_shader_buffer_descriptors(struct si_context
*sctx
, unsigned shader
)
1099 return &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(shader
)];
1102 void si_upload_const_buffer(struct si_context
*sctx
, struct r600_resource
**rbuffer
,
1103 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
)
1107 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, size
,
1108 si_optimal_tcc_alignment(sctx
, size
),
1110 (struct pipe_resource
**)rbuffer
, &tmp
);
1112 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
1115 static void si_set_constant_buffer(struct si_context
*sctx
,
1116 struct si_buffer_resources
*buffers
,
1117 unsigned descriptors_idx
,
1118 uint slot
, const struct pipe_constant_buffer
*input
)
1120 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1121 assert(slot
< descs
->num_elements
);
1122 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1124 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1125 * with a NULL buffer). We need to use a dummy buffer instead. */
1126 if (sctx
->b
.chip_class
== CIK
&&
1127 (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
1128 input
= &sctx
->null_const_buf
;
1130 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1131 struct pipe_resource
*buffer
= NULL
;
1134 /* Upload the user buffer if needed. */
1135 if (input
->user_buffer
) {
1136 unsigned buffer_offset
;
1138 si_upload_const_buffer(sctx
,
1139 (struct r600_resource
**)&buffer
, input
->user_buffer
,
1140 input
->buffer_size
, &buffer_offset
);
1142 /* Just unbind on failure. */
1143 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1146 va
= r600_resource(buffer
)->gpu_address
+ buffer_offset
;
1148 pipe_resource_reference(&buffer
, input
->buffer
);
1149 va
= r600_resource(buffer
)->gpu_address
+ input
->buffer_offset
;
1150 /* Only track usage for non-user buffers. */
1151 r600_resource(buffer
)->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
1154 /* Set the descriptor. */
1155 uint32_t *desc
= descs
->list
+ slot
*4;
1157 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1159 desc
[2] = input
->buffer_size
;
1160 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1161 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1162 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1163 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1164 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1165 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1167 buffers
->buffers
[slot
] = buffer
;
1168 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1169 (struct r600_resource
*)buffer
,
1170 buffers
->shader_usage_constbuf
,
1171 buffers
->priority_constbuf
, true);
1172 buffers
->enabled_mask
|= 1u << slot
;
1174 /* Clear the descriptor. */
1175 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1176 buffers
->enabled_mask
&= ~(1u << slot
);
1179 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1182 void si_set_rw_buffer(struct si_context
*sctx
,
1183 uint slot
, const struct pipe_constant_buffer
*input
)
1185 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
,
1186 SI_DESCS_RW_BUFFERS
, slot
, input
);
1189 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
,
1190 enum pipe_shader_type shader
, uint slot
,
1191 const struct pipe_constant_buffer
*input
)
1193 struct si_context
*sctx
= (struct si_context
*)ctx
;
1195 if (shader
>= SI_NUM_SHADERS
)
1198 slot
= si_get_constbuf_slot(slot
);
1199 si_set_constant_buffer(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1200 si_const_and_shader_buffer_descriptors_idx(shader
),
1204 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
1205 uint slot
, struct pipe_constant_buffer
*cbuf
)
1207 cbuf
->user_buffer
= NULL
;
1208 si_get_buffer_from_descriptors(
1209 &sctx
->const_and_shader_buffers
[shader
],
1210 si_const_and_shader_buffer_descriptors(sctx
, shader
),
1211 si_get_constbuf_slot(slot
),
1212 &cbuf
->buffer
, &cbuf
->buffer_offset
, &cbuf
->buffer_size
);
1215 /* SHADER BUFFERS */
1217 static void si_set_shader_buffers(struct pipe_context
*ctx
,
1218 enum pipe_shader_type shader
,
1219 unsigned start_slot
, unsigned count
,
1220 const struct pipe_shader_buffer
*sbuffers
)
1222 struct si_context
*sctx
= (struct si_context
*)ctx
;
1223 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1224 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1227 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1229 for (i
= 0; i
< count
; ++i
) {
1230 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1231 struct r600_resource
*buf
;
1232 unsigned slot
= si_get_shaderbuf_slot(start_slot
+ i
);
1233 uint32_t *desc
= descs
->list
+ slot
* 4;
1236 if (!sbuffer
|| !sbuffer
->buffer
) {
1237 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1238 memset(desc
, 0, sizeof(uint32_t) * 4);
1239 buffers
->enabled_mask
&= ~(1u << slot
);
1240 sctx
->descriptors_dirty
|=
1241 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1245 buf
= (struct r600_resource
*)sbuffer
->buffer
;
1246 va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1249 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1251 desc
[2] = sbuffer
->buffer_size
;
1252 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1253 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1254 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1255 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1256 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1257 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1259 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1260 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
, buf
,
1261 buffers
->shader_usage
,
1262 buffers
->priority
, true);
1263 buf
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1265 buffers
->enabled_mask
|= 1u << slot
;
1266 sctx
->descriptors_dirty
|=
1267 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1269 util_range_add(&buf
->valid_buffer_range
, sbuffer
->buffer_offset
,
1270 sbuffer
->buffer_offset
+ sbuffer
->buffer_size
);
1274 void si_get_shader_buffers(struct si_context
*sctx
,
1275 enum pipe_shader_type shader
,
1276 uint start_slot
, uint count
,
1277 struct pipe_shader_buffer
*sbuf
)
1279 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1280 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1282 for (unsigned i
= 0; i
< count
; ++i
) {
1283 si_get_buffer_from_descriptors(
1285 si_get_shaderbuf_slot(start_slot
+ i
),
1286 &sbuf
[i
].buffer
, &sbuf
[i
].buffer_offset
,
1287 &sbuf
[i
].buffer_size
);
1293 void si_set_ring_buffer(struct pipe_context
*ctx
, uint slot
,
1294 struct pipe_resource
*buffer
,
1295 unsigned stride
, unsigned num_records
,
1296 bool add_tid
, bool swizzle
,
1297 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1299 struct si_context
*sctx
= (struct si_context
*)ctx
;
1300 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1301 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1303 /* The stride field in the resource descriptor has 14 bits */
1304 assert(stride
< (1 << 14));
1306 assert(slot
< descs
->num_elements
);
1307 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1312 va
= r600_resource(buffer
)->gpu_address
+ offset
;
1314 switch (element_size
) {
1316 assert(!"Unsupported ring buffer element size");
1332 switch (index_stride
) {
1334 assert(!"Unsupported ring buffer index stride");
1350 if (sctx
->b
.chip_class
>= VI
&& stride
)
1351 num_records
*= stride
;
1353 /* Set the descriptor. */
1354 uint32_t *desc
= descs
->list
+ slot
*4;
1356 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1357 S_008F04_STRIDE(stride
) |
1358 S_008F04_SWIZZLE_ENABLE(swizzle
);
1359 desc
[2] = num_records
;
1360 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1361 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1362 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1363 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1364 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1365 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1366 S_008F0C_INDEX_STRIDE(index_stride
) |
1367 S_008F0C_ADD_TID_ENABLE(add_tid
);
1369 if (sctx
->b
.chip_class
>= GFX9
)
1370 assert(!swizzle
|| element_size
== 1); /* always 4 bytes on GFX9 */
1372 desc
[3] |= S_008F0C_ELEMENT_SIZE(element_size
);
1374 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1375 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1376 (struct r600_resource
*)buffer
,
1377 buffers
->shader_usage
, buffers
->priority
);
1378 buffers
->enabled_mask
|= 1u << slot
;
1380 /* Clear the descriptor. */
1381 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1382 buffers
->enabled_mask
&= ~(1u << slot
);
1385 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1388 static void si_desc_reset_buffer_offset(struct pipe_context
*ctx
,
1389 uint32_t *desc
, uint64_t old_buf_va
,
1390 struct pipe_resource
*new_buf
)
1392 /* Retrieve the buffer offset from the descriptor. */
1393 uint64_t old_desc_va
= si_desc_extract_buffer_address(desc
);
1395 assert(old_buf_va
<= old_desc_va
);
1396 uint64_t offset_within_buffer
= old_desc_va
- old_buf_va
;
1398 /* Update the descriptor. */
1399 si_set_buf_desc_address(r600_resource(new_buf
), offset_within_buffer
,
1403 /* INTERNAL CONST BUFFERS */
1405 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
1406 const struct pipe_poly_stipple
*state
)
1408 struct si_context
*sctx
= (struct si_context
*)ctx
;
1409 struct pipe_constant_buffer cb
= {};
1410 unsigned stipple
[32];
1413 for (i
= 0; i
< 32; i
++)
1414 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1416 cb
.user_buffer
= stipple
;
1417 cb
.buffer_size
= sizeof(stipple
);
1419 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1422 /* TEXTURE METADATA ENABLE/DISABLE */
1425 si_resident_handles_update_needs_color_decompress(struct si_context
*sctx
)
1427 util_dynarray_clear(&sctx
->resident_tex_needs_color_decompress
);
1428 util_dynarray_clear(&sctx
->resident_img_needs_color_decompress
);
1430 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1431 struct si_texture_handle
*, tex_handle
) {
1432 struct pipe_resource
*res
= (*tex_handle
)->view
->texture
;
1433 struct r600_texture
*rtex
;
1435 if (!res
|| res
->target
== PIPE_BUFFER
)
1438 rtex
= (struct r600_texture
*)res
;
1439 if (!color_needs_decompression(rtex
))
1442 util_dynarray_append(&sctx
->resident_tex_needs_color_decompress
,
1443 struct si_texture_handle
*, *tex_handle
);
1446 util_dynarray_foreach(&sctx
->resident_img_handles
,
1447 struct si_image_handle
*, img_handle
) {
1448 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1449 struct pipe_resource
*res
= view
->resource
;
1450 struct r600_texture
*rtex
;
1452 if (!res
|| res
->target
== PIPE_BUFFER
)
1455 rtex
= (struct r600_texture
*)res
;
1456 if (!color_needs_decompression(rtex
))
1459 util_dynarray_append(&sctx
->resident_img_needs_color_decompress
,
1460 struct si_image_handle
*, *img_handle
);
1464 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1465 * while the texture is bound, possibly by a different context. In that case,
1466 * call this function to update needs_*_decompress_masks.
1468 void si_update_needs_color_decompress_masks(struct si_context
*sctx
)
1470 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1471 si_samplers_update_needs_color_decompress_mask(&sctx
->samplers
[i
]);
1472 si_images_update_needs_color_decompress_mask(&sctx
->images
[i
]);
1473 si_update_shader_needs_decompress_mask(sctx
, i
);
1476 si_resident_handles_update_needs_color_decompress(sctx
);
1479 /* BUFFER DISCARD/INVALIDATION */
1481 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1482 static void si_reset_buffer_resources(struct si_context
*sctx
,
1483 struct si_buffer_resources
*buffers
,
1484 unsigned descriptors_idx
,
1486 struct pipe_resource
*buf
,
1488 enum radeon_bo_usage usage
,
1489 enum radeon_bo_priority priority
)
1491 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1492 unsigned mask
= buffers
->enabled_mask
& slot_mask
;
1495 unsigned i
= u_bit_scan(&mask
);
1496 if (buffers
->buffers
[i
] == buf
) {
1497 si_desc_reset_buffer_offset(&sctx
->b
.b
,
1500 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1502 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1503 (struct r600_resource
*)buf
,
1504 usage
, priority
, true);
1509 static void si_rebind_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
,
1512 struct si_context
*sctx
= (struct si_context
*)ctx
;
1513 struct r600_resource
*rbuffer
= r600_resource(buf
);
1515 unsigned num_elems
= sctx
->vertex_elements
?
1516 sctx
->vertex_elements
->count
: 0;
1518 /* We changed the buffer, now we need to bind it where the old one
1519 * was bound. This consists of 2 things:
1520 * 1) Updating the resource descriptor and dirtying it.
1521 * 2) Adding a relocation to the CS, so that it's usable.
1524 /* Vertex buffers. */
1525 if (rbuffer
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
1526 for (i
= 0; i
< num_elems
; i
++) {
1527 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1529 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1531 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1534 if (sctx
->vertex_buffer
[vb
].buffer
.resource
== buf
) {
1535 sctx
->vertex_buffers_dirty
= true;
1541 /* Streamout buffers. (other internal buffers can't be invalidated) */
1542 if (rbuffer
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
1543 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1544 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1545 struct si_descriptors
*descs
=
1546 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1548 if (buffers
->buffers
[i
] != buf
)
1551 si_desc_reset_buffer_offset(ctx
, descs
->list
+ i
*4,
1553 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1555 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1556 rbuffer
, buffers
->shader_usage
,
1557 RADEON_PRIO_SHADER_RW_BUFFER
,
1560 /* Update the streamout state. */
1561 if (sctx
->streamout
.begin_emitted
)
1562 si_emit_streamout_end(sctx
);
1563 sctx
->streamout
.append_bitmask
=
1564 sctx
->streamout
.enabled_mask
;
1565 si_streamout_buffers_dirty(sctx
);
1569 /* Constant and shader buffers. */
1570 if (rbuffer
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1571 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1572 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1573 si_const_and_shader_buffer_descriptors_idx(shader
),
1574 u_bit_consecutive(SI_NUM_SHADER_BUFFERS
, SI_NUM_CONST_BUFFERS
),
1576 sctx
->const_and_shader_buffers
[shader
].shader_usage_constbuf
,
1577 sctx
->const_and_shader_buffers
[shader
].priority_constbuf
);
1580 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
1581 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1582 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1583 si_const_and_shader_buffer_descriptors_idx(shader
),
1584 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
),
1586 sctx
->const_and_shader_buffers
[shader
].shader_usage
,
1587 sctx
->const_and_shader_buffers
[shader
].priority
);
1590 if (rbuffer
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
1591 /* Texture buffers - update bindings. */
1592 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1593 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1594 struct si_descriptors
*descs
=
1595 si_sampler_and_image_descriptors(sctx
, shader
);
1596 unsigned mask
= samplers
->enabled_mask
;
1599 unsigned i
= u_bit_scan(&mask
);
1600 if (samplers
->views
[i
]->texture
== buf
) {
1601 unsigned desc_slot
= si_get_sampler_slot(i
);
1603 si_desc_reset_buffer_offset(ctx
,
1607 sctx
->descriptors_dirty
|=
1608 1u << si_sampler_and_image_descriptors_idx(shader
);
1610 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1611 rbuffer
, RADEON_USAGE_READ
,
1612 RADEON_PRIO_SAMPLER_BUFFER
,
1620 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
1621 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1622 struct si_images
*images
= &sctx
->images
[shader
];
1623 struct si_descriptors
*descs
=
1624 si_sampler_and_image_descriptors(sctx
, shader
);
1625 unsigned mask
= images
->enabled_mask
;
1628 unsigned i
= u_bit_scan(&mask
);
1630 if (images
->views
[i
].resource
== buf
) {
1631 unsigned desc_slot
= si_get_image_slot(i
);
1633 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1634 si_mark_image_range_valid(&images
->views
[i
]);
1636 si_desc_reset_buffer_offset(
1637 ctx
, descs
->list
+ desc_slot
* 8 + 4,
1639 sctx
->descriptors_dirty
|=
1640 1u << si_sampler_and_image_descriptors_idx(shader
);
1642 radeon_add_to_buffer_list_check_mem(
1643 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1644 RADEON_USAGE_READWRITE
,
1645 RADEON_PRIO_SAMPLER_BUFFER
, true);
1651 /* Bindless texture handles */
1652 if (rbuffer
->texture_handle_allocated
) {
1653 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1655 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1656 struct si_texture_handle
*, tex_handle
) {
1657 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
1658 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1660 if (view
->texture
== buf
) {
1661 si_set_buf_desc_address(rbuffer
,
1664 desc_slot
* 16 + 4);
1666 (*tex_handle
)->desc_dirty
= true;
1667 sctx
->bindless_descriptors_dirty
= true;
1669 radeon_add_to_buffer_list_check_mem(
1670 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1672 RADEON_PRIO_SAMPLER_BUFFER
, true);
1677 /* Bindless image handles */
1678 if (rbuffer
->image_handle_allocated
) {
1679 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1681 util_dynarray_foreach(&sctx
->resident_img_handles
,
1682 struct si_image_handle
*, img_handle
) {
1683 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1684 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1686 if (view
->resource
== buf
) {
1687 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
1688 si_mark_image_range_valid(view
);
1690 si_set_buf_desc_address(rbuffer
,
1693 desc_slot
* 16 + 4);
1695 (*img_handle
)->desc_dirty
= true;
1696 sctx
->bindless_descriptors_dirty
= true;
1698 radeon_add_to_buffer_list_check_mem(
1699 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1700 RADEON_USAGE_READWRITE
,
1701 RADEON_PRIO_SAMPLER_BUFFER
, true);
1707 /* Reallocate a buffer a update all resource bindings where the buffer is
1710 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
1711 * idle by discarding its contents. Apps usually tell us when to do this using
1712 * map_buffer flags, for example.
1714 static void si_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
1716 struct si_context
*sctx
= (struct si_context
*)ctx
;
1717 struct r600_resource
*rbuffer
= r600_resource(buf
);
1718 uint64_t old_va
= rbuffer
->gpu_address
;
1720 /* Reallocate the buffer in the same pipe_resource. */
1721 si_alloc_resource(&sctx
->screen
->b
, rbuffer
);
1723 si_rebind_buffer(ctx
, buf
, old_va
);
1726 static void si_upload_bindless_descriptor(struct si_context
*sctx
,
1728 unsigned num_dwords
)
1730 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1731 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1732 unsigned desc_slot_offset
= desc_slot
* 16;
1736 data
= desc
->list
+ desc_slot_offset
;
1737 va
= desc
->gpu_address
+ desc_slot_offset
* 4;
1739 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + num_dwords
, 0));
1740 radeon_emit(cs
, S_370_DST_SEL(V_370_TC_L2
) |
1741 S_370_WR_CONFIRM(1) |
1742 S_370_ENGINE_SEL(V_370_ME
));
1743 radeon_emit(cs
, va
);
1744 radeon_emit(cs
, va
>> 32);
1745 radeon_emit_array(cs
, data
, num_dwords
);
1748 static void si_upload_bindless_descriptors(struct si_context
*sctx
)
1750 if (!sctx
->bindless_descriptors_dirty
)
1753 /* Wait for graphics/compute to be idle before updating the resident
1754 * descriptors directly in memory, in case the GPU is using them.
1756 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
1757 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1758 si_emit_cache_flush(sctx
);
1760 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1761 struct si_texture_handle
*, tex_handle
) {
1762 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1764 if (!(*tex_handle
)->desc_dirty
)
1767 si_upload_bindless_descriptor(sctx
, desc_slot
, 16);
1768 (*tex_handle
)->desc_dirty
= false;
1771 util_dynarray_foreach(&sctx
->resident_img_handles
,
1772 struct si_image_handle
*, img_handle
) {
1773 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1775 if (!(*img_handle
)->desc_dirty
)
1778 si_upload_bindless_descriptor(sctx
, desc_slot
, 8);
1779 (*img_handle
)->desc_dirty
= false;
1782 /* Invalidate L1 because it doesn't know that L2 changed. */
1783 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
;
1784 si_emit_cache_flush(sctx
);
1786 sctx
->bindless_descriptors_dirty
= false;
1789 /* Update mutable image descriptor fields of all resident textures. */
1790 static void si_update_bindless_texture_descriptor(struct si_context
*sctx
,
1791 struct si_texture_handle
*tex_handle
)
1793 struct si_sampler_view
*sview
= (struct si_sampler_view
*)tex_handle
->view
;
1794 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1795 unsigned desc_slot_offset
= tex_handle
->desc_slot
* 16;
1796 uint32_t desc_list
[16];
1798 if (sview
->base
.texture
->target
== PIPE_BUFFER
)
1801 memcpy(desc_list
, desc
->list
+ desc_slot_offset
, sizeof(desc_list
));
1802 si_set_sampler_view_desc(sctx
, sview
, &tex_handle
->sstate
,
1803 desc
->list
+ desc_slot_offset
);
1805 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1806 sizeof(desc_list
))) {
1807 tex_handle
->desc_dirty
= true;
1808 sctx
->bindless_descriptors_dirty
= true;
1812 static void si_update_bindless_image_descriptor(struct si_context
*sctx
,
1813 struct si_image_handle
*img_handle
)
1815 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1816 unsigned desc_slot_offset
= img_handle
->desc_slot
* 16;
1817 struct pipe_image_view
*view
= &img_handle
->view
;
1818 uint32_t desc_list
[8];
1820 if (view
->resource
->target
== PIPE_BUFFER
)
1823 memcpy(desc_list
, desc
->list
+ desc_slot_offset
,
1825 si_set_shader_image_desc(sctx
, view
, true,
1826 desc
->list
+ desc_slot_offset
);
1828 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1829 sizeof(desc_list
))) {
1830 img_handle
->desc_dirty
= true;
1831 sctx
->bindless_descriptors_dirty
= true;
1835 static void si_update_all_resident_texture_descriptors(struct si_context
*sctx
)
1837 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1838 struct si_texture_handle
*, tex_handle
) {
1839 si_update_bindless_texture_descriptor(sctx
, *tex_handle
);
1842 util_dynarray_foreach(&sctx
->resident_img_handles
,
1843 struct si_image_handle
*, img_handle
) {
1844 si_update_bindless_image_descriptor(sctx
, *img_handle
);
1847 si_upload_bindless_descriptors(sctx
);
1850 /* Update mutable image descriptor fields of all bound textures. */
1851 void si_update_all_texture_descriptors(struct si_context
*sctx
)
1855 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1856 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1857 struct si_images
*images
= &sctx
->images
[shader
];
1861 mask
= images
->enabled_mask
;
1863 unsigned i
= u_bit_scan(&mask
);
1864 struct pipe_image_view
*view
= &images
->views
[i
];
1866 if (!view
->resource
||
1867 view
->resource
->target
== PIPE_BUFFER
)
1870 si_set_shader_image(sctx
, shader
, i
, view
, true);
1873 /* Sampler views. */
1874 mask
= samplers
->enabled_mask
;
1876 unsigned i
= u_bit_scan(&mask
);
1877 struct pipe_sampler_view
*view
= samplers
->views
[i
];
1881 view
->texture
->target
== PIPE_BUFFER
)
1884 si_set_sampler_view(sctx
, shader
, i
,
1885 samplers
->views
[i
], true);
1888 si_update_shader_needs_decompress_mask(sctx
, shader
);
1891 si_update_all_resident_texture_descriptors(sctx
);
1894 /* SHADER USER DATA */
1896 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
,
1899 sctx
->shader_pointers_dirty
|=
1900 u_bit_consecutive(SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
,
1901 SI_NUM_SHADER_DESCS
);
1903 if (shader
== PIPE_SHADER_VERTEX
)
1904 sctx
->vertex_buffer_pointer_dirty
= sctx
->vertex_buffers
.buffer
!= NULL
;
1906 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1909 static void si_shader_pointers_begin_new_cs(struct si_context
*sctx
)
1911 sctx
->shader_pointers_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
1912 sctx
->vertex_buffer_pointer_dirty
= sctx
->vertex_buffers
.buffer
!= NULL
;
1913 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1914 sctx
->graphics_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
1915 sctx
->compute_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
1918 /* Set a base register address for user data constants in the given shader.
1919 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1921 static void si_set_user_data_base(struct si_context
*sctx
,
1922 unsigned shader
, uint32_t new_base
)
1924 uint32_t *base
= &sctx
->shader_pointers
.sh_base
[shader
];
1926 if (*base
!= new_base
) {
1930 si_mark_shader_pointers_dirty(sctx
, shader
);
1932 if (shader
== PIPE_SHADER_VERTEX
)
1933 sctx
->last_vs_state
= ~0;
1938 /* This must be called when these shaders are changed from non-NULL to NULL
1941 * - tessellation control shader
1942 * - tessellation evaluation shader
1944 void si_shader_change_notify(struct si_context
*sctx
)
1946 /* VS can be bound as VS, ES, or LS. */
1947 if (sctx
->tes_shader
.cso
) {
1948 if (sctx
->b
.chip_class
>= GFX9
) {
1949 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1950 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
1952 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1953 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
1955 } else if (sctx
->gs_shader
.cso
) {
1956 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1957 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1959 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1960 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1963 /* TES can be bound as ES, VS, or not bound. */
1964 if (sctx
->tes_shader
.cso
) {
1965 if (sctx
->gs_shader
.cso
)
1966 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
1967 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1969 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
1970 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1972 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
1976 static void si_emit_shader_pointer_head(struct radeon_winsys_cs
*cs
,
1977 struct si_descriptors
*desc
,
1979 unsigned pointer_count
)
1981 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* 2, 0));
1982 radeon_emit(cs
, (sh_base
+ desc
->shader_userdata_offset
- SI_SH_REG_OFFSET
) >> 2);
1985 static void si_emit_shader_pointer_body(struct radeon_winsys_cs
*cs
,
1986 struct si_descriptors
*desc
)
1988 uint64_t va
= desc
->gpu_address
;
1990 radeon_emit(cs
, va
);
1991 radeon_emit(cs
, va
>> 32);
1994 static void si_emit_shader_pointer(struct si_context
*sctx
,
1995 struct si_descriptors
*desc
,
1998 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2000 si_emit_shader_pointer_head(cs
, desc
, sh_base
, 1);
2001 si_emit_shader_pointer_body(cs
, desc
);
2004 static void si_emit_consecutive_shader_pointers(struct si_context
*sctx
,
2005 unsigned pointer_mask
,
2011 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2012 unsigned mask
= sctx
->shader_pointers_dirty
& pointer_mask
;
2016 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
2018 struct si_descriptors
*descs
= &sctx
->descriptors
[start
];
2020 si_emit_shader_pointer_head(cs
, descs
, sh_base
, count
);
2021 for (int i
= 0; i
< count
; i
++)
2022 si_emit_shader_pointer_body(cs
, descs
+ i
);
2026 static void si_emit_global_shader_pointers(struct si_context
*sctx
,
2027 struct si_descriptors
*descs
)
2029 if (sctx
->b
.chip_class
== GFX9
) {
2030 /* Broadcast it to all shader stages. */
2031 si_emit_shader_pointer(sctx
, descs
,
2032 R_00B530_SPI_SHADER_USER_DATA_COMMON_0
);
2036 si_emit_shader_pointer(sctx
, descs
,
2037 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2038 si_emit_shader_pointer(sctx
, descs
,
2039 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2040 si_emit_shader_pointer(sctx
, descs
,
2041 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2042 si_emit_shader_pointer(sctx
, descs
,
2043 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2044 si_emit_shader_pointer(sctx
, descs
,
2045 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2046 si_emit_shader_pointer(sctx
, descs
,
2047 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2050 void si_emit_graphics_shader_pointers(struct si_context
*sctx
,
2051 struct r600_atom
*atom
)
2053 uint32_t *sh_base
= sctx
->shader_pointers
.sh_base
;
2055 if (sctx
->shader_pointers_dirty
& (1 << SI_DESCS_RW_BUFFERS
)) {
2056 si_emit_global_shader_pointers(sctx
,
2057 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2060 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(VERTEX
),
2061 sh_base
[PIPE_SHADER_VERTEX
]);
2062 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_CTRL
),
2063 sh_base
[PIPE_SHADER_TESS_CTRL
]);
2064 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_EVAL
),
2065 sh_base
[PIPE_SHADER_TESS_EVAL
]);
2066 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(GEOMETRY
),
2067 sh_base
[PIPE_SHADER_GEOMETRY
]);
2068 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(FRAGMENT
),
2069 sh_base
[PIPE_SHADER_FRAGMENT
]);
2071 sctx
->shader_pointers_dirty
&=
2072 ~u_bit_consecutive(SI_DESCS_RW_BUFFERS
, SI_DESCS_FIRST_COMPUTE
);
2074 if (sctx
->vertex_buffer_pointer_dirty
) {
2075 si_emit_shader_pointer(sctx
, &sctx
->vertex_buffers
,
2076 sh_base
[PIPE_SHADER_VERTEX
]);
2077 sctx
->vertex_buffer_pointer_dirty
= false;
2080 if (sctx
->graphics_bindless_pointer_dirty
) {
2081 si_emit_global_shader_pointers(sctx
,
2082 &sctx
->bindless_descriptors
);
2083 sctx
->graphics_bindless_pointer_dirty
= false;
2087 void si_emit_compute_shader_pointers(struct si_context
*sctx
)
2089 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
2091 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(COMPUTE
),
2092 R_00B900_COMPUTE_USER_DATA_0
);
2093 sctx
->shader_pointers_dirty
&= ~SI_DESCS_SHADER_MASK(COMPUTE
);
2095 if (sctx
->compute_bindless_pointer_dirty
) {
2096 si_emit_shader_pointer(sctx
, &sctx
->bindless_descriptors
, base
);
2097 sctx
->compute_bindless_pointer_dirty
= false;
2103 static void si_init_bindless_descriptors(struct si_context
*sctx
,
2104 struct si_descriptors
*desc
,
2105 unsigned shader_userdata_index
,
2106 unsigned num_elements
)
2108 MAYBE_UNUSED
unsigned desc_slot
;
2110 si_init_descriptors(desc
, shader_userdata_index
, 16, num_elements
);
2111 sctx
->bindless_descriptors
.num_active_slots
= num_elements
;
2113 /* The first bindless descriptor is stored at slot 1, because 0 is not
2114 * considered to be a valid handle.
2116 sctx
->num_bindless_descriptors
= 1;
2118 /* Track which bindless slots are used (or not). */
2119 util_idalloc_init(&sctx
->bindless_used_slots
);
2120 util_idalloc_resize(&sctx
->bindless_used_slots
, num_elements
);
2122 /* Reserve slot 0 because it's an invalid handle for bindless. */
2123 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2124 assert(desc_slot
== 0);
2127 static void si_release_bindless_descriptors(struct si_context
*sctx
)
2129 si_release_descriptors(&sctx
->bindless_descriptors
);
2130 util_idalloc_fini(&sctx
->bindless_used_slots
);
2133 static unsigned si_get_first_free_bindless_slot(struct si_context
*sctx
)
2135 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2138 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2139 if (desc_slot
>= desc
->num_elements
) {
2140 /* The array of bindless descriptors is full, resize it. */
2141 unsigned slot_size
= desc
->element_dw_size
* 4;
2142 unsigned new_num_elements
= desc
->num_elements
* 2;
2144 desc
->list
= REALLOC(desc
->list
, desc
->num_elements
* slot_size
,
2145 new_num_elements
* slot_size
);
2146 desc
->num_elements
= new_num_elements
;
2147 desc
->num_active_slots
= new_num_elements
;
2155 si_create_bindless_descriptor(struct si_context
*sctx
, uint32_t *desc_list
,
2158 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2159 unsigned desc_slot
, desc_slot_offset
;
2161 /* Find a free slot. */
2162 desc_slot
= si_get_first_free_bindless_slot(sctx
);
2164 /* For simplicity, sampler and image bindless descriptors use fixed
2165 * 16-dword slots for now. Image descriptors only need 8-dword but this
2166 * doesn't really matter because no real apps use image handles.
2168 desc_slot_offset
= desc_slot
* 16;
2170 /* Copy the descriptor into the array. */
2171 memcpy(desc
->list
+ desc_slot_offset
, desc_list
, size
);
2173 /* Re-upload the whole array of bindless descriptors into a new buffer.
2175 if (!si_upload_descriptors(sctx
, desc
))
2178 /* Make sure to re-emit the shader pointers for all stages. */
2179 sctx
->graphics_bindless_pointer_dirty
= true;
2180 sctx
->compute_bindless_pointer_dirty
= true;
2185 static void si_update_bindless_buffer_descriptor(struct si_context
*sctx
,
2187 struct pipe_resource
*resource
,
2191 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2192 struct r600_resource
*buf
= r600_resource(resource
);
2193 unsigned desc_slot_offset
= desc_slot
* 16;
2194 uint32_t *desc_list
= desc
->list
+ desc_slot_offset
+ 4;
2195 uint64_t old_desc_va
;
2197 assert(resource
->target
== PIPE_BUFFER
);
2199 /* Retrieve the old buffer addr from the descriptor. */
2200 old_desc_va
= si_desc_extract_buffer_address(desc_list
);
2202 if (old_desc_va
!= buf
->gpu_address
+ offset
) {
2203 /* The buffer has been invalidated when the handle wasn't
2204 * resident, update the descriptor and the dirty flag.
2206 si_set_buf_desc_address(buf
, offset
, &desc_list
[0]);
2212 static uint64_t si_create_texture_handle(struct pipe_context
*ctx
,
2213 struct pipe_sampler_view
*view
,
2214 const struct pipe_sampler_state
*state
)
2216 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
2217 struct si_context
*sctx
= (struct si_context
*)ctx
;
2218 struct si_texture_handle
*tex_handle
;
2219 struct si_sampler_state
*sstate
;
2220 uint32_t desc_list
[16];
2223 tex_handle
= CALLOC_STRUCT(si_texture_handle
);
2227 memset(desc_list
, 0, sizeof(desc_list
));
2228 si_init_descriptor_list(&desc_list
[0], 16, 1, null_texture_descriptor
);
2230 sstate
= ctx
->create_sampler_state(ctx
, state
);
2236 si_set_sampler_view_desc(sctx
, sview
, sstate
, &desc_list
[0]);
2237 memcpy(&tex_handle
->sstate
, sstate
, sizeof(*sstate
));
2238 ctx
->delete_sampler_state(ctx
, sstate
);
2240 tex_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2242 if (!tex_handle
->desc_slot
) {
2247 handle
= tex_handle
->desc_slot
;
2249 if (!_mesa_hash_table_insert(sctx
->tex_handles
, (void *)handle
,
2255 pipe_sampler_view_reference(&tex_handle
->view
, view
);
2257 r600_resource(sview
->base
.texture
)->texture_handle_allocated
= true;
2262 static void si_delete_texture_handle(struct pipe_context
*ctx
, uint64_t handle
)
2264 struct si_context
*sctx
= (struct si_context
*)ctx
;
2265 struct si_texture_handle
*tex_handle
;
2266 struct hash_entry
*entry
;
2268 entry
= _mesa_hash_table_search(sctx
->tex_handles
, (void *)handle
);
2272 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2274 /* Allow this descriptor slot to be re-used. */
2275 util_idalloc_free(&sctx
->bindless_used_slots
, tex_handle
->desc_slot
);
2277 pipe_sampler_view_reference(&tex_handle
->view
, NULL
);
2278 _mesa_hash_table_remove(sctx
->tex_handles
, entry
);
2282 static void si_make_texture_handle_resident(struct pipe_context
*ctx
,
2283 uint64_t handle
, bool resident
)
2285 struct si_context
*sctx
= (struct si_context
*)ctx
;
2286 struct si_texture_handle
*tex_handle
;
2287 struct si_sampler_view
*sview
;
2288 struct hash_entry
*entry
;
2290 entry
= _mesa_hash_table_search(sctx
->tex_handles
, (void *)handle
);
2294 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2295 sview
= (struct si_sampler_view
*)tex_handle
->view
;
2298 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2299 struct r600_texture
*rtex
=
2300 (struct r600_texture
*)sview
->base
.texture
;
2302 if (depth_needs_decompression(rtex
)) {
2303 util_dynarray_append(
2304 &sctx
->resident_tex_needs_depth_decompress
,
2305 struct si_texture_handle
*,
2309 if (color_needs_decompression(rtex
)) {
2310 util_dynarray_append(
2311 &sctx
->resident_tex_needs_color_decompress
,
2312 struct si_texture_handle
*,
2316 if (rtex
->dcc_offset
&&
2317 p_atomic_read(&rtex
->framebuffers_bound
))
2318 sctx
->need_check_render_feedback
= true;
2320 si_update_bindless_texture_descriptor(sctx
, tex_handle
);
2322 si_update_bindless_buffer_descriptor(sctx
,
2323 tex_handle
->desc_slot
,
2324 sview
->base
.texture
,
2325 sview
->base
.u
.buf
.offset
,
2326 &tex_handle
->desc_dirty
);
2329 /* Re-upload the descriptor if it has been updated while it
2332 if (tex_handle
->desc_dirty
)
2333 sctx
->bindless_descriptors_dirty
= true;
2335 /* Add the texture handle to the per-context list. */
2336 util_dynarray_append(&sctx
->resident_tex_handles
,
2337 struct si_texture_handle
*, tex_handle
);
2339 /* Add the buffers to the current CS in case si_begin_new_cs()
2340 * is not going to be called.
2342 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2344 sview
->is_stencil_sampler
, false);
2346 /* Remove the texture handle from the per-context list. */
2347 util_dynarray_delete_unordered(&sctx
->resident_tex_handles
,
2348 struct si_texture_handle
*,
2351 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2352 util_dynarray_delete_unordered(
2353 &sctx
->resident_tex_needs_depth_decompress
,
2354 struct si_texture_handle
*, tex_handle
);
2356 util_dynarray_delete_unordered(
2357 &sctx
->resident_tex_needs_color_decompress
,
2358 struct si_texture_handle
*, tex_handle
);
2363 static uint64_t si_create_image_handle(struct pipe_context
*ctx
,
2364 const struct pipe_image_view
*view
)
2366 struct si_context
*sctx
= (struct si_context
*)ctx
;
2367 struct si_image_handle
*img_handle
;
2368 uint32_t desc_list
[8];
2371 if (!view
|| !view
->resource
)
2374 img_handle
= CALLOC_STRUCT(si_image_handle
);
2378 memset(desc_list
, 0, sizeof(desc_list
));
2379 si_init_descriptor_list(&desc_list
[0], 8, 1, null_image_descriptor
);
2381 si_set_shader_image_desc(sctx
, view
, false, &desc_list
[0]);
2383 img_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2385 if (!img_handle
->desc_slot
) {
2390 handle
= img_handle
->desc_slot
;
2392 if (!_mesa_hash_table_insert(sctx
->img_handles
, (void *)handle
,
2398 util_copy_image_view(&img_handle
->view
, view
);
2400 r600_resource(view
->resource
)->image_handle_allocated
= true;
2405 static void si_delete_image_handle(struct pipe_context
*ctx
, uint64_t handle
)
2407 struct si_context
*sctx
= (struct si_context
*)ctx
;
2408 struct si_image_handle
*img_handle
;
2409 struct hash_entry
*entry
;
2411 entry
= _mesa_hash_table_search(sctx
->img_handles
, (void *)handle
);
2415 img_handle
= (struct si_image_handle
*)entry
->data
;
2417 util_copy_image_view(&img_handle
->view
, NULL
);
2418 _mesa_hash_table_remove(sctx
->img_handles
, entry
);
2422 static void si_make_image_handle_resident(struct pipe_context
*ctx
,
2423 uint64_t handle
, unsigned access
,
2426 struct si_context
*sctx
= (struct si_context
*)ctx
;
2427 struct si_image_handle
*img_handle
;
2428 struct pipe_image_view
*view
;
2429 struct r600_resource
*res
;
2430 struct hash_entry
*entry
;
2432 entry
= _mesa_hash_table_search(sctx
->img_handles
, (void *)handle
);
2436 img_handle
= (struct si_image_handle
*)entry
->data
;
2437 view
= &img_handle
->view
;
2438 res
= (struct r600_resource
*)view
->resource
;
2441 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2442 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
2443 unsigned level
= view
->u
.tex
.level
;
2445 if (color_needs_decompression(rtex
)) {
2446 util_dynarray_append(
2447 &sctx
->resident_img_needs_color_decompress
,
2448 struct si_image_handle
*,
2452 if (vi_dcc_enabled(rtex
, level
) &&
2453 p_atomic_read(&rtex
->framebuffers_bound
))
2454 sctx
->need_check_render_feedback
= true;
2456 si_update_bindless_image_descriptor(sctx
, img_handle
);
2458 si_update_bindless_buffer_descriptor(sctx
,
2459 img_handle
->desc_slot
,
2462 &img_handle
->desc_dirty
);
2465 /* Re-upload the descriptor if it has been updated while it
2468 if (img_handle
->desc_dirty
)
2469 sctx
->bindless_descriptors_dirty
= true;
2471 /* Add the image handle to the per-context list. */
2472 util_dynarray_append(&sctx
->resident_img_handles
,
2473 struct si_image_handle
*, img_handle
);
2475 /* Add the buffers to the current CS in case si_begin_new_cs()
2476 * is not going to be called.
2478 si_sampler_view_add_buffer(sctx
, view
->resource
,
2479 (access
& PIPE_IMAGE_ACCESS_WRITE
) ?
2480 RADEON_USAGE_READWRITE
:
2481 RADEON_USAGE_READ
, false, false);
2483 /* Remove the image handle from the per-context list. */
2484 util_dynarray_delete_unordered(&sctx
->resident_img_handles
,
2485 struct si_image_handle
*,
2488 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2489 util_dynarray_delete_unordered(
2490 &sctx
->resident_img_needs_color_decompress
,
2491 struct si_image_handle
*,
2498 void si_all_resident_buffers_begin_new_cs(struct si_context
*sctx
)
2500 unsigned num_resident_tex_handles
, num_resident_img_handles
;
2502 num_resident_tex_handles
= sctx
->resident_tex_handles
.size
/
2503 sizeof(struct si_texture_handle
*);
2504 num_resident_img_handles
= sctx
->resident_img_handles
.size
/
2505 sizeof(struct si_image_handle
*);
2507 /* Add all resident texture handles. */
2508 util_dynarray_foreach(&sctx
->resident_tex_handles
,
2509 struct si_texture_handle
*, tex_handle
) {
2510 struct si_sampler_view
*sview
=
2511 (struct si_sampler_view
*)(*tex_handle
)->view
;
2513 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2515 sview
->is_stencil_sampler
, false);
2518 /* Add all resident image handles. */
2519 util_dynarray_foreach(&sctx
->resident_img_handles
,
2520 struct si_image_handle
*, img_handle
) {
2521 struct pipe_image_view
*view
= &(*img_handle
)->view
;
2523 si_sampler_view_add_buffer(sctx
, view
->resource
,
2524 RADEON_USAGE_READWRITE
,
2528 sctx
->b
.num_resident_handles
+= num_resident_tex_handles
+
2529 num_resident_img_handles
;
2532 /* INIT/DEINIT/UPLOAD */
2534 void si_init_all_descriptors(struct si_context
*sctx
)
2538 STATIC_ASSERT(GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS
% 2 == 0);
2539 STATIC_ASSERT(GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS
% 2 == 0);
2541 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2542 bool gfx9_tcs
= false;
2543 bool gfx9_gs
= false;
2544 unsigned num_sampler_slots
= SI_NUM_IMAGES
/ 2 + SI_NUM_SAMPLERS
;
2545 unsigned num_buffer_slots
= SI_NUM_SHADER_BUFFERS
+ SI_NUM_CONST_BUFFERS
;
2546 struct si_descriptors
*desc
;
2548 if (sctx
->b
.chip_class
>= GFX9
) {
2549 gfx9_tcs
= i
== PIPE_SHADER_TESS_CTRL
;
2550 gfx9_gs
= i
== PIPE_SHADER_GEOMETRY
;
2553 desc
= si_const_and_shader_buffer_descriptors(sctx
, i
);
2554 si_init_buffer_resources(&sctx
->const_and_shader_buffers
[i
], desc
,
2556 gfx9_tcs
? GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS
:
2557 gfx9_gs
? GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS
:
2558 SI_SGPR_CONST_AND_SHADER_BUFFERS
,
2559 RADEON_USAGE_READWRITE
,
2561 RADEON_PRIO_SHADER_RW_BUFFER
,
2562 RADEON_PRIO_CONST_BUFFER
);
2563 desc
->slot_index_to_bind_directly
= si_get_constbuf_slot(0);
2565 desc
= si_sampler_and_image_descriptors(sctx
, i
);
2566 si_init_descriptors(desc
,
2567 gfx9_tcs
? GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES
:
2568 gfx9_gs
? GFX9_SGPR_GS_SAMPLERS_AND_IMAGES
:
2569 SI_SGPR_SAMPLERS_AND_IMAGES
,
2570 16, num_sampler_slots
);
2573 for (j
= 0; j
< SI_NUM_IMAGES
; j
++)
2574 memcpy(desc
->list
+ j
* 8, null_image_descriptor
, 8 * 4);
2575 for (; j
< SI_NUM_IMAGES
+ SI_NUM_SAMPLERS
* 2; j
++)
2576 memcpy(desc
->list
+ j
* 8, null_texture_descriptor
, 8 * 4);
2579 si_init_buffer_resources(&sctx
->rw_buffers
,
2580 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
2581 SI_NUM_RW_BUFFERS
, SI_SGPR_RW_BUFFERS
,
2582 /* The second set of usage/priority is used by
2583 * const buffers in RW buffer slots. */
2584 RADEON_USAGE_READWRITE
, RADEON_USAGE_READ
,
2585 RADEON_PRIO_SHADER_RINGS
, RADEON_PRIO_CONST_BUFFER
);
2586 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
= SI_NUM_RW_BUFFERS
;
2588 si_init_descriptors(&sctx
->vertex_buffers
, SI_SGPR_VERTEX_BUFFERS
,
2589 4, SI_NUM_VERTEX_BUFFERS
);
2590 FREE(sctx
->vertex_buffers
.list
); /* not used */
2591 sctx
->vertex_buffers
.list
= NULL
;
2593 /* Initialize an array of 1024 bindless descriptors, when the limit is
2594 * reached, just make it larger and re-upload the whole array.
2596 si_init_bindless_descriptors(sctx
, &sctx
->bindless_descriptors
,
2597 SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
,
2600 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2602 /* Set pipe_context functions. */
2603 sctx
->b
.b
.bind_sampler_states
= si_bind_sampler_states
;
2604 sctx
->b
.b
.set_shader_images
= si_set_shader_images
;
2605 sctx
->b
.b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
2606 sctx
->b
.b
.set_polygon_stipple
= si_set_polygon_stipple
;
2607 sctx
->b
.b
.set_shader_buffers
= si_set_shader_buffers
;
2608 sctx
->b
.b
.set_sampler_views
= si_set_sampler_views
;
2609 sctx
->b
.b
.create_texture_handle
= si_create_texture_handle
;
2610 sctx
->b
.b
.delete_texture_handle
= si_delete_texture_handle
;
2611 sctx
->b
.b
.make_texture_handle_resident
= si_make_texture_handle_resident
;
2612 sctx
->b
.b
.create_image_handle
= si_create_image_handle
;
2613 sctx
->b
.b
.delete_image_handle
= si_delete_image_handle
;
2614 sctx
->b
.b
.make_image_handle_resident
= si_make_image_handle_resident
;
2615 sctx
->b
.invalidate_buffer
= si_invalidate_buffer
;
2616 sctx
->b
.rebind_buffer
= si_rebind_buffer
;
2618 /* Shader user data. */
2619 si_init_atom(sctx
, &sctx
->shader_pointers
.atom
, &sctx
->atoms
.s
.shader_pointers
,
2620 si_emit_graphics_shader_pointers
);
2622 /* Set default and immutable mappings. */
2623 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2625 if (sctx
->b
.chip_class
>= GFX9
) {
2626 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2627 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2628 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2629 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2631 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2632 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2633 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2634 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2636 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2639 static bool si_upload_shader_descriptors(struct si_context
*sctx
, unsigned mask
)
2641 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2643 /* Assume nothing will go wrong: */
2644 sctx
->shader_pointers_dirty
|= dirty
;
2647 unsigned i
= u_bit_scan(&dirty
);
2649 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
]))
2653 sctx
->descriptors_dirty
&= ~mask
;
2655 si_upload_bindless_descriptors(sctx
);
2660 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
2662 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
2663 return si_upload_shader_descriptors(sctx
, mask
);
2666 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
2668 /* Does not update rw_buffers as that is not needed for compute shaders
2669 * and the input buffer is using the same SGPR's anyway.
2671 const unsigned mask
= u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
,
2672 SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
2673 return si_upload_shader_descriptors(sctx
, mask
);
2676 void si_release_all_descriptors(struct si_context
*sctx
)
2680 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2681 si_release_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2682 si_const_and_shader_buffer_descriptors(sctx
, i
));
2683 si_release_sampler_views(&sctx
->samplers
[i
]);
2684 si_release_image_views(&sctx
->images
[i
]);
2686 si_release_buffer_resources(&sctx
->rw_buffers
,
2687 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2688 for (i
= 0; i
< SI_NUM_VERTEX_BUFFERS
; i
++)
2689 pipe_vertex_buffer_unreference(&sctx
->vertex_buffer
[i
]);
2691 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2692 si_release_descriptors(&sctx
->descriptors
[i
]);
2694 sctx
->vertex_buffers
.list
= NULL
; /* points into a mapped buffer */
2695 si_release_descriptors(&sctx
->vertex_buffers
);
2696 si_release_bindless_descriptors(sctx
);
2699 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
2703 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2704 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2705 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
]);
2706 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
2708 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2709 si_vertex_buffers_begin_new_cs(sctx
);
2711 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2712 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
2713 si_descriptors_begin_new_cs(sctx
, &sctx
->bindless_descriptors
);
2715 si_shader_pointers_begin_new_cs(sctx
);
2718 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
2719 uint64_t new_active_mask
)
2721 struct si_descriptors
*desc
= &sctx
->descriptors
[desc_idx
];
2723 /* Ignore no-op updates and updates that disable all slots. */
2724 if (!new_active_mask
||
2725 new_active_mask
== u_bit_consecutive64(desc
->first_active_slot
,
2726 desc
->num_active_slots
))
2730 u_bit_scan_consecutive_range64(&new_active_mask
, &first
, &count
);
2731 assert(new_active_mask
== 0);
2733 /* Upload/dump descriptors if slots are being enabled. */
2734 if (first
< desc
->first_active_slot
||
2735 first
+ count
> desc
->first_active_slot
+ desc
->num_active_slots
)
2736 sctx
->descriptors_dirty
|= 1u << desc_idx
;
2738 desc
->first_active_slot
= first
;
2739 desc
->num_active_slots
= count
;
2742 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
2743 struct si_shader_selector
*sel
)
2748 si_set_active_descriptors(sctx
,
2749 si_const_and_shader_buffer_descriptors_idx(sel
->type
),
2750 sel
->active_const_and_shader_buffers
);
2751 si_set_active_descriptors(sctx
,
2752 si_sampler_and_image_descriptors_idx(sel
->type
),
2753 sel
->active_samplers_and_images
);