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radeonsi: just save buffer sizes instead of buffers while recording IBs
[mesa.git] / src / gallium / drivers / radeonsi / si_descriptors.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Marek Olšák <marek.olsak@amd.com>
25 */
26
27 /* Resource binding slots and sampler states (each described with 8 or
28 * 4 dwords) are stored in lists in memory which is accessed by shaders
29 * using scalar load instructions.
30 *
31 * This file is responsible for managing such lists. It keeps a copy of all
32 * descriptors in CPU memory and re-uploads a whole list if some slots have
33 * been changed.
34 *
35 * This code is also reponsible for updating shader pointers to those lists.
36 *
37 * Note that CP DMA can't be used for updating the lists, because a GPU hang
38 * could leave the list in a mid-IB state and the next IB would get wrong
39 * descriptors and the whole context would be unusable at that point.
40 * (Note: The register shadowing can't be used due to the same reason)
41 *
42 * Also, uploading descriptors to newly allocated memory doesn't require
43 * a KCACHE flush.
44 *
45 *
46 * Possible scenarios for one 16 dword image+sampler slot:
47 *
48 * | Image | w/ FMASK | Buffer | NULL
49 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
50 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
51 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
52 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
53 *
54 * FMASK implies MSAA, therefore no sampler state.
55 * Sampler states are never unbound except when FMASK is bound.
56 */
57
58 #include "radeon/r600_cs.h"
59 #include "si_pipe.h"
60 #include "si_shader.h"
61 #include "sid.h"
62
63 #include "util/u_format.h"
64 #include "util/u_math.h"
65 #include "util/u_memory.h"
66 #include "util/u_suballoc.h"
67 #include "util/u_upload_mgr.h"
68
69
70 /* NULL image and buffer descriptor for textures (alpha = 1) and images
71 * (alpha = 0).
72 *
73 * For images, all fields must be zero except for the swizzle, which
74 * supports arbitrary combinations of 0s and 1s. The texture type must be
75 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
76 *
77 * For buffers, all fields must be zero. If they are not, the hw hangs.
78 *
79 * This is the only reason why the buffer descriptor must be in words [4:7].
80 */
81 static uint32_t null_texture_descriptor[8] = {
82 0,
83 0,
84 0,
85 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1) |
86 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
87 /* the rest must contain zeros, which is also used by the buffer
88 * descriptor */
89 };
90
91 static uint32_t null_image_descriptor[8] = {
92 0,
93 0,
94 0,
95 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
96 /* the rest must contain zeros, which is also used by the buffer
97 * descriptor */
98 };
99
100 static void si_init_descriptors(struct si_descriptors *desc,
101 unsigned shader_userdata_index,
102 unsigned element_dw_size,
103 unsigned num_elements,
104 const uint32_t *null_descriptor,
105 unsigned *ce_offset)
106 {
107 int i;
108
109 assert(num_elements <= sizeof(desc->dirty_mask)*8);
110
111 desc->list = CALLOC(num_elements, element_dw_size * 4);
112 desc->element_dw_size = element_dw_size;
113 desc->num_elements = num_elements;
114 desc->dirty_mask = num_elements == 32 ? ~0u : (1u << num_elements) - 1;
115 desc->shader_userdata_offset = shader_userdata_index * 4;
116
117 if (ce_offset) {
118 desc->ce_offset = *ce_offset;
119
120 /* make sure that ce_offset stays 32 byte aligned */
121 *ce_offset += align(element_dw_size * num_elements * 4, 32);
122 }
123
124 /* Initialize the array to NULL descriptors if the element size is 8. */
125 if (null_descriptor) {
126 assert(element_dw_size % 8 == 0);
127 for (i = 0; i < num_elements * element_dw_size / 8; i++)
128 memcpy(desc->list + i * 8, null_descriptor,
129 8 * 4);
130 }
131 }
132
133 static void si_release_descriptors(struct si_descriptors *desc)
134 {
135 r600_resource_reference(&desc->buffer, NULL);
136 FREE(desc->list);
137 }
138
139 static bool si_ce_upload(struct si_context *sctx, unsigned ce_offset, unsigned size,
140 unsigned *out_offset, struct r600_resource **out_buf) {
141 uint64_t va;
142
143 u_suballocator_alloc(sctx->ce_suballocator, size, 64, out_offset,
144 (struct pipe_resource**)out_buf);
145 if (!out_buf)
146 return false;
147
148 va = (*out_buf)->gpu_address + *out_offset;
149
150 radeon_emit(sctx->ce_ib, PKT3(PKT3_DUMP_CONST_RAM, 3, 0));
151 radeon_emit(sctx->ce_ib, ce_offset);
152 radeon_emit(sctx->ce_ib, size / 4);
153 radeon_emit(sctx->ce_ib, va);
154 radeon_emit(sctx->ce_ib, va >> 32);
155
156 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, *out_buf,
157 RADEON_USAGE_READWRITE, RADEON_PRIO_DESCRIPTORS);
158
159 sctx->ce_need_synchronization = true;
160 return true;
161 }
162
163 static void si_ce_reinitialize_descriptors(struct si_context *sctx,
164 struct si_descriptors *desc)
165 {
166 if (desc->buffer) {
167 struct r600_resource *buffer = (struct r600_resource*)desc->buffer;
168 unsigned list_size = desc->num_elements * desc->element_dw_size * 4;
169 uint64_t va = buffer->gpu_address + desc->buffer_offset;
170 struct radeon_winsys_cs *ib = sctx->ce_preamble_ib;
171
172 if (!ib)
173 ib = sctx->ce_ib;
174
175 list_size = align(list_size, 32);
176
177 radeon_emit(ib, PKT3(PKT3_LOAD_CONST_RAM, 3, 0));
178 radeon_emit(ib, va);
179 radeon_emit(ib, va >> 32);
180 radeon_emit(ib, list_size / 4);
181 radeon_emit(ib, desc->ce_offset);
182
183 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
184 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
185 }
186 desc->ce_ram_dirty = false;
187 }
188
189 void si_ce_reinitialize_all_descriptors(struct si_context *sctx)
190 {
191 int i;
192
193 for (i = 0; i < SI_NUM_DESCS; ++i)
194 si_ce_reinitialize_descriptors(sctx, &sctx->descriptors[i]);
195 }
196
197 void si_ce_enable_loads(struct radeon_winsys_cs *ib)
198 {
199 radeon_emit(ib, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
200 radeon_emit(ib, CONTEXT_CONTROL_LOAD_ENABLE(1) |
201 CONTEXT_CONTROL_LOAD_CE_RAM(1));
202 radeon_emit(ib, CONTEXT_CONTROL_SHADOW_ENABLE(1));
203 }
204
205 static bool si_upload_descriptors(struct si_context *sctx,
206 struct si_descriptors *desc,
207 struct r600_atom * atom)
208 {
209 unsigned list_size = desc->num_elements * desc->element_dw_size * 4;
210
211 if (!desc->dirty_mask)
212 return true;
213
214 if (sctx->ce_ib) {
215 uint32_t const* list = (uint32_t const*)desc->list;
216
217 if (desc->ce_ram_dirty)
218 si_ce_reinitialize_descriptors(sctx, desc);
219
220 while(desc->dirty_mask) {
221 int begin, count;
222 u_bit_scan_consecutive_range(&desc->dirty_mask, &begin,
223 &count);
224
225 begin *= desc->element_dw_size;
226 count *= desc->element_dw_size;
227
228 radeon_emit(sctx->ce_ib,
229 PKT3(PKT3_WRITE_CONST_RAM, count, 0));
230 radeon_emit(sctx->ce_ib, desc->ce_offset + begin * 4);
231 radeon_emit_array(sctx->ce_ib, list + begin, count);
232 }
233
234 if (!si_ce_upload(sctx, desc->ce_offset, list_size,
235 &desc->buffer_offset, &desc->buffer))
236 return false;
237 } else {
238 void *ptr;
239
240 u_upload_alloc(sctx->b.uploader, 0, list_size, 256,
241 &desc->buffer_offset,
242 (struct pipe_resource**)&desc->buffer, &ptr);
243 if (!desc->buffer)
244 return false; /* skip the draw call */
245
246 util_memcpy_cpu_to_le32(ptr, desc->list, list_size);
247
248 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
249 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
250 }
251 desc->pointer_dirty = true;
252 desc->dirty_mask = 0;
253
254 if (atom)
255 si_mark_atom_dirty(sctx, atom);
256
257 return true;
258 }
259
260 static void
261 si_descriptors_begin_new_cs(struct si_context *sctx, struct si_descriptors *desc)
262 {
263 desc->ce_ram_dirty = true;
264
265 if (!desc->buffer)
266 return;
267
268 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
269 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
270 }
271
272 /* SAMPLER VIEWS */
273
274 static unsigned
275 si_sampler_descriptors_idx(unsigned shader)
276 {
277 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
278 SI_SHADER_DESCS_SAMPLERS;
279 }
280
281 static struct si_descriptors *
282 si_sampler_descriptors(struct si_context *sctx, unsigned shader)
283 {
284 return &sctx->descriptors[si_sampler_descriptors_idx(shader)];
285 }
286
287 static void si_release_sampler_views(struct si_sampler_views *views)
288 {
289 int i;
290
291 for (i = 0; i < ARRAY_SIZE(views->views); i++) {
292 pipe_sampler_view_reference(&views->views[i], NULL);
293 }
294 }
295
296 static void si_sampler_view_add_buffer(struct si_context *sctx,
297 struct pipe_resource *resource,
298 enum radeon_bo_usage usage,
299 bool is_stencil_sampler)
300 {
301 struct r600_resource *rres;
302
303 if (!resource)
304 return;
305
306 if (resource->target != PIPE_BUFFER) {
307 struct r600_texture *tex = (struct r600_texture*)resource;
308
309 if (tex->is_depth && !r600_can_sample_zs(tex, is_stencil_sampler))
310 resource = &tex->flushed_depth_texture->resource.b.b;
311 }
312
313 rres = (struct r600_resource*)resource;
314 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, rres, usage,
315 r600_get_sampler_view_priority(rres));
316
317 if (resource->target != PIPE_BUFFER) {
318 struct r600_texture *rtex = (struct r600_texture*)resource;
319
320 if (rtex->dcc_separate_buffer)
321 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
322 rtex->dcc_separate_buffer, usage,
323 RADEON_PRIO_DCC);
324 }
325 }
326
327 static void si_sampler_views_begin_new_cs(struct si_context *sctx,
328 struct si_sampler_views *views)
329 {
330 unsigned mask = views->enabled_mask;
331
332 /* Add buffers to the CS. */
333 while (mask) {
334 int i = u_bit_scan(&mask);
335 struct si_sampler_view *sview = (struct si_sampler_view *)views->views[i];
336
337 si_sampler_view_add_buffer(sctx, sview->base.texture,
338 RADEON_USAGE_READ,
339 sview->is_stencil_sampler);
340 }
341 }
342
343 /* Set texture descriptor fields that can be changed by reallocations.
344 *
345 * \param tex texture
346 * \param base_level_info information of the level of BASE_ADDRESS
347 * \param base_level the level of BASE_ADDRESS
348 * \param first_level pipe_sampler_view.u.tex.first_level
349 * \param block_width util_format_get_blockwidth()
350 * \param is_stencil select between separate Z & Stencil
351 * \param state descriptor to update
352 */
353 void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
354 const struct radeon_surf_level *base_level_info,
355 unsigned base_level, unsigned first_level,
356 unsigned block_width, bool is_stencil,
357 uint32_t *state)
358 {
359 uint64_t va;
360 unsigned pitch = base_level_info->nblk_x * block_width;
361
362 if (tex->is_depth && !r600_can_sample_zs(tex, is_stencil)) {
363 tex = tex->flushed_depth_texture;
364 is_stencil = false;
365 }
366
367 va = tex->resource.gpu_address + base_level_info->offset;
368
369 state[1] &= C_008F14_BASE_ADDRESS_HI;
370 state[3] &= C_008F1C_TILING_INDEX;
371 state[4] &= C_008F20_PITCH;
372 state[6] &= C_008F28_COMPRESSION_EN;
373
374 state[0] = va >> 8;
375 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
376 state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(tex, base_level,
377 is_stencil));
378 state[4] |= S_008F20_PITCH(pitch - 1);
379
380 if (tex->dcc_offset && tex->surface.level[first_level].dcc_enabled) {
381 state[6] |= S_008F28_COMPRESSION_EN(1);
382 state[7] = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
383 tex->dcc_offset +
384 base_level_info->dcc_offset) >> 8;
385 }
386 }
387
388 static void si_set_sampler_view(struct si_context *sctx,
389 unsigned shader,
390 unsigned slot, struct pipe_sampler_view *view,
391 bool disallow_early_out)
392 {
393 struct si_sampler_views *views = &sctx->samplers[shader].views;
394 struct si_sampler_view *rview = (struct si_sampler_view*)view;
395 struct si_descriptors *descs = si_sampler_descriptors(sctx, shader);
396
397 if (views->views[slot] == view && !disallow_early_out)
398 return;
399
400 if (view) {
401 struct r600_texture *rtex = (struct r600_texture *)view->texture;
402 uint32_t *desc = descs->list + slot * 16;
403
404 si_sampler_view_add_buffer(sctx, view->texture,
405 RADEON_USAGE_READ,
406 rview->is_stencil_sampler);
407
408 pipe_sampler_view_reference(&views->views[slot], view);
409 memcpy(desc, rview->state, 8*4);
410
411 if (view->texture && view->texture->target != PIPE_BUFFER) {
412 bool is_separate_stencil =
413 rtex->db_compatible &&
414 rview->is_stencil_sampler;
415
416 si_set_mutable_tex_desc_fields(rtex,
417 rview->base_level_info,
418 rview->base_level,
419 rview->base.u.tex.first_level,
420 rview->block_width,
421 is_separate_stencil,
422 desc);
423 }
424
425 if (view->texture && view->texture->target != PIPE_BUFFER &&
426 rtex->fmask.size) {
427 memcpy(desc + 8,
428 rview->fmask_state, 8*4);
429 } else {
430 /* Disable FMASK and bind sampler state in [12:15]. */
431 memcpy(desc + 8,
432 null_texture_descriptor, 4*4);
433
434 if (views->sampler_states[slot])
435 memcpy(desc + 12,
436 views->sampler_states[slot], 4*4);
437 }
438
439 views->enabled_mask |= 1u << slot;
440 } else {
441 pipe_sampler_view_reference(&views->views[slot], NULL);
442 memcpy(descs->list + slot*16, null_texture_descriptor, 8*4);
443 /* Only clear the lower dwords of FMASK. */
444 memcpy(descs->list + slot*16 + 8, null_texture_descriptor, 4*4);
445 views->enabled_mask &= ~(1u << slot);
446 }
447
448 descs->dirty_mask |= 1u << slot;
449 sctx->descriptors_dirty |= 1u << si_sampler_descriptors_idx(shader);
450 }
451
452 static bool is_compressed_colortex(struct r600_texture *rtex)
453 {
454 return rtex->cmask.size || rtex->fmask.size ||
455 (rtex->dcc_offset && rtex->dirty_level_mask);
456 }
457
458 static void si_set_sampler_views(struct pipe_context *ctx,
459 unsigned shader, unsigned start,
460 unsigned count,
461 struct pipe_sampler_view **views)
462 {
463 struct si_context *sctx = (struct si_context *)ctx;
464 struct si_textures_info *samplers = &sctx->samplers[shader];
465 int i;
466
467 if (!count || shader >= SI_NUM_SHADERS)
468 return;
469
470 for (i = 0; i < count; i++) {
471 unsigned slot = start + i;
472
473 if (!views || !views[i]) {
474 samplers->depth_texture_mask &= ~(1u << slot);
475 samplers->compressed_colortex_mask &= ~(1u << slot);
476 si_set_sampler_view(sctx, shader, slot, NULL, false);
477 continue;
478 }
479
480 si_set_sampler_view(sctx, shader, slot, views[i], false);
481
482 if (views[i]->texture && views[i]->texture->target != PIPE_BUFFER) {
483 struct r600_texture *rtex =
484 (struct r600_texture*)views[i]->texture;
485
486 if (rtex->db_compatible) {
487 samplers->depth_texture_mask |= 1u << slot;
488 } else {
489 samplers->depth_texture_mask &= ~(1u << slot);
490 }
491 if (is_compressed_colortex(rtex)) {
492 samplers->compressed_colortex_mask |= 1u << slot;
493 } else {
494 samplers->compressed_colortex_mask &= ~(1u << slot);
495 }
496
497 if (rtex->dcc_offset &&
498 p_atomic_read(&rtex->framebuffers_bound))
499 sctx->need_check_render_feedback = true;
500 } else {
501 samplers->depth_texture_mask &= ~(1u << slot);
502 samplers->compressed_colortex_mask &= ~(1u << slot);
503 }
504 }
505 }
506
507 static void
508 si_samplers_update_compressed_colortex_mask(struct si_textures_info *samplers)
509 {
510 unsigned mask = samplers->views.enabled_mask;
511
512 while (mask) {
513 int i = u_bit_scan(&mask);
514 struct pipe_resource *res = samplers->views.views[i]->texture;
515
516 if (res && res->target != PIPE_BUFFER) {
517 struct r600_texture *rtex = (struct r600_texture *)res;
518
519 if (is_compressed_colortex(rtex)) {
520 samplers->compressed_colortex_mask |= 1u << i;
521 } else {
522 samplers->compressed_colortex_mask &= ~(1u << i);
523 }
524 }
525 }
526 }
527
528 /* IMAGE VIEWS */
529
530 static unsigned
531 si_image_descriptors_idx(unsigned shader)
532 {
533 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
534 SI_SHADER_DESCS_IMAGES;
535 }
536
537 static struct si_descriptors*
538 si_image_descriptors(struct si_context *sctx, unsigned shader)
539 {
540 return &sctx->descriptors[si_image_descriptors_idx(shader)];
541 }
542
543 static void
544 si_release_image_views(struct si_images_info *images)
545 {
546 unsigned i;
547
548 for (i = 0; i < SI_NUM_IMAGES; ++i) {
549 struct pipe_image_view *view = &images->views[i];
550
551 pipe_resource_reference(&view->resource, NULL);
552 }
553 }
554
555 static void
556 si_image_views_begin_new_cs(struct si_context *sctx, struct si_images_info *images)
557 {
558 uint mask = images->enabled_mask;
559
560 /* Add buffers to the CS. */
561 while (mask) {
562 int i = u_bit_scan(&mask);
563 struct pipe_image_view *view = &images->views[i];
564
565 assert(view->resource);
566
567 si_sampler_view_add_buffer(sctx, view->resource,
568 RADEON_USAGE_READWRITE, false);
569 }
570 }
571
572 static void
573 si_disable_shader_image(struct si_context *ctx, unsigned shader, unsigned slot)
574 {
575 struct si_images_info *images = &ctx->images[shader];
576
577 if (images->enabled_mask & (1u << slot)) {
578 struct si_descriptors *descs = si_image_descriptors(ctx, shader);
579
580 pipe_resource_reference(&images->views[slot].resource, NULL);
581 images->compressed_colortex_mask &= ~(1 << slot);
582
583 memcpy(descs->list + slot*8, null_image_descriptor, 8*4);
584 images->enabled_mask &= ~(1u << slot);
585 descs->dirty_mask |= 1u << slot;
586 ctx->descriptors_dirty |= 1u << si_image_descriptors_idx(shader);
587 }
588 }
589
590 static void
591 si_mark_image_range_valid(const struct pipe_image_view *view)
592 {
593 struct r600_resource *res = (struct r600_resource *)view->resource;
594 const struct util_format_description *desc;
595 unsigned stride;
596
597 assert(res && res->b.b.target == PIPE_BUFFER);
598
599 desc = util_format_description(view->format);
600 stride = desc->block.bits / 8;
601
602 util_range_add(&res->valid_buffer_range,
603 stride * (view->u.buf.first_element),
604 stride * (view->u.buf.last_element + 1));
605 }
606
607 static void si_set_shader_image(struct si_context *ctx,
608 unsigned shader,
609 unsigned slot, const struct pipe_image_view *view)
610 {
611 struct si_screen *screen = ctx->screen;
612 struct si_images_info *images = &ctx->images[shader];
613 struct si_descriptors *descs = si_image_descriptors(ctx, shader);
614 struct r600_resource *res;
615
616 if (!view || !view->resource) {
617 si_disable_shader_image(ctx, shader, slot);
618 return;
619 }
620
621 res = (struct r600_resource *)view->resource;
622
623 if (&images->views[slot] != view)
624 util_copy_image_view(&images->views[slot], view);
625
626 si_sampler_view_add_buffer(ctx, &res->b.b,
627 RADEON_USAGE_READWRITE, false);
628
629 if (res->b.b.target == PIPE_BUFFER) {
630 if (view->access & PIPE_IMAGE_ACCESS_WRITE)
631 si_mark_image_range_valid(view);
632
633 si_make_buffer_descriptor(screen, res,
634 view->format,
635 view->u.buf.first_element,
636 view->u.buf.last_element,
637 descs->list + slot * 8);
638 images->compressed_colortex_mask &= ~(1 << slot);
639 } else {
640 static const unsigned char swizzle[4] = { 0, 1, 2, 3 };
641 struct r600_texture *tex = (struct r600_texture *)res;
642 unsigned level = view->u.tex.level;
643 unsigned width, height, depth;
644 uint32_t *desc = descs->list + slot * 8;
645 bool uses_dcc = tex->dcc_offset &&
646 tex->surface.level[level].dcc_enabled;
647
648 assert(!tex->is_depth);
649 assert(tex->fmask.size == 0);
650
651 if (uses_dcc &&
652 view->access & PIPE_IMAGE_ACCESS_WRITE) {
653 /* If DCC can't be disabled, at least decompress it.
654 * The decompression is relatively cheap if the surface
655 * has been decompressed already.
656 */
657 if (r600_texture_disable_dcc(&screen->b, tex))
658 uses_dcc = false;
659 else
660 ctx->b.decompress_dcc(&ctx->b.b, tex);
661 }
662
663 if (is_compressed_colortex(tex)) {
664 images->compressed_colortex_mask |= 1 << slot;
665 } else {
666 images->compressed_colortex_mask &= ~(1 << slot);
667 }
668
669 if (uses_dcc &&
670 p_atomic_read(&tex->framebuffers_bound))
671 ctx->need_check_render_feedback = true;
672
673 /* Always force the base level to the selected level.
674 *
675 * This is required for 3D textures, where otherwise
676 * selecting a single slice for non-layered bindings
677 * fails. It doesn't hurt the other targets.
678 */
679 width = u_minify(res->b.b.width0, level);
680 height = u_minify(res->b.b.height0, level);
681 depth = u_minify(res->b.b.depth0, level);
682
683 si_make_texture_descriptor(screen, tex,
684 false, res->b.b.target,
685 view->format, swizzle,
686 0, 0,
687 view->u.tex.first_layer,
688 view->u.tex.last_layer,
689 width, height, depth,
690 desc, NULL);
691 si_set_mutable_tex_desc_fields(tex, &tex->surface.level[level],
692 level, level,
693 util_format_get_blockwidth(view->format),
694 false, desc);
695 }
696
697 images->enabled_mask |= 1u << slot;
698 descs->dirty_mask |= 1u << slot;
699 ctx->descriptors_dirty |= 1u << si_image_descriptors_idx(shader);
700 }
701
702 static void
703 si_set_shader_images(struct pipe_context *pipe, unsigned shader,
704 unsigned start_slot, unsigned count,
705 const struct pipe_image_view *views)
706 {
707 struct si_context *ctx = (struct si_context *)pipe;
708 unsigned i, slot;
709
710 assert(shader < SI_NUM_SHADERS);
711
712 if (!count)
713 return;
714
715 assert(start_slot + count <= SI_NUM_IMAGES);
716
717 if (views) {
718 for (i = 0, slot = start_slot; i < count; ++i, ++slot)
719 si_set_shader_image(ctx, shader, slot, &views[i]);
720 } else {
721 for (i = 0, slot = start_slot; i < count; ++i, ++slot)
722 si_set_shader_image(ctx, shader, slot, NULL);
723 }
724 }
725
726 static void
727 si_images_update_compressed_colortex_mask(struct si_images_info *images)
728 {
729 unsigned mask = images->enabled_mask;
730
731 while (mask) {
732 int i = u_bit_scan(&mask);
733 struct pipe_resource *res = images->views[i].resource;
734
735 if (res && res->target != PIPE_BUFFER) {
736 struct r600_texture *rtex = (struct r600_texture *)res;
737
738 if (is_compressed_colortex(rtex)) {
739 images->compressed_colortex_mask |= 1 << i;
740 } else {
741 images->compressed_colortex_mask &= ~(1 << i);
742 }
743 }
744 }
745 }
746
747 /* SAMPLER STATES */
748
749 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
750 unsigned start, unsigned count, void **states)
751 {
752 struct si_context *sctx = (struct si_context *)ctx;
753 struct si_textures_info *samplers = &sctx->samplers[shader];
754 struct si_descriptors *desc = si_sampler_descriptors(sctx, shader);
755 struct si_sampler_state **sstates = (struct si_sampler_state**)states;
756 int i;
757
758 if (!count || shader >= SI_NUM_SHADERS)
759 return;
760
761 for (i = 0; i < count; i++) {
762 unsigned slot = start + i;
763
764 if (!sstates[i] ||
765 sstates[i] == samplers->views.sampler_states[slot])
766 continue;
767
768 samplers->views.sampler_states[slot] = sstates[i];
769
770 /* If FMASK is bound, don't overwrite it.
771 * The sampler state will be set after FMASK is unbound.
772 */
773 if (samplers->views.views[i] &&
774 samplers->views.views[i]->texture &&
775 samplers->views.views[i]->texture->target != PIPE_BUFFER &&
776 ((struct r600_texture*)samplers->views.views[i]->texture)->fmask.size)
777 continue;
778
779 memcpy(desc->list + slot * 16 + 12, sstates[i]->val, 4*4);
780 desc->dirty_mask |= 1u << slot;
781 sctx->descriptors_dirty |= 1u << si_sampler_descriptors_idx(shader);
782 }
783 }
784
785 /* BUFFER RESOURCES */
786
787 static void si_init_buffer_resources(struct si_buffer_resources *buffers,
788 struct si_descriptors *descs,
789 unsigned num_buffers,
790 unsigned shader_userdata_index,
791 enum radeon_bo_usage shader_usage,
792 enum radeon_bo_priority priority,
793 unsigned *ce_offset)
794 {
795 buffers->shader_usage = shader_usage;
796 buffers->priority = priority;
797 buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource*));
798
799 si_init_descriptors(descs, shader_userdata_index, 4,
800 num_buffers, NULL, ce_offset);
801 }
802
803 static void si_release_buffer_resources(struct si_buffer_resources *buffers,
804 struct si_descriptors *descs)
805 {
806 int i;
807
808 for (i = 0; i < descs->num_elements; i++) {
809 pipe_resource_reference(&buffers->buffers[i], NULL);
810 }
811
812 FREE(buffers->buffers);
813 }
814
815 static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
816 struct si_buffer_resources *buffers)
817 {
818 unsigned mask = buffers->enabled_mask;
819
820 /* Add buffers to the CS. */
821 while (mask) {
822 int i = u_bit_scan(&mask);
823
824 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
825 (struct r600_resource*)buffers->buffers[i],
826 buffers->shader_usage, buffers->priority);
827 }
828 }
829
830 /* VERTEX BUFFERS */
831
832 static void si_vertex_buffers_begin_new_cs(struct si_context *sctx)
833 {
834 struct si_descriptors *desc = &sctx->vertex_buffers;
835 int count = sctx->vertex_elements ? sctx->vertex_elements->count : 0;
836 int i;
837
838 for (i = 0; i < count; i++) {
839 int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
840
841 if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
842 continue;
843 if (!sctx->vertex_buffer[vb].buffer)
844 continue;
845
846 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
847 (struct r600_resource*)sctx->vertex_buffer[vb].buffer,
848 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
849 }
850
851 if (!desc->buffer)
852 return;
853 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
854 desc->buffer, RADEON_USAGE_READ,
855 RADEON_PRIO_DESCRIPTORS);
856 }
857
858 static bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
859 {
860 struct si_descriptors *desc = &sctx->vertex_buffers;
861 bool bound[SI_NUM_VERTEX_BUFFERS] = {};
862 unsigned i, count = sctx->vertex_elements->count;
863 uint64_t va;
864 uint32_t *ptr;
865
866 if (!sctx->vertex_buffers_dirty)
867 return true;
868 if (!count || !sctx->vertex_elements)
869 return true;
870
871 /* Vertex buffer descriptors are the only ones which are uploaded
872 * directly through a staging buffer and don't go through
873 * the fine-grained upload path.
874 */
875 u_upload_alloc(sctx->b.uploader, 0, count * 16, 256, &desc->buffer_offset,
876 (struct pipe_resource**)&desc->buffer, (void**)&ptr);
877 if (!desc->buffer)
878 return false;
879
880 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
881 desc->buffer, RADEON_USAGE_READ,
882 RADEON_PRIO_DESCRIPTORS);
883
884 assert(count <= SI_NUM_VERTEX_BUFFERS);
885
886 for (i = 0; i < count; i++) {
887 struct pipe_vertex_element *ve = &sctx->vertex_elements->elements[i];
888 struct pipe_vertex_buffer *vb;
889 struct r600_resource *rbuffer;
890 unsigned offset;
891 uint32_t *desc = &ptr[i*4];
892
893 if (ve->vertex_buffer_index >= ARRAY_SIZE(sctx->vertex_buffer)) {
894 memset(desc, 0, 16);
895 continue;
896 }
897
898 vb = &sctx->vertex_buffer[ve->vertex_buffer_index];
899 rbuffer = (struct r600_resource*)vb->buffer;
900 if (!rbuffer) {
901 memset(desc, 0, 16);
902 continue;
903 }
904
905 offset = vb->buffer_offset + ve->src_offset;
906 va = rbuffer->gpu_address + offset;
907
908 /* Fill in T# buffer resource description */
909 desc[0] = va;
910 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
911 S_008F04_STRIDE(vb->stride);
912
913 if (sctx->b.chip_class <= CIK && vb->stride)
914 /* Round up by rounding down and adding 1 */
915 desc[2] = (vb->buffer->width0 - offset -
916 sctx->vertex_elements->format_size[i]) /
917 vb->stride + 1;
918 else
919 desc[2] = vb->buffer->width0 - offset;
920
921 desc[3] = sctx->vertex_elements->rsrc_word3[i];
922
923 if (!bound[ve->vertex_buffer_index]) {
924 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
925 (struct r600_resource*)vb->buffer,
926 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
927 bound[ve->vertex_buffer_index] = true;
928 }
929 }
930
931 /* Don't flush the const cache. It would have a very negative effect
932 * on performance (confirmed by testing). New descriptors are always
933 * uploaded to a fresh new buffer, so I don't think flushing the const
934 * cache is needed. */
935 desc->pointer_dirty = true;
936 si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
937 sctx->vertex_buffers_dirty = false;
938 return true;
939 }
940
941
942 /* CONSTANT BUFFERS */
943
944 static unsigned
945 si_const_buffer_descriptors_idx(unsigned shader)
946 {
947 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
948 SI_SHADER_DESCS_CONST_BUFFERS;
949 }
950
951 static struct si_descriptors *
952 si_const_buffer_descriptors(struct si_context *sctx, unsigned shader)
953 {
954 return &sctx->descriptors[si_const_buffer_descriptors_idx(shader)];
955 }
956
957 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
958 const uint8_t *ptr, unsigned size, uint32_t *const_offset)
959 {
960 void *tmp;
961
962 u_upload_alloc(sctx->b.uploader, 0, size, 256, const_offset,
963 (struct pipe_resource**)rbuffer, &tmp);
964 if (*rbuffer)
965 util_memcpy_cpu_to_le32(tmp, ptr, size);
966 }
967
968 static void si_set_constant_buffer(struct si_context *sctx,
969 struct si_buffer_resources *buffers,
970 unsigned descriptors_idx,
971 uint slot, const struct pipe_constant_buffer *input)
972 {
973 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
974 assert(slot < descs->num_elements);
975 pipe_resource_reference(&buffers->buffers[slot], NULL);
976
977 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
978 * with a NULL buffer). We need to use a dummy buffer instead. */
979 if (sctx->b.chip_class == CIK &&
980 (!input || (!input->buffer && !input->user_buffer)))
981 input = &sctx->null_const_buf;
982
983 if (input && (input->buffer || input->user_buffer)) {
984 struct pipe_resource *buffer = NULL;
985 uint64_t va;
986
987 /* Upload the user buffer if needed. */
988 if (input->user_buffer) {
989 unsigned buffer_offset;
990
991 si_upload_const_buffer(sctx,
992 (struct r600_resource**)&buffer, input->user_buffer,
993 input->buffer_size, &buffer_offset);
994 if (!buffer) {
995 /* Just unbind on failure. */
996 si_set_constant_buffer(sctx, buffers, descriptors_idx, slot, NULL);
997 return;
998 }
999 va = r600_resource(buffer)->gpu_address + buffer_offset;
1000 } else {
1001 pipe_resource_reference(&buffer, input->buffer);
1002 va = r600_resource(buffer)->gpu_address + input->buffer_offset;
1003 }
1004
1005 /* Set the descriptor. */
1006 uint32_t *desc = descs->list + slot*4;
1007 desc[0] = va;
1008 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1009 S_008F04_STRIDE(0);
1010 desc[2] = input->buffer_size;
1011 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1012 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1013 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1014 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1015 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1016 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1017
1018 buffers->buffers[slot] = buffer;
1019 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1020 (struct r600_resource*)buffer,
1021 buffers->shader_usage, buffers->priority);
1022 buffers->enabled_mask |= 1u << slot;
1023 } else {
1024 /* Clear the descriptor. */
1025 memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4);
1026 buffers->enabled_mask &= ~(1u << slot);
1027 }
1028
1029 descs->dirty_mask |= 1u << slot;
1030 sctx->descriptors_dirty |= 1u << descriptors_idx;
1031 }
1032
1033 void si_set_rw_buffer(struct si_context *sctx,
1034 uint slot, const struct pipe_constant_buffer *input)
1035 {
1036 si_set_constant_buffer(sctx, &sctx->rw_buffers,
1037 SI_DESCS_RW_BUFFERS, slot, input);
1038 }
1039
1040 static void si_pipe_set_constant_buffer(struct pipe_context *ctx,
1041 uint shader, uint slot,
1042 const struct pipe_constant_buffer *input)
1043 {
1044 struct si_context *sctx = (struct si_context *)ctx;
1045
1046 if (shader >= SI_NUM_SHADERS)
1047 return;
1048
1049 si_set_constant_buffer(sctx, &sctx->const_buffers[shader],
1050 si_const_buffer_descriptors_idx(shader),
1051 slot, input);
1052 }
1053
1054 /* SHADER BUFFERS */
1055
1056 static unsigned
1057 si_shader_buffer_descriptors_idx(unsigned shader)
1058 {
1059 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
1060 SI_SHADER_DESCS_SHADER_BUFFERS;
1061 }
1062
1063 static struct si_descriptors *
1064 si_shader_buffer_descriptors(struct si_context *sctx, unsigned shader)
1065 {
1066 return &sctx->descriptors[si_shader_buffer_descriptors_idx(shader)];
1067 }
1068
1069 static void si_set_shader_buffers(struct pipe_context *ctx, unsigned shader,
1070 unsigned start_slot, unsigned count,
1071 const struct pipe_shader_buffer *sbuffers)
1072 {
1073 struct si_context *sctx = (struct si_context *)ctx;
1074 struct si_buffer_resources *buffers = &sctx->shader_buffers[shader];
1075 struct si_descriptors *descs = si_shader_buffer_descriptors(sctx, shader);
1076 unsigned i;
1077
1078 assert(start_slot + count <= SI_NUM_SHADER_BUFFERS);
1079
1080 for (i = 0; i < count; ++i) {
1081 const struct pipe_shader_buffer *sbuffer = sbuffers ? &sbuffers[i] : NULL;
1082 struct r600_resource *buf;
1083 unsigned slot = start_slot + i;
1084 uint32_t *desc = descs->list + slot * 4;
1085 uint64_t va;
1086
1087 if (!sbuffer || !sbuffer->buffer) {
1088 pipe_resource_reference(&buffers->buffers[slot], NULL);
1089 memset(desc, 0, sizeof(uint32_t) * 4);
1090 buffers->enabled_mask &= ~(1u << slot);
1091 descs->dirty_mask |= 1u << slot;
1092 sctx->descriptors_dirty |=
1093 1u << si_shader_buffer_descriptors_idx(shader);
1094 continue;
1095 }
1096
1097 buf = (struct r600_resource *)sbuffer->buffer;
1098 va = buf->gpu_address + sbuffer->buffer_offset;
1099
1100 desc[0] = va;
1101 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1102 S_008F04_STRIDE(0);
1103 desc[2] = sbuffer->buffer_size;
1104 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1105 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1106 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1107 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1108 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1109 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1110
1111 pipe_resource_reference(&buffers->buffers[slot], &buf->b.b);
1112 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buf,
1113 buffers->shader_usage, buffers->priority);
1114 buffers->enabled_mask |= 1u << slot;
1115 descs->dirty_mask |= 1u << slot;
1116 sctx->descriptors_dirty |=
1117 1u << si_shader_buffer_descriptors_idx(shader);
1118 }
1119 }
1120
1121 /* RING BUFFERS */
1122
1123 void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
1124 struct pipe_resource *buffer,
1125 unsigned stride, unsigned num_records,
1126 bool add_tid, bool swizzle,
1127 unsigned element_size, unsigned index_stride, uint64_t offset)
1128 {
1129 struct si_context *sctx = (struct si_context *)ctx;
1130 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1131 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1132
1133 /* The stride field in the resource descriptor has 14 bits */
1134 assert(stride < (1 << 14));
1135
1136 assert(slot < descs->num_elements);
1137 pipe_resource_reference(&buffers->buffers[slot], NULL);
1138
1139 if (buffer) {
1140 uint64_t va;
1141
1142 va = r600_resource(buffer)->gpu_address + offset;
1143
1144 switch (element_size) {
1145 default:
1146 assert(!"Unsupported ring buffer element size");
1147 case 0:
1148 case 2:
1149 element_size = 0;
1150 break;
1151 case 4:
1152 element_size = 1;
1153 break;
1154 case 8:
1155 element_size = 2;
1156 break;
1157 case 16:
1158 element_size = 3;
1159 break;
1160 }
1161
1162 switch (index_stride) {
1163 default:
1164 assert(!"Unsupported ring buffer index stride");
1165 case 0:
1166 case 8:
1167 index_stride = 0;
1168 break;
1169 case 16:
1170 index_stride = 1;
1171 break;
1172 case 32:
1173 index_stride = 2;
1174 break;
1175 case 64:
1176 index_stride = 3;
1177 break;
1178 }
1179
1180 if (sctx->b.chip_class >= VI && stride)
1181 num_records *= stride;
1182
1183 /* Set the descriptor. */
1184 uint32_t *desc = descs->list + slot*4;
1185 desc[0] = va;
1186 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1187 S_008F04_STRIDE(stride) |
1188 S_008F04_SWIZZLE_ENABLE(swizzle);
1189 desc[2] = num_records;
1190 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1191 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1192 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1193 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1194 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1195 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1196 S_008F0C_ELEMENT_SIZE(element_size) |
1197 S_008F0C_INDEX_STRIDE(index_stride) |
1198 S_008F0C_ADD_TID_ENABLE(add_tid);
1199
1200 pipe_resource_reference(&buffers->buffers[slot], buffer);
1201 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1202 (struct r600_resource*)buffer,
1203 buffers->shader_usage, buffers->priority);
1204 buffers->enabled_mask |= 1u << slot;
1205 } else {
1206 /* Clear the descriptor. */
1207 memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4);
1208 buffers->enabled_mask &= ~(1u << slot);
1209 }
1210
1211 descs->dirty_mask |= 1u << slot;
1212 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1213 }
1214
1215 /* STREAMOUT BUFFERS */
1216
1217 static void si_set_streamout_targets(struct pipe_context *ctx,
1218 unsigned num_targets,
1219 struct pipe_stream_output_target **targets,
1220 const unsigned *offsets)
1221 {
1222 struct si_context *sctx = (struct si_context *)ctx;
1223 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1224 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1225 unsigned old_num_targets = sctx->b.streamout.num_targets;
1226 unsigned i, bufidx;
1227
1228 /* We are going to unbind the buffers. Mark which caches need to be flushed. */
1229 if (sctx->b.streamout.num_targets && sctx->b.streamout.begin_emitted) {
1230 /* Since streamout uses vector writes which go through TC L2
1231 * and most other clients can use TC L2 as well, we don't need
1232 * to flush it.
1233 *
1234 * The only case which requires flushing it is VGT DMA index
1235 * fetching, which is a rare case. Thus, flag the TC L2
1236 * dirtiness in the resource and handle it when index fetching
1237 * is used.
1238 */
1239 for (i = 0; i < sctx->b.streamout.num_targets; i++)
1240 if (sctx->b.streamout.targets[i])
1241 r600_resource(sctx->b.streamout.targets[i]->b.buffer)->TC_L2_dirty = true;
1242
1243 /* Invalidate the scalar cache in case a streamout buffer is
1244 * going to be used as a constant buffer.
1245 *
1246 * Invalidate TC L1, because streamout bypasses it (done by
1247 * setting GLC=1 in the store instruction), but it can contain
1248 * outdated data of streamout buffers.
1249 *
1250 * VS_PARTIAL_FLUSH is required if the buffers are going to be
1251 * used as an input immediately.
1252 */
1253 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
1254 SI_CONTEXT_INV_VMEM_L1 |
1255 SI_CONTEXT_VS_PARTIAL_FLUSH;
1256 }
1257
1258 /* All readers of the streamout targets need to be finished before we can
1259 * start writing to the targets.
1260 */
1261 if (num_targets)
1262 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
1263 SI_CONTEXT_CS_PARTIAL_FLUSH;
1264
1265 /* Streamout buffers must be bound in 2 places:
1266 * 1) in VGT by setting the VGT_STRMOUT registers
1267 * 2) as shader resources
1268 */
1269
1270 /* Set the VGT regs. */
1271 r600_set_streamout_targets(ctx, num_targets, targets, offsets);
1272
1273 /* Set the shader resources.*/
1274 for (i = 0; i < num_targets; i++) {
1275 bufidx = SI_VS_STREAMOUT_BUF0 + i;
1276
1277 if (targets[i]) {
1278 struct pipe_resource *buffer = targets[i]->buffer;
1279 uint64_t va = r600_resource(buffer)->gpu_address;
1280
1281 /* Set the descriptor.
1282 *
1283 * On VI, the format must be non-INVALID, otherwise
1284 * the buffer will be considered not bound and store
1285 * instructions will be no-ops.
1286 */
1287 uint32_t *desc = descs->list + bufidx*4;
1288 desc[0] = va;
1289 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1290 desc[2] = 0xffffffff;
1291 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1292 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1293 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1294 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1295 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1296
1297 /* Set the resource. */
1298 pipe_resource_reference(&buffers->buffers[bufidx],
1299 buffer);
1300 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1301 (struct r600_resource*)buffer,
1302 buffers->shader_usage, buffers->priority);
1303 buffers->enabled_mask |= 1u << bufidx;
1304 } else {
1305 /* Clear the descriptor and unset the resource. */
1306 memset(descs->list + bufidx*4, 0,
1307 sizeof(uint32_t) * 4);
1308 pipe_resource_reference(&buffers->buffers[bufidx],
1309 NULL);
1310 buffers->enabled_mask &= ~(1u << bufidx);
1311 }
1312 descs->dirty_mask |= 1u << bufidx;
1313 }
1314 for (; i < old_num_targets; i++) {
1315 bufidx = SI_VS_STREAMOUT_BUF0 + i;
1316 /* Clear the descriptor and unset the resource. */
1317 memset(descs->list + bufidx*4, 0, sizeof(uint32_t) * 4);
1318 pipe_resource_reference(&buffers->buffers[bufidx], NULL);
1319 buffers->enabled_mask &= ~(1u << bufidx);
1320 descs->dirty_mask |= 1u << bufidx;
1321 }
1322
1323 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1324 }
1325
1326 static void si_desc_reset_buffer_offset(struct pipe_context *ctx,
1327 uint32_t *desc, uint64_t old_buf_va,
1328 struct pipe_resource *new_buf)
1329 {
1330 /* Retrieve the buffer offset from the descriptor. */
1331 uint64_t old_desc_va =
1332 desc[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc[1]) << 32);
1333
1334 assert(old_buf_va <= old_desc_va);
1335 uint64_t offset_within_buffer = old_desc_va - old_buf_va;
1336
1337 /* Update the descriptor. */
1338 uint64_t va = r600_resource(new_buf)->gpu_address + offset_within_buffer;
1339
1340 desc[0] = va;
1341 desc[1] = (desc[1] & C_008F04_BASE_ADDRESS_HI) |
1342 S_008F04_BASE_ADDRESS_HI(va >> 32);
1343 }
1344
1345 /* INTERNAL CONST BUFFERS */
1346
1347 static void si_set_polygon_stipple(struct pipe_context *ctx,
1348 const struct pipe_poly_stipple *state)
1349 {
1350 struct si_context *sctx = (struct si_context *)ctx;
1351 struct pipe_constant_buffer cb = {};
1352 unsigned stipple[32];
1353 int i;
1354
1355 for (i = 0; i < 32; i++)
1356 stipple[i] = util_bitreverse(state->stipple[i]);
1357
1358 cb.user_buffer = stipple;
1359 cb.buffer_size = sizeof(stipple);
1360
1361 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE, &cb);
1362 }
1363
1364 /* TEXTURE METADATA ENABLE/DISABLE */
1365
1366 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1367 * while the texture is bound, possibly by a different context. In that case,
1368 * call this function to update compressed_colortex_masks.
1369 */
1370 void si_update_compressed_colortex_masks(struct si_context *sctx)
1371 {
1372 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
1373 si_samplers_update_compressed_colortex_mask(&sctx->samplers[i]);
1374 si_images_update_compressed_colortex_mask(&sctx->images[i]);
1375 }
1376 }
1377
1378 /* BUFFER DISCARD/INVALIDATION */
1379
1380 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1381 static void si_reset_buffer_resources(struct si_context *sctx,
1382 struct si_buffer_resources *buffers,
1383 unsigned descriptors_idx,
1384 struct pipe_resource *buf,
1385 uint64_t old_va)
1386 {
1387 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
1388 unsigned mask = buffers->enabled_mask;
1389
1390 while (mask) {
1391 unsigned i = u_bit_scan(&mask);
1392 if (buffers->buffers[i] == buf) {
1393 si_desc_reset_buffer_offset(&sctx->b.b,
1394 descs->list + i*4,
1395 old_va, buf);
1396 descs->dirty_mask |= 1u << i;
1397 sctx->descriptors_dirty |= 1u << descriptors_idx;
1398
1399 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1400 (struct r600_resource *)buf,
1401 buffers->shader_usage,
1402 buffers->priority);
1403 }
1404 }
1405 }
1406
1407 /* Reallocate a buffer a update all resource bindings where the buffer is
1408 * bound.
1409 *
1410 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
1411 * idle by discarding its contents. Apps usually tell us when to do this using
1412 * map_buffer flags, for example.
1413 */
1414 static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
1415 {
1416 struct si_context *sctx = (struct si_context*)ctx;
1417 struct r600_resource *rbuffer = r600_resource(buf);
1418 unsigned i, shader, alignment = rbuffer->buf->alignment;
1419 uint64_t old_va = rbuffer->gpu_address;
1420 unsigned num_elems = sctx->vertex_elements ?
1421 sctx->vertex_elements->count : 0;
1422 struct si_sampler_view *view;
1423
1424 /* Reallocate the buffer in the same pipe_resource. */
1425 r600_init_resource(&sctx->screen->b, rbuffer, rbuffer->b.b.width0,
1426 alignment);
1427
1428 /* We changed the buffer, now we need to bind it where the old one
1429 * was bound. This consists of 2 things:
1430 * 1) Updating the resource descriptor and dirtying it.
1431 * 2) Adding a relocation to the CS, so that it's usable.
1432 */
1433
1434 /* Vertex buffers. */
1435 for (i = 0; i < num_elems; i++) {
1436 int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
1437
1438 if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
1439 continue;
1440 if (!sctx->vertex_buffer[vb].buffer)
1441 continue;
1442
1443 if (sctx->vertex_buffer[vb].buffer == buf) {
1444 sctx->vertex_buffers_dirty = true;
1445 break;
1446 }
1447 }
1448
1449 /* Streamout buffers. (other internal buffers can't be invalidated) */
1450 for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) {
1451 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1452 struct si_descriptors *descs =
1453 &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1454
1455 if (buffers->buffers[i] != buf)
1456 continue;
1457
1458 si_desc_reset_buffer_offset(ctx, descs->list + i*4,
1459 old_va, buf);
1460 descs->dirty_mask |= 1u << i;
1461 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1462
1463 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1464 rbuffer, buffers->shader_usage,
1465 buffers->priority);
1466
1467 /* Update the streamout state. */
1468 if (sctx->b.streamout.begin_emitted)
1469 r600_emit_streamout_end(&sctx->b);
1470 sctx->b.streamout.append_bitmask =
1471 sctx->b.streamout.enabled_mask;
1472 r600_streamout_buffers_dirty(&sctx->b);
1473 }
1474
1475 /* Constant and shader buffers. */
1476 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1477 si_reset_buffer_resources(sctx, &sctx->const_buffers[shader],
1478 si_const_buffer_descriptors_idx(shader),
1479 buf, old_va);
1480 si_reset_buffer_resources(sctx, &sctx->shader_buffers[shader],
1481 si_shader_buffer_descriptors_idx(shader),
1482 buf, old_va);
1483 }
1484
1485 /* Texture buffers - update virtual addresses in sampler view descriptors. */
1486 LIST_FOR_EACH_ENTRY(view, &sctx->b.texture_buffers, list) {
1487 if (view->base.texture == buf) {
1488 si_desc_reset_buffer_offset(ctx, &view->state[4], old_va, buf);
1489 }
1490 }
1491 /* Texture buffers - update bindings. */
1492 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1493 struct si_sampler_views *views = &sctx->samplers[shader].views;
1494 struct si_descriptors *descs =
1495 si_sampler_descriptors(sctx, shader);
1496 unsigned mask = views->enabled_mask;
1497
1498 while (mask) {
1499 unsigned i = u_bit_scan(&mask);
1500 if (views->views[i]->texture == buf) {
1501 si_desc_reset_buffer_offset(ctx,
1502 descs->list +
1503 i * 16 + 4,
1504 old_va, buf);
1505 descs->dirty_mask |= 1u << i;
1506 sctx->descriptors_dirty |=
1507 1u << si_sampler_descriptors_idx(shader);
1508
1509 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1510 rbuffer, RADEON_USAGE_READ,
1511 RADEON_PRIO_SAMPLER_BUFFER);
1512 }
1513 }
1514 }
1515
1516 /* Shader images */
1517 for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
1518 struct si_images_info *images = &sctx->images[shader];
1519 struct si_descriptors *descs =
1520 si_image_descriptors(sctx, shader);
1521 unsigned mask = images->enabled_mask;
1522
1523 while (mask) {
1524 unsigned i = u_bit_scan(&mask);
1525
1526 if (images->views[i].resource == buf) {
1527 if (images->views[i].access & PIPE_IMAGE_ACCESS_WRITE)
1528 si_mark_image_range_valid(&images->views[i]);
1529
1530 si_desc_reset_buffer_offset(
1531 ctx, descs->list + i * 8 + 4,
1532 old_va, buf);
1533 descs->dirty_mask |= 1u << i;
1534 sctx->descriptors_dirty |=
1535 1u << si_image_descriptors_idx(shader);
1536
1537 radeon_add_to_buffer_list(
1538 &sctx->b, &sctx->b.gfx, rbuffer,
1539 RADEON_USAGE_READWRITE,
1540 RADEON_PRIO_SAMPLER_BUFFER);
1541 }
1542 }
1543 }
1544 }
1545
1546 /* Update mutable image descriptor fields of all bound textures. */
1547 void si_update_all_texture_descriptors(struct si_context *sctx)
1548 {
1549 unsigned shader;
1550
1551 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1552 struct si_sampler_views *samplers = &sctx->samplers[shader].views;
1553 struct si_images_info *images = &sctx->images[shader];
1554 unsigned mask;
1555
1556 /* Images. */
1557 mask = images->enabled_mask;
1558 while (mask) {
1559 unsigned i = u_bit_scan(&mask);
1560 struct pipe_image_view *view = &images->views[i];
1561
1562 if (!view->resource ||
1563 view->resource->target == PIPE_BUFFER)
1564 continue;
1565
1566 si_set_shader_image(sctx, shader, i, view);
1567 }
1568
1569 /* Sampler views. */
1570 mask = samplers->enabled_mask;
1571 while (mask) {
1572 unsigned i = u_bit_scan(&mask);
1573 struct pipe_sampler_view *view = samplers->views[i];
1574
1575 if (!view ||
1576 !view->texture ||
1577 view->texture->target == PIPE_BUFFER)
1578 continue;
1579
1580 si_set_sampler_view(sctx, shader, i,
1581 samplers->views[i], true);
1582 }
1583 }
1584 }
1585
1586 /* SHADER USER DATA */
1587
1588 static void si_mark_shader_pointers_dirty(struct si_context *sctx,
1589 unsigned shader)
1590 {
1591 struct si_descriptors *descs =
1592 &sctx->descriptors[SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS];
1593
1594 for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs)
1595 descs->pointer_dirty = true;
1596
1597 if (shader == PIPE_SHADER_VERTEX)
1598 sctx->vertex_buffers.pointer_dirty = true;
1599
1600 si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
1601 }
1602
1603 static void si_shader_userdata_begin_new_cs(struct si_context *sctx)
1604 {
1605 int i;
1606
1607 for (i = 0; i < SI_NUM_SHADERS; i++) {
1608 si_mark_shader_pointers_dirty(sctx, i);
1609 }
1610 sctx->descriptors[SI_DESCS_RW_BUFFERS].pointer_dirty = true;
1611 }
1612
1613 /* Set a base register address for user data constants in the given shader.
1614 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1615 */
1616 static void si_set_user_data_base(struct si_context *sctx,
1617 unsigned shader, uint32_t new_base)
1618 {
1619 uint32_t *base = &sctx->shader_userdata.sh_base[shader];
1620
1621 if (*base != new_base) {
1622 *base = new_base;
1623
1624 if (new_base)
1625 si_mark_shader_pointers_dirty(sctx, shader);
1626 }
1627 }
1628
1629 /* This must be called when these shaders are changed from non-NULL to NULL
1630 * and vice versa:
1631 * - geometry shader
1632 * - tessellation control shader
1633 * - tessellation evaluation shader
1634 */
1635 void si_shader_change_notify(struct si_context *sctx)
1636 {
1637 /* VS can be bound as VS, ES, or LS. */
1638 if (sctx->tes_shader.cso)
1639 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1640 R_00B530_SPI_SHADER_USER_DATA_LS_0);
1641 else if (sctx->gs_shader.cso)
1642 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1643 R_00B330_SPI_SHADER_USER_DATA_ES_0);
1644 else
1645 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1646 R_00B130_SPI_SHADER_USER_DATA_VS_0);
1647
1648 /* TES can be bound as ES, VS, or not bound. */
1649 if (sctx->tes_shader.cso) {
1650 if (sctx->gs_shader.cso)
1651 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
1652 R_00B330_SPI_SHADER_USER_DATA_ES_0);
1653 else
1654 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
1655 R_00B130_SPI_SHADER_USER_DATA_VS_0);
1656 } else {
1657 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, 0);
1658 }
1659 }
1660
1661 static void si_emit_shader_pointer(struct si_context *sctx,
1662 struct si_descriptors *desc,
1663 unsigned sh_base, bool keep_dirty)
1664 {
1665 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1666 uint64_t va;
1667
1668 if (!desc->pointer_dirty || !desc->buffer)
1669 return;
1670
1671 va = desc->buffer->gpu_address +
1672 desc->buffer_offset;
1673
1674 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0));
1675 radeon_emit(cs, (sh_base + desc->shader_userdata_offset - SI_SH_REG_OFFSET) >> 2);
1676 radeon_emit(cs, va);
1677 radeon_emit(cs, va >> 32);
1678
1679 desc->pointer_dirty = keep_dirty;
1680 }
1681
1682 void si_emit_graphics_shader_userdata(struct si_context *sctx,
1683 struct r600_atom *atom)
1684 {
1685 unsigned shader;
1686 uint32_t *sh_base = sctx->shader_userdata.sh_base;
1687 struct si_descriptors *descs;
1688
1689 descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1690
1691 if (descs->pointer_dirty) {
1692 si_emit_shader_pointer(sctx, descs,
1693 R_00B030_SPI_SHADER_USER_DATA_PS_0, true);
1694 si_emit_shader_pointer(sctx, descs,
1695 R_00B130_SPI_SHADER_USER_DATA_VS_0, true);
1696 si_emit_shader_pointer(sctx, descs,
1697 R_00B230_SPI_SHADER_USER_DATA_GS_0, true);
1698 si_emit_shader_pointer(sctx, descs,
1699 R_00B330_SPI_SHADER_USER_DATA_ES_0, true);
1700 si_emit_shader_pointer(sctx, descs,
1701 R_00B430_SPI_SHADER_USER_DATA_HS_0, true);
1702 descs->pointer_dirty = false;
1703 }
1704
1705 descs = &sctx->descriptors[SI_DESCS_FIRST_SHADER];
1706
1707 for (shader = 0; shader < SI_NUM_GRAPHICS_SHADERS; shader++) {
1708 unsigned base = sh_base[shader];
1709 unsigned i;
1710
1711 if (!base)
1712 continue;
1713
1714 for (i = 0; i < SI_NUM_SHADER_DESCS; i++, descs++)
1715 si_emit_shader_pointer(sctx, descs, base, false);
1716 }
1717 si_emit_shader_pointer(sctx, &sctx->vertex_buffers, sh_base[PIPE_SHADER_VERTEX], false);
1718 }
1719
1720 void si_emit_compute_shader_userdata(struct si_context *sctx)
1721 {
1722 unsigned base = R_00B900_COMPUTE_USER_DATA_0;
1723 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_FIRST_COMPUTE];
1724
1725 for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs)
1726 si_emit_shader_pointer(sctx, descs, base, false);
1727 }
1728
1729 /* INIT/DEINIT/UPLOAD */
1730
1731 void si_init_all_descriptors(struct si_context *sctx)
1732 {
1733 int i;
1734 unsigned ce_offset = 0;
1735
1736 for (i = 0; i < SI_NUM_SHADERS; i++) {
1737 si_init_buffer_resources(&sctx->const_buffers[i],
1738 si_const_buffer_descriptors(sctx, i),
1739 SI_NUM_CONST_BUFFERS, SI_SGPR_CONST_BUFFERS,
1740 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER,
1741 &ce_offset);
1742 si_init_buffer_resources(&sctx->shader_buffers[i],
1743 si_shader_buffer_descriptors(sctx, i),
1744 SI_NUM_SHADER_BUFFERS, SI_SGPR_SHADER_BUFFERS,
1745 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RW_BUFFER,
1746 &ce_offset);
1747
1748 si_init_descriptors(si_sampler_descriptors(sctx, i),
1749 SI_SGPR_SAMPLERS, 16, SI_NUM_SAMPLERS,
1750 null_texture_descriptor, &ce_offset);
1751
1752 si_init_descriptors(si_image_descriptors(sctx, i),
1753 SI_SGPR_IMAGES, 8, SI_NUM_IMAGES,
1754 null_image_descriptor, &ce_offset);
1755 }
1756
1757 si_init_buffer_resources(&sctx->rw_buffers,
1758 &sctx->descriptors[SI_DESCS_RW_BUFFERS],
1759 SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS,
1760 RADEON_USAGE_READWRITE, RADEON_PRIO_RINGS_STREAMOUT,
1761 &ce_offset);
1762 si_init_descriptors(&sctx->vertex_buffers, SI_SGPR_VERTEX_BUFFERS,
1763 4, SI_NUM_VERTEX_BUFFERS, NULL, NULL);
1764
1765 sctx->descriptors_dirty = u_bit_consecutive(0, SI_NUM_DESCS);
1766
1767 assert(ce_offset <= 32768);
1768
1769 /* Set pipe_context functions. */
1770 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
1771 sctx->b.b.set_shader_images = si_set_shader_images;
1772 sctx->b.b.set_constant_buffer = si_pipe_set_constant_buffer;
1773 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
1774 sctx->b.b.set_shader_buffers = si_set_shader_buffers;
1775 sctx->b.b.set_sampler_views = si_set_sampler_views;
1776 sctx->b.b.set_stream_output_targets = si_set_streamout_targets;
1777 sctx->b.invalidate_buffer = si_invalidate_buffer;
1778
1779 /* Shader user data. */
1780 si_init_atom(sctx, &sctx->shader_userdata.atom, &sctx->atoms.s.shader_userdata,
1781 si_emit_graphics_shader_userdata);
1782
1783 /* Set default and immutable mappings. */
1784 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
1785 si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, R_00B430_SPI_SHADER_USER_DATA_HS_0);
1786 si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, R_00B230_SPI_SHADER_USER_DATA_GS_0);
1787 si_set_user_data_base(sctx, PIPE_SHADER_FRAGMENT, R_00B030_SPI_SHADER_USER_DATA_PS_0);
1788 }
1789
1790 bool si_upload_graphics_shader_descriptors(struct si_context *sctx)
1791 {
1792 const unsigned mask = u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE);
1793 unsigned dirty = sctx->descriptors_dirty & mask;
1794
1795 while (dirty) {
1796 unsigned i = u_bit_scan(&dirty);
1797
1798 if (!si_upload_descriptors(sctx, &sctx->descriptors[i],
1799 &sctx->shader_userdata.atom))
1800 return false;
1801 }
1802
1803 sctx->descriptors_dirty &= ~mask;
1804
1805 return si_upload_vertex_buffer_descriptors(sctx);
1806 }
1807
1808 bool si_upload_compute_shader_descriptors(struct si_context *sctx)
1809 {
1810 /* Does not update rw_buffers as that is not needed for compute shaders
1811 * and the input buffer is using the same SGPR's anyway.
1812 */
1813 const unsigned mask = u_bit_consecutive(SI_DESCS_FIRST_COMPUTE,
1814 SI_NUM_DESCS - SI_DESCS_FIRST_COMPUTE);
1815 unsigned dirty = sctx->descriptors_dirty & mask;
1816
1817 while (dirty) {
1818 unsigned i = u_bit_scan(&dirty);
1819
1820 if (!si_upload_descriptors(sctx, &sctx->descriptors[i], NULL))
1821 return false;
1822 }
1823
1824 sctx->descriptors_dirty &= ~mask;
1825
1826 return true;
1827 }
1828
1829 void si_release_all_descriptors(struct si_context *sctx)
1830 {
1831 int i;
1832
1833 for (i = 0; i < SI_NUM_SHADERS; i++) {
1834 si_release_buffer_resources(&sctx->const_buffers[i],
1835 si_const_buffer_descriptors(sctx, i));
1836 si_release_buffer_resources(&sctx->shader_buffers[i],
1837 si_shader_buffer_descriptors(sctx, i));
1838 si_release_sampler_views(&sctx->samplers[i].views);
1839 si_release_image_views(&sctx->images[i]);
1840 }
1841 si_release_buffer_resources(&sctx->rw_buffers,
1842 &sctx->descriptors[SI_DESCS_RW_BUFFERS]);
1843
1844 for (i = 0; i < SI_NUM_DESCS; ++i)
1845 si_release_descriptors(&sctx->descriptors[i]);
1846 si_release_descriptors(&sctx->vertex_buffers);
1847 }
1848
1849 void si_all_descriptors_begin_new_cs(struct si_context *sctx)
1850 {
1851 int i;
1852
1853 for (i = 0; i < SI_NUM_SHADERS; i++) {
1854 si_buffer_resources_begin_new_cs(sctx, &sctx->const_buffers[i]);
1855 si_buffer_resources_begin_new_cs(sctx, &sctx->shader_buffers[i]);
1856 si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i].views);
1857 si_image_views_begin_new_cs(sctx, &sctx->images[i]);
1858 }
1859 si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers);
1860 si_vertex_buffers_begin_new_cs(sctx);
1861
1862 for (i = 0; i < SI_NUM_DESCS; ++i)
1863 si_descriptors_begin_new_cs(sctx, &sctx->descriptors[i]);
1864
1865 si_shader_userdata_begin_new_cs(sctx);
1866 }