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gallium: change pipe_sampler_view::first_element/last_element -> offset/size
[mesa.git] / src / gallium / drivers / radeonsi / si_descriptors.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Marek Olšák <marek.olsak@amd.com>
25 */
26
27 /* Resource binding slots and sampler states (each described with 8 or
28 * 4 dwords) are stored in lists in memory which is accessed by shaders
29 * using scalar load instructions.
30 *
31 * This file is responsible for managing such lists. It keeps a copy of all
32 * descriptors in CPU memory and re-uploads a whole list if some slots have
33 * been changed.
34 *
35 * This code is also reponsible for updating shader pointers to those lists.
36 *
37 * Note that CP DMA can't be used for updating the lists, because a GPU hang
38 * could leave the list in a mid-IB state and the next IB would get wrong
39 * descriptors and the whole context would be unusable at that point.
40 * (Note: The register shadowing can't be used due to the same reason)
41 *
42 * Also, uploading descriptors to newly allocated memory doesn't require
43 * a KCACHE flush.
44 *
45 *
46 * Possible scenarios for one 16 dword image+sampler slot:
47 *
48 * | Image | w/ FMASK | Buffer | NULL
49 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
50 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
51 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
52 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
53 *
54 * FMASK implies MSAA, therefore no sampler state.
55 * Sampler states are never unbound except when FMASK is bound.
56 */
57
58 #include "radeon/r600_cs.h"
59 #include "si_pipe.h"
60 #include "si_shader.h"
61 #include "sid.h"
62
63 #include "util/u_format.h"
64 #include "util/u_math.h"
65 #include "util/u_memory.h"
66 #include "util/u_suballoc.h"
67 #include "util/u_upload_mgr.h"
68
69
70 /* NULL image and buffer descriptor for textures (alpha = 1) and images
71 * (alpha = 0).
72 *
73 * For images, all fields must be zero except for the swizzle, which
74 * supports arbitrary combinations of 0s and 1s. The texture type must be
75 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
76 *
77 * For buffers, all fields must be zero. If they are not, the hw hangs.
78 *
79 * This is the only reason why the buffer descriptor must be in words [4:7].
80 */
81 static uint32_t null_texture_descriptor[8] = {
82 0,
83 0,
84 0,
85 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1) |
86 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
87 /* the rest must contain zeros, which is also used by the buffer
88 * descriptor */
89 };
90
91 static uint32_t null_image_descriptor[8] = {
92 0,
93 0,
94 0,
95 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
96 /* the rest must contain zeros, which is also used by the buffer
97 * descriptor */
98 };
99
100 static void si_init_descriptors(struct si_descriptors *desc,
101 unsigned shader_userdata_index,
102 unsigned element_dw_size,
103 unsigned num_elements,
104 const uint32_t *null_descriptor,
105 unsigned *ce_offset)
106 {
107 int i;
108
109 assert(num_elements <= sizeof(desc->dirty_mask)*8);
110
111 desc->list = CALLOC(num_elements, element_dw_size * 4);
112 desc->element_dw_size = element_dw_size;
113 desc->num_elements = num_elements;
114 desc->dirty_mask = num_elements == 32 ? ~0u : (1u << num_elements) - 1;
115 desc->shader_userdata_offset = shader_userdata_index * 4;
116
117 if (ce_offset) {
118 desc->ce_offset = *ce_offset;
119
120 /* make sure that ce_offset stays 32 byte aligned */
121 *ce_offset += align(element_dw_size * num_elements * 4, 32);
122 }
123
124 /* Initialize the array to NULL descriptors if the element size is 8. */
125 if (null_descriptor) {
126 assert(element_dw_size % 8 == 0);
127 for (i = 0; i < num_elements * element_dw_size / 8; i++)
128 memcpy(desc->list + i * 8, null_descriptor,
129 8 * 4);
130 }
131 }
132
133 static void si_release_descriptors(struct si_descriptors *desc)
134 {
135 r600_resource_reference(&desc->buffer, NULL);
136 FREE(desc->list);
137 }
138
139 static bool si_ce_upload(struct si_context *sctx, unsigned ce_offset, unsigned size,
140 unsigned *out_offset, struct r600_resource **out_buf) {
141 uint64_t va;
142
143 u_suballocator_alloc(sctx->ce_suballocator, size, 64, out_offset,
144 (struct pipe_resource**)out_buf);
145 if (!out_buf)
146 return false;
147
148 va = (*out_buf)->gpu_address + *out_offset;
149
150 radeon_emit(sctx->ce_ib, PKT3(PKT3_DUMP_CONST_RAM, 3, 0));
151 radeon_emit(sctx->ce_ib, ce_offset);
152 radeon_emit(sctx->ce_ib, size / 4);
153 radeon_emit(sctx->ce_ib, va);
154 radeon_emit(sctx->ce_ib, va >> 32);
155
156 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, *out_buf,
157 RADEON_USAGE_READWRITE, RADEON_PRIO_DESCRIPTORS);
158
159 sctx->ce_need_synchronization = true;
160 return true;
161 }
162
163 static void si_ce_reinitialize_descriptors(struct si_context *sctx,
164 struct si_descriptors *desc)
165 {
166 if (desc->buffer) {
167 struct r600_resource *buffer = (struct r600_resource*)desc->buffer;
168 unsigned list_size = desc->num_elements * desc->element_dw_size * 4;
169 uint64_t va = buffer->gpu_address + desc->buffer_offset;
170 struct radeon_winsys_cs *ib = sctx->ce_preamble_ib;
171
172 if (!ib)
173 ib = sctx->ce_ib;
174
175 list_size = align(list_size, 32);
176
177 radeon_emit(ib, PKT3(PKT3_LOAD_CONST_RAM, 3, 0));
178 radeon_emit(ib, va);
179 radeon_emit(ib, va >> 32);
180 radeon_emit(ib, list_size / 4);
181 radeon_emit(ib, desc->ce_offset);
182
183 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
184 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
185 }
186 desc->ce_ram_dirty = false;
187 }
188
189 void si_ce_reinitialize_all_descriptors(struct si_context *sctx)
190 {
191 int i;
192
193 for (i = 0; i < SI_NUM_DESCS; ++i)
194 si_ce_reinitialize_descriptors(sctx, &sctx->descriptors[i]);
195 }
196
197 void si_ce_enable_loads(struct radeon_winsys_cs *ib)
198 {
199 radeon_emit(ib, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
200 radeon_emit(ib, CONTEXT_CONTROL_LOAD_ENABLE(1) |
201 CONTEXT_CONTROL_LOAD_CE_RAM(1));
202 radeon_emit(ib, CONTEXT_CONTROL_SHADOW_ENABLE(1));
203 }
204
205 static bool si_upload_descriptors(struct si_context *sctx,
206 struct si_descriptors *desc,
207 struct r600_atom * atom)
208 {
209 unsigned list_size = desc->num_elements * desc->element_dw_size * 4;
210
211 if (!desc->dirty_mask)
212 return true;
213
214 if (sctx->ce_ib) {
215 uint32_t const* list = (uint32_t const*)desc->list;
216
217 if (desc->ce_ram_dirty)
218 si_ce_reinitialize_descriptors(sctx, desc);
219
220 while(desc->dirty_mask) {
221 int begin, count;
222 u_bit_scan_consecutive_range(&desc->dirty_mask, &begin,
223 &count);
224
225 begin *= desc->element_dw_size;
226 count *= desc->element_dw_size;
227
228 radeon_emit(sctx->ce_ib,
229 PKT3(PKT3_WRITE_CONST_RAM, count, 0));
230 radeon_emit(sctx->ce_ib, desc->ce_offset + begin * 4);
231 radeon_emit_array(sctx->ce_ib, list + begin, count);
232 }
233
234 if (!si_ce_upload(sctx, desc->ce_offset, list_size,
235 &desc->buffer_offset, &desc->buffer))
236 return false;
237 } else {
238 void *ptr;
239
240 u_upload_alloc(sctx->b.uploader, 0, list_size, 256,
241 &desc->buffer_offset,
242 (struct pipe_resource**)&desc->buffer, &ptr);
243 if (!desc->buffer)
244 return false; /* skip the draw call */
245
246 util_memcpy_cpu_to_le32(ptr, desc->list, list_size);
247
248 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
249 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
250 }
251 desc->pointer_dirty = true;
252 desc->dirty_mask = 0;
253
254 if (atom)
255 si_mark_atom_dirty(sctx, atom);
256
257 return true;
258 }
259
260 static void
261 si_descriptors_begin_new_cs(struct si_context *sctx, struct si_descriptors *desc)
262 {
263 desc->ce_ram_dirty = true;
264
265 if (!desc->buffer)
266 return;
267
268 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
269 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
270 }
271
272 /* SAMPLER VIEWS */
273
274 static unsigned
275 si_sampler_descriptors_idx(unsigned shader)
276 {
277 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
278 SI_SHADER_DESCS_SAMPLERS;
279 }
280
281 static struct si_descriptors *
282 si_sampler_descriptors(struct si_context *sctx, unsigned shader)
283 {
284 return &sctx->descriptors[si_sampler_descriptors_idx(shader)];
285 }
286
287 static void si_release_sampler_views(struct si_sampler_views *views)
288 {
289 int i;
290
291 for (i = 0; i < ARRAY_SIZE(views->views); i++) {
292 pipe_sampler_view_reference(&views->views[i], NULL);
293 }
294 }
295
296 static void si_sampler_view_add_buffer(struct si_context *sctx,
297 struct pipe_resource *resource,
298 enum radeon_bo_usage usage,
299 bool is_stencil_sampler,
300 bool check_mem)
301 {
302 struct r600_resource *rres;
303 struct r600_texture *rtex;
304 enum radeon_bo_priority priority;
305
306 if (!resource)
307 return;
308
309 if (resource->target != PIPE_BUFFER) {
310 struct r600_texture *tex = (struct r600_texture*)resource;
311
312 if (tex->is_depth && !r600_can_sample_zs(tex, is_stencil_sampler))
313 resource = &tex->flushed_depth_texture->resource.b.b;
314 }
315
316 rres = (struct r600_resource*)resource;
317 priority = r600_get_sampler_view_priority(rres);
318
319 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
320 rres, usage, priority,
321 check_mem);
322
323 if (resource->target == PIPE_BUFFER)
324 return;
325
326 /* Now add separate DCC if it's present. */
327 rtex = (struct r600_texture*)resource;
328 if (!rtex->dcc_separate_buffer)
329 return;
330
331 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
332 rtex->dcc_separate_buffer, usage,
333 RADEON_PRIO_DCC, check_mem);
334 }
335
336 static void si_sampler_views_begin_new_cs(struct si_context *sctx,
337 struct si_sampler_views *views)
338 {
339 unsigned mask = views->enabled_mask;
340
341 /* Add buffers to the CS. */
342 while (mask) {
343 int i = u_bit_scan(&mask);
344 struct si_sampler_view *sview = (struct si_sampler_view *)views->views[i];
345
346 si_sampler_view_add_buffer(sctx, sview->base.texture,
347 RADEON_USAGE_READ,
348 sview->is_stencil_sampler, false);
349 }
350 }
351
352 /* Set texture descriptor fields that can be changed by reallocations.
353 *
354 * \param tex texture
355 * \param base_level_info information of the level of BASE_ADDRESS
356 * \param base_level the level of BASE_ADDRESS
357 * \param first_level pipe_sampler_view.u.tex.first_level
358 * \param block_width util_format_get_blockwidth()
359 * \param is_stencil select between separate Z & Stencil
360 * \param state descriptor to update
361 */
362 void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
363 const struct radeon_surf_level *base_level_info,
364 unsigned base_level, unsigned first_level,
365 unsigned block_width, bool is_stencil,
366 uint32_t *state)
367 {
368 uint64_t va;
369 unsigned pitch = base_level_info->nblk_x * block_width;
370
371 if (tex->is_depth && !r600_can_sample_zs(tex, is_stencil)) {
372 tex = tex->flushed_depth_texture;
373 is_stencil = false;
374 }
375
376 va = tex->resource.gpu_address + base_level_info->offset;
377
378 state[1] &= C_008F14_BASE_ADDRESS_HI;
379 state[3] &= C_008F1C_TILING_INDEX;
380 state[4] &= C_008F20_PITCH;
381 state[6] &= C_008F28_COMPRESSION_EN;
382
383 state[0] = va >> 8;
384 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
385 state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(tex, base_level,
386 is_stencil));
387 state[4] |= S_008F20_PITCH(pitch - 1);
388
389 if (tex->dcc_offset && tex->surface.level[first_level].dcc_enabled) {
390 state[6] |= S_008F28_COMPRESSION_EN(1);
391 state[7] = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
392 tex->dcc_offset +
393 base_level_info->dcc_offset) >> 8;
394 }
395 }
396
397 static void si_set_sampler_view(struct si_context *sctx,
398 unsigned shader,
399 unsigned slot, struct pipe_sampler_view *view,
400 bool disallow_early_out)
401 {
402 struct si_sampler_views *views = &sctx->samplers[shader].views;
403 struct si_sampler_view *rview = (struct si_sampler_view*)view;
404 struct si_descriptors *descs = si_sampler_descriptors(sctx, shader);
405
406 if (views->views[slot] == view && !disallow_early_out)
407 return;
408
409 if (view) {
410 struct r600_texture *rtex = (struct r600_texture *)view->texture;
411 uint32_t *desc = descs->list + slot * 16;
412
413 si_sampler_view_add_buffer(sctx, view->texture,
414 RADEON_USAGE_READ,
415 rview->is_stencil_sampler, true);
416
417 pipe_sampler_view_reference(&views->views[slot], view);
418 memcpy(desc, rview->state, 8*4);
419
420 if (view->texture && view->texture->target != PIPE_BUFFER) {
421 bool is_separate_stencil =
422 rtex->db_compatible &&
423 rview->is_stencil_sampler;
424
425 si_set_mutable_tex_desc_fields(rtex,
426 rview->base_level_info,
427 rview->base_level,
428 rview->base.u.tex.first_level,
429 rview->block_width,
430 is_separate_stencil,
431 desc);
432 }
433
434 if (view->texture && view->texture->target != PIPE_BUFFER &&
435 rtex->fmask.size) {
436 memcpy(desc + 8,
437 rview->fmask_state, 8*4);
438 } else {
439 /* Disable FMASK and bind sampler state in [12:15]. */
440 memcpy(desc + 8,
441 null_texture_descriptor, 4*4);
442
443 if (views->sampler_states[slot])
444 memcpy(desc + 12,
445 views->sampler_states[slot], 4*4);
446 }
447
448 views->enabled_mask |= 1u << slot;
449 } else {
450 pipe_sampler_view_reference(&views->views[slot], NULL);
451 memcpy(descs->list + slot*16, null_texture_descriptor, 8*4);
452 /* Only clear the lower dwords of FMASK. */
453 memcpy(descs->list + slot*16 + 8, null_texture_descriptor, 4*4);
454 views->enabled_mask &= ~(1u << slot);
455 }
456
457 descs->dirty_mask |= 1u << slot;
458 sctx->descriptors_dirty |= 1u << si_sampler_descriptors_idx(shader);
459 }
460
461 static bool is_compressed_colortex(struct r600_texture *rtex)
462 {
463 return rtex->cmask.size || rtex->fmask.size ||
464 (rtex->dcc_offset && rtex->dirty_level_mask);
465 }
466
467 static void si_set_sampler_views(struct pipe_context *ctx,
468 unsigned shader, unsigned start,
469 unsigned count,
470 struct pipe_sampler_view **views)
471 {
472 struct si_context *sctx = (struct si_context *)ctx;
473 struct si_textures_info *samplers = &sctx->samplers[shader];
474 int i;
475
476 if (!count || shader >= SI_NUM_SHADERS)
477 return;
478
479 for (i = 0; i < count; i++) {
480 unsigned slot = start + i;
481
482 if (!views || !views[i]) {
483 samplers->depth_texture_mask &= ~(1u << slot);
484 samplers->compressed_colortex_mask &= ~(1u << slot);
485 si_set_sampler_view(sctx, shader, slot, NULL, false);
486 continue;
487 }
488
489 si_set_sampler_view(sctx, shader, slot, views[i], false);
490
491 if (views[i]->texture && views[i]->texture->target != PIPE_BUFFER) {
492 struct r600_texture *rtex =
493 (struct r600_texture*)views[i]->texture;
494
495 if (rtex->db_compatible) {
496 samplers->depth_texture_mask |= 1u << slot;
497 } else {
498 samplers->depth_texture_mask &= ~(1u << slot);
499 }
500 if (is_compressed_colortex(rtex)) {
501 samplers->compressed_colortex_mask |= 1u << slot;
502 } else {
503 samplers->compressed_colortex_mask &= ~(1u << slot);
504 }
505
506 if (rtex->dcc_offset &&
507 p_atomic_read(&rtex->framebuffers_bound))
508 sctx->need_check_render_feedback = true;
509 } else {
510 samplers->depth_texture_mask &= ~(1u << slot);
511 samplers->compressed_colortex_mask &= ~(1u << slot);
512 }
513 }
514 }
515
516 static void
517 si_samplers_update_compressed_colortex_mask(struct si_textures_info *samplers)
518 {
519 unsigned mask = samplers->views.enabled_mask;
520
521 while (mask) {
522 int i = u_bit_scan(&mask);
523 struct pipe_resource *res = samplers->views.views[i]->texture;
524
525 if (res && res->target != PIPE_BUFFER) {
526 struct r600_texture *rtex = (struct r600_texture *)res;
527
528 if (is_compressed_colortex(rtex)) {
529 samplers->compressed_colortex_mask |= 1u << i;
530 } else {
531 samplers->compressed_colortex_mask &= ~(1u << i);
532 }
533 }
534 }
535 }
536
537 /* IMAGE VIEWS */
538
539 static unsigned
540 si_image_descriptors_idx(unsigned shader)
541 {
542 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
543 SI_SHADER_DESCS_IMAGES;
544 }
545
546 static struct si_descriptors*
547 si_image_descriptors(struct si_context *sctx, unsigned shader)
548 {
549 return &sctx->descriptors[si_image_descriptors_idx(shader)];
550 }
551
552 static void
553 si_release_image_views(struct si_images_info *images)
554 {
555 unsigned i;
556
557 for (i = 0; i < SI_NUM_IMAGES; ++i) {
558 struct pipe_image_view *view = &images->views[i];
559
560 pipe_resource_reference(&view->resource, NULL);
561 }
562 }
563
564 static void
565 si_image_views_begin_new_cs(struct si_context *sctx, struct si_images_info *images)
566 {
567 uint mask = images->enabled_mask;
568
569 /* Add buffers to the CS. */
570 while (mask) {
571 int i = u_bit_scan(&mask);
572 struct pipe_image_view *view = &images->views[i];
573
574 assert(view->resource);
575
576 si_sampler_view_add_buffer(sctx, view->resource,
577 RADEON_USAGE_READWRITE, false, false);
578 }
579 }
580
581 static void
582 si_disable_shader_image(struct si_context *ctx, unsigned shader, unsigned slot)
583 {
584 struct si_images_info *images = &ctx->images[shader];
585
586 if (images->enabled_mask & (1u << slot)) {
587 struct si_descriptors *descs = si_image_descriptors(ctx, shader);
588
589 pipe_resource_reference(&images->views[slot].resource, NULL);
590 images->compressed_colortex_mask &= ~(1 << slot);
591
592 memcpy(descs->list + slot*8, null_image_descriptor, 8*4);
593 images->enabled_mask &= ~(1u << slot);
594 descs->dirty_mask |= 1u << slot;
595 ctx->descriptors_dirty |= 1u << si_image_descriptors_idx(shader);
596 }
597 }
598
599 static void
600 si_mark_image_range_valid(const struct pipe_image_view *view)
601 {
602 struct r600_resource *res = (struct r600_resource *)view->resource;
603 const struct util_format_description *desc;
604 unsigned stride;
605
606 assert(res && res->b.b.target == PIPE_BUFFER);
607
608 desc = util_format_description(view->format);
609 stride = desc->block.bits / 8;
610
611 util_range_add(&res->valid_buffer_range,
612 stride * (view->u.buf.first_element),
613 stride * (view->u.buf.last_element + 1));
614 }
615
616 static void si_set_shader_image(struct si_context *ctx,
617 unsigned shader,
618 unsigned slot, const struct pipe_image_view *view)
619 {
620 struct si_screen *screen = ctx->screen;
621 struct si_images_info *images = &ctx->images[shader];
622 struct si_descriptors *descs = si_image_descriptors(ctx, shader);
623 struct r600_resource *res;
624
625 if (!view || !view->resource) {
626 si_disable_shader_image(ctx, shader, slot);
627 return;
628 }
629
630 res = (struct r600_resource *)view->resource;
631
632 if (&images->views[slot] != view)
633 util_copy_image_view(&images->views[slot], view);
634
635 si_sampler_view_add_buffer(ctx, &res->b.b,
636 RADEON_USAGE_READWRITE, false, true);
637
638 if (res->b.b.target == PIPE_BUFFER) {
639 if (view->access & PIPE_IMAGE_ACCESS_WRITE)
640 si_mark_image_range_valid(view);
641
642 si_make_buffer_descriptor(screen, res,
643 view->format,
644 view->u.buf.first_element *
645 util_format_get_blocksize(view->format),
646 (view->u.buf.last_element -
647 view->u.buf.first_element + 1) *
648 util_format_get_blocksize(view->format),
649 descs->list + slot * 8);
650 images->compressed_colortex_mask &= ~(1 << slot);
651 } else {
652 static const unsigned char swizzle[4] = { 0, 1, 2, 3 };
653 struct r600_texture *tex = (struct r600_texture *)res;
654 unsigned level = view->u.tex.level;
655 unsigned width, height, depth;
656 uint32_t *desc = descs->list + slot * 8;
657 bool uses_dcc = tex->dcc_offset &&
658 tex->surface.level[level].dcc_enabled;
659
660 assert(!tex->is_depth);
661 assert(tex->fmask.size == 0);
662
663 if (uses_dcc &&
664 view->access & PIPE_IMAGE_ACCESS_WRITE) {
665 /* If DCC can't be disabled, at least decompress it.
666 * The decompression is relatively cheap if the surface
667 * has been decompressed already.
668 */
669 if (r600_texture_disable_dcc(&ctx->b, tex))
670 uses_dcc = false;
671 else
672 ctx->b.decompress_dcc(&ctx->b.b, tex);
673 }
674
675 if (is_compressed_colortex(tex)) {
676 images->compressed_colortex_mask |= 1 << slot;
677 } else {
678 images->compressed_colortex_mask &= ~(1 << slot);
679 }
680
681 if (uses_dcc &&
682 p_atomic_read(&tex->framebuffers_bound))
683 ctx->need_check_render_feedback = true;
684
685 /* Always force the base level to the selected level.
686 *
687 * This is required for 3D textures, where otherwise
688 * selecting a single slice for non-layered bindings
689 * fails. It doesn't hurt the other targets.
690 */
691 width = u_minify(res->b.b.width0, level);
692 height = u_minify(res->b.b.height0, level);
693 depth = u_minify(res->b.b.depth0, level);
694
695 si_make_texture_descriptor(screen, tex,
696 false, res->b.b.target,
697 view->format, swizzle,
698 0, 0,
699 view->u.tex.first_layer,
700 view->u.tex.last_layer,
701 width, height, depth,
702 desc, NULL);
703 si_set_mutable_tex_desc_fields(tex, &tex->surface.level[level],
704 level, level,
705 util_format_get_blockwidth(view->format),
706 false, desc);
707 }
708
709 images->enabled_mask |= 1u << slot;
710 descs->dirty_mask |= 1u << slot;
711 ctx->descriptors_dirty |= 1u << si_image_descriptors_idx(shader);
712 }
713
714 static void
715 si_set_shader_images(struct pipe_context *pipe, unsigned shader,
716 unsigned start_slot, unsigned count,
717 const struct pipe_image_view *views)
718 {
719 struct si_context *ctx = (struct si_context *)pipe;
720 unsigned i, slot;
721
722 assert(shader < SI_NUM_SHADERS);
723
724 if (!count)
725 return;
726
727 assert(start_slot + count <= SI_NUM_IMAGES);
728
729 if (views) {
730 for (i = 0, slot = start_slot; i < count; ++i, ++slot)
731 si_set_shader_image(ctx, shader, slot, &views[i]);
732 } else {
733 for (i = 0, slot = start_slot; i < count; ++i, ++slot)
734 si_set_shader_image(ctx, shader, slot, NULL);
735 }
736 }
737
738 static void
739 si_images_update_compressed_colortex_mask(struct si_images_info *images)
740 {
741 unsigned mask = images->enabled_mask;
742
743 while (mask) {
744 int i = u_bit_scan(&mask);
745 struct pipe_resource *res = images->views[i].resource;
746
747 if (res && res->target != PIPE_BUFFER) {
748 struct r600_texture *rtex = (struct r600_texture *)res;
749
750 if (is_compressed_colortex(rtex)) {
751 images->compressed_colortex_mask |= 1 << i;
752 } else {
753 images->compressed_colortex_mask &= ~(1 << i);
754 }
755 }
756 }
757 }
758
759 /* SAMPLER STATES */
760
761 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
762 unsigned start, unsigned count, void **states)
763 {
764 struct si_context *sctx = (struct si_context *)ctx;
765 struct si_textures_info *samplers = &sctx->samplers[shader];
766 struct si_descriptors *desc = si_sampler_descriptors(sctx, shader);
767 struct si_sampler_state **sstates = (struct si_sampler_state**)states;
768 int i;
769
770 if (!count || shader >= SI_NUM_SHADERS)
771 return;
772
773 for (i = 0; i < count; i++) {
774 unsigned slot = start + i;
775
776 if (!sstates[i] ||
777 sstates[i] == samplers->views.sampler_states[slot])
778 continue;
779
780 samplers->views.sampler_states[slot] = sstates[i];
781
782 /* If FMASK is bound, don't overwrite it.
783 * The sampler state will be set after FMASK is unbound.
784 */
785 if (samplers->views.views[i] &&
786 samplers->views.views[i]->texture &&
787 samplers->views.views[i]->texture->target != PIPE_BUFFER &&
788 ((struct r600_texture*)samplers->views.views[i]->texture)->fmask.size)
789 continue;
790
791 memcpy(desc->list + slot * 16 + 12, sstates[i]->val, 4*4);
792 desc->dirty_mask |= 1u << slot;
793 sctx->descriptors_dirty |= 1u << si_sampler_descriptors_idx(shader);
794 }
795 }
796
797 /* BUFFER RESOURCES */
798
799 static void si_init_buffer_resources(struct si_buffer_resources *buffers,
800 struct si_descriptors *descs,
801 unsigned num_buffers,
802 unsigned shader_userdata_index,
803 enum radeon_bo_usage shader_usage,
804 enum radeon_bo_priority priority,
805 unsigned *ce_offset)
806 {
807 buffers->shader_usage = shader_usage;
808 buffers->priority = priority;
809 buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource*));
810
811 si_init_descriptors(descs, shader_userdata_index, 4,
812 num_buffers, NULL, ce_offset);
813 }
814
815 static void si_release_buffer_resources(struct si_buffer_resources *buffers,
816 struct si_descriptors *descs)
817 {
818 int i;
819
820 for (i = 0; i < descs->num_elements; i++) {
821 pipe_resource_reference(&buffers->buffers[i], NULL);
822 }
823
824 FREE(buffers->buffers);
825 }
826
827 static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
828 struct si_buffer_resources *buffers)
829 {
830 unsigned mask = buffers->enabled_mask;
831
832 /* Add buffers to the CS. */
833 while (mask) {
834 int i = u_bit_scan(&mask);
835
836 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
837 (struct r600_resource*)buffers->buffers[i],
838 buffers->shader_usage, buffers->priority);
839 }
840 }
841
842 /* VERTEX BUFFERS */
843
844 static void si_vertex_buffers_begin_new_cs(struct si_context *sctx)
845 {
846 struct si_descriptors *desc = &sctx->vertex_buffers;
847 int count = sctx->vertex_elements ? sctx->vertex_elements->count : 0;
848 int i;
849
850 for (i = 0; i < count; i++) {
851 int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
852
853 if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
854 continue;
855 if (!sctx->vertex_buffer[vb].buffer)
856 continue;
857
858 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
859 (struct r600_resource*)sctx->vertex_buffer[vb].buffer,
860 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
861 }
862
863 if (!desc->buffer)
864 return;
865 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
866 desc->buffer, RADEON_USAGE_READ,
867 RADEON_PRIO_DESCRIPTORS);
868 }
869
870 bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
871 {
872 struct si_descriptors *desc = &sctx->vertex_buffers;
873 bool bound[SI_NUM_VERTEX_BUFFERS] = {};
874 unsigned i, count = sctx->vertex_elements->count;
875 uint64_t va;
876 uint32_t *ptr;
877
878 if (!sctx->vertex_buffers_dirty)
879 return true;
880 if (!count || !sctx->vertex_elements)
881 return true;
882
883 /* Vertex buffer descriptors are the only ones which are uploaded
884 * directly through a staging buffer and don't go through
885 * the fine-grained upload path.
886 */
887 u_upload_alloc(sctx->b.uploader, 0, count * 16, 256, &desc->buffer_offset,
888 (struct pipe_resource**)&desc->buffer, (void**)&ptr);
889 if (!desc->buffer)
890 return false;
891
892 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
893 desc->buffer, RADEON_USAGE_READ,
894 RADEON_PRIO_DESCRIPTORS);
895
896 assert(count <= SI_NUM_VERTEX_BUFFERS);
897
898 for (i = 0; i < count; i++) {
899 struct pipe_vertex_element *ve = &sctx->vertex_elements->elements[i];
900 struct pipe_vertex_buffer *vb;
901 struct r600_resource *rbuffer;
902 unsigned offset;
903 uint32_t *desc = &ptr[i*4];
904
905 if (ve->vertex_buffer_index >= ARRAY_SIZE(sctx->vertex_buffer)) {
906 memset(desc, 0, 16);
907 continue;
908 }
909
910 vb = &sctx->vertex_buffer[ve->vertex_buffer_index];
911 rbuffer = (struct r600_resource*)vb->buffer;
912 if (!rbuffer) {
913 memset(desc, 0, 16);
914 continue;
915 }
916
917 offset = vb->buffer_offset + ve->src_offset;
918 va = rbuffer->gpu_address + offset;
919
920 /* Fill in T# buffer resource description */
921 desc[0] = va;
922 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
923 S_008F04_STRIDE(vb->stride);
924
925 if (sctx->b.chip_class <= CIK && vb->stride)
926 /* Round up by rounding down and adding 1 */
927 desc[2] = (vb->buffer->width0 - offset -
928 sctx->vertex_elements->format_size[i]) /
929 vb->stride + 1;
930 else
931 desc[2] = vb->buffer->width0 - offset;
932
933 desc[3] = sctx->vertex_elements->rsrc_word3[i];
934
935 if (!bound[ve->vertex_buffer_index]) {
936 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
937 (struct r600_resource*)vb->buffer,
938 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
939 bound[ve->vertex_buffer_index] = true;
940 }
941 }
942
943 /* Don't flush the const cache. It would have a very negative effect
944 * on performance (confirmed by testing). New descriptors are always
945 * uploaded to a fresh new buffer, so I don't think flushing the const
946 * cache is needed. */
947 desc->pointer_dirty = true;
948 si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
949 sctx->vertex_buffers_dirty = false;
950 return true;
951 }
952
953
954 /* CONSTANT BUFFERS */
955
956 static unsigned
957 si_const_buffer_descriptors_idx(unsigned shader)
958 {
959 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
960 SI_SHADER_DESCS_CONST_BUFFERS;
961 }
962
963 static struct si_descriptors *
964 si_const_buffer_descriptors(struct si_context *sctx, unsigned shader)
965 {
966 return &sctx->descriptors[si_const_buffer_descriptors_idx(shader)];
967 }
968
969 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
970 const uint8_t *ptr, unsigned size, uint32_t *const_offset)
971 {
972 void *tmp;
973
974 u_upload_alloc(sctx->b.uploader, 0, size, 256, const_offset,
975 (struct pipe_resource**)rbuffer, &tmp);
976 if (*rbuffer)
977 util_memcpy_cpu_to_le32(tmp, ptr, size);
978 }
979
980 static void si_set_constant_buffer(struct si_context *sctx,
981 struct si_buffer_resources *buffers,
982 unsigned descriptors_idx,
983 uint slot, const struct pipe_constant_buffer *input)
984 {
985 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
986 assert(slot < descs->num_elements);
987 pipe_resource_reference(&buffers->buffers[slot], NULL);
988
989 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
990 * with a NULL buffer). We need to use a dummy buffer instead. */
991 if (sctx->b.chip_class == CIK &&
992 (!input || (!input->buffer && !input->user_buffer)))
993 input = &sctx->null_const_buf;
994
995 if (input && (input->buffer || input->user_buffer)) {
996 struct pipe_resource *buffer = NULL;
997 uint64_t va;
998
999 /* Upload the user buffer if needed. */
1000 if (input->user_buffer) {
1001 unsigned buffer_offset;
1002
1003 si_upload_const_buffer(sctx,
1004 (struct r600_resource**)&buffer, input->user_buffer,
1005 input->buffer_size, &buffer_offset);
1006 if (!buffer) {
1007 /* Just unbind on failure. */
1008 si_set_constant_buffer(sctx, buffers, descriptors_idx, slot, NULL);
1009 return;
1010 }
1011 va = r600_resource(buffer)->gpu_address + buffer_offset;
1012 } else {
1013 pipe_resource_reference(&buffer, input->buffer);
1014 va = r600_resource(buffer)->gpu_address + input->buffer_offset;
1015 }
1016
1017 /* Set the descriptor. */
1018 uint32_t *desc = descs->list + slot*4;
1019 desc[0] = va;
1020 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1021 S_008F04_STRIDE(0);
1022 desc[2] = input->buffer_size;
1023 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1024 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1025 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1026 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1027 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1028 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1029
1030 buffers->buffers[slot] = buffer;
1031 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1032 (struct r600_resource*)buffer,
1033 buffers->shader_usage,
1034 buffers->priority, true);
1035 buffers->enabled_mask |= 1u << slot;
1036 } else {
1037 /* Clear the descriptor. */
1038 memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4);
1039 buffers->enabled_mask &= ~(1u << slot);
1040 }
1041
1042 descs->dirty_mask |= 1u << slot;
1043 sctx->descriptors_dirty |= 1u << descriptors_idx;
1044 }
1045
1046 void si_set_rw_buffer(struct si_context *sctx,
1047 uint slot, const struct pipe_constant_buffer *input)
1048 {
1049 si_set_constant_buffer(sctx, &sctx->rw_buffers,
1050 SI_DESCS_RW_BUFFERS, slot, input);
1051 }
1052
1053 static void si_pipe_set_constant_buffer(struct pipe_context *ctx,
1054 uint shader, uint slot,
1055 const struct pipe_constant_buffer *input)
1056 {
1057 struct si_context *sctx = (struct si_context *)ctx;
1058
1059 if (shader >= SI_NUM_SHADERS)
1060 return;
1061
1062 si_set_constant_buffer(sctx, &sctx->const_buffers[shader],
1063 si_const_buffer_descriptors_idx(shader),
1064 slot, input);
1065 }
1066
1067 /* SHADER BUFFERS */
1068
1069 static unsigned
1070 si_shader_buffer_descriptors_idx(unsigned shader)
1071 {
1072 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
1073 SI_SHADER_DESCS_SHADER_BUFFERS;
1074 }
1075
1076 static struct si_descriptors *
1077 si_shader_buffer_descriptors(struct si_context *sctx, unsigned shader)
1078 {
1079 return &sctx->descriptors[si_shader_buffer_descriptors_idx(shader)];
1080 }
1081
1082 static void si_set_shader_buffers(struct pipe_context *ctx, unsigned shader,
1083 unsigned start_slot, unsigned count,
1084 const struct pipe_shader_buffer *sbuffers)
1085 {
1086 struct si_context *sctx = (struct si_context *)ctx;
1087 struct si_buffer_resources *buffers = &sctx->shader_buffers[shader];
1088 struct si_descriptors *descs = si_shader_buffer_descriptors(sctx, shader);
1089 unsigned i;
1090
1091 assert(start_slot + count <= SI_NUM_SHADER_BUFFERS);
1092
1093 for (i = 0; i < count; ++i) {
1094 const struct pipe_shader_buffer *sbuffer = sbuffers ? &sbuffers[i] : NULL;
1095 struct r600_resource *buf;
1096 unsigned slot = start_slot + i;
1097 uint32_t *desc = descs->list + slot * 4;
1098 uint64_t va;
1099
1100 if (!sbuffer || !sbuffer->buffer) {
1101 pipe_resource_reference(&buffers->buffers[slot], NULL);
1102 memset(desc, 0, sizeof(uint32_t) * 4);
1103 buffers->enabled_mask &= ~(1u << slot);
1104 descs->dirty_mask |= 1u << slot;
1105 sctx->descriptors_dirty |=
1106 1u << si_shader_buffer_descriptors_idx(shader);
1107 continue;
1108 }
1109
1110 buf = (struct r600_resource *)sbuffer->buffer;
1111 va = buf->gpu_address + sbuffer->buffer_offset;
1112
1113 desc[0] = va;
1114 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1115 S_008F04_STRIDE(0);
1116 desc[2] = sbuffer->buffer_size;
1117 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1118 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1119 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1120 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1121 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1122 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1123
1124 pipe_resource_reference(&buffers->buffers[slot], &buf->b.b);
1125 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx, buf,
1126 buffers->shader_usage,
1127 buffers->priority, true);
1128 buffers->enabled_mask |= 1u << slot;
1129 descs->dirty_mask |= 1u << slot;
1130 sctx->descriptors_dirty |=
1131 1u << si_shader_buffer_descriptors_idx(shader);
1132 }
1133 }
1134
1135 /* RING BUFFERS */
1136
1137 void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
1138 struct pipe_resource *buffer,
1139 unsigned stride, unsigned num_records,
1140 bool add_tid, bool swizzle,
1141 unsigned element_size, unsigned index_stride, uint64_t offset)
1142 {
1143 struct si_context *sctx = (struct si_context *)ctx;
1144 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1145 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1146
1147 /* The stride field in the resource descriptor has 14 bits */
1148 assert(stride < (1 << 14));
1149
1150 assert(slot < descs->num_elements);
1151 pipe_resource_reference(&buffers->buffers[slot], NULL);
1152
1153 if (buffer) {
1154 uint64_t va;
1155
1156 va = r600_resource(buffer)->gpu_address + offset;
1157
1158 switch (element_size) {
1159 default:
1160 assert(!"Unsupported ring buffer element size");
1161 case 0:
1162 case 2:
1163 element_size = 0;
1164 break;
1165 case 4:
1166 element_size = 1;
1167 break;
1168 case 8:
1169 element_size = 2;
1170 break;
1171 case 16:
1172 element_size = 3;
1173 break;
1174 }
1175
1176 switch (index_stride) {
1177 default:
1178 assert(!"Unsupported ring buffer index stride");
1179 case 0:
1180 case 8:
1181 index_stride = 0;
1182 break;
1183 case 16:
1184 index_stride = 1;
1185 break;
1186 case 32:
1187 index_stride = 2;
1188 break;
1189 case 64:
1190 index_stride = 3;
1191 break;
1192 }
1193
1194 if (sctx->b.chip_class >= VI && stride)
1195 num_records *= stride;
1196
1197 /* Set the descriptor. */
1198 uint32_t *desc = descs->list + slot*4;
1199 desc[0] = va;
1200 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1201 S_008F04_STRIDE(stride) |
1202 S_008F04_SWIZZLE_ENABLE(swizzle);
1203 desc[2] = num_records;
1204 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1205 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1206 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1207 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1208 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1209 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1210 S_008F0C_ELEMENT_SIZE(element_size) |
1211 S_008F0C_INDEX_STRIDE(index_stride) |
1212 S_008F0C_ADD_TID_ENABLE(add_tid);
1213
1214 pipe_resource_reference(&buffers->buffers[slot], buffer);
1215 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1216 (struct r600_resource*)buffer,
1217 buffers->shader_usage, buffers->priority);
1218 buffers->enabled_mask |= 1u << slot;
1219 } else {
1220 /* Clear the descriptor. */
1221 memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4);
1222 buffers->enabled_mask &= ~(1u << slot);
1223 }
1224
1225 descs->dirty_mask |= 1u << slot;
1226 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1227 }
1228
1229 /* STREAMOUT BUFFERS */
1230
1231 static void si_set_streamout_targets(struct pipe_context *ctx,
1232 unsigned num_targets,
1233 struct pipe_stream_output_target **targets,
1234 const unsigned *offsets)
1235 {
1236 struct si_context *sctx = (struct si_context *)ctx;
1237 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1238 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1239 unsigned old_num_targets = sctx->b.streamout.num_targets;
1240 unsigned i, bufidx;
1241
1242 /* We are going to unbind the buffers. Mark which caches need to be flushed. */
1243 if (sctx->b.streamout.num_targets && sctx->b.streamout.begin_emitted) {
1244 /* Since streamout uses vector writes which go through TC L2
1245 * and most other clients can use TC L2 as well, we don't need
1246 * to flush it.
1247 *
1248 * The only cases which requires flushing it is VGT DMA index
1249 * fetching (on <= CIK) and indirect draw data, which are rare
1250 * cases. Thus, flag the TC L2 dirtiness in the resource and
1251 * handle it at draw call time.
1252 */
1253 for (i = 0; i < sctx->b.streamout.num_targets; i++)
1254 if (sctx->b.streamout.targets[i])
1255 r600_resource(sctx->b.streamout.targets[i]->b.buffer)->TC_L2_dirty = true;
1256
1257 /* Invalidate the scalar cache in case a streamout buffer is
1258 * going to be used as a constant buffer.
1259 *
1260 * Invalidate TC L1, because streamout bypasses it (done by
1261 * setting GLC=1 in the store instruction), but it can contain
1262 * outdated data of streamout buffers.
1263 *
1264 * VS_PARTIAL_FLUSH is required if the buffers are going to be
1265 * used as an input immediately.
1266 */
1267 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
1268 SI_CONTEXT_INV_VMEM_L1 |
1269 SI_CONTEXT_VS_PARTIAL_FLUSH;
1270 }
1271
1272 /* All readers of the streamout targets need to be finished before we can
1273 * start writing to the targets.
1274 */
1275 if (num_targets)
1276 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
1277 SI_CONTEXT_CS_PARTIAL_FLUSH;
1278
1279 /* Streamout buffers must be bound in 2 places:
1280 * 1) in VGT by setting the VGT_STRMOUT registers
1281 * 2) as shader resources
1282 */
1283
1284 /* Set the VGT regs. */
1285 r600_set_streamout_targets(ctx, num_targets, targets, offsets);
1286
1287 /* Set the shader resources.*/
1288 for (i = 0; i < num_targets; i++) {
1289 bufidx = SI_VS_STREAMOUT_BUF0 + i;
1290
1291 if (targets[i]) {
1292 struct pipe_resource *buffer = targets[i]->buffer;
1293 uint64_t va = r600_resource(buffer)->gpu_address;
1294
1295 /* Set the descriptor.
1296 *
1297 * On VI, the format must be non-INVALID, otherwise
1298 * the buffer will be considered not bound and store
1299 * instructions will be no-ops.
1300 */
1301 uint32_t *desc = descs->list + bufidx*4;
1302 desc[0] = va;
1303 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1304 desc[2] = 0xffffffff;
1305 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1306 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1307 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1308 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1309 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1310
1311 /* Set the resource. */
1312 pipe_resource_reference(&buffers->buffers[bufidx],
1313 buffer);
1314 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1315 (struct r600_resource*)buffer,
1316 buffers->shader_usage,
1317 RADEON_PRIO_SHADER_RW_BUFFER,
1318 true);
1319 buffers->enabled_mask |= 1u << bufidx;
1320 } else {
1321 /* Clear the descriptor and unset the resource. */
1322 memset(descs->list + bufidx*4, 0,
1323 sizeof(uint32_t) * 4);
1324 pipe_resource_reference(&buffers->buffers[bufidx],
1325 NULL);
1326 buffers->enabled_mask &= ~(1u << bufidx);
1327 }
1328 descs->dirty_mask |= 1u << bufidx;
1329 }
1330 for (; i < old_num_targets; i++) {
1331 bufidx = SI_VS_STREAMOUT_BUF0 + i;
1332 /* Clear the descriptor and unset the resource. */
1333 memset(descs->list + bufidx*4, 0, sizeof(uint32_t) * 4);
1334 pipe_resource_reference(&buffers->buffers[bufidx], NULL);
1335 buffers->enabled_mask &= ~(1u << bufidx);
1336 descs->dirty_mask |= 1u << bufidx;
1337 }
1338
1339 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1340 }
1341
1342 static void si_desc_reset_buffer_offset(struct pipe_context *ctx,
1343 uint32_t *desc, uint64_t old_buf_va,
1344 struct pipe_resource *new_buf)
1345 {
1346 /* Retrieve the buffer offset from the descriptor. */
1347 uint64_t old_desc_va =
1348 desc[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc[1]) << 32);
1349
1350 assert(old_buf_va <= old_desc_va);
1351 uint64_t offset_within_buffer = old_desc_va - old_buf_va;
1352
1353 /* Update the descriptor. */
1354 uint64_t va = r600_resource(new_buf)->gpu_address + offset_within_buffer;
1355
1356 desc[0] = va;
1357 desc[1] = (desc[1] & C_008F04_BASE_ADDRESS_HI) |
1358 S_008F04_BASE_ADDRESS_HI(va >> 32);
1359 }
1360
1361 /* INTERNAL CONST BUFFERS */
1362
1363 static void si_set_polygon_stipple(struct pipe_context *ctx,
1364 const struct pipe_poly_stipple *state)
1365 {
1366 struct si_context *sctx = (struct si_context *)ctx;
1367 struct pipe_constant_buffer cb = {};
1368 unsigned stipple[32];
1369 int i;
1370
1371 for (i = 0; i < 32; i++)
1372 stipple[i] = util_bitreverse(state->stipple[i]);
1373
1374 cb.user_buffer = stipple;
1375 cb.buffer_size = sizeof(stipple);
1376
1377 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE, &cb);
1378 }
1379
1380 /* TEXTURE METADATA ENABLE/DISABLE */
1381
1382 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1383 * while the texture is bound, possibly by a different context. In that case,
1384 * call this function to update compressed_colortex_masks.
1385 */
1386 void si_update_compressed_colortex_masks(struct si_context *sctx)
1387 {
1388 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
1389 si_samplers_update_compressed_colortex_mask(&sctx->samplers[i]);
1390 si_images_update_compressed_colortex_mask(&sctx->images[i]);
1391 }
1392 }
1393
1394 /* BUFFER DISCARD/INVALIDATION */
1395
1396 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1397 static void si_reset_buffer_resources(struct si_context *sctx,
1398 struct si_buffer_resources *buffers,
1399 unsigned descriptors_idx,
1400 struct pipe_resource *buf,
1401 uint64_t old_va)
1402 {
1403 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
1404 unsigned mask = buffers->enabled_mask;
1405
1406 while (mask) {
1407 unsigned i = u_bit_scan(&mask);
1408 if (buffers->buffers[i] == buf) {
1409 si_desc_reset_buffer_offset(&sctx->b.b,
1410 descs->list + i*4,
1411 old_va, buf);
1412 descs->dirty_mask |= 1u << i;
1413 sctx->descriptors_dirty |= 1u << descriptors_idx;
1414
1415 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1416 (struct r600_resource *)buf,
1417 buffers->shader_usage,
1418 buffers->priority, true);
1419 }
1420 }
1421 }
1422
1423 /* Reallocate a buffer a update all resource bindings where the buffer is
1424 * bound.
1425 *
1426 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
1427 * idle by discarding its contents. Apps usually tell us when to do this using
1428 * map_buffer flags, for example.
1429 */
1430 static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
1431 {
1432 struct si_context *sctx = (struct si_context*)ctx;
1433 struct r600_resource *rbuffer = r600_resource(buf);
1434 unsigned i, shader, alignment = rbuffer->buf->alignment;
1435 uint64_t old_va = rbuffer->gpu_address;
1436 unsigned num_elems = sctx->vertex_elements ?
1437 sctx->vertex_elements->count : 0;
1438 struct si_sampler_view *view;
1439
1440 /* Reallocate the buffer in the same pipe_resource. */
1441 r600_init_resource(&sctx->screen->b, rbuffer, rbuffer->b.b.width0,
1442 alignment);
1443
1444 /* We changed the buffer, now we need to bind it where the old one
1445 * was bound. This consists of 2 things:
1446 * 1) Updating the resource descriptor and dirtying it.
1447 * 2) Adding a relocation to the CS, so that it's usable.
1448 */
1449
1450 /* Vertex buffers. */
1451 for (i = 0; i < num_elems; i++) {
1452 int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
1453
1454 if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
1455 continue;
1456 if (!sctx->vertex_buffer[vb].buffer)
1457 continue;
1458
1459 if (sctx->vertex_buffer[vb].buffer == buf) {
1460 sctx->vertex_buffers_dirty = true;
1461 break;
1462 }
1463 }
1464
1465 /* Streamout buffers. (other internal buffers can't be invalidated) */
1466 for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) {
1467 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1468 struct si_descriptors *descs =
1469 &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1470
1471 if (buffers->buffers[i] != buf)
1472 continue;
1473
1474 si_desc_reset_buffer_offset(ctx, descs->list + i*4,
1475 old_va, buf);
1476 descs->dirty_mask |= 1u << i;
1477 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1478
1479 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1480 rbuffer, buffers->shader_usage,
1481 RADEON_PRIO_SHADER_RW_BUFFER,
1482 true);
1483
1484 /* Update the streamout state. */
1485 if (sctx->b.streamout.begin_emitted)
1486 r600_emit_streamout_end(&sctx->b);
1487 sctx->b.streamout.append_bitmask =
1488 sctx->b.streamout.enabled_mask;
1489 r600_streamout_buffers_dirty(&sctx->b);
1490 }
1491
1492 /* Constant and shader buffers. */
1493 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1494 si_reset_buffer_resources(sctx, &sctx->const_buffers[shader],
1495 si_const_buffer_descriptors_idx(shader),
1496 buf, old_va);
1497 si_reset_buffer_resources(sctx, &sctx->shader_buffers[shader],
1498 si_shader_buffer_descriptors_idx(shader),
1499 buf, old_va);
1500 }
1501
1502 /* Texture buffers - update virtual addresses in sampler view descriptors. */
1503 LIST_FOR_EACH_ENTRY(view, &sctx->b.texture_buffers, list) {
1504 if (view->base.texture == buf) {
1505 si_desc_reset_buffer_offset(ctx, &view->state[4], old_va, buf);
1506 }
1507 }
1508 /* Texture buffers - update bindings. */
1509 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1510 struct si_sampler_views *views = &sctx->samplers[shader].views;
1511 struct si_descriptors *descs =
1512 si_sampler_descriptors(sctx, shader);
1513 unsigned mask = views->enabled_mask;
1514
1515 while (mask) {
1516 unsigned i = u_bit_scan(&mask);
1517 if (views->views[i]->texture == buf) {
1518 si_desc_reset_buffer_offset(ctx,
1519 descs->list +
1520 i * 16 + 4,
1521 old_va, buf);
1522 descs->dirty_mask |= 1u << i;
1523 sctx->descriptors_dirty |=
1524 1u << si_sampler_descriptors_idx(shader);
1525
1526 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1527 rbuffer, RADEON_USAGE_READ,
1528 RADEON_PRIO_SAMPLER_BUFFER,
1529 true);
1530 }
1531 }
1532 }
1533
1534 /* Shader images */
1535 for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
1536 struct si_images_info *images = &sctx->images[shader];
1537 struct si_descriptors *descs =
1538 si_image_descriptors(sctx, shader);
1539 unsigned mask = images->enabled_mask;
1540
1541 while (mask) {
1542 unsigned i = u_bit_scan(&mask);
1543
1544 if (images->views[i].resource == buf) {
1545 if (images->views[i].access & PIPE_IMAGE_ACCESS_WRITE)
1546 si_mark_image_range_valid(&images->views[i]);
1547
1548 si_desc_reset_buffer_offset(
1549 ctx, descs->list + i * 8 + 4,
1550 old_va, buf);
1551 descs->dirty_mask |= 1u << i;
1552 sctx->descriptors_dirty |=
1553 1u << si_image_descriptors_idx(shader);
1554
1555 radeon_add_to_buffer_list_check_mem(
1556 &sctx->b, &sctx->b.gfx, rbuffer,
1557 RADEON_USAGE_READWRITE,
1558 RADEON_PRIO_SAMPLER_BUFFER, true);
1559 }
1560 }
1561 }
1562 }
1563
1564 /* Update mutable image descriptor fields of all bound textures. */
1565 void si_update_all_texture_descriptors(struct si_context *sctx)
1566 {
1567 unsigned shader;
1568
1569 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1570 struct si_sampler_views *samplers = &sctx->samplers[shader].views;
1571 struct si_images_info *images = &sctx->images[shader];
1572 unsigned mask;
1573
1574 /* Images. */
1575 mask = images->enabled_mask;
1576 while (mask) {
1577 unsigned i = u_bit_scan(&mask);
1578 struct pipe_image_view *view = &images->views[i];
1579
1580 if (!view->resource ||
1581 view->resource->target == PIPE_BUFFER)
1582 continue;
1583
1584 si_set_shader_image(sctx, shader, i, view);
1585 }
1586
1587 /* Sampler views. */
1588 mask = samplers->enabled_mask;
1589 while (mask) {
1590 unsigned i = u_bit_scan(&mask);
1591 struct pipe_sampler_view *view = samplers->views[i];
1592
1593 if (!view ||
1594 !view->texture ||
1595 view->texture->target == PIPE_BUFFER)
1596 continue;
1597
1598 si_set_sampler_view(sctx, shader, i,
1599 samplers->views[i], true);
1600 }
1601 }
1602 }
1603
1604 /* SHADER USER DATA */
1605
1606 static void si_mark_shader_pointers_dirty(struct si_context *sctx,
1607 unsigned shader)
1608 {
1609 struct si_descriptors *descs =
1610 &sctx->descriptors[SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS];
1611
1612 for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs)
1613 descs->pointer_dirty = true;
1614
1615 if (shader == PIPE_SHADER_VERTEX)
1616 sctx->vertex_buffers.pointer_dirty = true;
1617
1618 si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
1619 }
1620
1621 static void si_shader_userdata_begin_new_cs(struct si_context *sctx)
1622 {
1623 int i;
1624
1625 for (i = 0; i < SI_NUM_SHADERS; i++) {
1626 si_mark_shader_pointers_dirty(sctx, i);
1627 }
1628 sctx->descriptors[SI_DESCS_RW_BUFFERS].pointer_dirty = true;
1629 }
1630
1631 /* Set a base register address for user data constants in the given shader.
1632 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1633 */
1634 static void si_set_user_data_base(struct si_context *sctx,
1635 unsigned shader, uint32_t new_base)
1636 {
1637 uint32_t *base = &sctx->shader_userdata.sh_base[shader];
1638
1639 if (*base != new_base) {
1640 *base = new_base;
1641
1642 if (new_base)
1643 si_mark_shader_pointers_dirty(sctx, shader);
1644 }
1645 }
1646
1647 /* This must be called when these shaders are changed from non-NULL to NULL
1648 * and vice versa:
1649 * - geometry shader
1650 * - tessellation control shader
1651 * - tessellation evaluation shader
1652 */
1653 void si_shader_change_notify(struct si_context *sctx)
1654 {
1655 /* VS can be bound as VS, ES, or LS. */
1656 if (sctx->tes_shader.cso)
1657 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1658 R_00B530_SPI_SHADER_USER_DATA_LS_0);
1659 else if (sctx->gs_shader.cso)
1660 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1661 R_00B330_SPI_SHADER_USER_DATA_ES_0);
1662 else
1663 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1664 R_00B130_SPI_SHADER_USER_DATA_VS_0);
1665
1666 /* TES can be bound as ES, VS, or not bound. */
1667 if (sctx->tes_shader.cso) {
1668 if (sctx->gs_shader.cso)
1669 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
1670 R_00B330_SPI_SHADER_USER_DATA_ES_0);
1671 else
1672 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
1673 R_00B130_SPI_SHADER_USER_DATA_VS_0);
1674 } else {
1675 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, 0);
1676 }
1677 }
1678
1679 static void si_emit_shader_pointer(struct si_context *sctx,
1680 struct si_descriptors *desc,
1681 unsigned sh_base, bool keep_dirty)
1682 {
1683 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1684 uint64_t va;
1685
1686 if (!desc->pointer_dirty || !desc->buffer)
1687 return;
1688
1689 va = desc->buffer->gpu_address +
1690 desc->buffer_offset;
1691
1692 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0));
1693 radeon_emit(cs, (sh_base + desc->shader_userdata_offset - SI_SH_REG_OFFSET) >> 2);
1694 radeon_emit(cs, va);
1695 radeon_emit(cs, va >> 32);
1696
1697 desc->pointer_dirty = keep_dirty;
1698 }
1699
1700 void si_emit_graphics_shader_userdata(struct si_context *sctx,
1701 struct r600_atom *atom)
1702 {
1703 unsigned shader;
1704 uint32_t *sh_base = sctx->shader_userdata.sh_base;
1705 struct si_descriptors *descs;
1706
1707 descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1708
1709 if (descs->pointer_dirty) {
1710 si_emit_shader_pointer(sctx, descs,
1711 R_00B030_SPI_SHADER_USER_DATA_PS_0, true);
1712 si_emit_shader_pointer(sctx, descs,
1713 R_00B130_SPI_SHADER_USER_DATA_VS_0, true);
1714 si_emit_shader_pointer(sctx, descs,
1715 R_00B230_SPI_SHADER_USER_DATA_GS_0, true);
1716 si_emit_shader_pointer(sctx, descs,
1717 R_00B330_SPI_SHADER_USER_DATA_ES_0, true);
1718 si_emit_shader_pointer(sctx, descs,
1719 R_00B430_SPI_SHADER_USER_DATA_HS_0, true);
1720 descs->pointer_dirty = false;
1721 }
1722
1723 descs = &sctx->descriptors[SI_DESCS_FIRST_SHADER];
1724
1725 for (shader = 0; shader < SI_NUM_GRAPHICS_SHADERS; shader++) {
1726 unsigned base = sh_base[shader];
1727 unsigned i;
1728
1729 if (!base)
1730 continue;
1731
1732 for (i = 0; i < SI_NUM_SHADER_DESCS; i++, descs++)
1733 si_emit_shader_pointer(sctx, descs, base, false);
1734 }
1735 si_emit_shader_pointer(sctx, &sctx->vertex_buffers, sh_base[PIPE_SHADER_VERTEX], false);
1736 }
1737
1738 void si_emit_compute_shader_userdata(struct si_context *sctx)
1739 {
1740 unsigned base = R_00B900_COMPUTE_USER_DATA_0;
1741 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_FIRST_COMPUTE];
1742
1743 for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs)
1744 si_emit_shader_pointer(sctx, descs, base, false);
1745 }
1746
1747 /* INIT/DEINIT/UPLOAD */
1748
1749 void si_init_all_descriptors(struct si_context *sctx)
1750 {
1751 int i;
1752 unsigned ce_offset = 0;
1753
1754 for (i = 0; i < SI_NUM_SHADERS; i++) {
1755 si_init_buffer_resources(&sctx->const_buffers[i],
1756 si_const_buffer_descriptors(sctx, i),
1757 SI_NUM_CONST_BUFFERS, SI_SGPR_CONST_BUFFERS,
1758 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER,
1759 &ce_offset);
1760 si_init_buffer_resources(&sctx->shader_buffers[i],
1761 si_shader_buffer_descriptors(sctx, i),
1762 SI_NUM_SHADER_BUFFERS, SI_SGPR_SHADER_BUFFERS,
1763 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RW_BUFFER,
1764 &ce_offset);
1765
1766 si_init_descriptors(si_sampler_descriptors(sctx, i),
1767 SI_SGPR_SAMPLERS, 16, SI_NUM_SAMPLERS,
1768 null_texture_descriptor, &ce_offset);
1769
1770 si_init_descriptors(si_image_descriptors(sctx, i),
1771 SI_SGPR_IMAGES, 8, SI_NUM_IMAGES,
1772 null_image_descriptor, &ce_offset);
1773 }
1774
1775 si_init_buffer_resources(&sctx->rw_buffers,
1776 &sctx->descriptors[SI_DESCS_RW_BUFFERS],
1777 SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS,
1778 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS,
1779 &ce_offset);
1780 si_init_descriptors(&sctx->vertex_buffers, SI_SGPR_VERTEX_BUFFERS,
1781 4, SI_NUM_VERTEX_BUFFERS, NULL, NULL);
1782
1783 sctx->descriptors_dirty = u_bit_consecutive(0, SI_NUM_DESCS);
1784
1785 assert(ce_offset <= 32768);
1786
1787 /* Set pipe_context functions. */
1788 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
1789 sctx->b.b.set_shader_images = si_set_shader_images;
1790 sctx->b.b.set_constant_buffer = si_pipe_set_constant_buffer;
1791 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
1792 sctx->b.b.set_shader_buffers = si_set_shader_buffers;
1793 sctx->b.b.set_sampler_views = si_set_sampler_views;
1794 sctx->b.b.set_stream_output_targets = si_set_streamout_targets;
1795 sctx->b.invalidate_buffer = si_invalidate_buffer;
1796
1797 /* Shader user data. */
1798 si_init_atom(sctx, &sctx->shader_userdata.atom, &sctx->atoms.s.shader_userdata,
1799 si_emit_graphics_shader_userdata);
1800
1801 /* Set default and immutable mappings. */
1802 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
1803 si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, R_00B430_SPI_SHADER_USER_DATA_HS_0);
1804 si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, R_00B230_SPI_SHADER_USER_DATA_GS_0);
1805 si_set_user_data_base(sctx, PIPE_SHADER_FRAGMENT, R_00B030_SPI_SHADER_USER_DATA_PS_0);
1806 }
1807
1808 bool si_upload_graphics_shader_descriptors(struct si_context *sctx)
1809 {
1810 const unsigned mask = u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE);
1811 unsigned dirty = sctx->descriptors_dirty & mask;
1812
1813 while (dirty) {
1814 unsigned i = u_bit_scan(&dirty);
1815
1816 if (!si_upload_descriptors(sctx, &sctx->descriptors[i],
1817 &sctx->shader_userdata.atom))
1818 return false;
1819 }
1820
1821 sctx->descriptors_dirty &= ~mask;
1822 return true;
1823 }
1824
1825 bool si_upload_compute_shader_descriptors(struct si_context *sctx)
1826 {
1827 /* Does not update rw_buffers as that is not needed for compute shaders
1828 * and the input buffer is using the same SGPR's anyway.
1829 */
1830 const unsigned mask = u_bit_consecutive(SI_DESCS_FIRST_COMPUTE,
1831 SI_NUM_DESCS - SI_DESCS_FIRST_COMPUTE);
1832 unsigned dirty = sctx->descriptors_dirty & mask;
1833
1834 while (dirty) {
1835 unsigned i = u_bit_scan(&dirty);
1836
1837 if (!si_upload_descriptors(sctx, &sctx->descriptors[i], NULL))
1838 return false;
1839 }
1840
1841 sctx->descriptors_dirty &= ~mask;
1842
1843 return true;
1844 }
1845
1846 void si_release_all_descriptors(struct si_context *sctx)
1847 {
1848 int i;
1849
1850 for (i = 0; i < SI_NUM_SHADERS; i++) {
1851 si_release_buffer_resources(&sctx->const_buffers[i],
1852 si_const_buffer_descriptors(sctx, i));
1853 si_release_buffer_resources(&sctx->shader_buffers[i],
1854 si_shader_buffer_descriptors(sctx, i));
1855 si_release_sampler_views(&sctx->samplers[i].views);
1856 si_release_image_views(&sctx->images[i]);
1857 }
1858 si_release_buffer_resources(&sctx->rw_buffers,
1859 &sctx->descriptors[SI_DESCS_RW_BUFFERS]);
1860
1861 for (i = 0; i < SI_NUM_DESCS; ++i)
1862 si_release_descriptors(&sctx->descriptors[i]);
1863 si_release_descriptors(&sctx->vertex_buffers);
1864 }
1865
1866 void si_all_descriptors_begin_new_cs(struct si_context *sctx)
1867 {
1868 int i;
1869
1870 for (i = 0; i < SI_NUM_SHADERS; i++) {
1871 si_buffer_resources_begin_new_cs(sctx, &sctx->const_buffers[i]);
1872 si_buffer_resources_begin_new_cs(sctx, &sctx->shader_buffers[i]);
1873 si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i].views);
1874 si_image_views_begin_new_cs(sctx, &sctx->images[i]);
1875 }
1876 si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers);
1877 si_vertex_buffers_begin_new_cs(sctx);
1878
1879 for (i = 0; i < SI_NUM_DESCS; ++i)
1880 si_descriptors_begin_new_cs(sctx, &sctx->descriptors[i]);
1881
1882 si_shader_userdata_begin_new_cs(sctx);
1883 }