2 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 /* Resource binding slots and sampler states (each described with 8 or
26 * 4 dwords) are stored in lists in memory which is accessed by shaders
27 * using scalar load instructions.
29 * This file is responsible for managing such lists. It keeps a copy of all
30 * descriptors in CPU memory and re-uploads a whole list if some slots have
33 * This code is also reponsible for updating shader pointers to those lists.
35 * Note that CP DMA can't be used for updating the lists, because a GPU hang
36 * could leave the list in a mid-IB state and the next IB would get wrong
37 * descriptors and the whole context would be unusable at that point.
38 * (Note: The register shadowing can't be used due to the same reason)
40 * Also, uploading descriptors to newly allocated memory doesn't require
44 * Possible scenarios for one 16 dword image+sampler slot:
46 * | Image | w/ FMASK | Buffer | NULL
47 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
48 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
49 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
50 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
52 * FMASK implies MSAA, therefore no sampler state.
53 * Sampler states are never unbound except when FMASK is bound.
59 #include "util/hash_table.h"
60 #include "util/u_idalloc.h"
61 #include "util/u_format.h"
62 #include "util/u_memory.h"
63 #include "util/u_upload_mgr.h"
66 /* NULL image and buffer descriptor for textures (alpha = 1) and images
69 * For images, all fields must be zero except for the swizzle, which
70 * supports arbitrary combinations of 0s and 1s. The texture type must be
71 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
73 * For buffers, all fields must be zero. If they are not, the hw hangs.
75 * This is the only reason why the buffer descriptor must be in words [4:7].
77 static uint32_t null_texture_descriptor
[8] = {
81 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) |
82 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
83 /* the rest must contain zeros, which is also used by the buffer
87 static uint32_t null_image_descriptor
[8] = {
91 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
92 /* the rest must contain zeros, which is also used by the buffer
96 static uint64_t si_desc_extract_buffer_address(const uint32_t *desc
)
98 uint64_t va
= desc
[0] |
99 ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
101 /* Sign-extend the 48-bit address. */
103 va
= (int64_t)va
>> 16;
107 static void si_init_descriptor_list(uint32_t *desc_list
,
108 unsigned element_dw_size
,
109 unsigned num_elements
,
110 const uint32_t *null_descriptor
)
114 /* Initialize the array to NULL descriptors if the element size is 8. */
115 if (null_descriptor
) {
116 assert(element_dw_size
% 8 == 0);
117 for (i
= 0; i
< num_elements
* element_dw_size
/ 8; i
++)
118 memcpy(desc_list
+ i
* 8, null_descriptor
, 8 * 4);
122 static void si_init_descriptors(struct si_descriptors
*desc
,
123 short shader_userdata_rel_index
,
124 unsigned element_dw_size
,
125 unsigned num_elements
)
127 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
128 desc
->element_dw_size
= element_dw_size
;
129 desc
->num_elements
= num_elements
;
130 desc
->shader_userdata_offset
= shader_userdata_rel_index
* 4;
131 desc
->slot_index_to_bind_directly
= -1;
134 static void si_release_descriptors(struct si_descriptors
*desc
)
136 si_resource_reference(&desc
->buffer
, NULL
);
140 static bool si_upload_descriptors(struct si_context
*sctx
,
141 struct si_descriptors
*desc
)
143 unsigned slot_size
= desc
->element_dw_size
* 4;
144 unsigned first_slot_offset
= desc
->first_active_slot
* slot_size
;
145 unsigned upload_size
= desc
->num_active_slots
* slot_size
;
147 /* Skip the upload if no shader is using the descriptors. dirty_mask
148 * will stay dirty and the descriptors will be uploaded when there is
149 * a shader using them.
154 /* If there is just one active descriptor, bind it directly. */
155 if ((int)desc
->first_active_slot
== desc
->slot_index_to_bind_directly
&&
156 desc
->num_active_slots
== 1) {
157 uint32_t *descriptor
= &desc
->list
[desc
->slot_index_to_bind_directly
*
158 desc
->element_dw_size
];
160 /* The buffer is already in the buffer list. */
161 si_resource_reference(&desc
->buffer
, NULL
);
162 desc
->gpu_list
= NULL
;
163 desc
->gpu_address
= si_desc_extract_buffer_address(descriptor
);
164 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
169 unsigned buffer_offset
;
170 u_upload_alloc(sctx
->b
.const_uploader
, first_slot_offset
, upload_size
,
171 si_optimal_tcc_alignment(sctx
, upload_size
),
172 &buffer_offset
, (struct pipe_resource
**)&desc
->buffer
,
175 desc
->gpu_address
= 0;
176 return false; /* skip the draw call */
179 util_memcpy_cpu_to_le32(ptr
, (char*)desc
->list
+ first_slot_offset
,
181 desc
->gpu_list
= ptr
- first_slot_offset
/ 4;
183 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, desc
->buffer
,
184 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
186 /* The shader pointer should point to slot 0. */
187 buffer_offset
-= first_slot_offset
;
188 desc
->gpu_address
= desc
->buffer
->gpu_address
+ buffer_offset
;
190 assert(desc
->buffer
->flags
& RADEON_FLAG_32BIT
);
191 assert((desc
->buffer
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
192 assert((desc
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
194 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
199 si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
204 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, desc
->buffer
,
205 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
210 static inline enum radeon_bo_priority
211 si_get_sampler_view_priority(struct si_resource
*res
)
213 if (res
->b
.b
.target
== PIPE_BUFFER
)
214 return RADEON_PRIO_SAMPLER_BUFFER
;
216 if (res
->b
.b
.nr_samples
> 1)
217 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
219 return RADEON_PRIO_SAMPLER_TEXTURE
;
222 static struct si_descriptors
*
223 si_sampler_and_image_descriptors(struct si_context
*sctx
, unsigned shader
)
225 return &sctx
->descriptors
[si_sampler_and_image_descriptors_idx(shader
)];
228 static void si_release_sampler_views(struct si_samplers
*samplers
)
232 for (i
= 0; i
< ARRAY_SIZE(samplers
->views
); i
++) {
233 pipe_sampler_view_reference(&samplers
->views
[i
], NULL
);
237 static void si_sampler_view_add_buffer(struct si_context
*sctx
,
238 struct pipe_resource
*resource
,
239 enum radeon_bo_usage usage
,
240 bool is_stencil_sampler
,
243 struct si_texture
*tex
= (struct si_texture
*)resource
;
244 enum radeon_bo_priority priority
;
249 /* Use the flushed depth texture if direct sampling is unsupported. */
250 if (resource
->target
!= PIPE_BUFFER
&&
251 tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil_sampler
))
252 tex
= tex
->flushed_depth_texture
;
254 priority
= si_get_sampler_view_priority(&tex
->buffer
);
255 radeon_add_to_gfx_buffer_list_check_mem(sctx
, &tex
->buffer
, usage
, priority
,
258 if (resource
->target
== PIPE_BUFFER
)
261 /* Add separate DCC. */
262 if (tex
->dcc_separate_buffer
) {
263 radeon_add_to_gfx_buffer_list_check_mem(sctx
, tex
->dcc_separate_buffer
,
264 usage
, RADEON_PRIO_SEPARATE_META
, check_mem
);
268 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
,
269 struct si_samplers
*samplers
)
271 unsigned mask
= samplers
->enabled_mask
;
273 /* Add buffers to the CS. */
275 int i
= u_bit_scan(&mask
);
276 struct si_sampler_view
*sview
= (struct si_sampler_view
*)samplers
->views
[i
];
278 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
280 sview
->is_stencil_sampler
, false);
284 /* Set buffer descriptor fields that can be changed by reallocations. */
285 static void si_set_buf_desc_address(struct si_resource
*buf
,
286 uint64_t offset
, uint32_t *state
)
288 uint64_t va
= buf
->gpu_address
+ offset
;
291 state
[1] &= C_008F04_BASE_ADDRESS_HI
;
292 state
[1] |= S_008F04_BASE_ADDRESS_HI(va
>> 32);
295 /* Set texture descriptor fields that can be changed by reallocations.
298 * \param base_level_info information of the level of BASE_ADDRESS
299 * \param base_level the level of BASE_ADDRESS
300 * \param first_level pipe_sampler_view.u.tex.first_level
301 * \param block_width util_format_get_blockwidth()
302 * \param is_stencil select between separate Z & Stencil
303 * \param state descriptor to update
305 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
306 struct si_texture
*tex
,
307 const struct legacy_surf_level
*base_level_info
,
308 unsigned base_level
, unsigned first_level
,
309 unsigned block_width
, bool is_stencil
,
312 uint64_t va
, meta_va
= 0;
314 if (tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil
)) {
315 tex
= tex
->flushed_depth_texture
;
319 va
= tex
->buffer
.gpu_address
;
321 if (sscreen
->info
.chip_class
>= GFX9
) {
322 /* Only stencil_offset needs to be added here. */
324 va
+= tex
->surface
.u
.gfx9
.stencil_offset
;
326 va
+= tex
->surface
.u
.gfx9
.surf_offset
;
328 va
+= base_level_info
->offset
;
332 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
333 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
335 /* Only macrotiled modes can set tile swizzle.
336 * GFX9 doesn't use (legacy) base_level_info.
338 if (sscreen
->info
.chip_class
>= GFX9
||
339 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
340 state
[0] |= tex
->surface
.tile_swizzle
;
342 if (sscreen
->info
.chip_class
>= GFX8
) {
343 state
[6] &= C_008F28_COMPRESSION_EN
;
345 if (vi_dcc_enabled(tex
, first_level
)) {
346 meta_va
= (!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) +
349 if (sscreen
->info
.chip_class
== GFX8
) {
350 meta_va
+= base_level_info
->dcc_offset
;
351 assert(base_level_info
->mode
== RADEON_SURF_MODE_2D
);
354 meta_va
|= (uint32_t)tex
->surface
.tile_swizzle
<< 8;
355 } else if (vi_tc_compat_htile_enabled(tex
, first_level
)) {
356 meta_va
= tex
->buffer
.gpu_address
+ tex
->htile_offset
;
360 state
[6] |= S_008F28_COMPRESSION_EN(1);
363 if (sscreen
->info
.chip_class
>= GFX8
&& sscreen
->info
.chip_class
<= GFX9
)
364 state
[7] = meta_va
>> 8;
366 if (sscreen
->info
.chip_class
>= GFX10
) {
367 state
[3] &= C_00A00C_SW_MODE
;
370 state
[3] |= S_00A00C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
372 state
[3] |= S_00A00C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
375 state
[6] &= C_00A018_META_DATA_ADDRESS_LO
&
376 C_00A018_META_PIPE_ALIGNED
;
379 struct gfx9_surf_meta_flags meta
;
382 meta
= tex
->surface
.u
.gfx9
.dcc
;
384 meta
= tex
->surface
.u
.gfx9
.htile
;
386 state
[6] |= S_00A018_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
387 S_00A018_META_DATA_ADDRESS_LO(meta_va
>> 8);
390 state
[7] = meta_va
>> 16;
391 } else if (sscreen
->info
.chip_class
>= GFX9
) {
392 state
[3] &= C_008F1C_SW_MODE
;
393 state
[4] &= C_008F20_PITCH
;
396 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
397 state
[4] |= S_008F20_PITCH(tex
->surface
.u
.gfx9
.stencil
.epitch
);
399 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
400 state
[4] |= S_008F20_PITCH(tex
->surface
.u
.gfx9
.surf
.epitch
);
403 state
[5] &= C_008F24_META_DATA_ADDRESS
&
404 C_008F24_META_PIPE_ALIGNED
&
405 C_008F24_META_RB_ALIGNED
;
407 struct gfx9_surf_meta_flags meta
;
410 meta
= tex
->surface
.u
.gfx9
.dcc
;
412 meta
= tex
->surface
.u
.gfx9
.htile
;
414 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
415 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
416 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
420 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
421 unsigned index
= si_tile_mode_index(tex
, base_level
, is_stencil
);
423 state
[3] &= C_008F1C_TILING_INDEX
;
424 state
[3] |= S_008F1C_TILING_INDEX(index
);
425 state
[4] &= C_008F20_PITCH
;
426 state
[4] |= S_008F20_PITCH(pitch
- 1);
430 static void si_set_sampler_state_desc(struct si_sampler_state
*sstate
,
431 struct si_sampler_view
*sview
,
432 struct si_texture
*tex
,
435 if (sview
&& sview
->is_integer
)
436 memcpy(desc
, sstate
->integer_val
, 4*4);
437 else if (tex
&& tex
->upgraded_depth
&&
438 (!sview
|| !sview
->is_stencil_sampler
))
439 memcpy(desc
, sstate
->upgraded_depth_val
, 4*4);
441 memcpy(desc
, sstate
->val
, 4*4);
444 static void si_set_sampler_view_desc(struct si_context
*sctx
,
445 struct si_sampler_view
*sview
,
446 struct si_sampler_state
*sstate
,
449 struct pipe_sampler_view
*view
= &sview
->base
;
450 struct si_texture
*tex
= (struct si_texture
*)view
->texture
;
451 bool is_buffer
= tex
->buffer
.b
.b
.target
== PIPE_BUFFER
;
453 if (unlikely(!is_buffer
&& sview
->dcc_incompatible
)) {
454 if (vi_dcc_enabled(tex
, view
->u
.tex
.first_level
))
455 if (!si_texture_disable_dcc(sctx
, tex
))
456 si_decompress_dcc(sctx
, tex
);
458 sview
->dcc_incompatible
= false;
461 assert(tex
); /* views with texture == NULL aren't supported */
462 memcpy(desc
, sview
->state
, 8*4);
465 si_set_buf_desc_address(&tex
->buffer
,
466 sview
->base
.u
.buf
.offset
,
469 bool is_separate_stencil
= tex
->db_compatible
&&
470 sview
->is_stencil_sampler
;
472 si_set_mutable_tex_desc_fields(sctx
->screen
, tex
,
473 sview
->base_level_info
,
475 sview
->base
.u
.tex
.first_level
,
481 if (!is_buffer
&& tex
->surface
.fmask_size
) {
482 memcpy(desc
+ 8, sview
->fmask_state
, 8*4);
484 /* Disable FMASK and bind sampler state in [12:15]. */
485 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
488 si_set_sampler_state_desc(sstate
, sview
,
489 is_buffer
? NULL
: tex
,
494 static bool color_needs_decompression(struct si_texture
*tex
)
496 return tex
->surface
.fmask_size
||
497 (tex
->dirty_level_mask
&&
498 (tex
->cmask_buffer
|| tex
->dcc_offset
));
501 static bool depth_needs_decompression(struct si_texture
*tex
)
503 /* If the depth/stencil texture is TC-compatible, no decompression
504 * will be done. The decompression function will only flush DB caches
505 * to make it coherent with shaders. That's necessary because the driver
506 * doesn't flush DB caches in any other case.
508 return tex
->db_compatible
;
511 static void si_set_sampler_view(struct si_context
*sctx
,
513 unsigned slot
, struct pipe_sampler_view
*view
,
514 bool disallow_early_out
)
516 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
517 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
518 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
519 unsigned desc_slot
= si_get_sampler_slot(slot
);
520 uint32_t *desc
= descs
->list
+ desc_slot
* 16;
522 if (samplers
->views
[slot
] == view
&& !disallow_early_out
)
526 struct si_texture
*tex
= (struct si_texture
*)view
->texture
;
528 si_set_sampler_view_desc(sctx
, sview
,
529 samplers
->sampler_states
[slot
], desc
);
531 if (tex
->buffer
.b
.b
.target
== PIPE_BUFFER
) {
532 tex
->buffer
.bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
533 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
534 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
536 if (depth_needs_decompression(tex
)) {
537 samplers
->needs_depth_decompress_mask
|= 1u << slot
;
539 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
541 if (color_needs_decompression(tex
)) {
542 samplers
->needs_color_decompress_mask
|= 1u << slot
;
544 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
547 if (tex
->dcc_offset
&&
548 p_atomic_read(&tex
->framebuffers_bound
))
549 sctx
->need_check_render_feedback
= true;
552 pipe_sampler_view_reference(&samplers
->views
[slot
], view
);
553 samplers
->enabled_mask
|= 1u << slot
;
555 /* Since this can flush, it must be done after enabled_mask is
557 si_sampler_view_add_buffer(sctx
, view
->texture
,
559 sview
->is_stencil_sampler
, true);
561 pipe_sampler_view_reference(&samplers
->views
[slot
], NULL
);
562 memcpy(desc
, null_texture_descriptor
, 8*4);
563 /* Only clear the lower dwords of FMASK. */
564 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
565 /* Re-set the sampler state if we are transitioning from FMASK. */
566 if (samplers
->sampler_states
[slot
])
567 si_set_sampler_state_desc(samplers
->sampler_states
[slot
], NULL
, NULL
,
570 samplers
->enabled_mask
&= ~(1u << slot
);
571 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
572 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
575 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
578 static void si_update_shader_needs_decompress_mask(struct si_context
*sctx
,
581 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
582 unsigned shader_bit
= 1 << shader
;
584 if (samplers
->needs_depth_decompress_mask
||
585 samplers
->needs_color_decompress_mask
||
586 sctx
->images
[shader
].needs_color_decompress_mask
)
587 sctx
->shader_needs_decompress_mask
|= shader_bit
;
589 sctx
->shader_needs_decompress_mask
&= ~shader_bit
;
592 static void si_set_sampler_views(struct pipe_context
*ctx
,
593 enum pipe_shader_type shader
, unsigned start
,
595 struct pipe_sampler_view
**views
)
597 struct si_context
*sctx
= (struct si_context
*)ctx
;
600 if (!count
|| shader
>= SI_NUM_SHADERS
)
604 for (i
= 0; i
< count
; i
++)
605 si_set_sampler_view(sctx
, shader
, start
+ i
, views
[i
], false);
607 for (i
= 0; i
< count
; i
++)
608 si_set_sampler_view(sctx
, shader
, start
+ i
, NULL
, false);
611 si_update_shader_needs_decompress_mask(sctx
, shader
);
615 si_samplers_update_needs_color_decompress_mask(struct si_samplers
*samplers
)
617 unsigned mask
= samplers
->enabled_mask
;
620 int i
= u_bit_scan(&mask
);
621 struct pipe_resource
*res
= samplers
->views
[i
]->texture
;
623 if (res
&& res
->target
!= PIPE_BUFFER
) {
624 struct si_texture
*tex
= (struct si_texture
*)res
;
626 if (color_needs_decompression(tex
)) {
627 samplers
->needs_color_decompress_mask
|= 1u << i
;
629 samplers
->needs_color_decompress_mask
&= ~(1u << i
);
638 si_release_image_views(struct si_images
*images
)
642 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
643 struct pipe_image_view
*view
= &images
->views
[i
];
645 pipe_resource_reference(&view
->resource
, NULL
);
650 si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images
*images
)
652 uint mask
= images
->enabled_mask
;
654 /* Add buffers to the CS. */
656 int i
= u_bit_scan(&mask
);
657 struct pipe_image_view
*view
= &images
->views
[i
];
659 assert(view
->resource
);
661 si_sampler_view_add_buffer(sctx
, view
->resource
,
662 RADEON_USAGE_READWRITE
, false, false);
667 si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
669 struct si_images
*images
= &ctx
->images
[shader
];
671 if (images
->enabled_mask
& (1u << slot
)) {
672 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
673 unsigned desc_slot
= si_get_image_slot(slot
);
675 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
676 images
->needs_color_decompress_mask
&= ~(1 << slot
);
678 memcpy(descs
->list
+ desc_slot
*8, null_image_descriptor
, 8*4);
679 images
->enabled_mask
&= ~(1u << slot
);
680 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
685 si_mark_image_range_valid(const struct pipe_image_view
*view
)
687 struct si_resource
*res
= si_resource(view
->resource
);
689 if (res
->b
.b
.target
!= PIPE_BUFFER
)
692 util_range_add(&res
->valid_buffer_range
,
694 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
697 static void si_set_shader_image_desc(struct si_context
*ctx
,
698 const struct pipe_image_view
*view
,
699 bool skip_decompress
,
700 uint32_t *desc
, uint32_t *fmask_desc
)
702 struct si_screen
*screen
= ctx
->screen
;
703 struct si_resource
*res
;
705 res
= si_resource(view
->resource
);
707 if (res
->b
.b
.target
== PIPE_BUFFER
||
708 view
->shader_access
& SI_IMAGE_ACCESS_AS_BUFFER
) {
709 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
710 si_mark_image_range_valid(view
);
712 si_make_buffer_descriptor(screen
, res
,
715 view
->u
.buf
.size
, desc
);
716 si_set_buf_desc_address(res
, view
->u
.buf
.offset
, desc
+ 4);
718 static const unsigned char swizzle
[4] = { 0, 1, 2, 3 };
719 struct si_texture
*tex
= (struct si_texture
*)res
;
720 unsigned level
= view
->u
.tex
.level
;
721 unsigned width
, height
, depth
, hw_level
;
722 bool uses_dcc
= vi_dcc_enabled(tex
, level
);
723 unsigned access
= view
->access
;
725 /* Clear the write flag when writes can't occur.
726 * Note that DCC_DECOMPRESS for MSAA doesn't work in some cases,
727 * so we don't wanna trigger it.
730 (!fmask_desc
&& tex
->surface
.fmask_size
!= 0)) {
731 assert(!"Z/S and MSAA image stores are not supported");
732 access
&= ~PIPE_IMAGE_ACCESS_WRITE
;
735 assert(!tex
->is_depth
);
736 assert(fmask_desc
|| tex
->surface
.fmask_size
== 0);
738 if (uses_dcc
&& !skip_decompress
&&
739 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
||
740 !vi_dcc_formats_compatible(res
->b
.b
.format
, view
->format
))) {
741 /* If DCC can't be disabled, at least decompress it.
742 * The decompression is relatively cheap if the surface
743 * has been decompressed already.
745 if (!si_texture_disable_dcc(ctx
, tex
))
746 si_decompress_dcc(ctx
, tex
);
749 if (ctx
->chip_class
>= GFX9
) {
750 /* Always set the base address. The swizzle modes don't
751 * allow setting mipmap level offsets as the base.
753 width
= res
->b
.b
.width0
;
754 height
= res
->b
.b
.height0
;
755 depth
= res
->b
.b
.depth0
;
758 /* Always force the base level to the selected level.
760 * This is required for 3D textures, where otherwise
761 * selecting a single slice for non-layered bindings
762 * fails. It doesn't hurt the other targets.
764 width
= u_minify(res
->b
.b
.width0
, level
);
765 height
= u_minify(res
->b
.b
.height0
, level
);
766 depth
= u_minify(res
->b
.b
.depth0
, level
);
770 screen
->make_texture_descriptor(screen
, tex
,
771 false, res
->b
.b
.target
,
772 view
->format
, swizzle
,
774 view
->u
.tex
.first_layer
,
775 view
->u
.tex
.last_layer
,
776 width
, height
, depth
,
778 si_set_mutable_tex_desc_fields(screen
, tex
,
779 &tex
->surface
.u
.legacy
.level
[level
],
781 util_format_get_blockwidth(view
->format
),
786 static void si_set_shader_image(struct si_context
*ctx
,
788 unsigned slot
, const struct pipe_image_view
*view
,
789 bool skip_decompress
)
791 struct si_images
*images
= &ctx
->images
[shader
];
792 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
793 struct si_resource
*res
;
794 unsigned desc_slot
= si_get_image_slot(slot
);
795 uint32_t *desc
= descs
->list
+ desc_slot
* 8;
797 if (!view
|| !view
->resource
) {
798 si_disable_shader_image(ctx
, shader
, slot
);
802 res
= si_resource(view
->resource
);
804 if (&images
->views
[slot
] != view
)
805 util_copy_image_view(&images
->views
[slot
], view
);
807 si_set_shader_image_desc(ctx
, view
, skip_decompress
, desc
, NULL
);
809 if (res
->b
.b
.target
== PIPE_BUFFER
||
810 view
->shader_access
& SI_IMAGE_ACCESS_AS_BUFFER
) {
811 images
->needs_color_decompress_mask
&= ~(1 << slot
);
812 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
814 struct si_texture
*tex
= (struct si_texture
*)res
;
815 unsigned level
= view
->u
.tex
.level
;
817 if (color_needs_decompression(tex
)) {
818 images
->needs_color_decompress_mask
|= 1 << slot
;
820 images
->needs_color_decompress_mask
&= ~(1 << slot
);
823 if (vi_dcc_enabled(tex
, level
) &&
824 p_atomic_read(&tex
->framebuffers_bound
))
825 ctx
->need_check_render_feedback
= true;
828 images
->enabled_mask
|= 1u << slot
;
829 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
831 /* Since this can flush, it must be done after enabled_mask is updated. */
832 si_sampler_view_add_buffer(ctx
, &res
->b
.b
,
833 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
) ?
834 RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
,
839 si_set_shader_images(struct pipe_context
*pipe
,
840 enum pipe_shader_type shader
,
841 unsigned start_slot
, unsigned count
,
842 const struct pipe_image_view
*views
)
844 struct si_context
*ctx
= (struct si_context
*)pipe
;
847 assert(shader
< SI_NUM_SHADERS
);
852 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
855 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
856 si_set_shader_image(ctx
, shader
, slot
, &views
[i
], false);
858 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
859 si_set_shader_image(ctx
, shader
, slot
, NULL
, false);
862 si_update_shader_needs_decompress_mask(ctx
, shader
);
866 si_images_update_needs_color_decompress_mask(struct si_images
*images
)
868 unsigned mask
= images
->enabled_mask
;
871 int i
= u_bit_scan(&mask
);
872 struct pipe_resource
*res
= images
->views
[i
].resource
;
874 if (res
&& res
->target
!= PIPE_BUFFER
) {
875 struct si_texture
*tex
= (struct si_texture
*)res
;
877 if (color_needs_decompression(tex
)) {
878 images
->needs_color_decompress_mask
|= 1 << i
;
880 images
->needs_color_decompress_mask
&= ~(1 << i
);
886 void si_update_ps_colorbuf0_slot(struct si_context
*sctx
)
888 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
889 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
890 unsigned slot
= SI_PS_IMAGE_COLORBUF0
;
891 struct pipe_surface
*surf
= NULL
;
893 /* si_texture_disable_dcc can get us here again. */
894 if (sctx
->blitter
->running
)
897 /* See whether FBFETCH is used and color buffer 0 is set. */
898 if (sctx
->ps_shader
.cso
&&
899 sctx
->ps_shader
.cso
->info
.opcode_count
[TGSI_OPCODE_FBFETCH
] &&
900 sctx
->framebuffer
.state
.nr_cbufs
&&
901 sctx
->framebuffer
.state
.cbufs
[0])
902 surf
= sctx
->framebuffer
.state
.cbufs
[0];
904 /* Return if FBFETCH transitions from disabled to disabled. */
905 if (!buffers
->buffers
[slot
] && !surf
)
908 sctx
->ps_uses_fbfetch
= surf
!= NULL
;
909 si_update_ps_iter_samples(sctx
);
912 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
913 struct pipe_image_view view
;
916 assert(!tex
->is_depth
);
918 /* Disable DCC, because the texture is used as both a sampler
921 si_texture_disable_dcc(sctx
, tex
);
923 if (tex
->buffer
.b
.b
.nr_samples
<= 1 && tex
->cmask_buffer
) {
925 assert(tex
->cmask_buffer
!= &tex
->buffer
);
926 si_eliminate_fast_color_clear(sctx
, tex
);
927 si_texture_discard_cmask(sctx
->screen
, tex
);
930 view
.resource
= surf
->texture
;
931 view
.format
= surf
->format
;
932 view
.access
= PIPE_IMAGE_ACCESS_READ
;
933 view
.u
.tex
.first_layer
= surf
->u
.tex
.first_layer
;
934 view
.u
.tex
.last_layer
= surf
->u
.tex
.last_layer
;
935 view
.u
.tex
.level
= surf
->u
.tex
.level
;
937 /* Set the descriptor. */
938 uint32_t *desc
= descs
->list
+ slot
*4;
939 memset(desc
, 0, 16 * 4);
940 si_set_shader_image_desc(sctx
, &view
, true, desc
, desc
+ 8);
942 pipe_resource_reference(&buffers
->buffers
[slot
], &tex
->buffer
.b
.b
);
943 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
944 &tex
->buffer
, RADEON_USAGE_READ
,
945 RADEON_PRIO_SHADER_RW_IMAGE
);
946 buffers
->enabled_mask
|= 1u << slot
;
948 /* Clear the descriptor. */
949 memset(descs
->list
+ slot
*4, 0, 8*4);
950 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
951 buffers
->enabled_mask
&= ~(1u << slot
);
954 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
959 static void si_bind_sampler_states(struct pipe_context
*ctx
,
960 enum pipe_shader_type shader
,
961 unsigned start
, unsigned count
, void **states
)
963 struct si_context
*sctx
= (struct si_context
*)ctx
;
964 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
965 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, shader
);
966 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
969 if (!count
|| shader
>= SI_NUM_SHADERS
|| !sstates
)
972 for (i
= 0; i
< count
; i
++) {
973 unsigned slot
= start
+ i
;
974 unsigned desc_slot
= si_get_sampler_slot(slot
);
977 sstates
[i
] == samplers
->sampler_states
[slot
])
981 assert(sstates
[i
]->magic
== SI_SAMPLER_STATE_MAGIC
);
983 samplers
->sampler_states
[slot
] = sstates
[i
];
985 /* If FMASK is bound, don't overwrite it.
986 * The sampler state will be set after FMASK is unbound.
988 struct si_sampler_view
*sview
=
989 (struct si_sampler_view
*)samplers
->views
[slot
];
991 struct si_texture
*tex
= NULL
;
993 if (sview
&& sview
->base
.texture
&&
994 sview
->base
.texture
->target
!= PIPE_BUFFER
)
995 tex
= (struct si_texture
*)sview
->base
.texture
;
997 if (tex
&& tex
->surface
.fmask_size
)
1000 si_set_sampler_state_desc(sstates
[i
], sview
, tex
,
1001 desc
->list
+ desc_slot
* 16 + 12);
1003 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
1007 /* BUFFER RESOURCES */
1009 static void si_init_buffer_resources(struct si_buffer_resources
*buffers
,
1010 struct si_descriptors
*descs
,
1011 unsigned num_buffers
,
1012 short shader_userdata_rel_index
,
1013 enum radeon_bo_priority priority
,
1014 enum radeon_bo_priority priority_constbuf
)
1016 buffers
->priority
= priority
;
1017 buffers
->priority_constbuf
= priority_constbuf
;
1018 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
1019 buffers
->offsets
= CALLOC(num_buffers
, sizeof(buffers
->offsets
[0]));
1021 si_init_descriptors(descs
, shader_userdata_rel_index
, 4, num_buffers
);
1024 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
1025 struct si_descriptors
*descs
)
1029 for (i
= 0; i
< descs
->num_elements
; i
++) {
1030 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
1033 FREE(buffers
->buffers
);
1034 FREE(buffers
->offsets
);
1037 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
1038 struct si_buffer_resources
*buffers
)
1040 unsigned mask
= buffers
->enabled_mask
;
1042 /* Add buffers to the CS. */
1044 int i
= u_bit_scan(&mask
);
1046 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1047 si_resource(buffers
->buffers
[i
]),
1048 buffers
->writable_mask
& (1u << i
) ? RADEON_USAGE_READWRITE
:
1050 i
< SI_NUM_SHADER_BUFFERS
? buffers
->priority
:
1051 buffers
->priority_constbuf
);
1055 static void si_get_buffer_from_descriptors(struct si_buffer_resources
*buffers
,
1056 struct si_descriptors
*descs
,
1057 unsigned idx
, struct pipe_resource
**buf
,
1058 unsigned *offset
, unsigned *size
)
1060 pipe_resource_reference(buf
, buffers
->buffers
[idx
]);
1062 struct si_resource
*res
= si_resource(*buf
);
1063 const uint32_t *desc
= descs
->list
+ idx
* 4;
1068 assert(G_008F04_STRIDE(desc
[1]) == 0);
1069 va
= si_desc_extract_buffer_address(desc
);
1071 assert(va
>= res
->gpu_address
&& va
+ *size
<= res
->gpu_address
+ res
->bo_size
);
1072 *offset
= va
- res
->gpu_address
;
1076 /* VERTEX BUFFERS */
1078 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
1080 int count
= sctx
->vertex_elements
? sctx
->vertex_elements
->count
: 0;
1083 for (i
= 0; i
< count
; i
++) {
1084 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1086 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1088 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1091 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1092 si_resource(sctx
->vertex_buffer
[vb
].buffer
.resource
),
1093 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1096 if (!sctx
->vb_descriptors_buffer
)
1098 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1099 sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1100 RADEON_PRIO_DESCRIPTORS
);
1103 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
1105 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
1107 unsigned desc_list_byte_size
;
1108 unsigned first_vb_use_mask
;
1111 if (!sctx
->vertex_buffers_dirty
|| !velems
)
1114 count
= velems
->count
;
1119 desc_list_byte_size
= velems
->desc_list_byte_size
;
1120 first_vb_use_mask
= velems
->first_vb_use_mask
;
1122 /* Vertex buffer descriptors are the only ones which are uploaded
1123 * directly through a staging buffer and don't go through
1124 * the fine-grained upload path.
1126 u_upload_alloc(sctx
->b
.const_uploader
, 0,
1127 desc_list_byte_size
,
1128 si_optimal_tcc_alignment(sctx
, desc_list_byte_size
),
1129 &sctx
->vb_descriptors_offset
,
1130 (struct pipe_resource
**)&sctx
->vb_descriptors_buffer
,
1132 if (!sctx
->vb_descriptors_buffer
) {
1133 sctx
->vb_descriptors_offset
= 0;
1134 sctx
->vb_descriptors_gpu_list
= NULL
;
1138 sctx
->vb_descriptors_gpu_list
= ptr
;
1139 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1140 sctx
->vb_descriptors_buffer
, RADEON_USAGE_READ
,
1141 RADEON_PRIO_DESCRIPTORS
);
1143 assert(count
<= SI_MAX_ATTRIBS
);
1145 for (i
= 0; i
< count
; i
++) {
1146 struct pipe_vertex_buffer
*vb
;
1147 struct si_resource
*buf
;
1148 unsigned vbo_index
= velems
->vertex_buffer_index
[i
];
1149 uint32_t *desc
= &ptr
[i
*4];
1151 vb
= &sctx
->vertex_buffer
[vbo_index
];
1152 buf
= si_resource(vb
->buffer
.resource
);
1154 memset(desc
, 0, 16);
1158 int64_t offset
= (int64_t)((int)vb
->buffer_offset
) +
1159 velems
->src_offset
[i
];
1160 uint64_t va
= buf
->gpu_address
+ offset
;
1162 int64_t num_records
= (int64_t)buf
->b
.b
.width0
- offset
;
1163 if (sctx
->chip_class
!= GFX8
&& vb
->stride
) {
1164 /* Round up by rounding down and adding 1 */
1165 num_records
= (num_records
- velems
->format_size
[i
]) /
1168 assert(num_records
>= 0 && num_records
<= UINT_MAX
);
1170 uint32_t rsrc_word3
= velems
->rsrc_word3
[i
];
1172 /* OOB_SELECT chooses the out-of-bounds check:
1173 * - 1: index >= NUM_RECORDS (Structured)
1174 * - 3: offset >= NUM_RECORDS (Raw)
1176 if (sctx
->chip_class
>= GFX10
)
1177 rsrc_word3
|= S_008F0C_OOB_SELECT(vb
->stride
? 1 : 3);
1180 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1181 S_008F04_STRIDE(vb
->stride
);
1182 desc
[2] = num_records
;
1183 desc
[3] = rsrc_word3
;
1185 if (first_vb_use_mask
& (1 << i
)) {
1186 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1187 si_resource(vb
->buffer
.resource
),
1188 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1192 /* Don't flush the const cache. It would have a very negative effect
1193 * on performance (confirmed by testing). New descriptors are always
1194 * uploaded to a fresh new buffer, so I don't think flushing the const
1195 * cache is needed. */
1196 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
1197 sctx
->vertex_buffers_dirty
= false;
1198 sctx
->vertex_buffer_pointer_dirty
= true;
1199 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VBO_DESCRIPTORS
;
1204 /* CONSTANT BUFFERS */
1206 static struct si_descriptors
*
1207 si_const_and_shader_buffer_descriptors(struct si_context
*sctx
, unsigned shader
)
1209 return &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(shader
)];
1212 void si_upload_const_buffer(struct si_context
*sctx
, struct si_resource
**buf
,
1213 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
)
1217 u_upload_alloc(sctx
->b
.const_uploader
, 0, size
,
1218 si_optimal_tcc_alignment(sctx
, size
),
1220 (struct pipe_resource
**)buf
, &tmp
);
1222 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
1225 static void si_set_constant_buffer(struct si_context
*sctx
,
1226 struct si_buffer_resources
*buffers
,
1227 unsigned descriptors_idx
,
1228 uint slot
, const struct pipe_constant_buffer
*input
)
1230 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1231 assert(slot
< descs
->num_elements
);
1232 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1234 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1235 * with a NULL buffer). We need to use a dummy buffer instead. */
1236 if (sctx
->chip_class
== GFX7
&&
1237 (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
1238 input
= &sctx
->null_const_buf
;
1240 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1241 struct pipe_resource
*buffer
= NULL
;
1243 unsigned buffer_offset
;
1245 /* Upload the user buffer if needed. */
1246 if (input
->user_buffer
) {
1247 si_upload_const_buffer(sctx
,
1248 (struct si_resource
**)&buffer
, input
->user_buffer
,
1249 input
->buffer_size
, &buffer_offset
);
1251 /* Just unbind on failure. */
1252 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1256 pipe_resource_reference(&buffer
, input
->buffer
);
1257 buffer_offset
= input
->buffer_offset
;
1260 va
= si_resource(buffer
)->gpu_address
+ buffer_offset
;
1262 /* Set the descriptor. */
1263 uint32_t *desc
= descs
->list
+ slot
*4;
1265 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1267 desc
[2] = input
->buffer_size
;
1268 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1269 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1270 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1271 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
1273 if (sctx
->chip_class
>= GFX10
) {
1274 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1275 S_008F0C_OOB_SELECT(3) |
1276 S_008F0C_RESOURCE_LEVEL(1);
1278 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1279 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1282 buffers
->buffers
[slot
] = buffer
;
1283 buffers
->offsets
[slot
] = buffer_offset
;
1284 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1285 si_resource(buffer
),
1287 buffers
->priority_constbuf
, true);
1288 buffers
->enabled_mask
|= 1u << slot
;
1290 /* Clear the descriptor. */
1291 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1292 buffers
->enabled_mask
&= ~(1u << slot
);
1295 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1298 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
,
1299 enum pipe_shader_type shader
, uint slot
,
1300 const struct pipe_constant_buffer
*input
)
1302 struct si_context
*sctx
= (struct si_context
*)ctx
;
1304 if (shader
>= SI_NUM_SHADERS
)
1307 if (slot
== 0 && input
&& input
->buffer
&&
1308 !(si_resource(input
->buffer
)->flags
& RADEON_FLAG_32BIT
)) {
1309 assert(!"constant buffer 0 must have a 32-bit VM address, use const_uploader");
1313 if (input
&& input
->buffer
)
1314 si_resource(input
->buffer
)->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
1316 slot
= si_get_constbuf_slot(slot
);
1317 si_set_constant_buffer(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1318 si_const_and_shader_buffer_descriptors_idx(shader
),
1322 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
1323 uint slot
, struct pipe_constant_buffer
*cbuf
)
1325 cbuf
->user_buffer
= NULL
;
1326 si_get_buffer_from_descriptors(
1327 &sctx
->const_and_shader_buffers
[shader
],
1328 si_const_and_shader_buffer_descriptors(sctx
, shader
),
1329 si_get_constbuf_slot(slot
),
1330 &cbuf
->buffer
, &cbuf
->buffer_offset
, &cbuf
->buffer_size
);
1333 /* SHADER BUFFERS */
1335 static void si_set_shader_buffer(struct si_context
*sctx
,
1336 struct si_buffer_resources
*buffers
,
1337 unsigned descriptors_idx
,
1338 uint slot
, const struct pipe_shader_buffer
*sbuffer
,
1339 bool writable
, enum radeon_bo_priority priority
)
1341 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1342 uint32_t *desc
= descs
->list
+ slot
* 4;
1344 if (!sbuffer
|| !sbuffer
->buffer
) {
1345 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1346 memset(desc
, 0, sizeof(uint32_t) * 4);
1347 buffers
->enabled_mask
&= ~(1u << slot
);
1348 buffers
->writable_mask
&= ~(1u << slot
);
1349 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1353 struct si_resource
*buf
= si_resource(sbuffer
->buffer
);
1354 uint64_t va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1357 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1359 desc
[2] = sbuffer
->buffer_size
;
1360 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1361 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1362 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1363 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
1365 if (sctx
->chip_class
>= GFX10
) {
1366 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1367 S_008F0C_OOB_SELECT(3) |
1368 S_008F0C_RESOURCE_LEVEL(1);
1370 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1371 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1374 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1375 buffers
->offsets
[slot
] = sbuffer
->buffer_offset
;
1376 radeon_add_to_gfx_buffer_list_check_mem(sctx
, buf
,
1377 writable
? RADEON_USAGE_READWRITE
:
1381 buffers
->writable_mask
|= 1u << slot
;
1383 buffers
->writable_mask
&= ~(1u << slot
);
1385 buffers
->enabled_mask
|= 1u << slot
;
1386 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1388 util_range_add(&buf
->valid_buffer_range
, sbuffer
->buffer_offset
,
1389 sbuffer
->buffer_offset
+ sbuffer
->buffer_size
);
1392 static void si_set_shader_buffers(struct pipe_context
*ctx
,
1393 enum pipe_shader_type shader
,
1394 unsigned start_slot
, unsigned count
,
1395 const struct pipe_shader_buffer
*sbuffers
,
1396 unsigned writable_bitmask
)
1398 struct si_context
*sctx
= (struct si_context
*)ctx
;
1399 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1400 unsigned descriptors_idx
= si_const_and_shader_buffer_descriptors_idx(shader
);
1403 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1405 for (i
= 0; i
< count
; ++i
) {
1406 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1407 unsigned slot
= si_get_shaderbuf_slot(start_slot
+ i
);
1409 if (sbuffer
&& sbuffer
->buffer
)
1410 si_resource(sbuffer
->buffer
)->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1412 si_set_shader_buffer(sctx
, buffers
, descriptors_idx
, slot
, sbuffer
,
1413 !!(writable_bitmask
& (1u << i
)),
1418 void si_get_shader_buffers(struct si_context
*sctx
,
1419 enum pipe_shader_type shader
,
1420 uint start_slot
, uint count
,
1421 struct pipe_shader_buffer
*sbuf
)
1423 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1424 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1426 for (unsigned i
= 0; i
< count
; ++i
) {
1427 si_get_buffer_from_descriptors(
1429 si_get_shaderbuf_slot(start_slot
+ i
),
1430 &sbuf
[i
].buffer
, &sbuf
[i
].buffer_offset
,
1431 &sbuf
[i
].buffer_size
);
1437 void si_set_rw_buffer(struct si_context
*sctx
,
1438 uint slot
, const struct pipe_constant_buffer
*input
)
1440 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
, SI_DESCS_RW_BUFFERS
,
1444 void si_set_rw_shader_buffer(struct si_context
*sctx
, uint slot
,
1445 const struct pipe_shader_buffer
*sbuffer
)
1447 si_set_shader_buffer(sctx
, &sctx
->rw_buffers
, SI_DESCS_RW_BUFFERS
,
1448 slot
, sbuffer
, true, RADEON_PRIO_SHADER_RW_BUFFER
);
1451 void si_set_ring_buffer(struct si_context
*sctx
, uint slot
,
1452 struct pipe_resource
*buffer
,
1453 unsigned stride
, unsigned num_records
,
1454 bool add_tid
, bool swizzle
,
1455 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1457 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1458 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1460 /* The stride field in the resource descriptor has 14 bits */
1461 assert(stride
< (1 << 14));
1463 assert(slot
< descs
->num_elements
);
1464 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1469 va
= si_resource(buffer
)->gpu_address
+ offset
;
1471 switch (element_size
) {
1473 assert(!"Unsupported ring buffer element size");
1489 switch (index_stride
) {
1491 assert(!"Unsupported ring buffer index stride");
1507 if (sctx
->chip_class
>= GFX8
&& stride
)
1508 num_records
*= stride
;
1510 /* Set the descriptor. */
1511 uint32_t *desc
= descs
->list
+ slot
*4;
1513 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1514 S_008F04_STRIDE(stride
) |
1515 S_008F04_SWIZZLE_ENABLE(swizzle
);
1516 desc
[2] = num_records
;
1517 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1518 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1519 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1520 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1521 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1522 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1523 S_008F0C_INDEX_STRIDE(index_stride
) |
1524 S_008F0C_ADD_TID_ENABLE(add_tid
);
1526 if (sctx
->chip_class
>= GFX9
)
1527 assert(!swizzle
|| element_size
== 1); /* always 4 bytes on GFX9 */
1529 desc
[3] |= S_008F0C_ELEMENT_SIZE(element_size
);
1531 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1532 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
1533 si_resource(buffer
),
1534 RADEON_USAGE_READWRITE
, buffers
->priority
);
1535 buffers
->enabled_mask
|= 1u << slot
;
1537 /* Clear the descriptor. */
1538 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1539 buffers
->enabled_mask
&= ~(1u << slot
);
1542 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1545 /* INTERNAL CONST BUFFERS */
1547 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
1548 const struct pipe_poly_stipple
*state
)
1550 struct si_context
*sctx
= (struct si_context
*)ctx
;
1551 struct pipe_constant_buffer cb
= {};
1552 unsigned stipple
[32];
1555 for (i
= 0; i
< 32; i
++)
1556 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1558 cb
.user_buffer
= stipple
;
1559 cb
.buffer_size
= sizeof(stipple
);
1561 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1564 /* TEXTURE METADATA ENABLE/DISABLE */
1567 si_resident_handles_update_needs_color_decompress(struct si_context
*sctx
)
1569 util_dynarray_clear(&sctx
->resident_tex_needs_color_decompress
);
1570 util_dynarray_clear(&sctx
->resident_img_needs_color_decompress
);
1572 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1573 struct si_texture_handle
*, tex_handle
) {
1574 struct pipe_resource
*res
= (*tex_handle
)->view
->texture
;
1575 struct si_texture
*tex
;
1577 if (!res
|| res
->target
== PIPE_BUFFER
)
1580 tex
= (struct si_texture
*)res
;
1581 if (!color_needs_decompression(tex
))
1584 util_dynarray_append(&sctx
->resident_tex_needs_color_decompress
,
1585 struct si_texture_handle
*, *tex_handle
);
1588 util_dynarray_foreach(&sctx
->resident_img_handles
,
1589 struct si_image_handle
*, img_handle
) {
1590 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1591 struct pipe_resource
*res
= view
->resource
;
1592 struct si_texture
*tex
;
1594 if (!res
|| res
->target
== PIPE_BUFFER
)
1597 tex
= (struct si_texture
*)res
;
1598 if (!color_needs_decompression(tex
))
1601 util_dynarray_append(&sctx
->resident_img_needs_color_decompress
,
1602 struct si_image_handle
*, *img_handle
);
1606 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1607 * while the texture is bound, possibly by a different context. In that case,
1608 * call this function to update needs_*_decompress_masks.
1610 void si_update_needs_color_decompress_masks(struct si_context
*sctx
)
1612 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1613 si_samplers_update_needs_color_decompress_mask(&sctx
->samplers
[i
]);
1614 si_images_update_needs_color_decompress_mask(&sctx
->images
[i
]);
1615 si_update_shader_needs_decompress_mask(sctx
, i
);
1618 si_resident_handles_update_needs_color_decompress(sctx
);
1621 /* BUFFER DISCARD/INVALIDATION */
1623 /* Reset descriptors of buffer resources after \p buf has been invalidated.
1624 * If buf == NULL, reset all descriptors.
1626 static void si_reset_buffer_resources(struct si_context
*sctx
,
1627 struct si_buffer_resources
*buffers
,
1628 unsigned descriptors_idx
,
1630 struct pipe_resource
*buf
,
1631 enum radeon_bo_priority priority
)
1633 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1634 unsigned mask
= buffers
->enabled_mask
& slot_mask
;
1637 unsigned i
= u_bit_scan(&mask
);
1638 struct pipe_resource
*buffer
= buffers
->buffers
[i
];
1640 if (buffer
&& (!buf
|| buffer
== buf
)) {
1641 si_set_buf_desc_address(si_resource(buffer
), buffers
->offsets
[i
],
1643 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1645 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1646 si_resource(buffer
),
1647 buffers
->writable_mask
& (1u << i
) ?
1648 RADEON_USAGE_READWRITE
:
1655 /* Update all buffer bindings where the buffer is bound, including
1656 * all resource descriptors. This is invalidate_buffer without
1659 * If buf == NULL, update all buffer bindings.
1661 void si_rebind_buffer(struct si_context
*sctx
, struct pipe_resource
*buf
)
1663 struct si_resource
*buffer
= si_resource(buf
);
1665 unsigned num_elems
= sctx
->vertex_elements
?
1666 sctx
->vertex_elements
->count
: 0;
1668 /* We changed the buffer, now we need to bind it where the old one
1669 * was bound. This consists of 2 things:
1670 * 1) Updating the resource descriptor and dirtying it.
1671 * 2) Adding a relocation to the CS, so that it's usable.
1674 /* Vertex buffers. */
1677 sctx
->vertex_buffers_dirty
= true;
1678 } else if (buffer
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
1679 for (i
= 0; i
< num_elems
; i
++) {
1680 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1682 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1684 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1687 if (sctx
->vertex_buffer
[vb
].buffer
.resource
== buf
) {
1688 sctx
->vertex_buffers_dirty
= true;
1694 /* Streamout buffers. (other internal buffers can't be invalidated) */
1695 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
1696 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1697 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1698 struct si_descriptors
*descs
=
1699 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1700 struct pipe_resource
*buffer
= buffers
->buffers
[i
];
1702 if (!buffer
|| (buf
&& buffer
!= buf
))
1705 si_set_buf_desc_address(si_resource(buffer
), buffers
->offsets
[i
],
1707 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1709 radeon_add_to_gfx_buffer_list_check_mem(sctx
,
1710 si_resource(buffer
),
1712 RADEON_PRIO_SHADER_RW_BUFFER
,
1715 /* Update the streamout state. */
1716 if (sctx
->streamout
.begin_emitted
)
1717 si_emit_streamout_end(sctx
);
1718 sctx
->streamout
.append_bitmask
=
1719 sctx
->streamout
.enabled_mask
;
1720 si_streamout_buffers_dirty(sctx
);
1724 /* Constant and shader buffers. */
1725 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1726 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1727 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1728 si_const_and_shader_buffer_descriptors_idx(shader
),
1729 u_bit_consecutive(SI_NUM_SHADER_BUFFERS
, SI_NUM_CONST_BUFFERS
),
1731 sctx
->const_and_shader_buffers
[shader
].priority_constbuf
);
1734 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
1735 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1736 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1737 si_const_and_shader_buffer_descriptors_idx(shader
),
1738 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
),
1740 sctx
->const_and_shader_buffers
[shader
].priority
);
1743 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
1744 /* Texture buffers - update bindings. */
1745 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1746 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1747 struct si_descriptors
*descs
=
1748 si_sampler_and_image_descriptors(sctx
, shader
);
1749 unsigned mask
= samplers
->enabled_mask
;
1752 unsigned i
= u_bit_scan(&mask
);
1753 struct pipe_resource
*buffer
= samplers
->views
[i
]->texture
;
1755 if (buffer
&& buffer
->target
== PIPE_BUFFER
&&
1756 (!buf
|| buffer
== buf
)) {
1757 unsigned desc_slot
= si_get_sampler_slot(i
);
1759 si_set_buf_desc_address(si_resource(buffer
),
1760 samplers
->views
[i
]->u
.buf
.offset
,
1761 descs
->list
+ desc_slot
* 16 + 4);
1762 sctx
->descriptors_dirty
|=
1763 1u << si_sampler_and_image_descriptors_idx(shader
);
1765 radeon_add_to_gfx_buffer_list_check_mem(
1766 sctx
, si_resource(buffer
),
1768 RADEON_PRIO_SAMPLER_BUFFER
, true);
1775 if (!buffer
|| buffer
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
1776 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1777 struct si_images
*images
= &sctx
->images
[shader
];
1778 struct si_descriptors
*descs
=
1779 si_sampler_and_image_descriptors(sctx
, shader
);
1780 unsigned mask
= images
->enabled_mask
;
1783 unsigned i
= u_bit_scan(&mask
);
1784 struct pipe_resource
*buffer
= images
->views
[i
].resource
;
1786 if (buffer
&& buffer
->target
== PIPE_BUFFER
&&
1787 (!buf
|| buffer
== buf
)) {
1788 unsigned desc_slot
= si_get_image_slot(i
);
1790 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1791 si_mark_image_range_valid(&images
->views
[i
]);
1793 si_set_buf_desc_address(si_resource(buffer
),
1794 images
->views
[i
].u
.buf
.offset
,
1795 descs
->list
+ desc_slot
* 8 + 4);
1796 sctx
->descriptors_dirty
|=
1797 1u << si_sampler_and_image_descriptors_idx(shader
);
1799 radeon_add_to_gfx_buffer_list_check_mem(
1800 sctx
, si_resource(buffer
),
1801 RADEON_USAGE_READWRITE
,
1802 RADEON_PRIO_SAMPLER_BUFFER
, true);
1808 /* Bindless texture handles */
1809 if (!buffer
|| buffer
->texture_handle_allocated
) {
1810 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1812 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1813 struct si_texture_handle
*, tex_handle
) {
1814 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
1815 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1816 struct pipe_resource
*buffer
= view
->texture
;
1818 if (buffer
&& buffer
->target
== PIPE_BUFFER
&&
1819 (!buf
|| buffer
== buf
)) {
1820 si_set_buf_desc_address(si_resource(buffer
),
1823 desc_slot
* 16 + 4);
1825 (*tex_handle
)->desc_dirty
= true;
1826 sctx
->bindless_descriptors_dirty
= true;
1828 radeon_add_to_gfx_buffer_list_check_mem(
1829 sctx
, si_resource(buffer
),
1831 RADEON_PRIO_SAMPLER_BUFFER
, true);
1836 /* Bindless image handles */
1837 if (!buffer
|| buffer
->image_handle_allocated
) {
1838 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1840 util_dynarray_foreach(&sctx
->resident_img_handles
,
1841 struct si_image_handle
*, img_handle
) {
1842 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1843 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1844 struct pipe_resource
*buffer
= view
->resource
;
1846 if (buffer
&& buffer
->target
== PIPE_BUFFER
&&
1847 (!buf
|| buffer
== buf
)) {
1848 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
1849 si_mark_image_range_valid(view
);
1851 si_set_buf_desc_address(si_resource(buffer
),
1854 desc_slot
* 16 + 4);
1856 (*img_handle
)->desc_dirty
= true;
1857 sctx
->bindless_descriptors_dirty
= true;
1859 radeon_add_to_gfx_buffer_list_check_mem(
1860 sctx
, si_resource(buffer
),
1861 RADEON_USAGE_READWRITE
,
1862 RADEON_PRIO_SAMPLER_BUFFER
, true);
1868 /* Do the same for other contexts. They will invoke this function
1869 * with buffer == NULL.
1871 unsigned new_counter
= p_atomic_inc_return(&sctx
->screen
->dirty_buf_counter
);
1873 /* Skip the update for the current context, because we have already updated
1874 * the buffer bindings.
1876 if (new_counter
== sctx
->last_dirty_buf_counter
+ 1)
1877 sctx
->last_dirty_buf_counter
= new_counter
;
1881 static void si_upload_bindless_descriptor(struct si_context
*sctx
,
1883 unsigned num_dwords
)
1885 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1886 unsigned desc_slot_offset
= desc_slot
* 16;
1890 data
= desc
->list
+ desc_slot_offset
;
1891 va
= desc
->gpu_address
+ desc_slot_offset
* 4;
1893 si_cp_write_data(sctx
, desc
->buffer
, va
- desc
->buffer
->gpu_address
,
1894 num_dwords
* 4, V_370_TC_L2
, V_370_ME
, data
);
1897 static void si_upload_bindless_descriptors(struct si_context
*sctx
)
1899 if (!sctx
->bindless_descriptors_dirty
)
1902 /* Wait for graphics/compute to be idle before updating the resident
1903 * descriptors directly in memory, in case the GPU is using them.
1905 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
1906 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1907 si_emit_cache_flush(sctx
);
1909 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1910 struct si_texture_handle
*, tex_handle
) {
1911 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1913 if (!(*tex_handle
)->desc_dirty
)
1916 si_upload_bindless_descriptor(sctx
, desc_slot
, 16);
1917 (*tex_handle
)->desc_dirty
= false;
1920 util_dynarray_foreach(&sctx
->resident_img_handles
,
1921 struct si_image_handle
*, img_handle
) {
1922 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1924 if (!(*img_handle
)->desc_dirty
)
1927 si_upload_bindless_descriptor(sctx
, desc_slot
, 8);
1928 (*img_handle
)->desc_dirty
= false;
1931 /* Invalidate L1 because it doesn't know that L2 changed. */
1932 sctx
->flags
|= SI_CONTEXT_INV_SCACHE
;
1933 si_emit_cache_flush(sctx
);
1935 sctx
->bindless_descriptors_dirty
= false;
1938 /* Update mutable image descriptor fields of all resident textures. */
1939 static void si_update_bindless_texture_descriptor(struct si_context
*sctx
,
1940 struct si_texture_handle
*tex_handle
)
1942 struct si_sampler_view
*sview
= (struct si_sampler_view
*)tex_handle
->view
;
1943 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1944 unsigned desc_slot_offset
= tex_handle
->desc_slot
* 16;
1945 uint32_t desc_list
[16];
1947 if (sview
->base
.texture
->target
== PIPE_BUFFER
)
1950 memcpy(desc_list
, desc
->list
+ desc_slot_offset
, sizeof(desc_list
));
1951 si_set_sampler_view_desc(sctx
, sview
, &tex_handle
->sstate
,
1952 desc
->list
+ desc_slot_offset
);
1954 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1955 sizeof(desc_list
))) {
1956 tex_handle
->desc_dirty
= true;
1957 sctx
->bindless_descriptors_dirty
= true;
1961 static void si_update_bindless_image_descriptor(struct si_context
*sctx
,
1962 struct si_image_handle
*img_handle
)
1964 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1965 unsigned desc_slot_offset
= img_handle
->desc_slot
* 16;
1966 struct pipe_image_view
*view
= &img_handle
->view
;
1967 uint32_t desc_list
[8];
1969 if (view
->resource
->target
== PIPE_BUFFER
)
1972 memcpy(desc_list
, desc
->list
+ desc_slot_offset
,
1974 si_set_shader_image_desc(sctx
, view
, true,
1975 desc
->list
+ desc_slot_offset
, NULL
);
1977 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1978 sizeof(desc_list
))) {
1979 img_handle
->desc_dirty
= true;
1980 sctx
->bindless_descriptors_dirty
= true;
1984 static void si_update_all_resident_texture_descriptors(struct si_context
*sctx
)
1986 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1987 struct si_texture_handle
*, tex_handle
) {
1988 si_update_bindless_texture_descriptor(sctx
, *tex_handle
);
1991 util_dynarray_foreach(&sctx
->resident_img_handles
,
1992 struct si_image_handle
*, img_handle
) {
1993 si_update_bindless_image_descriptor(sctx
, *img_handle
);
1996 si_upload_bindless_descriptors(sctx
);
1999 /* Update mutable image descriptor fields of all bound textures. */
2000 void si_update_all_texture_descriptors(struct si_context
*sctx
)
2004 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
2005 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
2006 struct si_images
*images
= &sctx
->images
[shader
];
2010 mask
= images
->enabled_mask
;
2012 unsigned i
= u_bit_scan(&mask
);
2013 struct pipe_image_view
*view
= &images
->views
[i
];
2015 if (!view
->resource
||
2016 view
->resource
->target
== PIPE_BUFFER
)
2019 si_set_shader_image(sctx
, shader
, i
, view
, true);
2022 /* Sampler views. */
2023 mask
= samplers
->enabled_mask
;
2025 unsigned i
= u_bit_scan(&mask
);
2026 struct pipe_sampler_view
*view
= samplers
->views
[i
];
2030 view
->texture
->target
== PIPE_BUFFER
)
2033 si_set_sampler_view(sctx
, shader
, i
,
2034 samplers
->views
[i
], true);
2037 si_update_shader_needs_decompress_mask(sctx
, shader
);
2040 si_update_all_resident_texture_descriptors(sctx
);
2041 si_update_ps_colorbuf0_slot(sctx
);
2044 /* SHADER USER DATA */
2046 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
,
2049 sctx
->shader_pointers_dirty
|=
2050 u_bit_consecutive(SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
,
2051 SI_NUM_SHADER_DESCS
);
2053 if (shader
== PIPE_SHADER_VERTEX
)
2054 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
2056 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
2059 static void si_shader_pointers_begin_new_cs(struct si_context
*sctx
)
2061 sctx
->shader_pointers_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2062 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
2063 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
2064 sctx
->graphics_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
2065 sctx
->compute_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
2068 /* Set a base register address for user data constants in the given shader.
2069 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
2071 static void si_set_user_data_base(struct si_context
*sctx
,
2072 unsigned shader
, uint32_t new_base
)
2074 uint32_t *base
= &sctx
->shader_pointers
.sh_base
[shader
];
2076 if (*base
!= new_base
) {
2080 si_mark_shader_pointers_dirty(sctx
, shader
);
2082 /* Any change in enabled shader stages requires re-emitting
2083 * the VS state SGPR, because it contains the clamp_vertex_color
2084 * state, which can be done in VS, TES, and GS.
2086 sctx
->last_vs_state
= ~0;
2090 /* This must be called when these shaders are changed from non-NULL to NULL
2093 * - tessellation control shader
2094 * - tessellation evaluation shader
2096 void si_shader_change_notify(struct si_context
*sctx
)
2098 /* VS can be bound as VS, ES, or LS. */
2099 if (sctx
->tes_shader
.cso
) {
2100 if (sctx
->chip_class
>= GFX9
) {
2101 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2102 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2104 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2105 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2107 } else if (sctx
->gs_shader
.cso
) {
2108 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2109 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2111 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2112 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2115 /* TES can be bound as ES, VS, or not bound. */
2116 if (sctx
->tes_shader
.cso
) {
2117 if (sctx
->gs_shader
.cso
)
2118 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2119 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2121 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2122 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2124 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
2128 static void si_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
2130 unsigned pointer_count
)
2132 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
, 0));
2133 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
2136 static void si_emit_shader_pointer_body(struct si_screen
*sscreen
,
2137 struct radeon_cmdbuf
*cs
,
2140 radeon_emit(cs
, va
);
2142 assert(va
== 0 || (va
>> 32) == sscreen
->info
.address32_hi
);
2145 static void si_emit_shader_pointer(struct si_context
*sctx
,
2146 struct si_descriptors
*desc
,
2149 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2150 unsigned sh_offset
= sh_base
+ desc
->shader_userdata_offset
;
2152 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2153 si_emit_shader_pointer_body(sctx
->screen
, cs
, desc
->gpu_address
);
2156 static void si_emit_consecutive_shader_pointers(struct si_context
*sctx
,
2157 unsigned pointer_mask
,
2163 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2164 unsigned mask
= sctx
->shader_pointers_dirty
& pointer_mask
;
2168 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
2170 struct si_descriptors
*descs
= &sctx
->descriptors
[start
];
2171 unsigned sh_offset
= sh_base
+ descs
->shader_userdata_offset
;
2173 si_emit_shader_pointer_head(cs
, sh_offset
, count
);
2174 for (int i
= 0; i
< count
; i
++)
2175 si_emit_shader_pointer_body(sctx
->screen
, cs
,
2176 descs
[i
].gpu_address
);
2180 static void si_emit_global_shader_pointers(struct si_context
*sctx
,
2181 struct si_descriptors
*descs
)
2183 if (sctx
->chip_class
== GFX9
) {
2184 /* Broadcast it to all shader stages. */
2185 si_emit_shader_pointer(sctx
, descs
,
2186 R_00B530_SPI_SHADER_USER_DATA_COMMON_0
);
2190 si_emit_shader_pointer(sctx
, descs
,
2191 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2192 si_emit_shader_pointer(sctx
, descs
,
2193 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2194 si_emit_shader_pointer(sctx
, descs
,
2195 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2196 si_emit_shader_pointer(sctx
, descs
,
2197 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2198 si_emit_shader_pointer(sctx
, descs
,
2199 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2200 si_emit_shader_pointer(sctx
, descs
,
2201 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2204 void si_emit_graphics_shader_pointers(struct si_context
*sctx
)
2206 uint32_t *sh_base
= sctx
->shader_pointers
.sh_base
;
2208 if (sctx
->shader_pointers_dirty
& (1 << SI_DESCS_RW_BUFFERS
)) {
2209 si_emit_global_shader_pointers(sctx
,
2210 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2213 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(VERTEX
),
2214 sh_base
[PIPE_SHADER_VERTEX
]);
2215 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_EVAL
),
2216 sh_base
[PIPE_SHADER_TESS_EVAL
]);
2217 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(FRAGMENT
),
2218 sh_base
[PIPE_SHADER_FRAGMENT
]);
2219 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_CTRL
),
2220 sh_base
[PIPE_SHADER_TESS_CTRL
]);
2221 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(GEOMETRY
),
2222 sh_base
[PIPE_SHADER_GEOMETRY
]);
2224 sctx
->shader_pointers_dirty
&=
2225 ~u_bit_consecutive(SI_DESCS_RW_BUFFERS
, SI_DESCS_FIRST_COMPUTE
);
2227 if (sctx
->vertex_buffer_pointer_dirty
) {
2228 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2230 /* Find the location of the VB descriptor pointer. */
2231 /* TODO: In the future, the pointer will be packed in unused
2232 * bits of the first 2 VB descriptors. */
2233 unsigned sh_dw_offset
= SI_VS_NUM_USER_SGPR
;
2234 if (sctx
->chip_class
>= GFX9
) {
2235 if (sctx
->tes_shader
.cso
)
2236 sh_dw_offset
= GFX9_TCS_NUM_USER_SGPR
;
2237 else if (sctx
->gs_shader
.cso
)
2238 sh_dw_offset
= GFX9_VSGS_NUM_USER_SGPR
;
2241 unsigned sh_offset
= sh_base
[PIPE_SHADER_VERTEX
] + sh_dw_offset
* 4;
2242 si_emit_shader_pointer_head(cs
, sh_offset
, 1);
2243 si_emit_shader_pointer_body(sctx
->screen
, cs
,
2244 sctx
->vb_descriptors_buffer
->gpu_address
+
2245 sctx
->vb_descriptors_offset
);
2246 sctx
->vertex_buffer_pointer_dirty
= false;
2249 if (sctx
->graphics_bindless_pointer_dirty
) {
2250 si_emit_global_shader_pointers(sctx
,
2251 &sctx
->bindless_descriptors
);
2252 sctx
->graphics_bindless_pointer_dirty
= false;
2256 void si_emit_compute_shader_pointers(struct si_context
*sctx
)
2258 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
2260 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(COMPUTE
),
2261 R_00B900_COMPUTE_USER_DATA_0
);
2262 sctx
->shader_pointers_dirty
&= ~SI_DESCS_SHADER_MASK(COMPUTE
);
2264 if (sctx
->compute_bindless_pointer_dirty
) {
2265 si_emit_shader_pointer(sctx
, &sctx
->bindless_descriptors
, base
);
2266 sctx
->compute_bindless_pointer_dirty
= false;
2272 static void si_init_bindless_descriptors(struct si_context
*sctx
,
2273 struct si_descriptors
*desc
,
2274 short shader_userdata_rel_index
,
2275 unsigned num_elements
)
2277 MAYBE_UNUSED
unsigned desc_slot
;
2279 si_init_descriptors(desc
, shader_userdata_rel_index
, 16, num_elements
);
2280 sctx
->bindless_descriptors
.num_active_slots
= num_elements
;
2282 /* The first bindless descriptor is stored at slot 1, because 0 is not
2283 * considered to be a valid handle.
2285 sctx
->num_bindless_descriptors
= 1;
2287 /* Track which bindless slots are used (or not). */
2288 util_idalloc_init(&sctx
->bindless_used_slots
);
2289 util_idalloc_resize(&sctx
->bindless_used_slots
, num_elements
);
2291 /* Reserve slot 0 because it's an invalid handle for bindless. */
2292 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2293 assert(desc_slot
== 0);
2296 static void si_release_bindless_descriptors(struct si_context
*sctx
)
2298 si_release_descriptors(&sctx
->bindless_descriptors
);
2299 util_idalloc_fini(&sctx
->bindless_used_slots
);
2302 static unsigned si_get_first_free_bindless_slot(struct si_context
*sctx
)
2304 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2307 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2308 if (desc_slot
>= desc
->num_elements
) {
2309 /* The array of bindless descriptors is full, resize it. */
2310 unsigned slot_size
= desc
->element_dw_size
* 4;
2311 unsigned new_num_elements
= desc
->num_elements
* 2;
2313 desc
->list
= REALLOC(desc
->list
, desc
->num_elements
* slot_size
,
2314 new_num_elements
* slot_size
);
2315 desc
->num_elements
= new_num_elements
;
2316 desc
->num_active_slots
= new_num_elements
;
2324 si_create_bindless_descriptor(struct si_context
*sctx
, uint32_t *desc_list
,
2327 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2328 unsigned desc_slot
, desc_slot_offset
;
2330 /* Find a free slot. */
2331 desc_slot
= si_get_first_free_bindless_slot(sctx
);
2333 /* For simplicity, sampler and image bindless descriptors use fixed
2334 * 16-dword slots for now. Image descriptors only need 8-dword but this
2335 * doesn't really matter because no real apps use image handles.
2337 desc_slot_offset
= desc_slot
* 16;
2339 /* Copy the descriptor into the array. */
2340 memcpy(desc
->list
+ desc_slot_offset
, desc_list
, size
);
2342 /* Re-upload the whole array of bindless descriptors into a new buffer.
2344 if (!si_upload_descriptors(sctx
, desc
))
2347 /* Make sure to re-emit the shader pointers for all stages. */
2348 sctx
->graphics_bindless_pointer_dirty
= true;
2349 sctx
->compute_bindless_pointer_dirty
= true;
2354 static void si_update_bindless_buffer_descriptor(struct si_context
*sctx
,
2356 struct pipe_resource
*resource
,
2360 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2361 struct si_resource
*buf
= si_resource(resource
);
2362 unsigned desc_slot_offset
= desc_slot
* 16;
2363 uint32_t *desc_list
= desc
->list
+ desc_slot_offset
+ 4;
2364 uint64_t old_desc_va
;
2366 assert(resource
->target
== PIPE_BUFFER
);
2368 /* Retrieve the old buffer addr from the descriptor. */
2369 old_desc_va
= si_desc_extract_buffer_address(desc_list
);
2371 if (old_desc_va
!= buf
->gpu_address
+ offset
) {
2372 /* The buffer has been invalidated when the handle wasn't
2373 * resident, update the descriptor and the dirty flag.
2375 si_set_buf_desc_address(buf
, offset
, &desc_list
[0]);
2381 static uint64_t si_create_texture_handle(struct pipe_context
*ctx
,
2382 struct pipe_sampler_view
*view
,
2383 const struct pipe_sampler_state
*state
)
2385 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
2386 struct si_context
*sctx
= (struct si_context
*)ctx
;
2387 struct si_texture_handle
*tex_handle
;
2388 struct si_sampler_state
*sstate
;
2389 uint32_t desc_list
[16];
2392 tex_handle
= CALLOC_STRUCT(si_texture_handle
);
2396 memset(desc_list
, 0, sizeof(desc_list
));
2397 si_init_descriptor_list(&desc_list
[0], 16, 1, null_texture_descriptor
);
2399 sstate
= ctx
->create_sampler_state(ctx
, state
);
2405 si_set_sampler_view_desc(sctx
, sview
, sstate
, &desc_list
[0]);
2406 memcpy(&tex_handle
->sstate
, sstate
, sizeof(*sstate
));
2407 ctx
->delete_sampler_state(ctx
, sstate
);
2409 tex_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2411 if (!tex_handle
->desc_slot
) {
2416 handle
= tex_handle
->desc_slot
;
2418 if (!_mesa_hash_table_insert(sctx
->tex_handles
,
2419 (void *)(uintptr_t)handle
,
2425 pipe_sampler_view_reference(&tex_handle
->view
, view
);
2427 si_resource(sview
->base
.texture
)->texture_handle_allocated
= true;
2432 static void si_delete_texture_handle(struct pipe_context
*ctx
, uint64_t handle
)
2434 struct si_context
*sctx
= (struct si_context
*)ctx
;
2435 struct si_texture_handle
*tex_handle
;
2436 struct hash_entry
*entry
;
2438 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2439 (void *)(uintptr_t)handle
);
2443 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2445 /* Allow this descriptor slot to be re-used. */
2446 util_idalloc_free(&sctx
->bindless_used_slots
, tex_handle
->desc_slot
);
2448 pipe_sampler_view_reference(&tex_handle
->view
, NULL
);
2449 _mesa_hash_table_remove(sctx
->tex_handles
, entry
);
2453 static void si_make_texture_handle_resident(struct pipe_context
*ctx
,
2454 uint64_t handle
, bool resident
)
2456 struct si_context
*sctx
= (struct si_context
*)ctx
;
2457 struct si_texture_handle
*tex_handle
;
2458 struct si_sampler_view
*sview
;
2459 struct hash_entry
*entry
;
2461 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2462 (void *)(uintptr_t)handle
);
2466 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2467 sview
= (struct si_sampler_view
*)tex_handle
->view
;
2470 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2471 struct si_texture
*tex
=
2472 (struct si_texture
*)sview
->base
.texture
;
2474 if (depth_needs_decompression(tex
)) {
2475 util_dynarray_append(
2476 &sctx
->resident_tex_needs_depth_decompress
,
2477 struct si_texture_handle
*,
2481 if (color_needs_decompression(tex
)) {
2482 util_dynarray_append(
2483 &sctx
->resident_tex_needs_color_decompress
,
2484 struct si_texture_handle
*,
2488 if (tex
->dcc_offset
&&
2489 p_atomic_read(&tex
->framebuffers_bound
))
2490 sctx
->need_check_render_feedback
= true;
2492 si_update_bindless_texture_descriptor(sctx
, tex_handle
);
2494 si_update_bindless_buffer_descriptor(sctx
,
2495 tex_handle
->desc_slot
,
2496 sview
->base
.texture
,
2497 sview
->base
.u
.buf
.offset
,
2498 &tex_handle
->desc_dirty
);
2501 /* Re-upload the descriptor if it has been updated while it
2504 if (tex_handle
->desc_dirty
)
2505 sctx
->bindless_descriptors_dirty
= true;
2507 /* Add the texture handle to the per-context list. */
2508 util_dynarray_append(&sctx
->resident_tex_handles
,
2509 struct si_texture_handle
*, tex_handle
);
2511 /* Add the buffers to the current CS in case si_begin_new_cs()
2512 * is not going to be called.
2514 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2516 sview
->is_stencil_sampler
, false);
2518 /* Remove the texture handle from the per-context list. */
2519 util_dynarray_delete_unordered(&sctx
->resident_tex_handles
,
2520 struct si_texture_handle
*,
2523 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2524 util_dynarray_delete_unordered(
2525 &sctx
->resident_tex_needs_depth_decompress
,
2526 struct si_texture_handle
*, tex_handle
);
2528 util_dynarray_delete_unordered(
2529 &sctx
->resident_tex_needs_color_decompress
,
2530 struct si_texture_handle
*, tex_handle
);
2535 static uint64_t si_create_image_handle(struct pipe_context
*ctx
,
2536 const struct pipe_image_view
*view
)
2538 struct si_context
*sctx
= (struct si_context
*)ctx
;
2539 struct si_image_handle
*img_handle
;
2540 uint32_t desc_list
[8];
2543 if (!view
|| !view
->resource
)
2546 img_handle
= CALLOC_STRUCT(si_image_handle
);
2550 memset(desc_list
, 0, sizeof(desc_list
));
2551 si_init_descriptor_list(&desc_list
[0], 8, 1, null_image_descriptor
);
2553 si_set_shader_image_desc(sctx
, view
, false, &desc_list
[0], NULL
);
2555 img_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2557 if (!img_handle
->desc_slot
) {
2562 handle
= img_handle
->desc_slot
;
2564 if (!_mesa_hash_table_insert(sctx
->img_handles
,
2565 (void *)(uintptr_t)handle
,
2571 util_copy_image_view(&img_handle
->view
, view
);
2573 si_resource(view
->resource
)->image_handle_allocated
= true;
2578 static void si_delete_image_handle(struct pipe_context
*ctx
, uint64_t handle
)
2580 struct si_context
*sctx
= (struct si_context
*)ctx
;
2581 struct si_image_handle
*img_handle
;
2582 struct hash_entry
*entry
;
2584 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2585 (void *)(uintptr_t)handle
);
2589 img_handle
= (struct si_image_handle
*)entry
->data
;
2591 util_copy_image_view(&img_handle
->view
, NULL
);
2592 _mesa_hash_table_remove(sctx
->img_handles
, entry
);
2596 static void si_make_image_handle_resident(struct pipe_context
*ctx
,
2597 uint64_t handle
, unsigned access
,
2600 struct si_context
*sctx
= (struct si_context
*)ctx
;
2601 struct si_image_handle
*img_handle
;
2602 struct pipe_image_view
*view
;
2603 struct si_resource
*res
;
2604 struct hash_entry
*entry
;
2606 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2607 (void *)(uintptr_t)handle
);
2611 img_handle
= (struct si_image_handle
*)entry
->data
;
2612 view
= &img_handle
->view
;
2613 res
= si_resource(view
->resource
);
2616 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2617 struct si_texture
*tex
= (struct si_texture
*)res
;
2618 unsigned level
= view
->u
.tex
.level
;
2620 if (color_needs_decompression(tex
)) {
2621 util_dynarray_append(
2622 &sctx
->resident_img_needs_color_decompress
,
2623 struct si_image_handle
*,
2627 if (vi_dcc_enabled(tex
, level
) &&
2628 p_atomic_read(&tex
->framebuffers_bound
))
2629 sctx
->need_check_render_feedback
= true;
2631 si_update_bindless_image_descriptor(sctx
, img_handle
);
2633 si_update_bindless_buffer_descriptor(sctx
,
2634 img_handle
->desc_slot
,
2637 &img_handle
->desc_dirty
);
2640 /* Re-upload the descriptor if it has been updated while it
2643 if (img_handle
->desc_dirty
)
2644 sctx
->bindless_descriptors_dirty
= true;
2646 /* Add the image handle to the per-context list. */
2647 util_dynarray_append(&sctx
->resident_img_handles
,
2648 struct si_image_handle
*, img_handle
);
2650 /* Add the buffers to the current CS in case si_begin_new_cs()
2651 * is not going to be called.
2653 si_sampler_view_add_buffer(sctx
, view
->resource
,
2654 (access
& PIPE_IMAGE_ACCESS_WRITE
) ?
2655 RADEON_USAGE_READWRITE
:
2656 RADEON_USAGE_READ
, false, false);
2658 /* Remove the image handle from the per-context list. */
2659 util_dynarray_delete_unordered(&sctx
->resident_img_handles
,
2660 struct si_image_handle
*,
2663 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2664 util_dynarray_delete_unordered(
2665 &sctx
->resident_img_needs_color_decompress
,
2666 struct si_image_handle
*,
2672 static void si_resident_buffers_add_all_to_bo_list(struct si_context
*sctx
)
2674 unsigned num_resident_tex_handles
, num_resident_img_handles
;
2676 num_resident_tex_handles
= sctx
->resident_tex_handles
.size
/
2677 sizeof(struct si_texture_handle
*);
2678 num_resident_img_handles
= sctx
->resident_img_handles
.size
/
2679 sizeof(struct si_image_handle
*);
2681 /* Add all resident texture handles. */
2682 util_dynarray_foreach(&sctx
->resident_tex_handles
,
2683 struct si_texture_handle
*, tex_handle
) {
2684 struct si_sampler_view
*sview
=
2685 (struct si_sampler_view
*)(*tex_handle
)->view
;
2687 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2689 sview
->is_stencil_sampler
, false);
2692 /* Add all resident image handles. */
2693 util_dynarray_foreach(&sctx
->resident_img_handles
,
2694 struct si_image_handle
*, img_handle
) {
2695 struct pipe_image_view
*view
= &(*img_handle
)->view
;
2697 si_sampler_view_add_buffer(sctx
, view
->resource
,
2698 RADEON_USAGE_READWRITE
,
2702 sctx
->num_resident_handles
+= num_resident_tex_handles
+
2703 num_resident_img_handles
;
2704 assert(sctx
->bo_list_add_all_resident_resources
);
2705 sctx
->bo_list_add_all_resident_resources
= false;
2708 /* INIT/DEINIT/UPLOAD */
2710 void si_init_all_descriptors(struct si_context
*sctx
)
2713 unsigned first_shader
=
2714 sctx
->has_graphics
? 0 : PIPE_SHADER_COMPUTE
;
2716 for (i
= first_shader
; i
< SI_NUM_SHADERS
; i
++) {
2717 bool is_2nd
= sctx
->chip_class
>= GFX9
&&
2718 (i
== PIPE_SHADER_TESS_CTRL
||
2719 i
== PIPE_SHADER_GEOMETRY
);
2720 unsigned num_sampler_slots
= SI_NUM_IMAGES
/ 2 + SI_NUM_SAMPLERS
;
2721 unsigned num_buffer_slots
= SI_NUM_SHADER_BUFFERS
+ SI_NUM_CONST_BUFFERS
;
2723 struct si_descriptors
*desc
;
2726 if (i
== PIPE_SHADER_TESS_CTRL
) {
2727 rel_dw_offset
= (R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
-
2728 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2729 } else { /* PIPE_SHADER_GEOMETRY */
2730 rel_dw_offset
= (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
-
2731 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2734 rel_dw_offset
= SI_SGPR_CONST_AND_SHADER_BUFFERS
;
2736 desc
= si_const_and_shader_buffer_descriptors(sctx
, i
);
2737 si_init_buffer_resources(&sctx
->const_and_shader_buffers
[i
], desc
,
2738 num_buffer_slots
, rel_dw_offset
,
2739 RADEON_PRIO_SHADER_RW_BUFFER
,
2740 RADEON_PRIO_CONST_BUFFER
);
2741 desc
->slot_index_to_bind_directly
= si_get_constbuf_slot(0);
2744 if (i
== PIPE_SHADER_TESS_CTRL
) {
2745 rel_dw_offset
= (R_00B40C_SPI_SHADER_USER_DATA_ADDR_HI_HS
-
2746 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2747 } else { /* PIPE_SHADER_GEOMETRY */
2748 rel_dw_offset
= (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS
-
2749 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2752 rel_dw_offset
= SI_SGPR_SAMPLERS_AND_IMAGES
;
2755 desc
= si_sampler_and_image_descriptors(sctx
, i
);
2756 si_init_descriptors(desc
, rel_dw_offset
, 16, num_sampler_slots
);
2759 for (j
= 0; j
< SI_NUM_IMAGES
; j
++)
2760 memcpy(desc
->list
+ j
* 8, null_image_descriptor
, 8 * 4);
2761 for (; j
< SI_NUM_IMAGES
+ SI_NUM_SAMPLERS
* 2; j
++)
2762 memcpy(desc
->list
+ j
* 8, null_texture_descriptor
, 8 * 4);
2765 si_init_buffer_resources(&sctx
->rw_buffers
,
2766 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
2767 SI_NUM_RW_BUFFERS
, SI_SGPR_RW_BUFFERS
,
2768 /* The second priority is used by
2769 * const buffers in RW buffer slots. */
2770 RADEON_PRIO_SHADER_RINGS
, RADEON_PRIO_CONST_BUFFER
);
2771 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
= SI_NUM_RW_BUFFERS
;
2773 /* Initialize an array of 1024 bindless descriptors, when the limit is
2774 * reached, just make it larger and re-upload the whole array.
2776 si_init_bindless_descriptors(sctx
, &sctx
->bindless_descriptors
,
2777 SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
,
2780 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2782 /* Set pipe_context functions. */
2783 sctx
->b
.bind_sampler_states
= si_bind_sampler_states
;
2784 sctx
->b
.set_shader_images
= si_set_shader_images
;
2785 sctx
->b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
2786 sctx
->b
.set_shader_buffers
= si_set_shader_buffers
;
2787 sctx
->b
.set_sampler_views
= si_set_sampler_views
;
2788 sctx
->b
.create_texture_handle
= si_create_texture_handle
;
2789 sctx
->b
.delete_texture_handle
= si_delete_texture_handle
;
2790 sctx
->b
.make_texture_handle_resident
= si_make_texture_handle_resident
;
2791 sctx
->b
.create_image_handle
= si_create_image_handle
;
2792 sctx
->b
.delete_image_handle
= si_delete_image_handle
;
2793 sctx
->b
.make_image_handle_resident
= si_make_image_handle_resident
;
2795 if (!sctx
->has_graphics
)
2798 sctx
->b
.set_polygon_stipple
= si_set_polygon_stipple
;
2800 /* Shader user data. */
2801 sctx
->atoms
.s
.shader_pointers
.emit
= si_emit_graphics_shader_pointers
;
2803 /* Set default and immutable mappings. */
2804 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2806 if (sctx
->chip_class
>= GFX9
) {
2807 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2808 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2809 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2810 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2812 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2813 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2814 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2815 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2817 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2820 static bool si_upload_shader_descriptors(struct si_context
*sctx
, unsigned mask
)
2822 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2824 /* Assume nothing will go wrong: */
2825 sctx
->shader_pointers_dirty
|= dirty
;
2828 unsigned i
= u_bit_scan(&dirty
);
2830 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
]))
2834 sctx
->descriptors_dirty
&= ~mask
;
2836 si_upload_bindless_descriptors(sctx
);
2841 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
2843 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
2844 return si_upload_shader_descriptors(sctx
, mask
);
2847 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
2849 /* Does not update rw_buffers as that is not needed for compute shaders
2850 * and the input buffer is using the same SGPR's anyway.
2852 const unsigned mask
= u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
,
2853 SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
2854 return si_upload_shader_descriptors(sctx
, mask
);
2857 void si_release_all_descriptors(struct si_context
*sctx
)
2861 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2862 si_release_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2863 si_const_and_shader_buffer_descriptors(sctx
, i
));
2864 si_release_sampler_views(&sctx
->samplers
[i
]);
2865 si_release_image_views(&sctx
->images
[i
]);
2867 si_release_buffer_resources(&sctx
->rw_buffers
,
2868 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2869 for (i
= 0; i
< SI_NUM_VERTEX_BUFFERS
; i
++)
2870 pipe_vertex_buffer_unreference(&sctx
->vertex_buffer
[i
]);
2872 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2873 si_release_descriptors(&sctx
->descriptors
[i
]);
2875 si_resource_reference(&sctx
->vb_descriptors_buffer
, NULL
);
2876 sctx
->vb_descriptors_gpu_list
= NULL
; /* points into a mapped buffer */
2878 si_release_bindless_descriptors(sctx
);
2881 void si_gfx_resources_add_all_to_bo_list(struct si_context
*sctx
)
2883 for (unsigned i
= 0; i
< SI_NUM_GRAPHICS_SHADERS
; i
++) {
2884 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2885 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
]);
2886 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
2888 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2889 si_vertex_buffers_begin_new_cs(sctx
);
2891 if (sctx
->bo_list_add_all_resident_resources
)
2892 si_resident_buffers_add_all_to_bo_list(sctx
);
2894 assert(sctx
->bo_list_add_all_gfx_resources
);
2895 sctx
->bo_list_add_all_gfx_resources
= false;
2898 void si_compute_resources_add_all_to_bo_list(struct si_context
*sctx
)
2900 unsigned sh
= PIPE_SHADER_COMPUTE
;
2902 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[sh
]);
2903 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[sh
]);
2904 si_image_views_begin_new_cs(sctx
, &sctx
->images
[sh
]);
2905 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2907 if (sctx
->bo_list_add_all_resident_resources
)
2908 si_resident_buffers_add_all_to_bo_list(sctx
);
2910 assert(sctx
->bo_list_add_all_compute_resources
);
2911 sctx
->bo_list_add_all_compute_resources
= false;
2914 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
2916 for (unsigned i
= 0; i
< SI_NUM_DESCS
; ++i
)
2917 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
2918 si_descriptors_begin_new_cs(sctx
, &sctx
->bindless_descriptors
);
2920 si_shader_pointers_begin_new_cs(sctx
);
2922 sctx
->bo_list_add_all_resident_resources
= true;
2923 sctx
->bo_list_add_all_gfx_resources
= true;
2924 sctx
->bo_list_add_all_compute_resources
= true;
2927 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
2928 uint64_t new_active_mask
)
2930 struct si_descriptors
*desc
= &sctx
->descriptors
[desc_idx
];
2932 /* Ignore no-op updates and updates that disable all slots. */
2933 if (!new_active_mask
||
2934 new_active_mask
== u_bit_consecutive64(desc
->first_active_slot
,
2935 desc
->num_active_slots
))
2939 u_bit_scan_consecutive_range64(&new_active_mask
, &first
, &count
);
2940 assert(new_active_mask
== 0);
2942 /* Upload/dump descriptors if slots are being enabled. */
2943 if (first
< desc
->first_active_slot
||
2944 first
+ count
> desc
->first_active_slot
+ desc
->num_active_slots
)
2945 sctx
->descriptors_dirty
|= 1u << desc_idx
;
2947 desc
->first_active_slot
= first
;
2948 desc
->num_active_slots
= count
;
2951 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
2952 struct si_shader_selector
*sel
)
2957 si_set_active_descriptors(sctx
,
2958 si_const_and_shader_buffer_descriptors_idx(sel
->type
),
2959 sel
->active_const_and_shader_buffers
);
2960 si_set_active_descriptors(sctx
,
2961 si_sampler_and_image_descriptors_idx(sel
->type
),
2962 sel
->active_samplers_and_images
);