2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Marek Olšák <marek.olsak@amd.com>
27 /* Resource binding slots and sampler states (each described with 8 or
28 * 4 dwords) are stored in lists in memory which is accessed by shaders
29 * using scalar load instructions.
31 * This file is responsible for managing such lists. It keeps a copy of all
32 * descriptors in CPU memory and re-uploads a whole list if some slots have
35 * This code is also reponsible for updating shader pointers to those lists.
37 * Note that CP DMA can't be used for updating the lists, because a GPU hang
38 * could leave the list in a mid-IB state and the next IB would get wrong
39 * descriptors and the whole context would be unusable at that point.
40 * (Note: The register shadowing can't be used due to the same reason)
42 * Also, uploading descriptors to newly allocated memory doesn't require
46 * Possible scenarios for one 16 dword image+sampler slot:
48 * | Image | w/ FMASK | Buffer | NULL
49 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
50 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
51 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
52 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
54 * FMASK implies MSAA, therefore no sampler state.
55 * Sampler states are never unbound except when FMASK is bound.
58 #include "radeon/r600_cs.h"
63 #include "util/hash_table.h"
64 #include "util/u_idalloc.h"
65 #include "util/u_format.h"
66 #include "util/u_memory.h"
67 #include "util/u_upload_mgr.h"
70 /* NULL image and buffer descriptor for textures (alpha = 1) and images
73 * For images, all fields must be zero except for the swizzle, which
74 * supports arbitrary combinations of 0s and 1s. The texture type must be
75 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
77 * For buffers, all fields must be zero. If they are not, the hw hangs.
79 * This is the only reason why the buffer descriptor must be in words [4:7].
81 static uint32_t null_texture_descriptor
[8] = {
85 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) |
86 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
87 /* the rest must contain zeros, which is also used by the buffer
91 static uint32_t null_image_descriptor
[8] = {
95 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
96 /* the rest must contain zeros, which is also used by the buffer
100 static uint64_t si_desc_extract_buffer_address(uint32_t *desc
)
102 return desc
[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
105 static void si_init_descriptor_list(uint32_t *desc_list
,
106 unsigned element_dw_size
,
107 unsigned num_elements
,
108 const uint32_t *null_descriptor
)
112 /* Initialize the array to NULL descriptors if the element size is 8. */
113 if (null_descriptor
) {
114 assert(element_dw_size
% 8 == 0);
115 for (i
= 0; i
< num_elements
* element_dw_size
/ 8; i
++)
116 memcpy(desc_list
+ i
* 8, null_descriptor
, 8 * 4);
120 static void si_init_descriptors(struct si_descriptors
*desc
,
121 unsigned shader_userdata_index
,
122 unsigned element_dw_size
,
123 unsigned num_elements
)
125 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
126 desc
->element_dw_size
= element_dw_size
;
127 desc
->num_elements
= num_elements
;
128 desc
->shader_userdata_offset
= shader_userdata_index
* 4;
129 desc
->slot_index_to_bind_directly
= -1;
132 static void si_release_descriptors(struct si_descriptors
*desc
)
134 r600_resource_reference(&desc
->buffer
, NULL
);
138 static bool si_upload_descriptors(struct si_context
*sctx
,
139 struct si_descriptors
*desc
)
141 unsigned slot_size
= desc
->element_dw_size
* 4;
142 unsigned first_slot_offset
= desc
->first_active_slot
* slot_size
;
143 unsigned upload_size
= desc
->num_active_slots
* slot_size
;
145 /* Skip the upload if no shader is using the descriptors. dirty_mask
146 * will stay dirty and the descriptors will be uploaded when there is
147 * a shader using them.
152 /* If there is just one active descriptor, bind it directly. */
153 if ((int)desc
->first_active_slot
== desc
->slot_index_to_bind_directly
&&
154 desc
->num_active_slots
== 1) {
155 uint32_t *descriptor
= &desc
->list
[desc
->slot_index_to_bind_directly
*
156 desc
->element_dw_size
];
158 /* The buffer is already in the buffer list. */
159 r600_resource_reference(&desc
->buffer
, NULL
);
160 desc
->gpu_list
= NULL
;
161 desc
->gpu_address
= si_desc_extract_buffer_address(descriptor
);
162 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
168 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, upload_size
,
169 si_optimal_tcc_alignment(sctx
, upload_size
),
170 (unsigned*)&buffer_offset
,
171 (struct pipe_resource
**)&desc
->buffer
,
174 desc
->gpu_address
= 0;
175 return false; /* skip the draw call */
178 util_memcpy_cpu_to_le32(ptr
, (char*)desc
->list
+ first_slot_offset
,
180 desc
->gpu_list
= ptr
- first_slot_offset
/ 4;
182 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
183 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
185 /* The shader pointer should point to slot 0. */
186 buffer_offset
-= first_slot_offset
;
187 desc
->gpu_address
= desc
->buffer
->gpu_address
+ buffer_offset
;
189 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
194 si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
199 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
200 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
206 si_sampler_and_image_descriptors_idx(unsigned shader
)
208 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
209 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
;
212 static struct si_descriptors
*
213 si_sampler_and_image_descriptors(struct si_context
*sctx
, unsigned shader
)
215 return &sctx
->descriptors
[si_sampler_and_image_descriptors_idx(shader
)];
218 static void si_release_sampler_views(struct si_samplers
*samplers
)
222 for (i
= 0; i
< ARRAY_SIZE(samplers
->views
); i
++) {
223 pipe_sampler_view_reference(&samplers
->views
[i
], NULL
);
227 static void si_sampler_view_add_buffer(struct si_context
*sctx
,
228 struct pipe_resource
*resource
,
229 enum radeon_bo_usage usage
,
230 bool is_stencil_sampler
,
233 struct r600_resource
*rres
;
234 struct r600_texture
*rtex
;
235 enum radeon_bo_priority priority
;
240 if (resource
->target
!= PIPE_BUFFER
) {
241 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
243 if (tex
->is_depth
&& !r600_can_sample_zs(tex
, is_stencil_sampler
))
244 resource
= &tex
->flushed_depth_texture
->resource
.b
.b
;
247 rres
= (struct r600_resource
*)resource
;
248 priority
= r600_get_sampler_view_priority(rres
);
250 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
251 rres
, usage
, priority
,
254 if (resource
->target
== PIPE_BUFFER
)
257 /* Now add separate DCC or HTILE. */
258 rtex
= (struct r600_texture
*)resource
;
259 if (rtex
->dcc_separate_buffer
) {
260 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
261 rtex
->dcc_separate_buffer
, usage
,
262 RADEON_PRIO_DCC
, check_mem
);
266 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
,
267 struct si_samplers
*samplers
)
269 unsigned mask
= samplers
->enabled_mask
;
271 /* Add buffers to the CS. */
273 int i
= u_bit_scan(&mask
);
274 struct si_sampler_view
*sview
= (struct si_sampler_view
*)samplers
->views
[i
];
276 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
278 sview
->is_stencil_sampler
, false);
282 /* Set buffer descriptor fields that can be changed by reallocations. */
283 static void si_set_buf_desc_address(struct r600_resource
*buf
,
284 uint64_t offset
, uint32_t *state
)
286 uint64_t va
= buf
->gpu_address
+ offset
;
289 state
[1] &= C_008F04_BASE_ADDRESS_HI
;
290 state
[1] |= S_008F04_BASE_ADDRESS_HI(va
>> 32);
293 /* Set texture descriptor fields that can be changed by reallocations.
296 * \param base_level_info information of the level of BASE_ADDRESS
297 * \param base_level the level of BASE_ADDRESS
298 * \param first_level pipe_sampler_view.u.tex.first_level
299 * \param block_width util_format_get_blockwidth()
300 * \param is_stencil select between separate Z & Stencil
301 * \param state descriptor to update
303 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
304 struct r600_texture
*tex
,
305 const struct legacy_surf_level
*base_level_info
,
306 unsigned base_level
, unsigned first_level
,
307 unsigned block_width
, bool is_stencil
,
310 uint64_t va
, meta_va
= 0;
312 if (tex
->is_depth
&& !r600_can_sample_zs(tex
, is_stencil
)) {
313 tex
= tex
->flushed_depth_texture
;
317 va
= tex
->resource
.gpu_address
;
319 if (sscreen
->b
.chip_class
>= GFX9
) {
320 /* Only stencil_offset needs to be added here. */
322 va
+= tex
->surface
.u
.gfx9
.stencil_offset
;
324 va
+= tex
->surface
.u
.gfx9
.surf_offset
;
326 va
+= base_level_info
->offset
;
330 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
331 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
333 /* Only macrotiled modes can set tile swizzle.
334 * GFX9 doesn't use (legacy) base_level_info.
336 if (sscreen
->b
.chip_class
>= GFX9
||
337 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
338 state
[0] |= tex
->surface
.tile_swizzle
;
340 if (sscreen
->b
.chip_class
>= VI
) {
341 state
[6] &= C_008F28_COMPRESSION_EN
;
344 if (vi_dcc_enabled(tex
, first_level
)) {
345 meta_va
= (!tex
->dcc_separate_buffer
? tex
->resource
.gpu_address
: 0) +
348 if (sscreen
->b
.chip_class
== VI
) {
349 meta_va
+= base_level_info
->dcc_offset
;
350 assert(base_level_info
->mode
== RADEON_SURF_MODE_2D
);
353 meta_va
|= (uint32_t)tex
->surface
.tile_swizzle
<< 8;
354 } else if (vi_tc_compat_htile_enabled(tex
, first_level
)) {
355 meta_va
= tex
->resource
.gpu_address
+ tex
->htile_offset
;
359 state
[6] |= S_008F28_COMPRESSION_EN(1);
360 state
[7] = meta_va
>> 8;
364 if (sscreen
->b
.chip_class
>= GFX9
) {
365 state
[3] &= C_008F1C_SW_MODE
;
366 state
[4] &= C_008F20_PITCH_GFX9
;
369 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
370 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.stencil
.epitch
);
372 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
373 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.surf
.epitch
);
376 state
[5] &= C_008F24_META_DATA_ADDRESS
&
377 C_008F24_META_PIPE_ALIGNED
&
378 C_008F24_META_RB_ALIGNED
;
380 struct gfx9_surf_meta_flags meta
;
383 meta
= tex
->surface
.u
.gfx9
.dcc
;
385 meta
= tex
->surface
.u
.gfx9
.htile
;
387 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
388 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
389 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
393 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
394 unsigned index
= si_tile_mode_index(tex
, base_level
, is_stencil
);
396 state
[3] &= C_008F1C_TILING_INDEX
;
397 state
[3] |= S_008F1C_TILING_INDEX(index
);
398 state
[4] &= C_008F20_PITCH_GFX6
;
399 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
403 static void si_set_sampler_state_desc(struct si_sampler_state
*sstate
,
404 struct si_sampler_view
*sview
,
405 struct r600_texture
*tex
,
408 if (sview
&& sview
->is_integer
)
409 memcpy(desc
, sstate
->integer_val
, 4*4);
410 else if (tex
&& tex
->upgraded_depth
&&
411 (!sview
|| !sview
->is_stencil_sampler
))
412 memcpy(desc
, sstate
->upgraded_depth_val
, 4*4);
414 memcpy(desc
, sstate
->val
, 4*4);
417 static void si_set_sampler_view_desc(struct si_context
*sctx
,
418 struct si_sampler_view
*sview
,
419 struct si_sampler_state
*sstate
,
422 struct pipe_sampler_view
*view
= &sview
->base
;
423 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
424 bool is_buffer
= rtex
->resource
.b
.b
.target
== PIPE_BUFFER
;
426 if (unlikely(!is_buffer
&& sview
->dcc_incompatible
)) {
427 if (vi_dcc_enabled(rtex
, view
->u
.tex
.first_level
))
428 if (!si_texture_disable_dcc(&sctx
->b
, rtex
))
429 sctx
->b
.decompress_dcc(&sctx
->b
.b
, rtex
);
431 sview
->dcc_incompatible
= false;
434 assert(rtex
); /* views with texture == NULL aren't supported */
435 memcpy(desc
, sview
->state
, 8*4);
438 si_set_buf_desc_address(&rtex
->resource
,
439 sview
->base
.u
.buf
.offset
,
442 bool is_separate_stencil
= rtex
->db_compatible
&&
443 sview
->is_stencil_sampler
;
445 si_set_mutable_tex_desc_fields(sctx
->screen
, rtex
,
446 sview
->base_level_info
,
448 sview
->base
.u
.tex
.first_level
,
454 if (!is_buffer
&& rtex
->fmask
.size
) {
455 memcpy(desc
+ 8, sview
->fmask_state
, 8*4);
457 /* Disable FMASK and bind sampler state in [12:15]. */
458 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
461 si_set_sampler_state_desc(sstate
, sview
,
462 is_buffer
? NULL
: rtex
,
467 static bool color_needs_decompression(struct r600_texture
*rtex
)
469 return rtex
->fmask
.size
||
470 (rtex
->dirty_level_mask
&&
471 (rtex
->cmask
.size
|| rtex
->dcc_offset
));
474 static bool depth_needs_decompression(struct r600_texture
*rtex
)
476 /* If the depth/stencil texture is TC-compatible, no decompression
477 * will be done. The decompression function will only flush DB caches
478 * to make it coherent with shaders. That's necessary because the driver
479 * doesn't flush DB caches in any other case.
481 return rtex
->db_compatible
;
484 static void si_set_sampler_view(struct si_context
*sctx
,
486 unsigned slot
, struct pipe_sampler_view
*view
,
487 bool disallow_early_out
)
489 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
490 struct si_sampler_view
*rview
= (struct si_sampler_view
*)view
;
491 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
492 unsigned desc_slot
= si_get_sampler_slot(slot
);
493 uint32_t *desc
= descs
->list
+ desc_slot
* 16;
495 if (samplers
->views
[slot
] == view
&& !disallow_early_out
)
499 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
501 si_set_sampler_view_desc(sctx
, rview
,
502 samplers
->sampler_states
[slot
], desc
);
504 if (rtex
->resource
.b
.b
.target
== PIPE_BUFFER
) {
505 rtex
->resource
.bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
506 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
507 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
509 if (depth_needs_decompression(rtex
)) {
510 samplers
->needs_depth_decompress_mask
|= 1u << slot
;
512 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
514 if (color_needs_decompression(rtex
)) {
515 samplers
->needs_color_decompress_mask
|= 1u << slot
;
517 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
520 if (rtex
->dcc_offset
&&
521 p_atomic_read(&rtex
->framebuffers_bound
))
522 sctx
->need_check_render_feedback
= true;
525 pipe_sampler_view_reference(&samplers
->views
[slot
], view
);
526 samplers
->enabled_mask
|= 1u << slot
;
528 /* Since this can flush, it must be done after enabled_mask is
530 si_sampler_view_add_buffer(sctx
, view
->texture
,
532 rview
->is_stencil_sampler
, true);
534 pipe_sampler_view_reference(&samplers
->views
[slot
], NULL
);
535 memcpy(desc
, null_texture_descriptor
, 8*4);
536 /* Only clear the lower dwords of FMASK. */
537 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
538 /* Re-set the sampler state if we are transitioning from FMASK. */
539 if (samplers
->sampler_states
[slot
])
540 si_set_sampler_state_desc(samplers
->sampler_states
[slot
], NULL
, NULL
,
543 samplers
->enabled_mask
&= ~(1u << slot
);
544 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
545 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
548 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
551 static void si_update_shader_needs_decompress_mask(struct si_context
*sctx
,
554 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
555 unsigned shader_bit
= 1 << shader
;
557 if (samplers
->needs_depth_decompress_mask
||
558 samplers
->needs_color_decompress_mask
||
559 sctx
->images
[shader
].needs_color_decompress_mask
)
560 sctx
->shader_needs_decompress_mask
|= shader_bit
;
562 sctx
->shader_needs_decompress_mask
&= ~shader_bit
;
565 static void si_set_sampler_views(struct pipe_context
*ctx
,
566 enum pipe_shader_type shader
, unsigned start
,
568 struct pipe_sampler_view
**views
)
570 struct si_context
*sctx
= (struct si_context
*)ctx
;
573 if (!count
|| shader
>= SI_NUM_SHADERS
)
577 for (i
= 0; i
< count
; i
++)
578 si_set_sampler_view(sctx
, shader
, start
+ i
, views
[i
], false);
580 for (i
= 0; i
< count
; i
++)
581 si_set_sampler_view(sctx
, shader
, start
+ i
, NULL
, false);
584 si_update_shader_needs_decompress_mask(sctx
, shader
);
588 si_samplers_update_needs_color_decompress_mask(struct si_samplers
*samplers
)
590 unsigned mask
= samplers
->enabled_mask
;
593 int i
= u_bit_scan(&mask
);
594 struct pipe_resource
*res
= samplers
->views
[i
]->texture
;
596 if (res
&& res
->target
!= PIPE_BUFFER
) {
597 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
599 if (color_needs_decompression(rtex
)) {
600 samplers
->needs_color_decompress_mask
|= 1u << i
;
602 samplers
->needs_color_decompress_mask
&= ~(1u << i
);
611 si_release_image_views(struct si_images
*images
)
615 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
616 struct pipe_image_view
*view
= &images
->views
[i
];
618 pipe_resource_reference(&view
->resource
, NULL
);
623 si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images
*images
)
625 uint mask
= images
->enabled_mask
;
627 /* Add buffers to the CS. */
629 int i
= u_bit_scan(&mask
);
630 struct pipe_image_view
*view
= &images
->views
[i
];
632 assert(view
->resource
);
634 si_sampler_view_add_buffer(sctx
, view
->resource
,
635 RADEON_USAGE_READWRITE
, false, false);
640 si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
642 struct si_images
*images
= &ctx
->images
[shader
];
644 if (images
->enabled_mask
& (1u << slot
)) {
645 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
646 unsigned desc_slot
= si_get_image_slot(slot
);
648 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
649 images
->needs_color_decompress_mask
&= ~(1 << slot
);
651 memcpy(descs
->list
+ desc_slot
*8, null_image_descriptor
, 8*4);
652 images
->enabled_mask
&= ~(1u << slot
);
653 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
658 si_mark_image_range_valid(const struct pipe_image_view
*view
)
660 struct r600_resource
*res
= (struct r600_resource
*)view
->resource
;
662 assert(res
&& res
->b
.b
.target
== PIPE_BUFFER
);
664 util_range_add(&res
->valid_buffer_range
,
666 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
669 static void si_set_shader_image_desc(struct si_context
*ctx
,
670 const struct pipe_image_view
*view
,
671 bool skip_decompress
,
674 struct si_screen
*screen
= ctx
->screen
;
675 struct r600_resource
*res
;
677 res
= (struct r600_resource
*)view
->resource
;
679 if (res
->b
.b
.target
== PIPE_BUFFER
) {
680 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
681 si_mark_image_range_valid(view
);
683 si_make_buffer_descriptor(screen
, res
,
686 view
->u
.buf
.size
, desc
);
687 si_set_buf_desc_address(res
, view
->u
.buf
.offset
, desc
+ 4);
689 static const unsigned char swizzle
[4] = { 0, 1, 2, 3 };
690 struct r600_texture
*tex
= (struct r600_texture
*)res
;
691 unsigned level
= view
->u
.tex
.level
;
692 unsigned width
, height
, depth
, hw_level
;
693 bool uses_dcc
= vi_dcc_enabled(tex
, level
);
695 assert(!tex
->is_depth
);
696 assert(tex
->fmask
.size
== 0);
698 if (uses_dcc
&& !skip_decompress
&&
699 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
||
700 !vi_dcc_formats_compatible(res
->b
.b
.format
, view
->format
))) {
701 /* If DCC can't be disabled, at least decompress it.
702 * The decompression is relatively cheap if the surface
703 * has been decompressed already.
705 if (!si_texture_disable_dcc(&ctx
->b
, tex
))
706 ctx
->b
.decompress_dcc(&ctx
->b
.b
, tex
);
709 if (ctx
->b
.chip_class
>= GFX9
) {
710 /* Always set the base address. The swizzle modes don't
711 * allow setting mipmap level offsets as the base.
713 width
= res
->b
.b
.width0
;
714 height
= res
->b
.b
.height0
;
715 depth
= res
->b
.b
.depth0
;
718 /* Always force the base level to the selected level.
720 * This is required for 3D textures, where otherwise
721 * selecting a single slice for non-layered bindings
722 * fails. It doesn't hurt the other targets.
724 width
= u_minify(res
->b
.b
.width0
, level
);
725 height
= u_minify(res
->b
.b
.height0
, level
);
726 depth
= u_minify(res
->b
.b
.depth0
, level
);
730 si_make_texture_descriptor(screen
, tex
,
731 false, res
->b
.b
.target
,
732 view
->format
, swizzle
,
734 view
->u
.tex
.first_layer
,
735 view
->u
.tex
.last_layer
,
736 width
, height
, depth
,
738 si_set_mutable_tex_desc_fields(screen
, tex
,
739 &tex
->surface
.u
.legacy
.level
[level
],
741 util_format_get_blockwidth(view
->format
),
746 static void si_set_shader_image(struct si_context
*ctx
,
748 unsigned slot
, const struct pipe_image_view
*view
,
749 bool skip_decompress
)
751 struct si_images
*images
= &ctx
->images
[shader
];
752 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
753 struct r600_resource
*res
;
754 unsigned desc_slot
= si_get_image_slot(slot
);
755 uint32_t *desc
= descs
->list
+ desc_slot
* 8;
757 if (!view
|| !view
->resource
) {
758 si_disable_shader_image(ctx
, shader
, slot
);
762 res
= (struct r600_resource
*)view
->resource
;
764 if (&images
->views
[slot
] != view
)
765 util_copy_image_view(&images
->views
[slot
], view
);
767 si_set_shader_image_desc(ctx
, view
, skip_decompress
, desc
);
769 if (res
->b
.b
.target
== PIPE_BUFFER
) {
770 images
->needs_color_decompress_mask
&= ~(1 << slot
);
771 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
773 struct r600_texture
*tex
= (struct r600_texture
*)res
;
774 unsigned level
= view
->u
.tex
.level
;
776 if (color_needs_decompression(tex
)) {
777 images
->needs_color_decompress_mask
|= 1 << slot
;
779 images
->needs_color_decompress_mask
&= ~(1 << slot
);
782 if (vi_dcc_enabled(tex
, level
) &&
783 p_atomic_read(&tex
->framebuffers_bound
))
784 ctx
->need_check_render_feedback
= true;
787 images
->enabled_mask
|= 1u << slot
;
788 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
790 /* Since this can flush, it must be done after enabled_mask is updated. */
791 si_sampler_view_add_buffer(ctx
, &res
->b
.b
,
792 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
) ?
793 RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
,
798 si_set_shader_images(struct pipe_context
*pipe
,
799 enum pipe_shader_type shader
,
800 unsigned start_slot
, unsigned count
,
801 const struct pipe_image_view
*views
)
803 struct si_context
*ctx
= (struct si_context
*)pipe
;
806 assert(shader
< SI_NUM_SHADERS
);
811 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
814 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
815 si_set_shader_image(ctx
, shader
, slot
, &views
[i
], false);
817 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
818 si_set_shader_image(ctx
, shader
, slot
, NULL
, false);
821 si_update_shader_needs_decompress_mask(ctx
, shader
);
825 si_images_update_needs_color_decompress_mask(struct si_images
*images
)
827 unsigned mask
= images
->enabled_mask
;
830 int i
= u_bit_scan(&mask
);
831 struct pipe_resource
*res
= images
->views
[i
].resource
;
833 if (res
&& res
->target
!= PIPE_BUFFER
) {
834 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
836 if (color_needs_decompression(rtex
)) {
837 images
->needs_color_decompress_mask
|= 1 << i
;
839 images
->needs_color_decompress_mask
&= ~(1 << i
);
847 static void si_bind_sampler_states(struct pipe_context
*ctx
,
848 enum pipe_shader_type shader
,
849 unsigned start
, unsigned count
, void **states
)
851 struct si_context
*sctx
= (struct si_context
*)ctx
;
852 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
853 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, shader
);
854 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
857 if (!count
|| shader
>= SI_NUM_SHADERS
)
860 for (i
= 0; i
< count
; i
++) {
861 unsigned slot
= start
+ i
;
862 unsigned desc_slot
= si_get_sampler_slot(slot
);
865 sstates
[i
] == samplers
->sampler_states
[slot
])
869 assert(sstates
[i
]->magic
== SI_SAMPLER_STATE_MAGIC
);
871 samplers
->sampler_states
[slot
] = sstates
[i
];
873 /* If FMASK is bound, don't overwrite it.
874 * The sampler state will be set after FMASK is unbound.
876 struct si_sampler_view
*sview
=
877 (struct si_sampler_view
*)samplers
->views
[slot
];
879 struct r600_texture
*tex
= NULL
;
881 if (sview
&& sview
->base
.texture
&&
882 sview
->base
.texture
->target
!= PIPE_BUFFER
)
883 tex
= (struct r600_texture
*)sview
->base
.texture
;
885 if (tex
&& tex
->fmask
.size
)
888 si_set_sampler_state_desc(sstates
[i
], sview
, tex
,
889 desc
->list
+ desc_slot
* 16 + 12);
891 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
895 /* BUFFER RESOURCES */
897 static void si_init_buffer_resources(struct si_buffer_resources
*buffers
,
898 struct si_descriptors
*descs
,
899 unsigned num_buffers
,
900 unsigned shader_userdata_index
,
901 enum radeon_bo_usage shader_usage
,
902 enum radeon_bo_usage shader_usage_constbuf
,
903 enum radeon_bo_priority priority
,
904 enum radeon_bo_priority priority_constbuf
)
906 buffers
->shader_usage
= shader_usage
;
907 buffers
->shader_usage_constbuf
= shader_usage_constbuf
;
908 buffers
->priority
= priority
;
909 buffers
->priority_constbuf
= priority_constbuf
;
910 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
912 si_init_descriptors(descs
, shader_userdata_index
, 4, num_buffers
);
915 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
916 struct si_descriptors
*descs
)
920 for (i
= 0; i
< descs
->num_elements
; i
++) {
921 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
924 FREE(buffers
->buffers
);
927 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
928 struct si_buffer_resources
*buffers
)
930 unsigned mask
= buffers
->enabled_mask
;
932 /* Add buffers to the CS. */
934 int i
= u_bit_scan(&mask
);
936 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
937 r600_resource(buffers
->buffers
[i
]),
938 i
< SI_NUM_SHADER_BUFFERS
? buffers
->shader_usage
:
939 buffers
->shader_usage_constbuf
,
940 i
< SI_NUM_SHADER_BUFFERS
? buffers
->priority
:
941 buffers
->priority_constbuf
);
945 static void si_get_buffer_from_descriptors(struct si_buffer_resources
*buffers
,
946 struct si_descriptors
*descs
,
947 unsigned idx
, struct pipe_resource
**buf
,
948 unsigned *offset
, unsigned *size
)
950 pipe_resource_reference(buf
, buffers
->buffers
[idx
]);
952 struct r600_resource
*res
= r600_resource(*buf
);
953 const uint32_t *desc
= descs
->list
+ idx
* 4;
958 assert(G_008F04_STRIDE(desc
[1]) == 0);
959 va
= ((uint64_t)desc
[1] << 32) | desc
[0];
961 assert(va
>= res
->gpu_address
&& va
+ *size
<= res
->gpu_address
+ res
->bo_size
);
962 *offset
= va
- res
->gpu_address
;
968 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
970 struct si_descriptors
*desc
= &sctx
->vertex_buffers
;
971 int count
= sctx
->vertex_elements
? sctx
->vertex_elements
->count
: 0;
974 for (i
= 0; i
< count
; i
++) {
975 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
977 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
979 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
982 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
983 (struct r600_resource
*)sctx
->vertex_buffer
[vb
].buffer
.resource
,
984 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
989 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
990 desc
->buffer
, RADEON_USAGE_READ
,
991 RADEON_PRIO_DESCRIPTORS
);
994 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
996 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
997 struct si_descriptors
*desc
= &sctx
->vertex_buffers
;
999 unsigned desc_list_byte_size
;
1000 unsigned first_vb_use_mask
;
1004 if (!sctx
->vertex_buffers_dirty
|| !velems
)
1007 count
= velems
->count
;
1012 desc_list_byte_size
= velems
->desc_list_byte_size
;
1013 first_vb_use_mask
= velems
->first_vb_use_mask
;
1015 /* Vertex buffer descriptors are the only ones which are uploaded
1016 * directly through a staging buffer and don't go through
1017 * the fine-grained upload path.
1019 unsigned buffer_offset
= 0;
1020 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0,
1021 desc_list_byte_size
,
1022 si_optimal_tcc_alignment(sctx
, desc_list_byte_size
),
1024 (struct pipe_resource
**)&desc
->buffer
, (void**)&ptr
);
1025 if (!desc
->buffer
) {
1026 desc
->gpu_address
= 0;
1030 desc
->gpu_address
= desc
->buffer
->gpu_address
+ buffer_offset
;
1032 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1033 desc
->buffer
, RADEON_USAGE_READ
,
1034 RADEON_PRIO_DESCRIPTORS
);
1036 assert(count
<= SI_MAX_ATTRIBS
);
1038 for (i
= 0; i
< count
; i
++) {
1039 struct pipe_vertex_buffer
*vb
;
1040 struct r600_resource
*rbuffer
;
1042 unsigned vbo_index
= velems
->vertex_buffer_index
[i
];
1043 uint32_t *desc
= &ptr
[i
*4];
1045 vb
= &sctx
->vertex_buffer
[vbo_index
];
1046 rbuffer
= (struct r600_resource
*)vb
->buffer
.resource
;
1048 memset(desc
, 0, 16);
1052 offset
= vb
->buffer_offset
+ velems
->src_offset
[i
];
1053 va
= rbuffer
->gpu_address
+ offset
;
1055 /* Fill in T# buffer resource description */
1057 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1058 S_008F04_STRIDE(vb
->stride
);
1060 if (sctx
->b
.chip_class
!= VI
&& vb
->stride
) {
1061 /* Round up by rounding down and adding 1 */
1062 desc
[2] = (vb
->buffer
.resource
->width0
- offset
-
1063 velems
->format_size
[i
]) /
1066 desc
[2] = vb
->buffer
.resource
->width0
- offset
;
1069 desc
[3] = velems
->rsrc_word3
[i
];
1071 if (first_vb_use_mask
& (1 << i
)) {
1072 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1073 (struct r600_resource
*)vb
->buffer
.resource
,
1074 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1078 /* Don't flush the const cache. It would have a very negative effect
1079 * on performance (confirmed by testing). New descriptors are always
1080 * uploaded to a fresh new buffer, so I don't think flushing the const
1081 * cache is needed. */
1082 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1083 sctx
->vertex_buffers_dirty
= false;
1084 sctx
->vertex_buffer_pointer_dirty
= true;
1085 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VBO_DESCRIPTORS
;
1090 /* CONSTANT BUFFERS */
1093 si_const_and_shader_buffer_descriptors_idx(unsigned shader
)
1095 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
1096 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
;
1099 static struct si_descriptors
*
1100 si_const_and_shader_buffer_descriptors(struct si_context
*sctx
, unsigned shader
)
1102 return &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(shader
)];
1105 void si_upload_const_buffer(struct si_context
*sctx
, struct r600_resource
**rbuffer
,
1106 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
)
1110 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, size
,
1111 si_optimal_tcc_alignment(sctx
, size
),
1113 (struct pipe_resource
**)rbuffer
, &tmp
);
1115 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
1118 static void si_set_constant_buffer(struct si_context
*sctx
,
1119 struct si_buffer_resources
*buffers
,
1120 unsigned descriptors_idx
,
1121 uint slot
, const struct pipe_constant_buffer
*input
)
1123 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1124 assert(slot
< descs
->num_elements
);
1125 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1127 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1128 * with a NULL buffer). We need to use a dummy buffer instead. */
1129 if (sctx
->b
.chip_class
== CIK
&&
1130 (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
1131 input
= &sctx
->null_const_buf
;
1133 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1134 struct pipe_resource
*buffer
= NULL
;
1137 /* Upload the user buffer if needed. */
1138 if (input
->user_buffer
) {
1139 unsigned buffer_offset
;
1141 si_upload_const_buffer(sctx
,
1142 (struct r600_resource
**)&buffer
, input
->user_buffer
,
1143 input
->buffer_size
, &buffer_offset
);
1145 /* Just unbind on failure. */
1146 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1149 va
= r600_resource(buffer
)->gpu_address
+ buffer_offset
;
1151 pipe_resource_reference(&buffer
, input
->buffer
);
1152 va
= r600_resource(buffer
)->gpu_address
+ input
->buffer_offset
;
1153 /* Only track usage for non-user buffers. */
1154 r600_resource(buffer
)->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
1157 /* Set the descriptor. */
1158 uint32_t *desc
= descs
->list
+ slot
*4;
1160 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1162 desc
[2] = input
->buffer_size
;
1163 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1164 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1165 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1166 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1167 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1168 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1170 buffers
->buffers
[slot
] = buffer
;
1171 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1172 (struct r600_resource
*)buffer
,
1173 buffers
->shader_usage_constbuf
,
1174 buffers
->priority_constbuf
, true);
1175 buffers
->enabled_mask
|= 1u << slot
;
1177 /* Clear the descriptor. */
1178 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1179 buffers
->enabled_mask
&= ~(1u << slot
);
1182 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1185 void si_set_rw_buffer(struct si_context
*sctx
,
1186 uint slot
, const struct pipe_constant_buffer
*input
)
1188 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
,
1189 SI_DESCS_RW_BUFFERS
, slot
, input
);
1192 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
,
1193 enum pipe_shader_type shader
, uint slot
,
1194 const struct pipe_constant_buffer
*input
)
1196 struct si_context
*sctx
= (struct si_context
*)ctx
;
1198 if (shader
>= SI_NUM_SHADERS
)
1201 slot
= si_get_constbuf_slot(slot
);
1202 si_set_constant_buffer(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1203 si_const_and_shader_buffer_descriptors_idx(shader
),
1207 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
1208 uint slot
, struct pipe_constant_buffer
*cbuf
)
1210 cbuf
->user_buffer
= NULL
;
1211 si_get_buffer_from_descriptors(
1212 &sctx
->const_and_shader_buffers
[shader
],
1213 si_const_and_shader_buffer_descriptors(sctx
, shader
),
1214 si_get_constbuf_slot(slot
),
1215 &cbuf
->buffer
, &cbuf
->buffer_offset
, &cbuf
->buffer_size
);
1218 /* SHADER BUFFERS */
1220 static void si_set_shader_buffers(struct pipe_context
*ctx
,
1221 enum pipe_shader_type shader
,
1222 unsigned start_slot
, unsigned count
,
1223 const struct pipe_shader_buffer
*sbuffers
)
1225 struct si_context
*sctx
= (struct si_context
*)ctx
;
1226 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1227 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1230 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1232 for (i
= 0; i
< count
; ++i
) {
1233 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1234 struct r600_resource
*buf
;
1235 unsigned slot
= si_get_shaderbuf_slot(start_slot
+ i
);
1236 uint32_t *desc
= descs
->list
+ slot
* 4;
1239 if (!sbuffer
|| !sbuffer
->buffer
) {
1240 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1241 memset(desc
, 0, sizeof(uint32_t) * 4);
1242 buffers
->enabled_mask
&= ~(1u << slot
);
1243 sctx
->descriptors_dirty
|=
1244 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1248 buf
= (struct r600_resource
*)sbuffer
->buffer
;
1249 va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1252 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1254 desc
[2] = sbuffer
->buffer_size
;
1255 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1256 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1257 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1258 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1259 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1260 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1262 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1263 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
, buf
,
1264 buffers
->shader_usage
,
1265 buffers
->priority
, true);
1266 buf
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1268 buffers
->enabled_mask
|= 1u << slot
;
1269 sctx
->descriptors_dirty
|=
1270 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1272 util_range_add(&buf
->valid_buffer_range
, sbuffer
->buffer_offset
,
1273 sbuffer
->buffer_offset
+ sbuffer
->buffer_size
);
1277 void si_get_shader_buffers(struct si_context
*sctx
,
1278 enum pipe_shader_type shader
,
1279 uint start_slot
, uint count
,
1280 struct pipe_shader_buffer
*sbuf
)
1282 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1283 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1285 for (unsigned i
= 0; i
< count
; ++i
) {
1286 si_get_buffer_from_descriptors(
1288 si_get_shaderbuf_slot(start_slot
+ i
),
1289 &sbuf
[i
].buffer
, &sbuf
[i
].buffer_offset
,
1290 &sbuf
[i
].buffer_size
);
1296 void si_set_ring_buffer(struct pipe_context
*ctx
, uint slot
,
1297 struct pipe_resource
*buffer
,
1298 unsigned stride
, unsigned num_records
,
1299 bool add_tid
, bool swizzle
,
1300 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1302 struct si_context
*sctx
= (struct si_context
*)ctx
;
1303 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1304 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1306 /* The stride field in the resource descriptor has 14 bits */
1307 assert(stride
< (1 << 14));
1309 assert(slot
< descs
->num_elements
);
1310 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1315 va
= r600_resource(buffer
)->gpu_address
+ offset
;
1317 switch (element_size
) {
1319 assert(!"Unsupported ring buffer element size");
1335 switch (index_stride
) {
1337 assert(!"Unsupported ring buffer index stride");
1353 if (sctx
->b
.chip_class
>= VI
&& stride
)
1354 num_records
*= stride
;
1356 /* Set the descriptor. */
1357 uint32_t *desc
= descs
->list
+ slot
*4;
1359 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1360 S_008F04_STRIDE(stride
) |
1361 S_008F04_SWIZZLE_ENABLE(swizzle
);
1362 desc
[2] = num_records
;
1363 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1364 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1365 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1366 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1367 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1368 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1369 S_008F0C_INDEX_STRIDE(index_stride
) |
1370 S_008F0C_ADD_TID_ENABLE(add_tid
);
1372 if (sctx
->b
.chip_class
>= GFX9
)
1373 assert(!swizzle
|| element_size
== 1); /* always 4 bytes on GFX9 */
1375 desc
[3] |= S_008F0C_ELEMENT_SIZE(element_size
);
1377 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1378 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1379 (struct r600_resource
*)buffer
,
1380 buffers
->shader_usage
, buffers
->priority
);
1381 buffers
->enabled_mask
|= 1u << slot
;
1383 /* Clear the descriptor. */
1384 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1385 buffers
->enabled_mask
&= ~(1u << slot
);
1388 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1391 static void si_desc_reset_buffer_offset(struct pipe_context
*ctx
,
1392 uint32_t *desc
, uint64_t old_buf_va
,
1393 struct pipe_resource
*new_buf
)
1395 /* Retrieve the buffer offset from the descriptor. */
1396 uint64_t old_desc_va
= si_desc_extract_buffer_address(desc
);
1398 assert(old_buf_va
<= old_desc_va
);
1399 uint64_t offset_within_buffer
= old_desc_va
- old_buf_va
;
1401 /* Update the descriptor. */
1402 si_set_buf_desc_address(r600_resource(new_buf
), offset_within_buffer
,
1406 /* INTERNAL CONST BUFFERS */
1408 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
1409 const struct pipe_poly_stipple
*state
)
1411 struct si_context
*sctx
= (struct si_context
*)ctx
;
1412 struct pipe_constant_buffer cb
= {};
1413 unsigned stipple
[32];
1416 for (i
= 0; i
< 32; i
++)
1417 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1419 cb
.user_buffer
= stipple
;
1420 cb
.buffer_size
= sizeof(stipple
);
1422 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1425 /* TEXTURE METADATA ENABLE/DISABLE */
1428 si_resident_handles_update_needs_color_decompress(struct si_context
*sctx
)
1430 util_dynarray_clear(&sctx
->resident_tex_needs_color_decompress
);
1431 util_dynarray_clear(&sctx
->resident_img_needs_color_decompress
);
1433 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1434 struct si_texture_handle
*, tex_handle
) {
1435 struct pipe_resource
*res
= (*tex_handle
)->view
->texture
;
1436 struct r600_texture
*rtex
;
1438 if (!res
|| res
->target
== PIPE_BUFFER
)
1441 rtex
= (struct r600_texture
*)res
;
1442 if (!color_needs_decompression(rtex
))
1445 util_dynarray_append(&sctx
->resident_tex_needs_color_decompress
,
1446 struct si_texture_handle
*, *tex_handle
);
1449 util_dynarray_foreach(&sctx
->resident_img_handles
,
1450 struct si_image_handle
*, img_handle
) {
1451 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1452 struct pipe_resource
*res
= view
->resource
;
1453 struct r600_texture
*rtex
;
1455 if (!res
|| res
->target
== PIPE_BUFFER
)
1458 rtex
= (struct r600_texture
*)res
;
1459 if (!color_needs_decompression(rtex
))
1462 util_dynarray_append(&sctx
->resident_img_needs_color_decompress
,
1463 struct si_image_handle
*, *img_handle
);
1467 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1468 * while the texture is bound, possibly by a different context. In that case,
1469 * call this function to update needs_*_decompress_masks.
1471 void si_update_needs_color_decompress_masks(struct si_context
*sctx
)
1473 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1474 si_samplers_update_needs_color_decompress_mask(&sctx
->samplers
[i
]);
1475 si_images_update_needs_color_decompress_mask(&sctx
->images
[i
]);
1476 si_update_shader_needs_decompress_mask(sctx
, i
);
1479 si_resident_handles_update_needs_color_decompress(sctx
);
1482 /* BUFFER DISCARD/INVALIDATION */
1484 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1485 static void si_reset_buffer_resources(struct si_context
*sctx
,
1486 struct si_buffer_resources
*buffers
,
1487 unsigned descriptors_idx
,
1489 struct pipe_resource
*buf
,
1491 enum radeon_bo_usage usage
,
1492 enum radeon_bo_priority priority
)
1494 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1495 unsigned mask
= buffers
->enabled_mask
& slot_mask
;
1498 unsigned i
= u_bit_scan(&mask
);
1499 if (buffers
->buffers
[i
] == buf
) {
1500 si_desc_reset_buffer_offset(&sctx
->b
.b
,
1503 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1505 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1506 (struct r600_resource
*)buf
,
1507 usage
, priority
, true);
1512 static void si_rebind_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
,
1515 struct si_context
*sctx
= (struct si_context
*)ctx
;
1516 struct r600_resource
*rbuffer
= r600_resource(buf
);
1518 unsigned num_elems
= sctx
->vertex_elements
?
1519 sctx
->vertex_elements
->count
: 0;
1521 /* We changed the buffer, now we need to bind it where the old one
1522 * was bound. This consists of 2 things:
1523 * 1) Updating the resource descriptor and dirtying it.
1524 * 2) Adding a relocation to the CS, so that it's usable.
1527 /* Vertex buffers. */
1528 if (rbuffer
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
1529 for (i
= 0; i
< num_elems
; i
++) {
1530 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1532 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1534 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1537 if (sctx
->vertex_buffer
[vb
].buffer
.resource
== buf
) {
1538 sctx
->vertex_buffers_dirty
= true;
1544 /* Streamout buffers. (other internal buffers can't be invalidated) */
1545 if (rbuffer
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
1546 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1547 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1548 struct si_descriptors
*descs
=
1549 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1551 if (buffers
->buffers
[i
] != buf
)
1554 si_desc_reset_buffer_offset(ctx
, descs
->list
+ i
*4,
1556 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1558 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1559 rbuffer
, buffers
->shader_usage
,
1560 RADEON_PRIO_SHADER_RW_BUFFER
,
1563 /* Update the streamout state. */
1564 if (sctx
->streamout
.begin_emitted
)
1565 si_emit_streamout_end(sctx
);
1566 sctx
->streamout
.append_bitmask
=
1567 sctx
->streamout
.enabled_mask
;
1568 si_streamout_buffers_dirty(sctx
);
1572 /* Constant and shader buffers. */
1573 if (rbuffer
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1574 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1575 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1576 si_const_and_shader_buffer_descriptors_idx(shader
),
1577 u_bit_consecutive(SI_NUM_SHADER_BUFFERS
, SI_NUM_CONST_BUFFERS
),
1579 sctx
->const_and_shader_buffers
[shader
].shader_usage_constbuf
,
1580 sctx
->const_and_shader_buffers
[shader
].priority_constbuf
);
1583 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
1584 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1585 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1586 si_const_and_shader_buffer_descriptors_idx(shader
),
1587 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
),
1589 sctx
->const_and_shader_buffers
[shader
].shader_usage
,
1590 sctx
->const_and_shader_buffers
[shader
].priority
);
1593 if (rbuffer
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
1594 /* Texture buffers - update bindings. */
1595 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1596 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1597 struct si_descriptors
*descs
=
1598 si_sampler_and_image_descriptors(sctx
, shader
);
1599 unsigned mask
= samplers
->enabled_mask
;
1602 unsigned i
= u_bit_scan(&mask
);
1603 if (samplers
->views
[i
]->texture
== buf
) {
1604 unsigned desc_slot
= si_get_sampler_slot(i
);
1606 si_desc_reset_buffer_offset(ctx
,
1610 sctx
->descriptors_dirty
|=
1611 1u << si_sampler_and_image_descriptors_idx(shader
);
1613 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1614 rbuffer
, RADEON_USAGE_READ
,
1615 RADEON_PRIO_SAMPLER_BUFFER
,
1623 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
1624 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1625 struct si_images
*images
= &sctx
->images
[shader
];
1626 struct si_descriptors
*descs
=
1627 si_sampler_and_image_descriptors(sctx
, shader
);
1628 unsigned mask
= images
->enabled_mask
;
1631 unsigned i
= u_bit_scan(&mask
);
1633 if (images
->views
[i
].resource
== buf
) {
1634 unsigned desc_slot
= si_get_image_slot(i
);
1636 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1637 si_mark_image_range_valid(&images
->views
[i
]);
1639 si_desc_reset_buffer_offset(
1640 ctx
, descs
->list
+ desc_slot
* 8 + 4,
1642 sctx
->descriptors_dirty
|=
1643 1u << si_sampler_and_image_descriptors_idx(shader
);
1645 radeon_add_to_buffer_list_check_mem(
1646 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1647 RADEON_USAGE_READWRITE
,
1648 RADEON_PRIO_SAMPLER_BUFFER
, true);
1654 /* Bindless texture handles */
1655 if (rbuffer
->texture_handle_allocated
) {
1656 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1658 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1659 struct si_texture_handle
*, tex_handle
) {
1660 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
1661 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1663 if (view
->texture
== buf
) {
1664 si_set_buf_desc_address(rbuffer
,
1667 desc_slot
* 16 + 4);
1669 (*tex_handle
)->desc_dirty
= true;
1670 sctx
->bindless_descriptors_dirty
= true;
1672 radeon_add_to_buffer_list_check_mem(
1673 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1675 RADEON_PRIO_SAMPLER_BUFFER
, true);
1680 /* Bindless image handles */
1681 if (rbuffer
->image_handle_allocated
) {
1682 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1684 util_dynarray_foreach(&sctx
->resident_img_handles
,
1685 struct si_image_handle
*, img_handle
) {
1686 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1687 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1689 if (view
->resource
== buf
) {
1690 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
1691 si_mark_image_range_valid(view
);
1693 si_set_buf_desc_address(rbuffer
,
1696 desc_slot
* 16 + 4);
1698 (*img_handle
)->desc_dirty
= true;
1699 sctx
->bindless_descriptors_dirty
= true;
1701 radeon_add_to_buffer_list_check_mem(
1702 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1703 RADEON_USAGE_READWRITE
,
1704 RADEON_PRIO_SAMPLER_BUFFER
, true);
1710 /* Reallocate a buffer a update all resource bindings where the buffer is
1713 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
1714 * idle by discarding its contents. Apps usually tell us when to do this using
1715 * map_buffer flags, for example.
1717 static void si_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
1719 struct si_context
*sctx
= (struct si_context
*)ctx
;
1720 struct r600_resource
*rbuffer
= r600_resource(buf
);
1721 uint64_t old_va
= rbuffer
->gpu_address
;
1723 /* Reallocate the buffer in the same pipe_resource. */
1724 si_alloc_resource(&sctx
->screen
->b
, rbuffer
);
1726 si_rebind_buffer(ctx
, buf
, old_va
);
1729 static void si_upload_bindless_descriptor(struct si_context
*sctx
,
1731 unsigned num_dwords
)
1733 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1734 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1735 unsigned desc_slot_offset
= desc_slot
* 16;
1739 data
= desc
->list
+ desc_slot_offset
;
1740 va
= desc
->gpu_address
+ desc_slot_offset
* 4;
1742 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + num_dwords
, 0));
1743 radeon_emit(cs
, S_370_DST_SEL(V_370_TC_L2
) |
1744 S_370_WR_CONFIRM(1) |
1745 S_370_ENGINE_SEL(V_370_ME
));
1746 radeon_emit(cs
, va
);
1747 radeon_emit(cs
, va
>> 32);
1748 radeon_emit_array(cs
, data
, num_dwords
);
1751 static void si_upload_bindless_descriptors(struct si_context
*sctx
)
1753 if (!sctx
->bindless_descriptors_dirty
)
1756 /* Wait for graphics/compute to be idle before updating the resident
1757 * descriptors directly in memory, in case the GPU is using them.
1759 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
1760 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1761 si_emit_cache_flush(sctx
);
1763 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1764 struct si_texture_handle
*, tex_handle
) {
1765 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1767 if (!(*tex_handle
)->desc_dirty
)
1770 si_upload_bindless_descriptor(sctx
, desc_slot
, 16);
1771 (*tex_handle
)->desc_dirty
= false;
1774 util_dynarray_foreach(&sctx
->resident_img_handles
,
1775 struct si_image_handle
*, img_handle
) {
1776 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1778 if (!(*img_handle
)->desc_dirty
)
1781 si_upload_bindless_descriptor(sctx
, desc_slot
, 8);
1782 (*img_handle
)->desc_dirty
= false;
1785 /* Invalidate L1 because it doesn't know that L2 changed. */
1786 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
;
1787 si_emit_cache_flush(sctx
);
1789 sctx
->bindless_descriptors_dirty
= false;
1792 /* Update mutable image descriptor fields of all resident textures. */
1793 static void si_update_bindless_texture_descriptor(struct si_context
*sctx
,
1794 struct si_texture_handle
*tex_handle
)
1796 struct si_sampler_view
*sview
= (struct si_sampler_view
*)tex_handle
->view
;
1797 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1798 unsigned desc_slot_offset
= tex_handle
->desc_slot
* 16;
1799 uint32_t desc_list
[16];
1801 if (sview
->base
.texture
->target
== PIPE_BUFFER
)
1804 memcpy(desc_list
, desc
->list
+ desc_slot_offset
, sizeof(desc_list
));
1805 si_set_sampler_view_desc(sctx
, sview
, &tex_handle
->sstate
,
1806 desc
->list
+ desc_slot_offset
);
1808 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1809 sizeof(desc_list
))) {
1810 tex_handle
->desc_dirty
= true;
1811 sctx
->bindless_descriptors_dirty
= true;
1815 static void si_update_bindless_image_descriptor(struct si_context
*sctx
,
1816 struct si_image_handle
*img_handle
)
1818 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1819 unsigned desc_slot_offset
= img_handle
->desc_slot
* 16;
1820 struct pipe_image_view
*view
= &img_handle
->view
;
1821 uint32_t desc_list
[8];
1823 if (view
->resource
->target
== PIPE_BUFFER
)
1826 memcpy(desc_list
, desc
->list
+ desc_slot_offset
,
1828 si_set_shader_image_desc(sctx
, view
, true,
1829 desc
->list
+ desc_slot_offset
);
1831 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1832 sizeof(desc_list
))) {
1833 img_handle
->desc_dirty
= true;
1834 sctx
->bindless_descriptors_dirty
= true;
1838 static void si_update_all_resident_texture_descriptors(struct si_context
*sctx
)
1840 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1841 struct si_texture_handle
*, tex_handle
) {
1842 si_update_bindless_texture_descriptor(sctx
, *tex_handle
);
1845 util_dynarray_foreach(&sctx
->resident_img_handles
,
1846 struct si_image_handle
*, img_handle
) {
1847 si_update_bindless_image_descriptor(sctx
, *img_handle
);
1850 si_upload_bindless_descriptors(sctx
);
1853 /* Update mutable image descriptor fields of all bound textures. */
1854 void si_update_all_texture_descriptors(struct si_context
*sctx
)
1858 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1859 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1860 struct si_images
*images
= &sctx
->images
[shader
];
1864 mask
= images
->enabled_mask
;
1866 unsigned i
= u_bit_scan(&mask
);
1867 struct pipe_image_view
*view
= &images
->views
[i
];
1869 if (!view
->resource
||
1870 view
->resource
->target
== PIPE_BUFFER
)
1873 si_set_shader_image(sctx
, shader
, i
, view
, true);
1876 /* Sampler views. */
1877 mask
= samplers
->enabled_mask
;
1879 unsigned i
= u_bit_scan(&mask
);
1880 struct pipe_sampler_view
*view
= samplers
->views
[i
];
1884 view
->texture
->target
== PIPE_BUFFER
)
1887 si_set_sampler_view(sctx
, shader
, i
,
1888 samplers
->views
[i
], true);
1891 si_update_shader_needs_decompress_mask(sctx
, shader
);
1894 si_update_all_resident_texture_descriptors(sctx
);
1897 /* SHADER USER DATA */
1899 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
,
1902 sctx
->shader_pointers_dirty
|=
1903 u_bit_consecutive(SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
,
1904 SI_NUM_SHADER_DESCS
);
1906 if (shader
== PIPE_SHADER_VERTEX
)
1907 sctx
->vertex_buffer_pointer_dirty
= sctx
->vertex_buffers
.buffer
!= NULL
;
1909 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1912 static void si_shader_pointers_begin_new_cs(struct si_context
*sctx
)
1914 sctx
->shader_pointers_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
1915 sctx
->vertex_buffer_pointer_dirty
= sctx
->vertex_buffers
.buffer
!= NULL
;
1916 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1917 sctx
->graphics_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
1918 sctx
->compute_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
1921 /* Set a base register address for user data constants in the given shader.
1922 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1924 static void si_set_user_data_base(struct si_context
*sctx
,
1925 unsigned shader
, uint32_t new_base
)
1927 uint32_t *base
= &sctx
->shader_pointers
.sh_base
[shader
];
1929 if (*base
!= new_base
) {
1933 si_mark_shader_pointers_dirty(sctx
, shader
);
1935 if (shader
== PIPE_SHADER_VERTEX
)
1936 sctx
->last_vs_state
= ~0;
1941 /* This must be called when these shaders are changed from non-NULL to NULL
1944 * - tessellation control shader
1945 * - tessellation evaluation shader
1947 void si_shader_change_notify(struct si_context
*sctx
)
1949 /* VS can be bound as VS, ES, or LS. */
1950 if (sctx
->tes_shader
.cso
) {
1951 if (sctx
->b
.chip_class
>= GFX9
) {
1952 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1953 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
1955 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1956 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
1958 } else if (sctx
->gs_shader
.cso
) {
1959 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1960 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1962 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1963 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1966 /* TES can be bound as ES, VS, or not bound. */
1967 if (sctx
->tes_shader
.cso
) {
1968 if (sctx
->gs_shader
.cso
)
1969 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
1970 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1972 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
1973 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1975 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
1979 static void si_emit_shader_pointer_head(struct radeon_winsys_cs
*cs
,
1980 struct si_descriptors
*desc
,
1982 unsigned pointer_count
)
1984 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* 2, 0));
1985 radeon_emit(cs
, (sh_base
+ desc
->shader_userdata_offset
- SI_SH_REG_OFFSET
) >> 2);
1988 static void si_emit_shader_pointer_body(struct radeon_winsys_cs
*cs
,
1989 struct si_descriptors
*desc
)
1991 uint64_t va
= desc
->gpu_address
;
1993 radeon_emit(cs
, va
);
1994 radeon_emit(cs
, va
>> 32);
1997 static void si_emit_shader_pointer(struct si_context
*sctx
,
1998 struct si_descriptors
*desc
,
2001 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2003 si_emit_shader_pointer_head(cs
, desc
, sh_base
, 1);
2004 si_emit_shader_pointer_body(cs
, desc
);
2007 static void si_emit_consecutive_shader_pointers(struct si_context
*sctx
,
2008 unsigned pointer_mask
,
2014 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2015 unsigned mask
= sctx
->shader_pointers_dirty
& pointer_mask
;
2019 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
2021 struct si_descriptors
*descs
= &sctx
->descriptors
[start
];
2023 si_emit_shader_pointer_head(cs
, descs
, sh_base
, count
);
2024 for (int i
= 0; i
< count
; i
++)
2025 si_emit_shader_pointer_body(cs
, descs
+ i
);
2029 static void si_emit_global_shader_pointers(struct si_context
*sctx
,
2030 struct si_descriptors
*descs
)
2032 if (sctx
->b
.chip_class
== GFX9
) {
2033 /* Broadcast it to all shader stages. */
2034 si_emit_shader_pointer(sctx
, descs
,
2035 R_00B530_SPI_SHADER_USER_DATA_COMMON_0
);
2039 si_emit_shader_pointer(sctx
, descs
,
2040 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2041 si_emit_shader_pointer(sctx
, descs
,
2042 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2043 si_emit_shader_pointer(sctx
, descs
,
2044 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2045 si_emit_shader_pointer(sctx
, descs
,
2046 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2047 si_emit_shader_pointer(sctx
, descs
,
2048 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2049 si_emit_shader_pointer(sctx
, descs
,
2050 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2053 void si_emit_graphics_shader_pointers(struct si_context
*sctx
,
2054 struct r600_atom
*atom
)
2056 uint32_t *sh_base
= sctx
->shader_pointers
.sh_base
;
2058 if (sctx
->shader_pointers_dirty
& (1 << SI_DESCS_RW_BUFFERS
)) {
2059 si_emit_global_shader_pointers(sctx
,
2060 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2063 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(VERTEX
),
2064 sh_base
[PIPE_SHADER_VERTEX
]);
2065 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_CTRL
),
2066 sh_base
[PIPE_SHADER_TESS_CTRL
]);
2067 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_EVAL
),
2068 sh_base
[PIPE_SHADER_TESS_EVAL
]);
2069 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(GEOMETRY
),
2070 sh_base
[PIPE_SHADER_GEOMETRY
]);
2071 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(FRAGMENT
),
2072 sh_base
[PIPE_SHADER_FRAGMENT
]);
2074 sctx
->shader_pointers_dirty
&=
2075 ~u_bit_consecutive(SI_DESCS_RW_BUFFERS
, SI_DESCS_FIRST_COMPUTE
);
2077 if (sctx
->vertex_buffer_pointer_dirty
) {
2078 si_emit_shader_pointer(sctx
, &sctx
->vertex_buffers
,
2079 sh_base
[PIPE_SHADER_VERTEX
]);
2080 sctx
->vertex_buffer_pointer_dirty
= false;
2083 if (sctx
->graphics_bindless_pointer_dirty
) {
2084 si_emit_global_shader_pointers(sctx
,
2085 &sctx
->bindless_descriptors
);
2086 sctx
->graphics_bindless_pointer_dirty
= false;
2090 void si_emit_compute_shader_pointers(struct si_context
*sctx
)
2092 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
2094 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(COMPUTE
),
2095 R_00B900_COMPUTE_USER_DATA_0
);
2096 sctx
->shader_pointers_dirty
&= ~SI_DESCS_SHADER_MASK(COMPUTE
);
2098 if (sctx
->compute_bindless_pointer_dirty
) {
2099 si_emit_shader_pointer(sctx
, &sctx
->bindless_descriptors
, base
);
2100 sctx
->compute_bindless_pointer_dirty
= false;
2106 static void si_init_bindless_descriptors(struct si_context
*sctx
,
2107 struct si_descriptors
*desc
,
2108 unsigned shader_userdata_index
,
2109 unsigned num_elements
)
2111 MAYBE_UNUSED
unsigned desc_slot
;
2113 si_init_descriptors(desc
, shader_userdata_index
, 16, num_elements
);
2114 sctx
->bindless_descriptors
.num_active_slots
= num_elements
;
2116 /* The first bindless descriptor is stored at slot 1, because 0 is not
2117 * considered to be a valid handle.
2119 sctx
->num_bindless_descriptors
= 1;
2121 /* Track which bindless slots are used (or not). */
2122 util_idalloc_init(&sctx
->bindless_used_slots
);
2123 util_idalloc_resize(&sctx
->bindless_used_slots
, num_elements
);
2125 /* Reserve slot 0 because it's an invalid handle for bindless. */
2126 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2127 assert(desc_slot
== 0);
2130 static void si_release_bindless_descriptors(struct si_context
*sctx
)
2132 si_release_descriptors(&sctx
->bindless_descriptors
);
2133 util_idalloc_fini(&sctx
->bindless_used_slots
);
2136 static unsigned si_get_first_free_bindless_slot(struct si_context
*sctx
)
2138 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2141 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2142 if (desc_slot
>= desc
->num_elements
) {
2143 /* The array of bindless descriptors is full, resize it. */
2144 unsigned slot_size
= desc
->element_dw_size
* 4;
2145 unsigned new_num_elements
= desc
->num_elements
* 2;
2147 desc
->list
= REALLOC(desc
->list
, desc
->num_elements
* slot_size
,
2148 new_num_elements
* slot_size
);
2149 desc
->num_elements
= new_num_elements
;
2150 desc
->num_active_slots
= new_num_elements
;
2158 si_create_bindless_descriptor(struct si_context
*sctx
, uint32_t *desc_list
,
2161 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2162 unsigned desc_slot
, desc_slot_offset
;
2164 /* Find a free slot. */
2165 desc_slot
= si_get_first_free_bindless_slot(sctx
);
2167 /* For simplicity, sampler and image bindless descriptors use fixed
2168 * 16-dword slots for now. Image descriptors only need 8-dword but this
2169 * doesn't really matter because no real apps use image handles.
2171 desc_slot_offset
= desc_slot
* 16;
2173 /* Copy the descriptor into the array. */
2174 memcpy(desc
->list
+ desc_slot_offset
, desc_list
, size
);
2176 /* Re-upload the whole array of bindless descriptors into a new buffer.
2178 if (!si_upload_descriptors(sctx
, desc
))
2181 /* Make sure to re-emit the shader pointers for all stages. */
2182 sctx
->graphics_bindless_pointer_dirty
= true;
2183 sctx
->compute_bindless_pointer_dirty
= true;
2188 static void si_update_bindless_buffer_descriptor(struct si_context
*sctx
,
2190 struct pipe_resource
*resource
,
2194 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2195 struct r600_resource
*buf
= r600_resource(resource
);
2196 unsigned desc_slot_offset
= desc_slot
* 16;
2197 uint32_t *desc_list
= desc
->list
+ desc_slot_offset
+ 4;
2198 uint64_t old_desc_va
;
2200 assert(resource
->target
== PIPE_BUFFER
);
2202 /* Retrieve the old buffer addr from the descriptor. */
2203 old_desc_va
= si_desc_extract_buffer_address(desc_list
);
2205 if (old_desc_va
!= buf
->gpu_address
+ offset
) {
2206 /* The buffer has been invalidated when the handle wasn't
2207 * resident, update the descriptor and the dirty flag.
2209 si_set_buf_desc_address(buf
, offset
, &desc_list
[0]);
2215 static uint64_t si_create_texture_handle(struct pipe_context
*ctx
,
2216 struct pipe_sampler_view
*view
,
2217 const struct pipe_sampler_state
*state
)
2219 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
2220 struct si_context
*sctx
= (struct si_context
*)ctx
;
2221 struct si_texture_handle
*tex_handle
;
2222 struct si_sampler_state
*sstate
;
2223 uint32_t desc_list
[16];
2226 tex_handle
= CALLOC_STRUCT(si_texture_handle
);
2230 memset(desc_list
, 0, sizeof(desc_list
));
2231 si_init_descriptor_list(&desc_list
[0], 16, 1, null_texture_descriptor
);
2233 sstate
= ctx
->create_sampler_state(ctx
, state
);
2239 si_set_sampler_view_desc(sctx
, sview
, sstate
, &desc_list
[0]);
2240 memcpy(&tex_handle
->sstate
, sstate
, sizeof(*sstate
));
2241 ctx
->delete_sampler_state(ctx
, sstate
);
2243 tex_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2245 if (!tex_handle
->desc_slot
) {
2250 handle
= tex_handle
->desc_slot
;
2252 if (!_mesa_hash_table_insert(sctx
->tex_handles
, (void *)handle
,
2258 pipe_sampler_view_reference(&tex_handle
->view
, view
);
2260 r600_resource(sview
->base
.texture
)->texture_handle_allocated
= true;
2265 static void si_delete_texture_handle(struct pipe_context
*ctx
, uint64_t handle
)
2267 struct si_context
*sctx
= (struct si_context
*)ctx
;
2268 struct si_texture_handle
*tex_handle
;
2269 struct hash_entry
*entry
;
2271 entry
= _mesa_hash_table_search(sctx
->tex_handles
, (void *)handle
);
2275 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2277 /* Allow this descriptor slot to be re-used. */
2278 util_idalloc_free(&sctx
->bindless_used_slots
, tex_handle
->desc_slot
);
2280 pipe_sampler_view_reference(&tex_handle
->view
, NULL
);
2281 _mesa_hash_table_remove(sctx
->tex_handles
, entry
);
2285 static void si_make_texture_handle_resident(struct pipe_context
*ctx
,
2286 uint64_t handle
, bool resident
)
2288 struct si_context
*sctx
= (struct si_context
*)ctx
;
2289 struct si_texture_handle
*tex_handle
;
2290 struct si_sampler_view
*sview
;
2291 struct hash_entry
*entry
;
2293 entry
= _mesa_hash_table_search(sctx
->tex_handles
, (void *)handle
);
2297 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2298 sview
= (struct si_sampler_view
*)tex_handle
->view
;
2301 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2302 struct r600_texture
*rtex
=
2303 (struct r600_texture
*)sview
->base
.texture
;
2305 if (depth_needs_decompression(rtex
)) {
2306 util_dynarray_append(
2307 &sctx
->resident_tex_needs_depth_decompress
,
2308 struct si_texture_handle
*,
2312 if (color_needs_decompression(rtex
)) {
2313 util_dynarray_append(
2314 &sctx
->resident_tex_needs_color_decompress
,
2315 struct si_texture_handle
*,
2319 if (rtex
->dcc_offset
&&
2320 p_atomic_read(&rtex
->framebuffers_bound
))
2321 sctx
->need_check_render_feedback
= true;
2323 si_update_bindless_texture_descriptor(sctx
, tex_handle
);
2325 si_update_bindless_buffer_descriptor(sctx
,
2326 tex_handle
->desc_slot
,
2327 sview
->base
.texture
,
2328 sview
->base
.u
.buf
.offset
,
2329 &tex_handle
->desc_dirty
);
2332 /* Re-upload the descriptor if it has been updated while it
2335 if (tex_handle
->desc_dirty
)
2336 sctx
->bindless_descriptors_dirty
= true;
2338 /* Add the texture handle to the per-context list. */
2339 util_dynarray_append(&sctx
->resident_tex_handles
,
2340 struct si_texture_handle
*, tex_handle
);
2342 /* Add the buffers to the current CS in case si_begin_new_cs()
2343 * is not going to be called.
2345 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2347 sview
->is_stencil_sampler
, false);
2349 /* Remove the texture handle from the per-context list. */
2350 util_dynarray_delete_unordered(&sctx
->resident_tex_handles
,
2351 struct si_texture_handle
*,
2354 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2355 util_dynarray_delete_unordered(
2356 &sctx
->resident_tex_needs_depth_decompress
,
2357 struct si_texture_handle
*, tex_handle
);
2359 util_dynarray_delete_unordered(
2360 &sctx
->resident_tex_needs_color_decompress
,
2361 struct si_texture_handle
*, tex_handle
);
2366 static uint64_t si_create_image_handle(struct pipe_context
*ctx
,
2367 const struct pipe_image_view
*view
)
2369 struct si_context
*sctx
= (struct si_context
*)ctx
;
2370 struct si_image_handle
*img_handle
;
2371 uint32_t desc_list
[8];
2374 if (!view
|| !view
->resource
)
2377 img_handle
= CALLOC_STRUCT(si_image_handle
);
2381 memset(desc_list
, 0, sizeof(desc_list
));
2382 si_init_descriptor_list(&desc_list
[0], 8, 1, null_image_descriptor
);
2384 si_set_shader_image_desc(sctx
, view
, false, &desc_list
[0]);
2386 img_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2388 if (!img_handle
->desc_slot
) {
2393 handle
= img_handle
->desc_slot
;
2395 if (!_mesa_hash_table_insert(sctx
->img_handles
, (void *)handle
,
2401 util_copy_image_view(&img_handle
->view
, view
);
2403 r600_resource(view
->resource
)->image_handle_allocated
= true;
2408 static void si_delete_image_handle(struct pipe_context
*ctx
, uint64_t handle
)
2410 struct si_context
*sctx
= (struct si_context
*)ctx
;
2411 struct si_image_handle
*img_handle
;
2412 struct hash_entry
*entry
;
2414 entry
= _mesa_hash_table_search(sctx
->img_handles
, (void *)handle
);
2418 img_handle
= (struct si_image_handle
*)entry
->data
;
2420 util_copy_image_view(&img_handle
->view
, NULL
);
2421 _mesa_hash_table_remove(sctx
->img_handles
, entry
);
2425 static void si_make_image_handle_resident(struct pipe_context
*ctx
,
2426 uint64_t handle
, unsigned access
,
2429 struct si_context
*sctx
= (struct si_context
*)ctx
;
2430 struct si_image_handle
*img_handle
;
2431 struct pipe_image_view
*view
;
2432 struct r600_resource
*res
;
2433 struct hash_entry
*entry
;
2435 entry
= _mesa_hash_table_search(sctx
->img_handles
, (void *)handle
);
2439 img_handle
= (struct si_image_handle
*)entry
->data
;
2440 view
= &img_handle
->view
;
2441 res
= (struct r600_resource
*)view
->resource
;
2444 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2445 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
2446 unsigned level
= view
->u
.tex
.level
;
2448 if (color_needs_decompression(rtex
)) {
2449 util_dynarray_append(
2450 &sctx
->resident_img_needs_color_decompress
,
2451 struct si_image_handle
*,
2455 if (vi_dcc_enabled(rtex
, level
) &&
2456 p_atomic_read(&rtex
->framebuffers_bound
))
2457 sctx
->need_check_render_feedback
= true;
2459 si_update_bindless_image_descriptor(sctx
, img_handle
);
2461 si_update_bindless_buffer_descriptor(sctx
,
2462 img_handle
->desc_slot
,
2465 &img_handle
->desc_dirty
);
2468 /* Re-upload the descriptor if it has been updated while it
2471 if (img_handle
->desc_dirty
)
2472 sctx
->bindless_descriptors_dirty
= true;
2474 /* Add the image handle to the per-context list. */
2475 util_dynarray_append(&sctx
->resident_img_handles
,
2476 struct si_image_handle
*, img_handle
);
2478 /* Add the buffers to the current CS in case si_begin_new_cs()
2479 * is not going to be called.
2481 si_sampler_view_add_buffer(sctx
, view
->resource
,
2482 (access
& PIPE_IMAGE_ACCESS_WRITE
) ?
2483 RADEON_USAGE_READWRITE
:
2484 RADEON_USAGE_READ
, false, false);
2486 /* Remove the image handle from the per-context list. */
2487 util_dynarray_delete_unordered(&sctx
->resident_img_handles
,
2488 struct si_image_handle
*,
2491 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2492 util_dynarray_delete_unordered(
2493 &sctx
->resident_img_needs_color_decompress
,
2494 struct si_image_handle
*,
2501 void si_all_resident_buffers_begin_new_cs(struct si_context
*sctx
)
2503 unsigned num_resident_tex_handles
, num_resident_img_handles
;
2505 num_resident_tex_handles
= sctx
->resident_tex_handles
.size
/
2506 sizeof(struct si_texture_handle
*);
2507 num_resident_img_handles
= sctx
->resident_img_handles
.size
/
2508 sizeof(struct si_image_handle
*);
2510 /* Add all resident texture handles. */
2511 util_dynarray_foreach(&sctx
->resident_tex_handles
,
2512 struct si_texture_handle
*, tex_handle
) {
2513 struct si_sampler_view
*sview
=
2514 (struct si_sampler_view
*)(*tex_handle
)->view
;
2516 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2518 sview
->is_stencil_sampler
, false);
2521 /* Add all resident image handles. */
2522 util_dynarray_foreach(&sctx
->resident_img_handles
,
2523 struct si_image_handle
*, img_handle
) {
2524 struct pipe_image_view
*view
= &(*img_handle
)->view
;
2526 si_sampler_view_add_buffer(sctx
, view
->resource
,
2527 RADEON_USAGE_READWRITE
,
2531 sctx
->b
.num_resident_handles
+= num_resident_tex_handles
+
2532 num_resident_img_handles
;
2535 /* INIT/DEINIT/UPLOAD */
2537 void si_init_all_descriptors(struct si_context
*sctx
)
2541 STATIC_ASSERT(GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS
% 2 == 0);
2542 STATIC_ASSERT(GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS
% 2 == 0);
2544 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2545 bool gfx9_tcs
= false;
2546 bool gfx9_gs
= false;
2547 unsigned num_sampler_slots
= SI_NUM_IMAGES
/ 2 + SI_NUM_SAMPLERS
;
2548 unsigned num_buffer_slots
= SI_NUM_SHADER_BUFFERS
+ SI_NUM_CONST_BUFFERS
;
2549 struct si_descriptors
*desc
;
2551 if (sctx
->b
.chip_class
>= GFX9
) {
2552 gfx9_tcs
= i
== PIPE_SHADER_TESS_CTRL
;
2553 gfx9_gs
= i
== PIPE_SHADER_GEOMETRY
;
2556 desc
= si_const_and_shader_buffer_descriptors(sctx
, i
);
2557 si_init_buffer_resources(&sctx
->const_and_shader_buffers
[i
], desc
,
2559 gfx9_tcs
? GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS
:
2560 gfx9_gs
? GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS
:
2561 SI_SGPR_CONST_AND_SHADER_BUFFERS
,
2562 RADEON_USAGE_READWRITE
,
2564 RADEON_PRIO_SHADER_RW_BUFFER
,
2565 RADEON_PRIO_CONST_BUFFER
);
2566 desc
->slot_index_to_bind_directly
= si_get_constbuf_slot(0);
2568 desc
= si_sampler_and_image_descriptors(sctx
, i
);
2569 si_init_descriptors(desc
,
2570 gfx9_tcs
? GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES
:
2571 gfx9_gs
? GFX9_SGPR_GS_SAMPLERS_AND_IMAGES
:
2572 SI_SGPR_SAMPLERS_AND_IMAGES
,
2573 16, num_sampler_slots
);
2576 for (j
= 0; j
< SI_NUM_IMAGES
; j
++)
2577 memcpy(desc
->list
+ j
* 8, null_image_descriptor
, 8 * 4);
2578 for (; j
< SI_NUM_IMAGES
+ SI_NUM_SAMPLERS
* 2; j
++)
2579 memcpy(desc
->list
+ j
* 8, null_texture_descriptor
, 8 * 4);
2582 si_init_buffer_resources(&sctx
->rw_buffers
,
2583 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
2584 SI_NUM_RW_BUFFERS
, SI_SGPR_RW_BUFFERS
,
2585 /* The second set of usage/priority is used by
2586 * const buffers in RW buffer slots. */
2587 RADEON_USAGE_READWRITE
, RADEON_USAGE_READ
,
2588 RADEON_PRIO_SHADER_RINGS
, RADEON_PRIO_CONST_BUFFER
);
2589 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
= SI_NUM_RW_BUFFERS
;
2591 si_init_descriptors(&sctx
->vertex_buffers
, SI_SGPR_VERTEX_BUFFERS
,
2592 4, SI_NUM_VERTEX_BUFFERS
);
2593 FREE(sctx
->vertex_buffers
.list
); /* not used */
2594 sctx
->vertex_buffers
.list
= NULL
;
2596 /* Initialize an array of 1024 bindless descriptors, when the limit is
2597 * reached, just make it larger and re-upload the whole array.
2599 si_init_bindless_descriptors(sctx
, &sctx
->bindless_descriptors
,
2600 SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
,
2603 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2605 /* Set pipe_context functions. */
2606 sctx
->b
.b
.bind_sampler_states
= si_bind_sampler_states
;
2607 sctx
->b
.b
.set_shader_images
= si_set_shader_images
;
2608 sctx
->b
.b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
2609 sctx
->b
.b
.set_polygon_stipple
= si_set_polygon_stipple
;
2610 sctx
->b
.b
.set_shader_buffers
= si_set_shader_buffers
;
2611 sctx
->b
.b
.set_sampler_views
= si_set_sampler_views
;
2612 sctx
->b
.b
.create_texture_handle
= si_create_texture_handle
;
2613 sctx
->b
.b
.delete_texture_handle
= si_delete_texture_handle
;
2614 sctx
->b
.b
.make_texture_handle_resident
= si_make_texture_handle_resident
;
2615 sctx
->b
.b
.create_image_handle
= si_create_image_handle
;
2616 sctx
->b
.b
.delete_image_handle
= si_delete_image_handle
;
2617 sctx
->b
.b
.make_image_handle_resident
= si_make_image_handle_resident
;
2618 sctx
->b
.invalidate_buffer
= si_invalidate_buffer
;
2619 sctx
->b
.rebind_buffer
= si_rebind_buffer
;
2621 /* Shader user data. */
2622 si_init_atom(sctx
, &sctx
->shader_pointers
.atom
, &sctx
->atoms
.s
.shader_pointers
,
2623 si_emit_graphics_shader_pointers
);
2625 /* Set default and immutable mappings. */
2626 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2628 if (sctx
->b
.chip_class
>= GFX9
) {
2629 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2630 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2631 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2632 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2634 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2635 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2636 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2637 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2639 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2642 static bool si_upload_shader_descriptors(struct si_context
*sctx
, unsigned mask
)
2644 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2646 /* Assume nothing will go wrong: */
2647 sctx
->shader_pointers_dirty
|= dirty
;
2650 unsigned i
= u_bit_scan(&dirty
);
2652 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
]))
2656 sctx
->descriptors_dirty
&= ~mask
;
2658 si_upload_bindless_descriptors(sctx
);
2663 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
2665 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
2666 return si_upload_shader_descriptors(sctx
, mask
);
2669 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
2671 /* Does not update rw_buffers as that is not needed for compute shaders
2672 * and the input buffer is using the same SGPR's anyway.
2674 const unsigned mask
= u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
,
2675 SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
2676 return si_upload_shader_descriptors(sctx
, mask
);
2679 void si_release_all_descriptors(struct si_context
*sctx
)
2683 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2684 si_release_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2685 si_const_and_shader_buffer_descriptors(sctx
, i
));
2686 si_release_sampler_views(&sctx
->samplers
[i
]);
2687 si_release_image_views(&sctx
->images
[i
]);
2689 si_release_buffer_resources(&sctx
->rw_buffers
,
2690 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2691 for (i
= 0; i
< SI_NUM_VERTEX_BUFFERS
; i
++)
2692 pipe_vertex_buffer_unreference(&sctx
->vertex_buffer
[i
]);
2694 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2695 si_release_descriptors(&sctx
->descriptors
[i
]);
2697 sctx
->vertex_buffers
.list
= NULL
; /* points into a mapped buffer */
2698 si_release_descriptors(&sctx
->vertex_buffers
);
2699 si_release_bindless_descriptors(sctx
);
2702 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
2706 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2707 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2708 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
]);
2709 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
2711 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2712 si_vertex_buffers_begin_new_cs(sctx
);
2714 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2715 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
2716 si_descriptors_begin_new_cs(sctx
, &sctx
->bindless_descriptors
);
2718 si_shader_pointers_begin_new_cs(sctx
);
2721 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
2722 uint64_t new_active_mask
)
2724 struct si_descriptors
*desc
= &sctx
->descriptors
[desc_idx
];
2726 /* Ignore no-op updates and updates that disable all slots. */
2727 if (!new_active_mask
||
2728 new_active_mask
== u_bit_consecutive64(desc
->first_active_slot
,
2729 desc
->num_active_slots
))
2733 u_bit_scan_consecutive_range64(&new_active_mask
, &first
, &count
);
2734 assert(new_active_mask
== 0);
2736 /* Upload/dump descriptors if slots are being enabled. */
2737 if (first
< desc
->first_active_slot
||
2738 first
+ count
> desc
->first_active_slot
+ desc
->num_active_slots
)
2739 sctx
->descriptors_dirty
|= 1u << desc_idx
;
2741 desc
->first_active_slot
= first
;
2742 desc
->num_active_slots
= count
;
2745 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
2746 struct si_shader_selector
*sel
)
2751 si_set_active_descriptors(sctx
,
2752 si_const_and_shader_buffer_descriptors_idx(sel
->type
),
2753 sel
->active_const_and_shader_buffers
);
2754 si_set_active_descriptors(sctx
,
2755 si_sampler_and_image_descriptors_idx(sel
->type
),
2756 sel
->active_samplers_and_images
);