src/gallium/drivers/radeonsi/si_descriptors.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Marek Olšák <marek.olsak@amd.com>
  25  */
  26 #include "../radeon/r600_cs.h"
  27 #include "radeonsi_pipe.h"
  28 #include "radeonsi_resource.h"
  29 #include "radeonsi_shader.h"
  30
  31 #include "util/u_memory.h"
  32
  33 #define SI_NUM_CONTEXTS 256
  34
  35 static const uint32_t null_desc[8]; /* zeros */
  36
  37 /* Set this if you want the 3D engine to wait until CP DMA is done.
  38  * It should be set on the last CP DMA packet. */
  39 #define R600_CP_DMA_SYNC        (1 << 0) /* R600+ */
  40
  41 /* Set this if the source data was used as a destination in a previous CP DMA
  42  * packet. It's for preventing a read-after-write (RAW) hazard between two
  43  * CP DMA packets. */
  44 #define SI_CP_DMA_RAW_WAIT      (1 << 1) /* SI+ */
  45
  46 /* Emit a CP DMA packet to do a copy from one buffer to another.
  47  * The size must fit in bits [20:0]. Notes:
  48  */
  49 static void si_emit_cp_dma_copy_buffer(struct r600_context *rctx,
  50                                        uint64_t dst_va, uint64_t src_va,
  51                                        unsigned size, unsigned flags)
  52 {
  53         struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
  54         uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? PKT3_CP_DMA_CP_SYNC : 0;
  55         uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? PKT3_CP_DMA_CMD_RAW_WAIT : 0;
  56
  57         assert(size);
  58         assert((size & ((1<<21)-1)) == size);
  59
  60         if (rctx->b.chip_class >= CIK) {
  61                 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
  62                 radeon_emit(cs, sync_flag);             /* CP_SYNC [31] */
  63                 radeon_emit(cs, src_va);                /* SRC_ADDR_LO [31:0] */
  64                 radeon_emit(cs, src_va >> 32);          /* SRC_ADDR_HI [31:0] */
  65                 radeon_emit(cs, dst_va);                /* DST_ADDR_LO [31:0] */
  66                 radeon_emit(cs, dst_va >> 32);          /* DST_ADDR_HI [31:0] */
  67                 radeon_emit(cs, size | raw_wait);       /* COMMAND [29:22] | BYTE_COUNT [20:0] */
  68         } else {
  69                 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
  70                 radeon_emit(cs, src_va);                        /* SRC_ADDR_LO [31:0] */
  71                 radeon_emit(cs, sync_flag | ((src_va >> 32) & 0xffff)); /* CP_SYNC [31] | SRC_ADDR_HI [15:0] */
  72                 radeon_emit(cs, dst_va);                        /* DST_ADDR_LO [31:0] */
  73                 radeon_emit(cs, (dst_va >> 32) & 0xffff);       /* DST_ADDR_HI [15:0] */
  74                 radeon_emit(cs, size | raw_wait);               /* COMMAND [29:22] | BYTE_COUNT [20:0] */
  75         }
  76 }
  77
  78 /* Emit a CP DMA packet to clear a buffer. The size must fit in bits [20:0]. */
  79 static void si_emit_cp_dma_clear_buffer(struct r600_context *rctx,
  80                                         uint64_t dst_va, unsigned size,
  81                                         uint32_t clear_value, unsigned flags)
  82 {
  83         struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
  84         uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? PKT3_CP_DMA_CP_SYNC : 0;
  85         uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? PKT3_CP_DMA_CMD_RAW_WAIT : 0;
  86
  87         assert(size);
  88         assert((size & ((1<<21)-1)) == size);
  89
  90         if (rctx->b.chip_class >= CIK) {
  91                 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
  92                 radeon_emit(cs, sync_flag | PKT3_CP_DMA_SRC_SEL(2)); /* CP_SYNC [31] | SRC_SEL[30:29] */
  93                 radeon_emit(cs, clear_value);           /* DATA [31:0] */
  94                 radeon_emit(cs, 0);
  95                 radeon_emit(cs, dst_va);                /* DST_ADDR_LO [31:0] */
  96                 radeon_emit(cs, dst_va >> 32);          /* DST_ADDR_HI [15:0] */
  97                 radeon_emit(cs, size | raw_wait);       /* COMMAND [29:22] | BYTE_COUNT [20:0] */
  98         } else {
  99                 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
 100                 radeon_emit(cs, clear_value);           /* DATA [31:0] */
 101                 radeon_emit(cs, sync_flag | PKT3_CP_DMA_SRC_SEL(2)); /* CP_SYNC [31] | SRC_SEL[30:29] */
 102                 radeon_emit(cs, dst_va);                        /* DST_ADDR_LO [31:0] */
 103                 radeon_emit(cs, (dst_va >> 32) & 0xffff);       /* DST_ADDR_HI [15:0] */
 104                 radeon_emit(cs, size | raw_wait);               /* COMMAND [29:22] | BYTE_COUNT [20:0] */
 105         }
 106 }
 107
 108 static void si_init_descriptors(struct r600_context *rctx,
 109                                 struct si_descriptors *desc,
 110                                 unsigned shader_userdata_reg,
 111                                 unsigned element_dw_size,
 112                                 unsigned num_elements,
 113                                 void (*emit_func)(struct r600_context *ctx, struct r600_atom *state))
 114 {
 115         uint64_t va;
 116
 117         assert(num_elements <= sizeof(desc->enabled_mask)*8);
 118         assert(num_elements <= sizeof(desc->dirty_mask)*8);
 119
 120         desc->atom.emit = (void*)emit_func;
 121         desc->shader_userdata_reg = shader_userdata_reg;
 122         desc->element_dw_size = element_dw_size;
 123         desc->num_elements = num_elements;
 124         desc->context_size = num_elements * element_dw_size * 4;
 125
 126         desc->buffer = (struct r600_resource*)
 127                 pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
 128                                    PIPE_USAGE_STATIC,
 129                                    SI_NUM_CONTEXTS * desc->context_size);
 130
 131         r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, desc->buffer, RADEON_USAGE_READWRITE);
 132         va = r600_resource_va(rctx->b.b.screen, &desc->buffer->b.b);
 133
 134         /* We don't check for CS space here, because this should be called
 135          * only once at context initialization. */
 136         si_emit_cp_dma_clear_buffer(rctx, va, desc->buffer->b.b.width0, 0,
 137                                     R600_CP_DMA_SYNC);
 138 }
 139
 140 static void si_release_descriptors(struct si_descriptors *desc)
 141 {
 142         pipe_resource_reference((struct pipe_resource**)&desc->buffer, NULL);
 143 }
 144
 145 static void si_update_descriptors(struct si_descriptors *desc)
 146 {
 147         if (desc->dirty_mask) {
 148                 desc->atom.num_dw =
 149                         7 + /* copy */
 150                         (4 + desc->element_dw_size) * util_bitcount(desc->dirty_mask) + /* update */
 151                         4; /* pointer update */
 152                 desc->atom.dirty = true;
 153         } else {
 154                 desc->atom.dirty = false;
 155         }
 156 }
 157
 158 static void si_emit_shader_pointer(struct r600_context *rctx,
 159                                    struct si_descriptors *desc)
 160 {
 161         struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
 162         uint64_t va = r600_resource_va(rctx->b.b.screen, &desc->buffer->b.b) +
 163                       desc->current_context_id * desc->context_size;
 164
 165         radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0));
 166         radeon_emit(cs, (desc->shader_userdata_reg - SI_SH_REG_OFFSET) >> 2);
 167         radeon_emit(cs, va);
 168         radeon_emit(cs, va >> 32);
 169 }
 170
 171 static void si_emit_descriptors(struct r600_context *rctx,
 172                                 struct si_descriptors *desc,
 173                                 const uint32_t **descriptors)
 174 {
 175         struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
 176         uint64_t va_base;
 177         int packet_start;
 178         int packet_size = 0;
 179         int last_index = desc->num_elements; /* point to a non-existing element */
 180         unsigned dirty_mask = desc->dirty_mask;
 181         unsigned new_context_id = (desc->current_context_id + 1) % SI_NUM_CONTEXTS;
 182
 183         assert(dirty_mask);
 184
 185         va_base = r600_resource_va(rctx->b.b.screen, &desc->buffer->b.b);
 186
 187         /* Copy the descriptors to a new context slot. */
 188         si_emit_cp_dma_copy_buffer(rctx,
 189                                    va_base + new_context_id * desc->context_size,
 190                                    va_base + desc->current_context_id * desc->context_size,
 191                                    desc->context_size, R600_CP_DMA_SYNC);
 192
 193         va_base += new_context_id * desc->context_size;
 194
 195         /* Update the descriptors.
 196          * Updates of consecutive descriptors are merged to one WRITE_DATA packet.
 197          *
 198          * XXX When unbinding lots of resources, consider clearing the memory
 199          *     with CP DMA instead of emitting zeros.
 200          */
 201         while (dirty_mask) {
 202                 int i = u_bit_scan(&dirty_mask);
 203
 204                 assert(i < desc->num_elements);
 205
 206                 if (last_index+1 == i && packet_size) {
 207                         /* Append new data at the end of the last packet. */
 208                         packet_size += desc->element_dw_size;
 209                         cs->buf[packet_start] = PKT3(PKT3_WRITE_DATA, packet_size, 0);
 210                 } else {
 211                         /* Start a new packet. */
 212                         uint64_t va = va_base + i * desc->element_dw_size * 4;
 213
 214                         packet_start = cs->cdw;
 215                         packet_size = 2 + desc->element_dw_size;
 216
 217                         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, packet_size, 0));
 218                         radeon_emit(cs, PKT3_WRITE_DATA_DST_SEL(PKT3_WRITE_DATA_DST_SEL_MEM_SYNC) |
 219                                              PKT3_WRITE_DATA_WR_CONFIRM |
 220                                              PKT3_WRITE_DATA_ENGINE_SEL(PKT3_WRITE_DATA_ENGINE_SEL_ME));
 221                         radeon_emit(cs, va & 0xFFFFFFFFUL);
 222                         radeon_emit(cs, (va >> 32UL) & 0xFFFFFFFFUL);
 223                 }
 224
 225                 radeon_emit_array(cs, descriptors[i], desc->element_dw_size);
 226
 227                 last_index = i;
 228         }
 229
 230         desc->dirty_mask = 0;
 231         desc->current_context_id = new_context_id;
 232
 233         /* Now update the shader userdata pointer. */
 234         si_emit_shader_pointer(rctx, desc);
 235 }
 236
 237 static unsigned si_get_shader_user_data_base(unsigned shader)
 238 {
 239         switch (shader) {
 240         case PIPE_SHADER_VERTEX:
 241                 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
 242         case PIPE_SHADER_GEOMETRY:
 243                 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
 244         case PIPE_SHADER_FRAGMENT:
 245                 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
 246         default:
 247                 assert(0);
 248                 return 0;
 249         }
 250 }
 251
 252 /* SAMPLER VIEWS */
 253
 254 static void si_emit_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
 255 {
 256         struct si_sampler_views *views = (struct si_sampler_views*)atom;
 257
 258         si_emit_descriptors(rctx, &views->desc, views->desc_data);
 259 }
 260
 261 static void si_init_sampler_views(struct r600_context *rctx,
 262                                   struct si_sampler_views *views,
 263                                   unsigned shader)
 264 {
 265         si_init_descriptors(rctx, &views->desc,
 266                             si_get_shader_user_data_base(shader) +
 267                             SI_SGPR_RESOURCE * 4,
 268                             8, NUM_SAMPLER_VIEWS, si_emit_sampler_views);
 269 }
 270
 271 static void si_release_sampler_views(struct si_sampler_views *views)
 272 {
 273         int i;
 274
 275         for (i = 0; i < Elements(views->views); i++) {
 276                 pipe_sampler_view_reference(&views->views[i], NULL);
 277         }
 278         si_release_descriptors(&views->desc);
 279 }
 280
 281 static void si_sampler_views_begin_new_cs(struct r600_context *rctx,
 282                                           struct si_sampler_views *views)
 283 {
 284         unsigned mask = views->desc.enabled_mask;
 285
 286         /* Add relocations to the CS. */
 287         while (mask) {
 288                 int i = u_bit_scan(&mask);
 289                 struct si_pipe_sampler_view *rview =
 290                         (struct si_pipe_sampler_view*)views->views[i];
 291
 292                 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->resource, RADEON_USAGE_READ);
 293         }
 294
 295         r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, views->desc.buffer, RADEON_USAGE_READWRITE);
 296
 297         si_emit_shader_pointer(rctx, &views->desc);
 298 }
 299
 300 void si_set_sampler_view(struct r600_context *rctx, unsigned shader,
 301                          unsigned slot, struct pipe_sampler_view *view,
 302                          unsigned *view_desc)
 303 {
 304         struct si_sampler_views *views = &rctx->samplers[shader].views;
 305
 306         if (views->views[slot] == view)
 307                 return;
 308
 309         if (view) {
 310                 struct si_pipe_sampler_view *rview =
 311                         (struct si_pipe_sampler_view*)view;
 312
 313                 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->resource, RADEON_USAGE_READ);
 314
 315                 pipe_sampler_view_reference(&views->views[slot], view);
 316                 views->desc_data[slot] = view_desc;
 317                 views->desc.enabled_mask |= 1 << slot;
 318         } else {
 319                 pipe_sampler_view_reference(&views->views[slot], NULL);
 320                 views->desc_data[slot] = null_desc;
 321                 views->desc.enabled_mask &= ~(1 << slot);
 322         }
 323
 324         views->desc.dirty_mask |= 1 << slot;
 325         si_update_descriptors(&views->desc);
 326 }
 327
 328 /* INIT/DEINIT */
 329
 330 void si_init_all_descriptors(struct r600_context *rctx)
 331 {
 332         int i;
 333
 334         for (i = 0; i < SI_NUM_SHADERS; i++) {
 335                 si_init_sampler_views(rctx, &rctx->samplers[i].views, i);
 336
 337                 rctx->atoms.sampler_views[i] = &rctx->samplers[i].views.desc.atom;
 338         }
 339 }
 340
 341 void si_release_all_descriptors(struct r600_context *rctx)
 342 {
 343         int i;
 344
 345         for (i = 0; i < SI_NUM_SHADERS; i++) {
 346                 si_release_sampler_views(&rctx->samplers[i].views);
 347         }
 348 }
 349
 350 void si_all_descriptors_begin_new_cs(struct r600_context *rctx)
 351 {
 352         int i;
 353
 354         for (i = 0; i < SI_NUM_SHADERS; i++) {
 355                 si_sampler_views_begin_new_cs(rctx, &rctx->samplers[i].views);
 356         }
 357 }