2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Marek Olšák <marek.olsak@amd.com>
26 #include "../radeon/r600_cs.h"
28 #include "si_resource.h"
29 #include "si_shader.h"
31 #include "util/u_memory.h"
33 #define SI_NUM_CONTEXTS 16
35 static uint32_t null_desc
[8]; /* zeros */
37 /* Set this if you want the 3D engine to wait until CP DMA is done.
38 * It should be set on the last CP DMA packet. */
39 #define R600_CP_DMA_SYNC (1 << 0) /* R600+ */
41 /* Set this if the source data was used as a destination in a previous CP DMA
42 * packet. It's for preventing a read-after-write (RAW) hazard between two
44 #define SI_CP_DMA_RAW_WAIT (1 << 1) /* SI+ */
46 /* Emit a CP DMA packet to do a copy from one buffer to another.
47 * The size must fit in bits [20:0].
49 static void si_emit_cp_dma_copy_buffer(struct si_context
*sctx
,
50 uint64_t dst_va
, uint64_t src_va
,
51 unsigned size
, unsigned flags
)
53 struct radeon_winsys_cs
*cs
= sctx
->b
.rings
.gfx
.cs
;
54 uint32_t sync_flag
= flags
& R600_CP_DMA_SYNC
? PKT3_CP_DMA_CP_SYNC
: 0;
55 uint32_t raw_wait
= flags
& SI_CP_DMA_RAW_WAIT
? PKT3_CP_DMA_CMD_RAW_WAIT
: 0;
58 assert((size
& ((1<<21)-1)) == size
);
60 if (sctx
->b
.chip_class
>= CIK
) {
61 radeon_emit(cs
, PKT3(PKT3_DMA_DATA
, 5, 0));
62 radeon_emit(cs
, sync_flag
); /* CP_SYNC [31] */
63 radeon_emit(cs
, src_va
); /* SRC_ADDR_LO [31:0] */
64 radeon_emit(cs
, src_va
>> 32); /* SRC_ADDR_HI [31:0] */
65 radeon_emit(cs
, dst_va
); /* DST_ADDR_LO [31:0] */
66 radeon_emit(cs
, dst_va
>> 32); /* DST_ADDR_HI [31:0] */
67 radeon_emit(cs
, size
| raw_wait
); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
69 radeon_emit(cs
, PKT3(PKT3_CP_DMA
, 4, 0));
70 radeon_emit(cs
, src_va
); /* SRC_ADDR_LO [31:0] */
71 radeon_emit(cs
, sync_flag
| ((src_va
>> 32) & 0xffff)); /* CP_SYNC [31] | SRC_ADDR_HI [15:0] */
72 radeon_emit(cs
, dst_va
); /* DST_ADDR_LO [31:0] */
73 radeon_emit(cs
, (dst_va
>> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
74 radeon_emit(cs
, size
| raw_wait
); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
78 /* Emit a CP DMA packet to clear a buffer. The size must fit in bits [20:0]. */
79 static void si_emit_cp_dma_clear_buffer(struct si_context
*sctx
,
80 uint64_t dst_va
, unsigned size
,
81 uint32_t clear_value
, unsigned flags
)
83 struct radeon_winsys_cs
*cs
= sctx
->b
.rings
.gfx
.cs
;
84 uint32_t sync_flag
= flags
& R600_CP_DMA_SYNC
? PKT3_CP_DMA_CP_SYNC
: 0;
85 uint32_t raw_wait
= flags
& SI_CP_DMA_RAW_WAIT
? PKT3_CP_DMA_CMD_RAW_WAIT
: 0;
88 assert((size
& ((1<<21)-1)) == size
);
90 if (sctx
->b
.chip_class
>= CIK
) {
91 radeon_emit(cs
, PKT3(PKT3_DMA_DATA
, 5, 0));
92 radeon_emit(cs
, sync_flag
| PKT3_CP_DMA_SRC_SEL(2)); /* CP_SYNC [31] | SRC_SEL[30:29] */
93 radeon_emit(cs
, clear_value
); /* DATA [31:0] */
95 radeon_emit(cs
, dst_va
); /* DST_ADDR_LO [31:0] */
96 radeon_emit(cs
, dst_va
>> 32); /* DST_ADDR_HI [15:0] */
97 radeon_emit(cs
, size
| raw_wait
); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
99 radeon_emit(cs
, PKT3(PKT3_CP_DMA
, 4, 0));
100 radeon_emit(cs
, clear_value
); /* DATA [31:0] */
101 radeon_emit(cs
, sync_flag
| PKT3_CP_DMA_SRC_SEL(2)); /* CP_SYNC [31] | SRC_SEL[30:29] */
102 radeon_emit(cs
, dst_va
); /* DST_ADDR_LO [31:0] */
103 radeon_emit(cs
, (dst_va
>> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
104 radeon_emit(cs
, size
| raw_wait
); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
108 static void si_init_descriptors(struct si_context
*sctx
,
109 struct si_descriptors
*desc
,
110 unsigned shader_userdata_reg
,
111 unsigned element_dw_size
,
112 unsigned num_elements
,
113 void (*emit_func
)(struct si_context
*ctx
, struct r600_atom
*state
))
117 assert(num_elements
<= sizeof(desc
->enabled_mask
)*8);
118 assert(num_elements
<= sizeof(desc
->dirty_mask
)*8);
120 desc
->atom
.emit
= (void*)emit_func
;
121 desc
->shader_userdata_reg
= shader_userdata_reg
;
122 desc
->element_dw_size
= element_dw_size
;
123 desc
->num_elements
= num_elements
;
124 desc
->context_size
= num_elements
* element_dw_size
* 4;
126 desc
->buffer
= (struct r600_resource
*)
127 pipe_buffer_create(sctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
129 SI_NUM_CONTEXTS
* desc
->context_size
);
131 r600_context_bo_reloc(&sctx
->b
, &sctx
->b
.rings
.gfx
, desc
->buffer
, RADEON_USAGE_READWRITE
);
132 va
= r600_resource_va(sctx
->b
.b
.screen
, &desc
->buffer
->b
.b
);
134 /* We don't check for CS space here, because this should be called
135 * only once at context initialization. */
136 si_emit_cp_dma_clear_buffer(sctx
, va
, desc
->buffer
->b
.b
.width0
, 0,
140 static void si_release_descriptors(struct si_descriptors
*desc
)
142 pipe_resource_reference((struct pipe_resource
**)&desc
->buffer
, NULL
);
145 static void si_update_descriptors(struct si_context
*sctx
,
146 struct si_descriptors
*desc
)
148 if (desc
->dirty_mask
) {
151 (4 + desc
->element_dw_size
) * util_bitcount(desc
->dirty_mask
) + /* update */
152 4; /* pointer update */
153 desc
->atom
.dirty
= true;
154 /* The descriptors are read with the K cache. */
155 sctx
->b
.flags
|= R600_CONTEXT_INV_CONST_CACHE
;
157 desc
->atom
.dirty
= false;
161 static void si_emit_shader_pointer(struct si_context
*sctx
,
162 struct si_descriptors
*desc
)
164 struct radeon_winsys_cs
*cs
= sctx
->b
.rings
.gfx
.cs
;
165 uint64_t va
= r600_resource_va(sctx
->b
.b
.screen
, &desc
->buffer
->b
.b
) +
166 desc
->current_context_id
* desc
->context_size
;
168 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, 2, 0));
169 radeon_emit(cs
, (desc
->shader_userdata_reg
- SI_SH_REG_OFFSET
) >> 2);
171 radeon_emit(cs
, va
>> 32);
174 static void si_emit_descriptors(struct si_context
*sctx
,
175 struct si_descriptors
*desc
,
176 uint32_t **descriptors
)
178 struct radeon_winsys_cs
*cs
= sctx
->b
.rings
.gfx
.cs
;
182 int last_index
= desc
->num_elements
; /* point to a non-existing element */
183 unsigned dirty_mask
= desc
->dirty_mask
;
184 unsigned new_context_id
= (desc
->current_context_id
+ 1) % SI_NUM_CONTEXTS
;
188 va_base
= r600_resource_va(sctx
->b
.b
.screen
, &desc
->buffer
->b
.b
);
190 /* Copy the descriptors to a new context slot. */
191 /* XXX Consider using TC or L2 for this copy on CIK. */
192 si_emit_cp_dma_copy_buffer(sctx
,
193 va_base
+ new_context_id
* desc
->context_size
,
194 va_base
+ desc
->current_context_id
* desc
->context_size
,
195 desc
->context_size
, R600_CP_DMA_SYNC
);
197 va_base
+= new_context_id
* desc
->context_size
;
199 /* Update the descriptors.
200 * Updates of consecutive descriptors are merged to one WRITE_DATA packet.
202 * XXX When unbinding lots of resources, consider clearing the memory
203 * with CP DMA instead of emitting zeros.
206 int i
= u_bit_scan(&dirty_mask
);
208 assert(i
< desc
->num_elements
);
210 if (last_index
+1 == i
&& packet_size
) {
211 /* Append new data at the end of the last packet. */
212 packet_size
+= desc
->element_dw_size
;
213 cs
->buf
[packet_start
] = PKT3(PKT3_WRITE_DATA
, packet_size
, 0);
215 /* Start a new packet. */
216 uint64_t va
= va_base
+ i
* desc
->element_dw_size
* 4;
218 packet_start
= cs
->cdw
;
219 packet_size
= 2 + desc
->element_dw_size
;
221 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, packet_size
, 0));
222 radeon_emit(cs
, PKT3_WRITE_DATA_DST_SEL(PKT3_WRITE_DATA_DST_SEL_TC_OR_L2
) |
223 PKT3_WRITE_DATA_WR_CONFIRM
|
224 PKT3_WRITE_DATA_ENGINE_SEL(PKT3_WRITE_DATA_ENGINE_SEL_ME
));
225 radeon_emit(cs
, va
& 0xFFFFFFFFUL
);
226 radeon_emit(cs
, (va
>> 32UL) & 0xFFFFFFFFUL
);
229 radeon_emit_array(cs
, descriptors
[i
], desc
->element_dw_size
);
234 desc
->dirty_mask
= 0;
235 desc
->current_context_id
= new_context_id
;
237 /* Now update the shader userdata pointer. */
238 si_emit_shader_pointer(sctx
, desc
);
241 static unsigned si_get_shader_user_data_base(unsigned shader
)
244 case PIPE_SHADER_VERTEX
:
245 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
246 case PIPE_SHADER_GEOMETRY
:
247 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
248 case PIPE_SHADER_FRAGMENT
:
249 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
258 static void si_emit_sampler_views(struct si_context
*sctx
, struct r600_atom
*atom
)
260 struct si_sampler_views
*views
= (struct si_sampler_views
*)atom
;
262 si_emit_descriptors(sctx
, &views
->desc
, views
->desc_data
);
265 static void si_init_sampler_views(struct si_context
*sctx
,
266 struct si_sampler_views
*views
,
269 si_init_descriptors(sctx
, &views
->desc
,
270 si_get_shader_user_data_base(shader
) +
271 SI_SGPR_RESOURCE
* 4,
272 8, NUM_SAMPLER_VIEWS
, si_emit_sampler_views
);
275 static void si_release_sampler_views(struct si_sampler_views
*views
)
279 for (i
= 0; i
< Elements(views
->views
); i
++) {
280 pipe_sampler_view_reference(&views
->views
[i
], NULL
);
282 si_release_descriptors(&views
->desc
);
285 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
,
286 struct si_sampler_views
*views
)
288 unsigned mask
= views
->desc
.enabled_mask
;
290 /* Add relocations to the CS. */
292 int i
= u_bit_scan(&mask
);
293 struct si_pipe_sampler_view
*rview
=
294 (struct si_pipe_sampler_view
*)views
->views
[i
];
296 r600_context_bo_reloc(&sctx
->b
, &sctx
->b
.rings
.gfx
, rview
->resource
, RADEON_USAGE_READ
);
299 r600_context_bo_reloc(&sctx
->b
, &sctx
->b
.rings
.gfx
, views
->desc
.buffer
, RADEON_USAGE_READWRITE
);
301 si_emit_shader_pointer(sctx
, &views
->desc
);
304 void si_set_sampler_view(struct si_context
*sctx
, unsigned shader
,
305 unsigned slot
, struct pipe_sampler_view
*view
,
308 struct si_sampler_views
*views
= &sctx
->samplers
[shader
].views
;
310 if (views
->views
[slot
] == view
)
314 struct si_pipe_sampler_view
*rview
=
315 (struct si_pipe_sampler_view
*)view
;
317 r600_context_bo_reloc(&sctx
->b
, &sctx
->b
.rings
.gfx
, rview
->resource
, RADEON_USAGE_READ
);
319 pipe_sampler_view_reference(&views
->views
[slot
], view
);
320 views
->desc_data
[slot
] = view_desc
;
321 views
->desc
.enabled_mask
|= 1 << slot
;
323 pipe_sampler_view_reference(&views
->views
[slot
], NULL
);
324 views
->desc_data
[slot
] = null_desc
;
325 views
->desc
.enabled_mask
&= ~(1 << slot
);
328 views
->desc
.dirty_mask
|= 1 << slot
;
329 si_update_descriptors(sctx
, &views
->desc
);
332 /* BUFFER RESOURCES */
334 static void si_emit_buffer_resources(struct si_context
*sctx
, struct r600_atom
*atom
)
336 struct si_buffer_resources
*buffers
= (struct si_buffer_resources
*)atom
;
338 si_emit_descriptors(sctx
, &buffers
->desc
, buffers
->desc_data
);
341 static void si_init_buffer_resources(struct si_context
*sctx
,
342 struct si_buffer_resources
*buffers
,
343 unsigned num_buffers
, unsigned shader
,
344 unsigned shader_userdata_index
,
345 enum radeon_bo_usage shader_usage
)
349 buffers
->num_buffers
= num_buffers
;
350 buffers
->shader_usage
= shader_usage
;
351 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
352 buffers
->desc_storage
= CALLOC(num_buffers
, sizeof(uint32_t) * 4);
354 /* si_emit_descriptors only accepts an array of arrays.
355 * This adds such an array. */
356 buffers
->desc_data
= CALLOC(num_buffers
, sizeof(uint32_t*));
357 for (i
= 0; i
< num_buffers
; i
++) {
358 buffers
->desc_data
[i
] = &buffers
->desc_storage
[i
*4];
361 si_init_descriptors(sctx
, &buffers
->desc
,
362 si_get_shader_user_data_base(shader
) +
363 shader_userdata_index
*4, 4, num_buffers
,
364 si_emit_buffer_resources
);
367 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
)
371 for (i
= 0; i
< Elements(buffers
->buffers
); i
++) {
372 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
375 FREE(buffers
->buffers
);
376 FREE(buffers
->desc_storage
);
377 FREE(buffers
->desc_data
);
378 si_release_descriptors(&buffers
->desc
);
381 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
382 struct si_buffer_resources
*buffers
)
384 unsigned mask
= buffers
->desc
.enabled_mask
;
386 /* Add relocations to the CS. */
388 int i
= u_bit_scan(&mask
);
390 r600_context_bo_reloc(&sctx
->b
, &sctx
->b
.rings
.gfx
,
391 (struct r600_resource
*)buffers
->buffers
[i
],
392 buffers
->shader_usage
);
395 r600_context_bo_reloc(&sctx
->b
, &sctx
->b
.rings
.gfx
,
396 buffers
->desc
.buffer
, RADEON_USAGE_READWRITE
);
398 si_emit_shader_pointer(sctx
, &buffers
->desc
);
401 /* CONSTANT BUFFERS */
403 static void si_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint slot
,
404 struct pipe_constant_buffer
*input
)
406 struct si_context
*sctx
= (struct si_context
*)ctx
;
407 struct si_buffer_resources
*buffers
= &sctx
->const_buffers
[shader
];
409 if (shader
>= SI_NUM_SHADERS
)
412 assert(slot
< buffers
->num_buffers
);
413 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
415 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
416 * with a NULL buffer). We need to use a dummy buffer instead. */
417 if (sctx
->b
.chip_class
== CIK
&&
418 (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
419 input
= &sctx
->null_const_buf
;
421 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
422 struct pipe_resource
*buffer
= NULL
;
425 /* Upload the user buffer if needed. */
426 if (input
->user_buffer
) {
427 unsigned buffer_offset
;
429 si_upload_const_buffer(sctx
,
430 (struct r600_resource
**)&buffer
, input
->user_buffer
,
431 input
->buffer_size
, &buffer_offset
);
432 va
= r600_resource_va(ctx
->screen
, buffer
) + buffer_offset
;
434 pipe_resource_reference(&buffer
, input
->buffer
);
435 va
= r600_resource_va(ctx
->screen
, buffer
) + input
->buffer_offset
;
438 /* Set the descriptor. */
439 uint32_t *desc
= buffers
->desc_data
[slot
];
441 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
443 desc
[2] = input
->buffer_size
;
444 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
445 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
446 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
447 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
448 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
449 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
451 buffers
->buffers
[slot
] = buffer
;
452 r600_context_bo_reloc(&sctx
->b
, &sctx
->b
.rings
.gfx
,
453 (struct r600_resource
*)buffer
, buffers
->shader_usage
);
454 buffers
->desc
.enabled_mask
|= 1 << slot
;
456 /* Clear the descriptor. */
457 memset(buffers
->desc_data
[slot
], 0, sizeof(uint32_t) * 4);
458 buffers
->desc
.enabled_mask
&= ~(1 << slot
);
461 buffers
->desc
.dirty_mask
|= 1 << slot
;
462 si_update_descriptors(sctx
, &buffers
->desc
);
465 /* STREAMOUT BUFFERS */
467 static void si_set_streamout_targets(struct pipe_context
*ctx
,
468 unsigned num_targets
,
469 struct pipe_stream_output_target
**targets
,
470 unsigned append_bitmask
)
472 struct si_context
*sctx
= (struct si_context
*)ctx
;
473 struct si_buffer_resources
*buffers
= &sctx
->streamout_buffers
;
474 unsigned old_num_targets
= sctx
->b
.streamout
.num_targets
;
477 /* Streamout buffers must be bound in 2 places:
478 * 1) in VGT by setting the VGT_STRMOUT registers
479 * 2) as shader resources
482 /* Set the VGT regs. */
483 r600_set_streamout_targets(ctx
, num_targets
, targets
, append_bitmask
);
485 /* Set the shader resources.*/
486 for (i
= 0; i
< num_targets
; i
++) {
488 struct pipe_resource
*buffer
= targets
[i
]->buffer
;
489 uint64_t va
= r600_resource_va(ctx
->screen
, buffer
);
491 /* Set the descriptor. */
492 uint32_t *desc
= buffers
->desc_data
[i
];
494 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
495 desc
[2] = 0xffffffff;
496 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
497 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
498 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
499 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
501 /* Set the resource. */
502 pipe_resource_reference(&buffers
->buffers
[i
], buffer
);
503 r600_context_bo_reloc(&sctx
->b
, &sctx
->b
.rings
.gfx
,
504 (struct r600_resource
*)buffer
,
505 buffers
->shader_usage
);
506 buffers
->desc
.enabled_mask
|= 1 << i
;
508 /* Clear the descriptor and unset the resource. */
509 memset(buffers
->desc_data
[i
], 0, sizeof(uint32_t) * 4);
510 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
511 buffers
->desc
.enabled_mask
&= ~(1 << i
);
513 buffers
->desc
.dirty_mask
|= 1 << i
;
515 for (; i
< old_num_targets
; i
++) {
516 /* Clear the descriptor and unset the resource. */
517 memset(buffers
->desc_data
[i
], 0, sizeof(uint32_t) * 4);
518 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
519 buffers
->desc
.enabled_mask
&= ~(1 << i
);
520 buffers
->desc
.dirty_mask
|= 1 << i
;
523 si_update_descriptors(sctx
, &buffers
->desc
);
526 static void si_desc_reset_buffer_offset(struct pipe_context
*ctx
,
527 uint32_t *desc
, uint64_t old_buf_va
,
528 struct pipe_resource
*new_buf
)
530 /* Retrieve the buffer offset from the descriptor. */
531 uint64_t old_desc_va
=
532 desc
[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
534 assert(old_buf_va
<= old_desc_va
);
535 uint64_t offset_within_buffer
= old_desc_va
- old_buf_va
;
537 /* Update the descriptor. */
538 uint64_t va
= r600_resource_va(ctx
->screen
, new_buf
) + offset_within_buffer
;
541 desc
[1] = (desc
[1] & C_008F04_BASE_ADDRESS_HI
) |
542 S_008F04_BASE_ADDRESS_HI(va
>> 32);
545 /* BUFFER DISCARD/INVALIDATION */
547 /* Reallocate a buffer a update all resource bindings where the buffer is
550 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
551 * idle by discarding its contents. Apps usually tell us when to do this using
552 * map_buffer flags, for example.
554 static void si_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
556 struct si_context
*sctx
= (struct si_context
*)ctx
;
557 struct r600_resource
*rbuffer
= r600_resource(buf
);
558 unsigned i
, shader
, alignment
= rbuffer
->buf
->alignment
;
559 uint64_t old_va
= r600_resource_va(ctx
->screen
, buf
);
561 /* Discard the buffer. */
562 pb_reference(&rbuffer
->buf
, NULL
);
564 /* Create a new one in the same pipe_resource. */
565 r600_init_resource(&sctx
->screen
->b
, rbuffer
, rbuffer
->b
.b
.width0
, alignment
,
566 TRUE
, rbuffer
->b
.b
.usage
);
568 /* We changed the buffer, now we need to bind it where the old one
569 * was bound. This consists of 2 things:
570 * 1) Updating the resource descriptor and dirtying it.
571 * 2) Adding a relocation to the CS, so that it's usable.
574 /* Vertex buffers. */
575 /* Nothing to do. Vertex buffer bindings are updated before every draw call. */
577 /* Streamout buffers. */
578 for (i
= 0; i
< sctx
->streamout_buffers
.num_buffers
; i
++) {
579 if (sctx
->streamout_buffers
.buffers
[i
] == buf
) {
580 /* Update the descriptor. */
581 si_desc_reset_buffer_offset(ctx
, sctx
->streamout_buffers
.desc_data
[i
],
584 r600_context_bo_reloc(&sctx
->b
, &sctx
->b
.rings
.gfx
,
585 (struct r600_resource
*)buf
,
586 sctx
->streamout_buffers
.shader_usage
);
587 sctx
->streamout_buffers
.desc
.dirty_mask
|= 1 << i
;
588 si_update_descriptors(sctx
, &sctx
->streamout_buffers
.desc
);
590 /* Update the streamout state. */
591 if (sctx
->b
.streamout
.begin_emitted
) {
592 r600_emit_streamout_end(&sctx
->b
);
594 sctx
->b
.streamout
.append_bitmask
= sctx
->b
.streamout
.enabled_mask
;
595 r600_streamout_buffers_dirty(&sctx
->b
);
599 /* Constant buffers. */
600 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
601 struct si_buffer_resources
*buffers
= &sctx
->const_buffers
[shader
];
603 uint32_t mask
= buffers
->desc
.enabled_mask
;
606 unsigned i
= u_bit_scan(&mask
);
607 if (buffers
->buffers
[i
] == buf
) {
608 si_desc_reset_buffer_offset(ctx
, buffers
->desc_data
[i
],
611 r600_context_bo_reloc(&sctx
->b
, &sctx
->b
.rings
.gfx
,
612 rbuffer
, buffers
->shader_usage
);
614 buffers
->desc
.dirty_mask
|= 1 << i
;
619 si_update_descriptors(sctx
, &buffers
->desc
);
623 /* Texture buffers. */
624 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
625 struct si_sampler_views
*views
= &sctx
->samplers
[shader
].views
;
627 uint32_t mask
= views
->desc
.enabled_mask
;
630 unsigned i
= u_bit_scan(&mask
);
631 if (views
->views
[i
]->texture
== buf
) {
632 /* This updates the sampler view directly. */
633 si_desc_reset_buffer_offset(ctx
, views
->desc_data
[i
],
636 r600_context_bo_reloc(&sctx
->b
, &sctx
->b
.rings
.gfx
,
637 rbuffer
, RADEON_USAGE_READ
);
639 views
->desc
.dirty_mask
|= 1 << i
;
644 si_update_descriptors(sctx
, &views
->desc
);
651 /* The max number of bytes to copy per packet. */
652 #define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - 8)
654 static void si_clear_buffer(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
655 unsigned offset
, unsigned size
, unsigned value
)
657 struct si_context
*sctx
= (struct si_context
*)ctx
;
662 /* Mark the buffer range of destination as valid (initialized),
663 * so that transfer_map knows it should wait for the GPU when mapping
665 util_range_add(&r600_resource(dst
)->valid_buffer_range
, offset
,
668 /* Fallback for unaligned clears. */
669 if (offset
% 4 != 0 || size
% 4 != 0) {
670 uint32_t *map
= sctx
->b
.ws
->buffer_map(r600_resource(dst
)->cs_buf
,
671 sctx
->b
.rings
.gfx
.cs
,
672 PIPE_TRANSFER_WRITE
);
674 for (unsigned i
= 0; i
< size
; i
++)
679 uint64_t va
= r600_resource_va(&sctx
->screen
->b
.b
, dst
) + offset
;
681 /* Flush the caches where the resource is bound. */
682 /* XXX only flush the caches where the buffer is bound. */
683 sctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
|
684 R600_CONTEXT_INV_CONST_CACHE
|
685 R600_CONTEXT_FLUSH_AND_INV_CB
|
686 R600_CONTEXT_FLUSH_AND_INV_DB
|
687 R600_CONTEXT_FLUSH_AND_INV_CB_META
|
688 R600_CONTEXT_FLUSH_AND_INV_DB_META
;
689 sctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
692 unsigned byte_count
= MIN2(size
, CP_DMA_MAX_BYTE_COUNT
);
693 unsigned dma_flags
= 0;
695 si_need_cs_space(sctx
, 7 + (sctx
->b
.flags
? sctx
->cache_flush
.num_dw
: 0),
698 /* This must be done after need_cs_space. */
699 r600_context_bo_reloc(&sctx
->b
, &sctx
->b
.rings
.gfx
,
700 (struct r600_resource
*)dst
, RADEON_USAGE_WRITE
);
702 /* Flush the caches for the first copy only.
703 * Also wait for the previous CP DMA operations. */
705 si_emit_cache_flush(&sctx
->b
, NULL
);
706 dma_flags
|= SI_CP_DMA_RAW_WAIT
; /* same as WAIT_UNTIL=CP_DMA_IDLE */
709 /* Do the synchronization after the last copy, so that all data is written to memory. */
710 if (size
== byte_count
)
711 dma_flags
|= R600_CP_DMA_SYNC
;
713 /* Emit the clear packet. */
714 si_emit_cp_dma_clear_buffer(sctx
, va
, byte_count
, value
, dma_flags
);
720 /* Flush the caches again in case the 3D engine has been prefetching
722 /* XXX only flush the caches where the buffer is bound. */
723 sctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
|
724 R600_CONTEXT_INV_CONST_CACHE
|
725 R600_CONTEXT_FLUSH_AND_INV_CB
|
726 R600_CONTEXT_FLUSH_AND_INV_DB
|
727 R600_CONTEXT_FLUSH_AND_INV_CB_META
|
728 R600_CONTEXT_FLUSH_AND_INV_DB_META
;
731 void si_copy_buffer(struct si_context
*sctx
,
732 struct pipe_resource
*dst
, struct pipe_resource
*src
,
733 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
)
738 /* Mark the buffer range of destination as valid (initialized),
739 * so that transfer_map knows it should wait for the GPU when mapping
741 util_range_add(&r600_resource(dst
)->valid_buffer_range
, dst_offset
,
744 dst_offset
+= r600_resource_va(&sctx
->screen
->b
.b
, dst
);
745 src_offset
+= r600_resource_va(&sctx
->screen
->b
.b
, src
);
747 /* Flush the caches where the resource is bound. */
748 sctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
|
749 R600_CONTEXT_INV_CONST_CACHE
|
750 R600_CONTEXT_FLUSH_AND_INV_CB
|
751 R600_CONTEXT_FLUSH_AND_INV_DB
|
752 R600_CONTEXT_FLUSH_AND_INV_CB_META
|
753 R600_CONTEXT_FLUSH_AND_INV_DB_META
|
754 R600_CONTEXT_WAIT_3D_IDLE
;
757 unsigned sync_flags
= 0;
758 unsigned byte_count
= MIN2(size
, CP_DMA_MAX_BYTE_COUNT
);
760 si_need_cs_space(sctx
, 7 + (sctx
->b
.flags
? sctx
->cache_flush
.num_dw
: 0), FALSE
);
762 /* Flush the caches for the first copy only. Also wait for old CP DMA packets to complete. */
764 si_emit_cache_flush(&sctx
->b
, NULL
);
765 sync_flags
|= SI_CP_DMA_RAW_WAIT
;
768 /* Do the synchronization after the last copy, so that all data is written to memory. */
769 if (size
== byte_count
) {
770 sync_flags
|= R600_CP_DMA_SYNC
;
773 /* This must be done after r600_need_cs_space. */
774 r600_context_bo_reloc(&sctx
->b
, &sctx
->b
.rings
.gfx
, (struct r600_resource
*)src
, RADEON_USAGE_READ
);
775 r600_context_bo_reloc(&sctx
->b
, &sctx
->b
.rings
.gfx
, (struct r600_resource
*)dst
, RADEON_USAGE_WRITE
);
777 si_emit_cp_dma_copy_buffer(sctx
, dst_offset
, src_offset
, byte_count
, sync_flags
);
780 src_offset
+= byte_count
;
781 dst_offset
+= byte_count
;
784 sctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
|
785 R600_CONTEXT_INV_CONST_CACHE
|
786 R600_CONTEXT_FLUSH_AND_INV_CB
|
787 R600_CONTEXT_FLUSH_AND_INV_DB
|
788 R600_CONTEXT_FLUSH_AND_INV_CB_META
|
789 R600_CONTEXT_FLUSH_AND_INV_DB_META
;
794 void si_init_all_descriptors(struct si_context
*sctx
)
798 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
799 si_init_buffer_resources(sctx
, &sctx
->const_buffers
[i
],
800 NUM_CONST_BUFFERS
, i
, SI_SGPR_CONST
,
803 si_init_sampler_views(sctx
, &sctx
->samplers
[i
].views
, i
);
805 sctx
->atoms
.const_buffers
[i
] = &sctx
->const_buffers
[i
].desc
.atom
;
806 sctx
->atoms
.sampler_views
[i
] = &sctx
->samplers
[i
].views
.desc
.atom
;
809 si_init_buffer_resources(sctx
, &sctx
->streamout_buffers
, 4, PIPE_SHADER_VERTEX
,
810 SI_SGPR_SO_BUFFER
, RADEON_USAGE_WRITE
);
811 sctx
->atoms
.streamout_buffers
= &sctx
->streamout_buffers
.desc
.atom
;
813 /* Set pipe_context functions. */
814 sctx
->b
.b
.set_constant_buffer
= si_set_constant_buffer
;
815 sctx
->b
.b
.set_stream_output_targets
= si_set_streamout_targets
;
816 sctx
->b
.clear_buffer
= si_clear_buffer
;
817 sctx
->b
.invalidate_buffer
= si_invalidate_buffer
;
820 void si_release_all_descriptors(struct si_context
*sctx
)
824 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
825 si_release_buffer_resources(&sctx
->const_buffers
[i
]);
826 si_release_sampler_views(&sctx
->samplers
[i
].views
);
828 si_release_buffer_resources(&sctx
->streamout_buffers
);
831 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
835 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
836 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_buffers
[i
]);
837 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
].views
);
839 si_buffer_resources_begin_new_cs(sctx
, &sctx
->streamout_buffers
);