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radeonsi: remove si.h
[mesa.git] / src / gallium / drivers / radeonsi / si_descriptors.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Marek Olšák <marek.olsak@amd.com>
25 */
26 #include "../radeon/r600_cs.h"
27 #include "si_pipe.h"
28 #include "si_resource.h"
29 #include "si_shader.h"
30
31 #include "util/u_memory.h"
32 #include "util/u_upload_mgr.h"
33
34 #define SI_NUM_CONTEXTS 16
35
36 static uint32_t null_desc[8]; /* zeros */
37
38 /* Set this if you want the 3D engine to wait until CP DMA is done.
39 * It should be set on the last CP DMA packet. */
40 #define R600_CP_DMA_SYNC (1 << 0) /* R600+ */
41
42 /* Set this if the source data was used as a destination in a previous CP DMA
43 * packet. It's for preventing a read-after-write (RAW) hazard between two
44 * CP DMA packets. */
45 #define SI_CP_DMA_RAW_WAIT (1 << 1) /* SI+ */
46
47 /* Emit a CP DMA packet to do a copy from one buffer to another.
48 * The size must fit in bits [20:0].
49 */
50 static void si_emit_cp_dma_copy_buffer(struct si_context *sctx,
51 uint64_t dst_va, uint64_t src_va,
52 unsigned size, unsigned flags)
53 {
54 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
55 uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? PKT3_CP_DMA_CP_SYNC : 0;
56 uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? PKT3_CP_DMA_CMD_RAW_WAIT : 0;
57
58 assert(size);
59 assert((size & ((1<<21)-1)) == size);
60
61 if (sctx->b.chip_class >= CIK) {
62 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
63 radeon_emit(cs, sync_flag); /* CP_SYNC [31] */
64 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
65 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
66 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
67 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
68 radeon_emit(cs, size | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
69 } else {
70 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
71 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
72 radeon_emit(cs, sync_flag | ((src_va >> 32) & 0xffff)); /* CP_SYNC [31] | SRC_ADDR_HI [15:0] */
73 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
74 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
75 radeon_emit(cs, size | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
76 }
77 }
78
79 /* Emit a CP DMA packet to clear a buffer. The size must fit in bits [20:0]. */
80 static void si_emit_cp_dma_clear_buffer(struct si_context *sctx,
81 uint64_t dst_va, unsigned size,
82 uint32_t clear_value, unsigned flags)
83 {
84 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
85 uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? PKT3_CP_DMA_CP_SYNC : 0;
86 uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? PKT3_CP_DMA_CMD_RAW_WAIT : 0;
87
88 assert(size);
89 assert((size & ((1<<21)-1)) == size);
90
91 if (sctx->b.chip_class >= CIK) {
92 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
93 radeon_emit(cs, sync_flag | PKT3_CP_DMA_SRC_SEL(2)); /* CP_SYNC [31] | SRC_SEL[30:29] */
94 radeon_emit(cs, clear_value); /* DATA [31:0] */
95 radeon_emit(cs, 0);
96 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
97 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [15:0] */
98 radeon_emit(cs, size | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
99 } else {
100 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
101 radeon_emit(cs, clear_value); /* DATA [31:0] */
102 radeon_emit(cs, sync_flag | PKT3_CP_DMA_SRC_SEL(2)); /* CP_SYNC [31] | SRC_SEL[30:29] */
103 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
104 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
105 radeon_emit(cs, size | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
106 }
107 }
108
109 static void si_init_descriptors(struct si_context *sctx,
110 struct si_descriptors *desc,
111 unsigned shader_userdata_reg,
112 unsigned element_dw_size,
113 unsigned num_elements,
114 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
115 {
116 uint64_t va;
117
118 assert(num_elements <= sizeof(desc->enabled_mask)*8);
119 assert(num_elements <= sizeof(desc->dirty_mask)*8);
120
121 desc->atom.emit = (void*)emit_func;
122 desc->shader_userdata_reg = shader_userdata_reg;
123 desc->element_dw_size = element_dw_size;
124 desc->num_elements = num_elements;
125 desc->context_size = num_elements * element_dw_size * 4;
126
127 desc->buffer = (struct r600_resource*)
128 pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
129 PIPE_USAGE_STATIC,
130 SI_NUM_CONTEXTS * desc->context_size);
131
132 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, desc->buffer, RADEON_USAGE_READWRITE);
133 va = r600_resource_va(sctx->b.b.screen, &desc->buffer->b.b);
134
135 /* We don't check for CS space here, because this should be called
136 * only once at context initialization. */
137 si_emit_cp_dma_clear_buffer(sctx, va, desc->buffer->b.b.width0, 0,
138 R600_CP_DMA_SYNC);
139 }
140
141 static void si_release_descriptors(struct si_descriptors *desc)
142 {
143 pipe_resource_reference((struct pipe_resource**)&desc->buffer, NULL);
144 }
145
146 static void si_update_descriptors(struct si_context *sctx,
147 struct si_descriptors *desc)
148 {
149 if (desc->dirty_mask) {
150 desc->atom.num_dw =
151 7 + /* copy */
152 (4 + desc->element_dw_size) * util_bitcount(desc->dirty_mask) + /* update */
153 4; /* pointer update */
154 desc->atom.dirty = true;
155 /* The descriptors are read with the K cache. */
156 sctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
157 } else {
158 desc->atom.dirty = false;
159 }
160 }
161
162 static void si_emit_shader_pointer(struct si_context *sctx,
163 struct si_descriptors *desc)
164 {
165 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
166 uint64_t va = r600_resource_va(sctx->b.b.screen, &desc->buffer->b.b) +
167 desc->current_context_id * desc->context_size;
168
169 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0));
170 radeon_emit(cs, (desc->shader_userdata_reg - SI_SH_REG_OFFSET) >> 2);
171 radeon_emit(cs, va);
172 radeon_emit(cs, va >> 32);
173 }
174
175 static void si_emit_descriptors(struct si_context *sctx,
176 struct si_descriptors *desc,
177 uint32_t **descriptors)
178 {
179 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
180 uint64_t va_base;
181 int packet_start;
182 int packet_size = 0;
183 int last_index = desc->num_elements; /* point to a non-existing element */
184 unsigned dirty_mask = desc->dirty_mask;
185 unsigned new_context_id = (desc->current_context_id + 1) % SI_NUM_CONTEXTS;
186
187 assert(dirty_mask);
188
189 va_base = r600_resource_va(sctx->b.b.screen, &desc->buffer->b.b);
190
191 /* Copy the descriptors to a new context slot. */
192 /* XXX Consider using TC or L2 for this copy on CIK. */
193 si_emit_cp_dma_copy_buffer(sctx,
194 va_base + new_context_id * desc->context_size,
195 va_base + desc->current_context_id * desc->context_size,
196 desc->context_size, R600_CP_DMA_SYNC);
197
198 va_base += new_context_id * desc->context_size;
199
200 /* Update the descriptors.
201 * Updates of consecutive descriptors are merged to one WRITE_DATA packet.
202 *
203 * XXX When unbinding lots of resources, consider clearing the memory
204 * with CP DMA instead of emitting zeros.
205 */
206 while (dirty_mask) {
207 int i = u_bit_scan(&dirty_mask);
208
209 assert(i < desc->num_elements);
210
211 if (last_index+1 == i && packet_size) {
212 /* Append new data at the end of the last packet. */
213 packet_size += desc->element_dw_size;
214 cs->buf[packet_start] = PKT3(PKT3_WRITE_DATA, packet_size, 0);
215 } else {
216 /* Start a new packet. */
217 uint64_t va = va_base + i * desc->element_dw_size * 4;
218
219 packet_start = cs->cdw;
220 packet_size = 2 + desc->element_dw_size;
221
222 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, packet_size, 0));
223 radeon_emit(cs, PKT3_WRITE_DATA_DST_SEL(PKT3_WRITE_DATA_DST_SEL_TC_OR_L2) |
224 PKT3_WRITE_DATA_WR_CONFIRM |
225 PKT3_WRITE_DATA_ENGINE_SEL(PKT3_WRITE_DATA_ENGINE_SEL_ME));
226 radeon_emit(cs, va & 0xFFFFFFFFUL);
227 radeon_emit(cs, (va >> 32UL) & 0xFFFFFFFFUL);
228 }
229
230 radeon_emit_array(cs, descriptors[i], desc->element_dw_size);
231
232 last_index = i;
233 }
234
235 desc->dirty_mask = 0;
236 desc->current_context_id = new_context_id;
237
238 /* Now update the shader userdata pointer. */
239 si_emit_shader_pointer(sctx, desc);
240 }
241
242 static unsigned si_get_shader_user_data_base(unsigned shader)
243 {
244 switch (shader) {
245 case PIPE_SHADER_VERTEX:
246 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
247 case PIPE_SHADER_GEOMETRY:
248 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
249 case PIPE_SHADER_FRAGMENT:
250 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
251 default:
252 assert(0);
253 return 0;
254 }
255 }
256
257 /* SAMPLER VIEWS */
258
259 static void si_emit_sampler_views(struct si_context *sctx, struct r600_atom *atom)
260 {
261 struct si_sampler_views *views = (struct si_sampler_views*)atom;
262
263 si_emit_descriptors(sctx, &views->desc, views->desc_data);
264 }
265
266 static void si_init_sampler_views(struct si_context *sctx,
267 struct si_sampler_views *views,
268 unsigned shader)
269 {
270 si_init_descriptors(sctx, &views->desc,
271 si_get_shader_user_data_base(shader) +
272 SI_SGPR_RESOURCE * 4,
273 8, NUM_SAMPLER_VIEWS, si_emit_sampler_views);
274 }
275
276 static void si_release_sampler_views(struct si_sampler_views *views)
277 {
278 int i;
279
280 for (i = 0; i < Elements(views->views); i++) {
281 pipe_sampler_view_reference(&views->views[i], NULL);
282 }
283 si_release_descriptors(&views->desc);
284 }
285
286 static void si_sampler_views_begin_new_cs(struct si_context *sctx,
287 struct si_sampler_views *views)
288 {
289 unsigned mask = views->desc.enabled_mask;
290
291 /* Add relocations to the CS. */
292 while (mask) {
293 int i = u_bit_scan(&mask);
294 struct si_pipe_sampler_view *rview =
295 (struct si_pipe_sampler_view*)views->views[i];
296
297 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, rview->resource, RADEON_USAGE_READ);
298 }
299
300 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, views->desc.buffer, RADEON_USAGE_READWRITE);
301
302 si_emit_shader_pointer(sctx, &views->desc);
303 }
304
305 void si_set_sampler_view(struct si_context *sctx, unsigned shader,
306 unsigned slot, struct pipe_sampler_view *view,
307 unsigned *view_desc)
308 {
309 struct si_sampler_views *views = &sctx->samplers[shader].views;
310
311 if (views->views[slot] == view)
312 return;
313
314 if (view) {
315 struct si_pipe_sampler_view *rview =
316 (struct si_pipe_sampler_view*)view;
317
318 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, rview->resource, RADEON_USAGE_READ);
319
320 pipe_sampler_view_reference(&views->views[slot], view);
321 views->desc_data[slot] = view_desc;
322 views->desc.enabled_mask |= 1 << slot;
323 } else {
324 pipe_sampler_view_reference(&views->views[slot], NULL);
325 views->desc_data[slot] = null_desc;
326 views->desc.enabled_mask &= ~(1 << slot);
327 }
328
329 views->desc.dirty_mask |= 1 << slot;
330 si_update_descriptors(sctx, &views->desc);
331 }
332
333 /* BUFFER RESOURCES */
334
335 static void si_emit_buffer_resources(struct si_context *sctx, struct r600_atom *atom)
336 {
337 struct si_buffer_resources *buffers = (struct si_buffer_resources*)atom;
338
339 si_emit_descriptors(sctx, &buffers->desc, buffers->desc_data);
340 }
341
342 static void si_init_buffer_resources(struct si_context *sctx,
343 struct si_buffer_resources *buffers,
344 unsigned num_buffers, unsigned shader,
345 unsigned shader_userdata_index,
346 enum radeon_bo_usage shader_usage)
347 {
348 int i;
349
350 buffers->num_buffers = num_buffers;
351 buffers->shader_usage = shader_usage;
352 buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource*));
353 buffers->desc_storage = CALLOC(num_buffers, sizeof(uint32_t) * 4);
354
355 /* si_emit_descriptors only accepts an array of arrays.
356 * This adds such an array. */
357 buffers->desc_data = CALLOC(num_buffers, sizeof(uint32_t*));
358 for (i = 0; i < num_buffers; i++) {
359 buffers->desc_data[i] = &buffers->desc_storage[i*4];
360 }
361
362 si_init_descriptors(sctx, &buffers->desc,
363 si_get_shader_user_data_base(shader) +
364 shader_userdata_index*4, 4, num_buffers,
365 si_emit_buffer_resources);
366 }
367
368 static void si_release_buffer_resources(struct si_buffer_resources *buffers)
369 {
370 int i;
371
372 for (i = 0; i < Elements(buffers->buffers); i++) {
373 pipe_resource_reference(&buffers->buffers[i], NULL);
374 }
375
376 FREE(buffers->buffers);
377 FREE(buffers->desc_storage);
378 FREE(buffers->desc_data);
379 si_release_descriptors(&buffers->desc);
380 }
381
382 static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
383 struct si_buffer_resources *buffers)
384 {
385 unsigned mask = buffers->desc.enabled_mask;
386
387 /* Add relocations to the CS. */
388 while (mask) {
389 int i = u_bit_scan(&mask);
390
391 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
392 (struct r600_resource*)buffers->buffers[i],
393 buffers->shader_usage);
394 }
395
396 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
397 buffers->desc.buffer, RADEON_USAGE_READWRITE);
398
399 si_emit_shader_pointer(sctx, &buffers->desc);
400 }
401
402 /* CONSTANT BUFFERS */
403
404 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
405 const uint8_t *ptr, unsigned size, uint32_t *const_offset)
406 {
407 if (SI_BIG_ENDIAN) {
408 uint32_t *tmpPtr;
409 unsigned i;
410
411 if (!(tmpPtr = malloc(size))) {
412 R600_ERR("Failed to allocate BE swap buffer.\n");
413 return;
414 }
415
416 for (i = 0; i < size / 4; ++i) {
417 tmpPtr[i] = util_bswap32(((uint32_t *)ptr)[i]);
418 }
419
420 u_upload_data(sctx->b.uploader, 0, size, tmpPtr, const_offset,
421 (struct pipe_resource**)rbuffer);
422
423 free(tmpPtr);
424 } else {
425 u_upload_data(sctx->b.uploader, 0, size, ptr, const_offset,
426 (struct pipe_resource**)rbuffer);
427 }
428 }
429
430 static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint slot,
431 struct pipe_constant_buffer *input)
432 {
433 struct si_context *sctx = (struct si_context *)ctx;
434 struct si_buffer_resources *buffers = &sctx->const_buffers[shader];
435
436 if (shader >= SI_NUM_SHADERS)
437 return;
438
439 assert(slot < buffers->num_buffers);
440 pipe_resource_reference(&buffers->buffers[slot], NULL);
441
442 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
443 * with a NULL buffer). We need to use a dummy buffer instead. */
444 if (sctx->b.chip_class == CIK &&
445 (!input || (!input->buffer && !input->user_buffer)))
446 input = &sctx->null_const_buf;
447
448 if (input && (input->buffer || input->user_buffer)) {
449 struct pipe_resource *buffer = NULL;
450 uint64_t va;
451
452 /* Upload the user buffer if needed. */
453 if (input->user_buffer) {
454 unsigned buffer_offset;
455
456 si_upload_const_buffer(sctx,
457 (struct r600_resource**)&buffer, input->user_buffer,
458 input->buffer_size, &buffer_offset);
459 va = r600_resource_va(ctx->screen, buffer) + buffer_offset;
460 } else {
461 pipe_resource_reference(&buffer, input->buffer);
462 va = r600_resource_va(ctx->screen, buffer) + input->buffer_offset;
463 }
464
465 /* Set the descriptor. */
466 uint32_t *desc = buffers->desc_data[slot];
467 desc[0] = va;
468 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
469 S_008F04_STRIDE(0);
470 desc[2] = input->buffer_size;
471 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
472 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
473 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
474 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
475 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
476 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
477
478 buffers->buffers[slot] = buffer;
479 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
480 (struct r600_resource*)buffer, buffers->shader_usage);
481 buffers->desc.enabled_mask |= 1 << slot;
482 } else {
483 /* Clear the descriptor. */
484 memset(buffers->desc_data[slot], 0, sizeof(uint32_t) * 4);
485 buffers->desc.enabled_mask &= ~(1 << slot);
486 }
487
488 buffers->desc.dirty_mask |= 1 << slot;
489 si_update_descriptors(sctx, &buffers->desc);
490 }
491
492 /* STREAMOUT BUFFERS */
493
494 static void si_set_streamout_targets(struct pipe_context *ctx,
495 unsigned num_targets,
496 struct pipe_stream_output_target **targets,
497 unsigned append_bitmask)
498 {
499 struct si_context *sctx = (struct si_context *)ctx;
500 struct si_buffer_resources *buffers = &sctx->streamout_buffers;
501 unsigned old_num_targets = sctx->b.streamout.num_targets;
502 unsigned i;
503
504 /* Streamout buffers must be bound in 2 places:
505 * 1) in VGT by setting the VGT_STRMOUT registers
506 * 2) as shader resources
507 */
508
509 /* Set the VGT regs. */
510 r600_set_streamout_targets(ctx, num_targets, targets, append_bitmask);
511
512 /* Set the shader resources.*/
513 for (i = 0; i < num_targets; i++) {
514 if (targets[i]) {
515 struct pipe_resource *buffer = targets[i]->buffer;
516 uint64_t va = r600_resource_va(ctx->screen, buffer);
517
518 /* Set the descriptor. */
519 uint32_t *desc = buffers->desc_data[i];
520 desc[0] = va;
521 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
522 desc[2] = 0xffffffff;
523 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
524 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
525 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
526 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
527
528 /* Set the resource. */
529 pipe_resource_reference(&buffers->buffers[i], buffer);
530 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
531 (struct r600_resource*)buffer,
532 buffers->shader_usage);
533 buffers->desc.enabled_mask |= 1 << i;
534 } else {
535 /* Clear the descriptor and unset the resource. */
536 memset(buffers->desc_data[i], 0, sizeof(uint32_t) * 4);
537 pipe_resource_reference(&buffers->buffers[i], NULL);
538 buffers->desc.enabled_mask &= ~(1 << i);
539 }
540 buffers->desc.dirty_mask |= 1 << i;
541 }
542 for (; i < old_num_targets; i++) {
543 /* Clear the descriptor and unset the resource. */
544 memset(buffers->desc_data[i], 0, sizeof(uint32_t) * 4);
545 pipe_resource_reference(&buffers->buffers[i], NULL);
546 buffers->desc.enabled_mask &= ~(1 << i);
547 buffers->desc.dirty_mask |= 1 << i;
548 }
549
550 si_update_descriptors(sctx, &buffers->desc);
551 }
552
553 static void si_desc_reset_buffer_offset(struct pipe_context *ctx,
554 uint32_t *desc, uint64_t old_buf_va,
555 struct pipe_resource *new_buf)
556 {
557 /* Retrieve the buffer offset from the descriptor. */
558 uint64_t old_desc_va =
559 desc[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc[1]) << 32);
560
561 assert(old_buf_va <= old_desc_va);
562 uint64_t offset_within_buffer = old_desc_va - old_buf_va;
563
564 /* Update the descriptor. */
565 uint64_t va = r600_resource_va(ctx->screen, new_buf) + offset_within_buffer;
566
567 desc[0] = va;
568 desc[1] = (desc[1] & C_008F04_BASE_ADDRESS_HI) |
569 S_008F04_BASE_ADDRESS_HI(va >> 32);
570 }
571
572 /* BUFFER DISCARD/INVALIDATION */
573
574 /* Reallocate a buffer a update all resource bindings where the buffer is
575 * bound.
576 *
577 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
578 * idle by discarding its contents. Apps usually tell us when to do this using
579 * map_buffer flags, for example.
580 */
581 static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
582 {
583 struct si_context *sctx = (struct si_context*)ctx;
584 struct r600_resource *rbuffer = r600_resource(buf);
585 unsigned i, shader, alignment = rbuffer->buf->alignment;
586 uint64_t old_va = r600_resource_va(ctx->screen, buf);
587
588 /* Discard the buffer. */
589 pb_reference(&rbuffer->buf, NULL);
590
591 /* Create a new one in the same pipe_resource. */
592 r600_init_resource(&sctx->screen->b, rbuffer, rbuffer->b.b.width0, alignment,
593 TRUE, rbuffer->b.b.usage);
594
595 /* We changed the buffer, now we need to bind it where the old one
596 * was bound. This consists of 2 things:
597 * 1) Updating the resource descriptor and dirtying it.
598 * 2) Adding a relocation to the CS, so that it's usable.
599 */
600
601 /* Vertex buffers. */
602 /* Nothing to do. Vertex buffer bindings are updated before every draw call. */
603
604 /* Streamout buffers. */
605 for (i = 0; i < sctx->streamout_buffers.num_buffers; i++) {
606 if (sctx->streamout_buffers.buffers[i] == buf) {
607 /* Update the descriptor. */
608 si_desc_reset_buffer_offset(ctx, sctx->streamout_buffers.desc_data[i],
609 old_va, buf);
610
611 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
612 (struct r600_resource*)buf,
613 sctx->streamout_buffers.shader_usage);
614 sctx->streamout_buffers.desc.dirty_mask |= 1 << i;
615 si_update_descriptors(sctx, &sctx->streamout_buffers.desc);
616
617 /* Update the streamout state. */
618 if (sctx->b.streamout.begin_emitted) {
619 r600_emit_streamout_end(&sctx->b);
620 }
621 sctx->b.streamout.append_bitmask = sctx->b.streamout.enabled_mask;
622 r600_streamout_buffers_dirty(&sctx->b);
623 }
624 }
625
626 /* Constant buffers. */
627 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
628 struct si_buffer_resources *buffers = &sctx->const_buffers[shader];
629 bool found = false;
630 uint32_t mask = buffers->desc.enabled_mask;
631
632 while (mask) {
633 unsigned i = u_bit_scan(&mask);
634 if (buffers->buffers[i] == buf) {
635 si_desc_reset_buffer_offset(ctx, buffers->desc_data[i],
636 old_va, buf);
637
638 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
639 rbuffer, buffers->shader_usage);
640
641 buffers->desc.dirty_mask |= 1 << i;
642 found = true;
643 }
644 }
645 if (found) {
646 si_update_descriptors(sctx, &buffers->desc);
647 }
648 }
649
650 /* Texture buffers. */
651 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
652 struct si_sampler_views *views = &sctx->samplers[shader].views;
653 bool found = false;
654 uint32_t mask = views->desc.enabled_mask;
655
656 while (mask) {
657 unsigned i = u_bit_scan(&mask);
658 if (views->views[i]->texture == buf) {
659 /* This updates the sampler view directly. */
660 si_desc_reset_buffer_offset(ctx, views->desc_data[i],
661 old_va, buf);
662
663 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
664 rbuffer, RADEON_USAGE_READ);
665
666 views->desc.dirty_mask |= 1 << i;
667 found = true;
668 }
669 }
670 if (found) {
671 si_update_descriptors(sctx, &views->desc);
672 }
673 }
674 }
675
676 /* CP DMA */
677
678 /* The max number of bytes to copy per packet. */
679 #define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - 8)
680
681 static void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
682 unsigned offset, unsigned size, unsigned value)
683 {
684 struct si_context *sctx = (struct si_context*)ctx;
685
686 if (!size)
687 return;
688
689 /* Mark the buffer range of destination as valid (initialized),
690 * so that transfer_map knows it should wait for the GPU when mapping
691 * that range. */
692 util_range_add(&r600_resource(dst)->valid_buffer_range, offset,
693 offset + size);
694
695 /* Fallback for unaligned clears. */
696 if (offset % 4 != 0 || size % 4 != 0) {
697 uint32_t *map = sctx->b.ws->buffer_map(r600_resource(dst)->cs_buf,
698 sctx->b.rings.gfx.cs,
699 PIPE_TRANSFER_WRITE);
700 size /= 4;
701 for (unsigned i = 0; i < size; i++)
702 *map++ = value;
703 return;
704 }
705
706 uint64_t va = r600_resource_va(&sctx->screen->b.b, dst) + offset;
707
708 /* Flush the caches where the resource is bound. */
709 /* XXX only flush the caches where the buffer is bound. */
710 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
711 R600_CONTEXT_INV_CONST_CACHE |
712 R600_CONTEXT_FLUSH_AND_INV_CB |
713 R600_CONTEXT_FLUSH_AND_INV_DB |
714 R600_CONTEXT_FLUSH_AND_INV_CB_META |
715 R600_CONTEXT_FLUSH_AND_INV_DB_META;
716 sctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
717
718 while (size) {
719 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
720 unsigned dma_flags = 0;
721
722 si_need_cs_space(sctx, 7 + (sctx->b.flags ? sctx->cache_flush.num_dw : 0),
723 FALSE);
724
725 /* This must be done after need_cs_space. */
726 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
727 (struct r600_resource*)dst, RADEON_USAGE_WRITE);
728
729 /* Flush the caches for the first copy only.
730 * Also wait for the previous CP DMA operations. */
731 if (sctx->b.flags) {
732 si_emit_cache_flush(&sctx->b, NULL);
733 dma_flags |= SI_CP_DMA_RAW_WAIT; /* same as WAIT_UNTIL=CP_DMA_IDLE */
734 }
735
736 /* Do the synchronization after the last copy, so that all data is written to memory. */
737 if (size == byte_count)
738 dma_flags |= R600_CP_DMA_SYNC;
739
740 /* Emit the clear packet. */
741 si_emit_cp_dma_clear_buffer(sctx, va, byte_count, value, dma_flags);
742
743 size -= byte_count;
744 va += byte_count;
745 }
746
747 /* Flush the caches again in case the 3D engine has been prefetching
748 * the resource. */
749 /* XXX only flush the caches where the buffer is bound. */
750 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
751 R600_CONTEXT_INV_CONST_CACHE |
752 R600_CONTEXT_FLUSH_AND_INV_CB |
753 R600_CONTEXT_FLUSH_AND_INV_DB |
754 R600_CONTEXT_FLUSH_AND_INV_CB_META |
755 R600_CONTEXT_FLUSH_AND_INV_DB_META;
756 }
757
758 void si_copy_buffer(struct si_context *sctx,
759 struct pipe_resource *dst, struct pipe_resource *src,
760 uint64_t dst_offset, uint64_t src_offset, unsigned size)
761 {
762 if (!size)
763 return;
764
765 /* Mark the buffer range of destination as valid (initialized),
766 * so that transfer_map knows it should wait for the GPU when mapping
767 * that range. */
768 util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
769 dst_offset + size);
770
771 dst_offset += r600_resource_va(&sctx->screen->b.b, dst);
772 src_offset += r600_resource_va(&sctx->screen->b.b, src);
773
774 /* Flush the caches where the resource is bound. */
775 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
776 R600_CONTEXT_INV_CONST_CACHE |
777 R600_CONTEXT_FLUSH_AND_INV_CB |
778 R600_CONTEXT_FLUSH_AND_INV_DB |
779 R600_CONTEXT_FLUSH_AND_INV_CB_META |
780 R600_CONTEXT_FLUSH_AND_INV_DB_META |
781 R600_CONTEXT_WAIT_3D_IDLE;
782
783 while (size) {
784 unsigned sync_flags = 0;
785 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
786
787 si_need_cs_space(sctx, 7 + (sctx->b.flags ? sctx->cache_flush.num_dw : 0), FALSE);
788
789 /* Flush the caches for the first copy only. Also wait for old CP DMA packets to complete. */
790 if (sctx->b.flags) {
791 si_emit_cache_flush(&sctx->b, NULL);
792 sync_flags |= SI_CP_DMA_RAW_WAIT;
793 }
794
795 /* Do the synchronization after the last copy, so that all data is written to memory. */
796 if (size == byte_count) {
797 sync_flags |= R600_CP_DMA_SYNC;
798 }
799
800 /* This must be done after r600_need_cs_space. */
801 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource*)src, RADEON_USAGE_READ);
802 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, (struct r600_resource*)dst, RADEON_USAGE_WRITE);
803
804 si_emit_cp_dma_copy_buffer(sctx, dst_offset, src_offset, byte_count, sync_flags);
805
806 size -= byte_count;
807 src_offset += byte_count;
808 dst_offset += byte_count;
809 }
810
811 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
812 R600_CONTEXT_INV_CONST_CACHE |
813 R600_CONTEXT_FLUSH_AND_INV_CB |
814 R600_CONTEXT_FLUSH_AND_INV_DB |
815 R600_CONTEXT_FLUSH_AND_INV_CB_META |
816 R600_CONTEXT_FLUSH_AND_INV_DB_META;
817 }
818
819 /* INIT/DEINIT */
820
821 void si_init_all_descriptors(struct si_context *sctx)
822 {
823 int i;
824
825 for (i = 0; i < SI_NUM_SHADERS; i++) {
826 si_init_buffer_resources(sctx, &sctx->const_buffers[i],
827 NUM_CONST_BUFFERS, i, SI_SGPR_CONST,
828 RADEON_USAGE_READ);
829
830 si_init_sampler_views(sctx, &sctx->samplers[i].views, i);
831
832 sctx->atoms.const_buffers[i] = &sctx->const_buffers[i].desc.atom;
833 sctx->atoms.sampler_views[i] = &sctx->samplers[i].views.desc.atom;
834 }
835
836 si_init_buffer_resources(sctx, &sctx->streamout_buffers, 4, PIPE_SHADER_VERTEX,
837 SI_SGPR_SO_BUFFER, RADEON_USAGE_WRITE);
838 sctx->atoms.streamout_buffers = &sctx->streamout_buffers.desc.atom;
839
840 /* Set pipe_context functions. */
841 sctx->b.b.set_constant_buffer = si_set_constant_buffer;
842 sctx->b.b.set_stream_output_targets = si_set_streamout_targets;
843 sctx->b.clear_buffer = si_clear_buffer;
844 sctx->b.invalidate_buffer = si_invalidate_buffer;
845 }
846
847 void si_release_all_descriptors(struct si_context *sctx)
848 {
849 int i;
850
851 for (i = 0; i < SI_NUM_SHADERS; i++) {
852 si_release_buffer_resources(&sctx->const_buffers[i]);
853 si_release_sampler_views(&sctx->samplers[i].views);
854 }
855 si_release_buffer_resources(&sctx->streamout_buffers);
856 }
857
858 void si_all_descriptors_begin_new_cs(struct si_context *sctx)
859 {
860 int i;
861
862 for (i = 0; i < SI_NUM_SHADERS; i++) {
863 si_buffer_resources_begin_new_cs(sctx, &sctx->const_buffers[i]);
864 si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i].views);
865 }
866 si_buffer_resources_begin_new_cs(sctx, &sctx->streamout_buffers);
867 }