2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 /* Resource binding slots and sampler states (each described with 8 or
25 * 4 dwords) are stored in lists in memory which is accessed by shaders
26 * using scalar load instructions.
28 * This file is responsible for managing such lists. It keeps a copy of all
29 * descriptors in CPU memory and re-uploads a whole list if some slots have
32 * This code is also reponsible for updating shader pointers to those lists.
34 * Note that CP DMA can't be used for updating the lists, because a GPU hang
35 * could leave the list in a mid-IB state and the next IB would get wrong
36 * descriptors and the whole context would be unusable at that point.
37 * (Note: The register shadowing can't be used due to the same reason)
39 * Also, uploading descriptors to newly allocated memory doesn't require
43 * Possible scenarios for one 16 dword image+sampler slot:
45 * | Image | w/ FMASK | Buffer | NULL
46 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
47 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
48 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
49 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
51 * FMASK implies MSAA, therefore no sampler state.
52 * Sampler states are never unbound except when FMASK is bound.
55 #include "radeon/r600_cs.h"
60 #include "util/hash_table.h"
61 #include "util/u_idalloc.h"
62 #include "util/u_format.h"
63 #include "util/u_memory.h"
64 #include "util/u_upload_mgr.h"
67 /* NULL image and buffer descriptor for textures (alpha = 1) and images
70 * For images, all fields must be zero except for the swizzle, which
71 * supports arbitrary combinations of 0s and 1s. The texture type must be
72 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
74 * For buffers, all fields must be zero. If they are not, the hw hangs.
76 * This is the only reason why the buffer descriptor must be in words [4:7].
78 static uint32_t null_texture_descriptor
[8] = {
82 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) |
83 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
84 /* the rest must contain zeros, which is also used by the buffer
88 static uint32_t null_image_descriptor
[8] = {
92 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
93 /* the rest must contain zeros, which is also used by the buffer
97 static uint64_t si_desc_extract_buffer_address(uint32_t *desc
)
99 return desc
[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
102 static void si_init_descriptor_list(uint32_t *desc_list
,
103 unsigned element_dw_size
,
104 unsigned num_elements
,
105 const uint32_t *null_descriptor
)
109 /* Initialize the array to NULL descriptors if the element size is 8. */
110 if (null_descriptor
) {
111 assert(element_dw_size
% 8 == 0);
112 for (i
= 0; i
< num_elements
* element_dw_size
/ 8; i
++)
113 memcpy(desc_list
+ i
* 8, null_descriptor
, 8 * 4);
117 static void si_init_descriptors(struct si_descriptors
*desc
,
118 short shader_userdata_rel_index
,
119 unsigned element_dw_size
,
120 unsigned num_elements
)
122 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
123 desc
->element_dw_size
= element_dw_size
;
124 desc
->num_elements
= num_elements
;
125 desc
->shader_userdata_offset
= shader_userdata_rel_index
* 4;
126 desc
->slot_index_to_bind_directly
= -1;
129 static void si_release_descriptors(struct si_descriptors
*desc
)
131 r600_resource_reference(&desc
->buffer
, NULL
);
135 static bool si_upload_descriptors(struct si_context
*sctx
,
136 struct si_descriptors
*desc
)
138 unsigned slot_size
= desc
->element_dw_size
* 4;
139 unsigned first_slot_offset
= desc
->first_active_slot
* slot_size
;
140 unsigned upload_size
= desc
->num_active_slots
* slot_size
;
142 /* Skip the upload if no shader is using the descriptors. dirty_mask
143 * will stay dirty and the descriptors will be uploaded when there is
144 * a shader using them.
149 /* If there is just one active descriptor, bind it directly. */
150 if ((int)desc
->first_active_slot
== desc
->slot_index_to_bind_directly
&&
151 desc
->num_active_slots
== 1) {
152 uint32_t *descriptor
= &desc
->list
[desc
->slot_index_to_bind_directly
*
153 desc
->element_dw_size
];
155 /* The buffer is already in the buffer list. */
156 r600_resource_reference(&desc
->buffer
, NULL
);
157 desc
->gpu_list
= NULL
;
158 desc
->gpu_address
= si_desc_extract_buffer_address(descriptor
);
159 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
165 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, upload_size
,
166 si_optimal_tcc_alignment(sctx
, upload_size
),
167 (unsigned*)&buffer_offset
,
168 (struct pipe_resource
**)&desc
->buffer
,
171 desc
->gpu_address
= 0;
172 return false; /* skip the draw call */
175 util_memcpy_cpu_to_le32(ptr
, (char*)desc
->list
+ first_slot_offset
,
177 desc
->gpu_list
= ptr
- first_slot_offset
/ 4;
179 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
180 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
182 /* The shader pointer should point to slot 0. */
183 buffer_offset
-= first_slot_offset
;
184 desc
->gpu_address
= desc
->buffer
->gpu_address
+ buffer_offset
;
186 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
191 si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
196 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
197 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
202 static inline enum radeon_bo_priority
203 si_get_sampler_view_priority(struct r600_resource
*res
)
205 if (res
->b
.b
.target
== PIPE_BUFFER
)
206 return RADEON_PRIO_SAMPLER_BUFFER
;
208 if (res
->b
.b
.nr_samples
> 1)
209 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
211 return RADEON_PRIO_SAMPLER_TEXTURE
;
215 si_sampler_and_image_descriptors_idx(unsigned shader
)
217 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
218 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
;
221 static struct si_descriptors
*
222 si_sampler_and_image_descriptors(struct si_context
*sctx
, unsigned shader
)
224 return &sctx
->descriptors
[si_sampler_and_image_descriptors_idx(shader
)];
227 static void si_release_sampler_views(struct si_samplers
*samplers
)
231 for (i
= 0; i
< ARRAY_SIZE(samplers
->views
); i
++) {
232 pipe_sampler_view_reference(&samplers
->views
[i
], NULL
);
236 static void si_sampler_view_add_buffer(struct si_context
*sctx
,
237 struct pipe_resource
*resource
,
238 enum radeon_bo_usage usage
,
239 bool is_stencil_sampler
,
242 struct r600_resource
*rres
;
243 struct r600_texture
*rtex
;
244 enum radeon_bo_priority priority
;
249 if (resource
->target
!= PIPE_BUFFER
) {
250 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
252 if (tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil_sampler
))
253 resource
= &tex
->flushed_depth_texture
->resource
.b
.b
;
256 rres
= (struct r600_resource
*)resource
;
257 priority
= si_get_sampler_view_priority(rres
);
259 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
260 rres
, usage
, priority
,
263 if (resource
->target
== PIPE_BUFFER
)
266 /* Now add separate DCC or HTILE. */
267 rtex
= (struct r600_texture
*)resource
;
268 if (rtex
->dcc_separate_buffer
) {
269 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
270 rtex
->dcc_separate_buffer
, usage
,
271 RADEON_PRIO_DCC
, check_mem
);
275 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
,
276 struct si_samplers
*samplers
)
278 unsigned mask
= samplers
->enabled_mask
;
280 /* Add buffers to the CS. */
282 int i
= u_bit_scan(&mask
);
283 struct si_sampler_view
*sview
= (struct si_sampler_view
*)samplers
->views
[i
];
285 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
287 sview
->is_stencil_sampler
, false);
291 /* Set buffer descriptor fields that can be changed by reallocations. */
292 static void si_set_buf_desc_address(struct r600_resource
*buf
,
293 uint64_t offset
, uint32_t *state
)
295 uint64_t va
= buf
->gpu_address
+ offset
;
298 state
[1] &= C_008F04_BASE_ADDRESS_HI
;
299 state
[1] |= S_008F04_BASE_ADDRESS_HI(va
>> 32);
302 /* Set texture descriptor fields that can be changed by reallocations.
305 * \param base_level_info information of the level of BASE_ADDRESS
306 * \param base_level the level of BASE_ADDRESS
307 * \param first_level pipe_sampler_view.u.tex.first_level
308 * \param block_width util_format_get_blockwidth()
309 * \param is_stencil select between separate Z & Stencil
310 * \param state descriptor to update
312 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
313 struct r600_texture
*tex
,
314 const struct legacy_surf_level
*base_level_info
,
315 unsigned base_level
, unsigned first_level
,
316 unsigned block_width
, bool is_stencil
,
319 uint64_t va
, meta_va
= 0;
321 if (tex
->is_depth
&& !si_can_sample_zs(tex
, is_stencil
)) {
322 tex
= tex
->flushed_depth_texture
;
326 va
= tex
->resource
.gpu_address
;
328 if (sscreen
->info
.chip_class
>= GFX9
) {
329 /* Only stencil_offset needs to be added here. */
331 va
+= tex
->surface
.u
.gfx9
.stencil_offset
;
333 va
+= tex
->surface
.u
.gfx9
.surf_offset
;
335 va
+= base_level_info
->offset
;
339 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
340 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
342 /* Only macrotiled modes can set tile swizzle.
343 * GFX9 doesn't use (legacy) base_level_info.
345 if (sscreen
->info
.chip_class
>= GFX9
||
346 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
347 state
[0] |= tex
->surface
.tile_swizzle
;
349 if (sscreen
->info
.chip_class
>= VI
) {
350 state
[6] &= C_008F28_COMPRESSION_EN
;
353 if (vi_dcc_enabled(tex
, first_level
)) {
354 meta_va
= (!tex
->dcc_separate_buffer
? tex
->resource
.gpu_address
: 0) +
357 if (sscreen
->info
.chip_class
== VI
) {
358 meta_va
+= base_level_info
->dcc_offset
;
359 assert(base_level_info
->mode
== RADEON_SURF_MODE_2D
);
362 meta_va
|= (uint32_t)tex
->surface
.tile_swizzle
<< 8;
363 } else if (vi_tc_compat_htile_enabled(tex
, first_level
)) {
364 meta_va
= tex
->resource
.gpu_address
+ tex
->htile_offset
;
368 state
[6] |= S_008F28_COMPRESSION_EN(1);
369 state
[7] = meta_va
>> 8;
373 if (sscreen
->info
.chip_class
>= GFX9
) {
374 state
[3] &= C_008F1C_SW_MODE
;
375 state
[4] &= C_008F20_PITCH_GFX9
;
378 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
379 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.stencil
.epitch
);
381 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
382 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.surf
.epitch
);
385 state
[5] &= C_008F24_META_DATA_ADDRESS
&
386 C_008F24_META_PIPE_ALIGNED
&
387 C_008F24_META_RB_ALIGNED
;
389 struct gfx9_surf_meta_flags meta
;
392 meta
= tex
->surface
.u
.gfx9
.dcc
;
394 meta
= tex
->surface
.u
.gfx9
.htile
;
396 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
397 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
398 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
402 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
403 unsigned index
= si_tile_mode_index(tex
, base_level
, is_stencil
);
405 state
[3] &= C_008F1C_TILING_INDEX
;
406 state
[3] |= S_008F1C_TILING_INDEX(index
);
407 state
[4] &= C_008F20_PITCH_GFX6
;
408 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
412 static void si_set_sampler_state_desc(struct si_sampler_state
*sstate
,
413 struct si_sampler_view
*sview
,
414 struct r600_texture
*tex
,
417 if (sview
&& sview
->is_integer
)
418 memcpy(desc
, sstate
->integer_val
, 4*4);
419 else if (tex
&& tex
->upgraded_depth
&&
420 (!sview
|| !sview
->is_stencil_sampler
))
421 memcpy(desc
, sstate
->upgraded_depth_val
, 4*4);
423 memcpy(desc
, sstate
->val
, 4*4);
426 static void si_set_sampler_view_desc(struct si_context
*sctx
,
427 struct si_sampler_view
*sview
,
428 struct si_sampler_state
*sstate
,
431 struct pipe_sampler_view
*view
= &sview
->base
;
432 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
433 bool is_buffer
= rtex
->resource
.b
.b
.target
== PIPE_BUFFER
;
435 if (unlikely(!is_buffer
&& sview
->dcc_incompatible
)) {
436 if (vi_dcc_enabled(rtex
, view
->u
.tex
.first_level
))
437 if (!si_texture_disable_dcc(&sctx
->b
, rtex
))
438 sctx
->b
.decompress_dcc(&sctx
->b
.b
, rtex
);
440 sview
->dcc_incompatible
= false;
443 assert(rtex
); /* views with texture == NULL aren't supported */
444 memcpy(desc
, sview
->state
, 8*4);
447 si_set_buf_desc_address(&rtex
->resource
,
448 sview
->base
.u
.buf
.offset
,
451 bool is_separate_stencil
= rtex
->db_compatible
&&
452 sview
->is_stencil_sampler
;
454 si_set_mutable_tex_desc_fields(sctx
->screen
, rtex
,
455 sview
->base_level_info
,
457 sview
->base
.u
.tex
.first_level
,
463 if (!is_buffer
&& rtex
->fmask
.size
) {
464 memcpy(desc
+ 8, sview
->fmask_state
, 8*4);
466 /* Disable FMASK and bind sampler state in [12:15]. */
467 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
470 si_set_sampler_state_desc(sstate
, sview
,
471 is_buffer
? NULL
: rtex
,
476 static bool color_needs_decompression(struct r600_texture
*rtex
)
478 return rtex
->fmask
.size
||
479 (rtex
->dirty_level_mask
&&
480 (rtex
->cmask
.size
|| rtex
->dcc_offset
));
483 static bool depth_needs_decompression(struct r600_texture
*rtex
)
485 /* If the depth/stencil texture is TC-compatible, no decompression
486 * will be done. The decompression function will only flush DB caches
487 * to make it coherent with shaders. That's necessary because the driver
488 * doesn't flush DB caches in any other case.
490 return rtex
->db_compatible
;
493 static void si_set_sampler_view(struct si_context
*sctx
,
495 unsigned slot
, struct pipe_sampler_view
*view
,
496 bool disallow_early_out
)
498 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
499 struct si_sampler_view
*rview
= (struct si_sampler_view
*)view
;
500 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
501 unsigned desc_slot
= si_get_sampler_slot(slot
);
502 uint32_t *desc
= descs
->list
+ desc_slot
* 16;
504 if (samplers
->views
[slot
] == view
&& !disallow_early_out
)
508 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
510 si_set_sampler_view_desc(sctx
, rview
,
511 samplers
->sampler_states
[slot
], desc
);
513 if (rtex
->resource
.b
.b
.target
== PIPE_BUFFER
) {
514 rtex
->resource
.bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
515 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
516 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
518 if (depth_needs_decompression(rtex
)) {
519 samplers
->needs_depth_decompress_mask
|= 1u << slot
;
521 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
523 if (color_needs_decompression(rtex
)) {
524 samplers
->needs_color_decompress_mask
|= 1u << slot
;
526 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
529 if (rtex
->dcc_offset
&&
530 p_atomic_read(&rtex
->framebuffers_bound
))
531 sctx
->need_check_render_feedback
= true;
534 pipe_sampler_view_reference(&samplers
->views
[slot
], view
);
535 samplers
->enabled_mask
|= 1u << slot
;
537 /* Since this can flush, it must be done after enabled_mask is
539 si_sampler_view_add_buffer(sctx
, view
->texture
,
541 rview
->is_stencil_sampler
, true);
543 pipe_sampler_view_reference(&samplers
->views
[slot
], NULL
);
544 memcpy(desc
, null_texture_descriptor
, 8*4);
545 /* Only clear the lower dwords of FMASK. */
546 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
547 /* Re-set the sampler state if we are transitioning from FMASK. */
548 if (samplers
->sampler_states
[slot
])
549 si_set_sampler_state_desc(samplers
->sampler_states
[slot
], NULL
, NULL
,
552 samplers
->enabled_mask
&= ~(1u << slot
);
553 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
554 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
557 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
560 static void si_update_shader_needs_decompress_mask(struct si_context
*sctx
,
563 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
564 unsigned shader_bit
= 1 << shader
;
566 if (samplers
->needs_depth_decompress_mask
||
567 samplers
->needs_color_decompress_mask
||
568 sctx
->images
[shader
].needs_color_decompress_mask
)
569 sctx
->shader_needs_decompress_mask
|= shader_bit
;
571 sctx
->shader_needs_decompress_mask
&= ~shader_bit
;
574 static void si_set_sampler_views(struct pipe_context
*ctx
,
575 enum pipe_shader_type shader
, unsigned start
,
577 struct pipe_sampler_view
**views
)
579 struct si_context
*sctx
= (struct si_context
*)ctx
;
582 if (!count
|| shader
>= SI_NUM_SHADERS
)
586 for (i
= 0; i
< count
; i
++)
587 si_set_sampler_view(sctx
, shader
, start
+ i
, views
[i
], false);
589 for (i
= 0; i
< count
; i
++)
590 si_set_sampler_view(sctx
, shader
, start
+ i
, NULL
, false);
593 si_update_shader_needs_decompress_mask(sctx
, shader
);
597 si_samplers_update_needs_color_decompress_mask(struct si_samplers
*samplers
)
599 unsigned mask
= samplers
->enabled_mask
;
602 int i
= u_bit_scan(&mask
);
603 struct pipe_resource
*res
= samplers
->views
[i
]->texture
;
605 if (res
&& res
->target
!= PIPE_BUFFER
) {
606 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
608 if (color_needs_decompression(rtex
)) {
609 samplers
->needs_color_decompress_mask
|= 1u << i
;
611 samplers
->needs_color_decompress_mask
&= ~(1u << i
);
620 si_release_image_views(struct si_images
*images
)
624 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
625 struct pipe_image_view
*view
= &images
->views
[i
];
627 pipe_resource_reference(&view
->resource
, NULL
);
632 si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images
*images
)
634 uint mask
= images
->enabled_mask
;
636 /* Add buffers to the CS. */
638 int i
= u_bit_scan(&mask
);
639 struct pipe_image_view
*view
= &images
->views
[i
];
641 assert(view
->resource
);
643 si_sampler_view_add_buffer(sctx
, view
->resource
,
644 RADEON_USAGE_READWRITE
, false, false);
649 si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
651 struct si_images
*images
= &ctx
->images
[shader
];
653 if (images
->enabled_mask
& (1u << slot
)) {
654 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
655 unsigned desc_slot
= si_get_image_slot(slot
);
657 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
658 images
->needs_color_decompress_mask
&= ~(1 << slot
);
660 memcpy(descs
->list
+ desc_slot
*8, null_image_descriptor
, 8*4);
661 images
->enabled_mask
&= ~(1u << slot
);
662 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
667 si_mark_image_range_valid(const struct pipe_image_view
*view
)
669 struct r600_resource
*res
= (struct r600_resource
*)view
->resource
;
671 assert(res
&& res
->b
.b
.target
== PIPE_BUFFER
);
673 util_range_add(&res
->valid_buffer_range
,
675 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
678 static void si_set_shader_image_desc(struct si_context
*ctx
,
679 const struct pipe_image_view
*view
,
680 bool skip_decompress
,
683 struct si_screen
*screen
= ctx
->screen
;
684 struct r600_resource
*res
;
686 res
= (struct r600_resource
*)view
->resource
;
688 if (res
->b
.b
.target
== PIPE_BUFFER
) {
689 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
690 si_mark_image_range_valid(view
);
692 si_make_buffer_descriptor(screen
, res
,
695 view
->u
.buf
.size
, desc
);
696 si_set_buf_desc_address(res
, view
->u
.buf
.offset
, desc
+ 4);
698 static const unsigned char swizzle
[4] = { 0, 1, 2, 3 };
699 struct r600_texture
*tex
= (struct r600_texture
*)res
;
700 unsigned level
= view
->u
.tex
.level
;
701 unsigned width
, height
, depth
, hw_level
;
702 bool uses_dcc
= vi_dcc_enabled(tex
, level
);
703 unsigned access
= view
->access
;
705 /* Clear the write flag when writes can't occur.
706 * Note that DCC_DECOMPRESS for MSAA doesn't work in some cases,
707 * so we don't wanna trigger it.
709 if (tex
->is_depth
|| tex
->resource
.b
.b
.nr_samples
>= 2) {
710 assert(!"Z/S and MSAA image stores are not supported");
711 access
&= ~PIPE_IMAGE_ACCESS_WRITE
;
714 assert(!tex
->is_depth
);
715 assert(tex
->fmask
.size
== 0);
717 if (uses_dcc
&& !skip_decompress
&&
718 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
||
719 !vi_dcc_formats_compatible(res
->b
.b
.format
, view
->format
))) {
720 /* If DCC can't be disabled, at least decompress it.
721 * The decompression is relatively cheap if the surface
722 * has been decompressed already.
724 if (!si_texture_disable_dcc(&ctx
->b
, tex
))
725 ctx
->b
.decompress_dcc(&ctx
->b
.b
, tex
);
728 if (ctx
->b
.chip_class
>= GFX9
) {
729 /* Always set the base address. The swizzle modes don't
730 * allow setting mipmap level offsets as the base.
732 width
= res
->b
.b
.width0
;
733 height
= res
->b
.b
.height0
;
734 depth
= res
->b
.b
.depth0
;
737 /* Always force the base level to the selected level.
739 * This is required for 3D textures, where otherwise
740 * selecting a single slice for non-layered bindings
741 * fails. It doesn't hurt the other targets.
743 width
= u_minify(res
->b
.b
.width0
, level
);
744 height
= u_minify(res
->b
.b
.height0
, level
);
745 depth
= u_minify(res
->b
.b
.depth0
, level
);
749 si_make_texture_descriptor(screen
, tex
,
750 false, res
->b
.b
.target
,
751 view
->format
, swizzle
,
753 view
->u
.tex
.first_layer
,
754 view
->u
.tex
.last_layer
,
755 width
, height
, depth
,
757 si_set_mutable_tex_desc_fields(screen
, tex
,
758 &tex
->surface
.u
.legacy
.level
[level
],
760 util_format_get_blockwidth(view
->format
),
765 static void si_set_shader_image(struct si_context
*ctx
,
767 unsigned slot
, const struct pipe_image_view
*view
,
768 bool skip_decompress
)
770 struct si_images
*images
= &ctx
->images
[shader
];
771 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
772 struct r600_resource
*res
;
773 unsigned desc_slot
= si_get_image_slot(slot
);
774 uint32_t *desc
= descs
->list
+ desc_slot
* 8;
776 if (!view
|| !view
->resource
) {
777 si_disable_shader_image(ctx
, shader
, slot
);
781 res
= (struct r600_resource
*)view
->resource
;
783 if (&images
->views
[slot
] != view
)
784 util_copy_image_view(&images
->views
[slot
], view
);
786 si_set_shader_image_desc(ctx
, view
, skip_decompress
, desc
);
788 if (res
->b
.b
.target
== PIPE_BUFFER
) {
789 images
->needs_color_decompress_mask
&= ~(1 << slot
);
790 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
792 struct r600_texture
*tex
= (struct r600_texture
*)res
;
793 unsigned level
= view
->u
.tex
.level
;
795 if (color_needs_decompression(tex
)) {
796 images
->needs_color_decompress_mask
|= 1 << slot
;
798 images
->needs_color_decompress_mask
&= ~(1 << slot
);
801 if (vi_dcc_enabled(tex
, level
) &&
802 p_atomic_read(&tex
->framebuffers_bound
))
803 ctx
->need_check_render_feedback
= true;
806 images
->enabled_mask
|= 1u << slot
;
807 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
809 /* Since this can flush, it must be done after enabled_mask is updated. */
810 si_sampler_view_add_buffer(ctx
, &res
->b
.b
,
811 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
) ?
812 RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
,
817 si_set_shader_images(struct pipe_context
*pipe
,
818 enum pipe_shader_type shader
,
819 unsigned start_slot
, unsigned count
,
820 const struct pipe_image_view
*views
)
822 struct si_context
*ctx
= (struct si_context
*)pipe
;
825 assert(shader
< SI_NUM_SHADERS
);
830 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
833 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
834 si_set_shader_image(ctx
, shader
, slot
, &views
[i
], false);
836 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
837 si_set_shader_image(ctx
, shader
, slot
, NULL
, false);
840 si_update_shader_needs_decompress_mask(ctx
, shader
);
844 si_images_update_needs_color_decompress_mask(struct si_images
*images
)
846 unsigned mask
= images
->enabled_mask
;
849 int i
= u_bit_scan(&mask
);
850 struct pipe_resource
*res
= images
->views
[i
].resource
;
852 if (res
&& res
->target
!= PIPE_BUFFER
) {
853 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
855 if (color_needs_decompression(rtex
)) {
856 images
->needs_color_decompress_mask
|= 1 << i
;
858 images
->needs_color_decompress_mask
&= ~(1 << i
);
866 static void si_bind_sampler_states(struct pipe_context
*ctx
,
867 enum pipe_shader_type shader
,
868 unsigned start
, unsigned count
, void **states
)
870 struct si_context
*sctx
= (struct si_context
*)ctx
;
871 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
872 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, shader
);
873 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
876 if (!count
|| shader
>= SI_NUM_SHADERS
)
879 for (i
= 0; i
< count
; i
++) {
880 unsigned slot
= start
+ i
;
881 unsigned desc_slot
= si_get_sampler_slot(slot
);
884 sstates
[i
] == samplers
->sampler_states
[slot
])
888 assert(sstates
[i
]->magic
== SI_SAMPLER_STATE_MAGIC
);
890 samplers
->sampler_states
[slot
] = sstates
[i
];
892 /* If FMASK is bound, don't overwrite it.
893 * The sampler state will be set after FMASK is unbound.
895 struct si_sampler_view
*sview
=
896 (struct si_sampler_view
*)samplers
->views
[slot
];
898 struct r600_texture
*tex
= NULL
;
900 if (sview
&& sview
->base
.texture
&&
901 sview
->base
.texture
->target
!= PIPE_BUFFER
)
902 tex
= (struct r600_texture
*)sview
->base
.texture
;
904 if (tex
&& tex
->fmask
.size
)
907 si_set_sampler_state_desc(sstates
[i
], sview
, tex
,
908 desc
->list
+ desc_slot
* 16 + 12);
910 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
914 /* BUFFER RESOURCES */
916 static void si_init_buffer_resources(struct si_buffer_resources
*buffers
,
917 struct si_descriptors
*descs
,
918 unsigned num_buffers
,
919 short shader_userdata_rel_index
,
920 enum radeon_bo_usage shader_usage
,
921 enum radeon_bo_usage shader_usage_constbuf
,
922 enum radeon_bo_priority priority
,
923 enum radeon_bo_priority priority_constbuf
)
925 buffers
->shader_usage
= shader_usage
;
926 buffers
->shader_usage_constbuf
= shader_usage_constbuf
;
927 buffers
->priority
= priority
;
928 buffers
->priority_constbuf
= priority_constbuf
;
929 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
931 si_init_descriptors(descs
, shader_userdata_rel_index
, 4, num_buffers
);
934 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
935 struct si_descriptors
*descs
)
939 for (i
= 0; i
< descs
->num_elements
; i
++) {
940 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
943 FREE(buffers
->buffers
);
946 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
947 struct si_buffer_resources
*buffers
)
949 unsigned mask
= buffers
->enabled_mask
;
951 /* Add buffers to the CS. */
953 int i
= u_bit_scan(&mask
);
955 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
956 r600_resource(buffers
->buffers
[i
]),
957 i
< SI_NUM_SHADER_BUFFERS
? buffers
->shader_usage
:
958 buffers
->shader_usage_constbuf
,
959 i
< SI_NUM_SHADER_BUFFERS
? buffers
->priority
:
960 buffers
->priority_constbuf
);
964 static void si_get_buffer_from_descriptors(struct si_buffer_resources
*buffers
,
965 struct si_descriptors
*descs
,
966 unsigned idx
, struct pipe_resource
**buf
,
967 unsigned *offset
, unsigned *size
)
969 pipe_resource_reference(buf
, buffers
->buffers
[idx
]);
971 struct r600_resource
*res
= r600_resource(*buf
);
972 const uint32_t *desc
= descs
->list
+ idx
* 4;
977 assert(G_008F04_STRIDE(desc
[1]) == 0);
978 va
= ((uint64_t)desc
[1] << 32) | desc
[0];
980 assert(va
>= res
->gpu_address
&& va
+ *size
<= res
->gpu_address
+ res
->bo_size
);
981 *offset
= va
- res
->gpu_address
;
987 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
989 struct si_descriptors
*desc
= &sctx
->vertex_buffers
;
990 int count
= sctx
->vertex_elements
? sctx
->vertex_elements
->count
: 0;
993 for (i
= 0; i
< count
; i
++) {
994 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
996 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
998 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1001 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1002 (struct r600_resource
*)sctx
->vertex_buffer
[vb
].buffer
.resource
,
1003 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1008 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1009 desc
->buffer
, RADEON_USAGE_READ
,
1010 RADEON_PRIO_DESCRIPTORS
);
1013 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
1015 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
1016 struct si_descriptors
*desc
= &sctx
->vertex_buffers
;
1018 unsigned desc_list_byte_size
;
1019 unsigned first_vb_use_mask
;
1022 if (!sctx
->vertex_buffers_dirty
|| !velems
)
1025 count
= velems
->count
;
1030 desc_list_byte_size
= velems
->desc_list_byte_size
;
1031 first_vb_use_mask
= velems
->first_vb_use_mask
;
1033 /* Vertex buffer descriptors are the only ones which are uploaded
1034 * directly through a staging buffer and don't go through
1035 * the fine-grained upload path.
1037 unsigned buffer_offset
= 0;
1038 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0,
1039 desc_list_byte_size
,
1040 si_optimal_tcc_alignment(sctx
, desc_list_byte_size
),
1042 (struct pipe_resource
**)&desc
->buffer
, (void**)&ptr
);
1043 if (!desc
->buffer
) {
1044 desc
->gpu_address
= 0;
1048 desc
->gpu_address
= desc
->buffer
->gpu_address
+ buffer_offset
;
1050 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1051 desc
->buffer
, RADEON_USAGE_READ
,
1052 RADEON_PRIO_DESCRIPTORS
);
1054 assert(count
<= SI_MAX_ATTRIBS
);
1056 for (i
= 0; i
< count
; i
++) {
1057 struct pipe_vertex_buffer
*vb
;
1058 struct r600_resource
*rbuffer
;
1059 unsigned vbo_index
= velems
->vertex_buffer_index
[i
];
1060 uint32_t *desc
= &ptr
[i
*4];
1062 vb
= &sctx
->vertex_buffer
[vbo_index
];
1063 rbuffer
= (struct r600_resource
*)vb
->buffer
.resource
;
1065 memset(desc
, 0, 16);
1069 int offset
= (int)vb
->buffer_offset
+ (int)velems
->src_offset
[i
];
1070 int64_t va
= (int64_t)rbuffer
->gpu_address
+ offset
;
1073 int64_t num_records
= (int64_t)rbuffer
->b
.b
.width0
- offset
;
1074 if (sctx
->b
.chip_class
!= VI
&& vb
->stride
) {
1075 /* Round up by rounding down and adding 1 */
1076 num_records
= (num_records
- velems
->format_size
[i
]) /
1079 assert(num_records
>= 0 && num_records
<= UINT_MAX
);
1082 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1083 S_008F04_STRIDE(vb
->stride
);
1084 desc
[2] = num_records
;
1085 desc
[3] = velems
->rsrc_word3
[i
];
1087 if (first_vb_use_mask
& (1 << i
)) {
1088 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1089 (struct r600_resource
*)vb
->buffer
.resource
,
1090 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1094 /* Don't flush the const cache. It would have a very negative effect
1095 * on performance (confirmed by testing). New descriptors are always
1096 * uploaded to a fresh new buffer, so I don't think flushing the const
1097 * cache is needed. */
1098 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1099 sctx
->vertex_buffers_dirty
= false;
1100 sctx
->vertex_buffer_pointer_dirty
= true;
1101 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VBO_DESCRIPTORS
;
1106 /* CONSTANT BUFFERS */
1109 si_const_and_shader_buffer_descriptors_idx(unsigned shader
)
1111 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
1112 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
;
1115 static struct si_descriptors
*
1116 si_const_and_shader_buffer_descriptors(struct si_context
*sctx
, unsigned shader
)
1118 return &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(shader
)];
1121 void si_upload_const_buffer(struct si_context
*sctx
, struct r600_resource
**rbuffer
,
1122 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
)
1126 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, size
,
1127 si_optimal_tcc_alignment(sctx
, size
),
1129 (struct pipe_resource
**)rbuffer
, &tmp
);
1131 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
1134 static void si_set_constant_buffer(struct si_context
*sctx
,
1135 struct si_buffer_resources
*buffers
,
1136 unsigned descriptors_idx
,
1137 uint slot
, const struct pipe_constant_buffer
*input
)
1139 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1140 assert(slot
< descs
->num_elements
);
1141 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1143 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1144 * with a NULL buffer). We need to use a dummy buffer instead. */
1145 if (sctx
->b
.chip_class
== CIK
&&
1146 (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
1147 input
= &sctx
->null_const_buf
;
1149 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1150 struct pipe_resource
*buffer
= NULL
;
1153 /* Upload the user buffer if needed. */
1154 if (input
->user_buffer
) {
1155 unsigned buffer_offset
;
1157 si_upload_const_buffer(sctx
,
1158 (struct r600_resource
**)&buffer
, input
->user_buffer
,
1159 input
->buffer_size
, &buffer_offset
);
1161 /* Just unbind on failure. */
1162 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1165 va
= r600_resource(buffer
)->gpu_address
+ buffer_offset
;
1167 pipe_resource_reference(&buffer
, input
->buffer
);
1168 va
= r600_resource(buffer
)->gpu_address
+ input
->buffer_offset
;
1169 /* Only track usage for non-user buffers. */
1170 r600_resource(buffer
)->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
1173 /* Set the descriptor. */
1174 uint32_t *desc
= descs
->list
+ slot
*4;
1176 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1178 desc
[2] = input
->buffer_size
;
1179 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1180 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1181 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1182 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1183 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1184 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1186 buffers
->buffers
[slot
] = buffer
;
1187 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1188 (struct r600_resource
*)buffer
,
1189 buffers
->shader_usage_constbuf
,
1190 buffers
->priority_constbuf
, true);
1191 buffers
->enabled_mask
|= 1u << slot
;
1193 /* Clear the descriptor. */
1194 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1195 buffers
->enabled_mask
&= ~(1u << slot
);
1198 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1201 void si_set_rw_buffer(struct si_context
*sctx
,
1202 uint slot
, const struct pipe_constant_buffer
*input
)
1204 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
,
1205 SI_DESCS_RW_BUFFERS
, slot
, input
);
1208 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
,
1209 enum pipe_shader_type shader
, uint slot
,
1210 const struct pipe_constant_buffer
*input
)
1212 struct si_context
*sctx
= (struct si_context
*)ctx
;
1214 if (shader
>= SI_NUM_SHADERS
)
1217 if (slot
== 0 && input
&& input
->buffer
&&
1218 !(r600_resource(input
->buffer
)->flags
& RADEON_FLAG_32BIT
)) {
1219 assert(!"constant buffer 0 must have a 32-bit VM address, use const_uploader");
1223 slot
= si_get_constbuf_slot(slot
);
1224 si_set_constant_buffer(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1225 si_const_and_shader_buffer_descriptors_idx(shader
),
1229 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
1230 uint slot
, struct pipe_constant_buffer
*cbuf
)
1232 cbuf
->user_buffer
= NULL
;
1233 si_get_buffer_from_descriptors(
1234 &sctx
->const_and_shader_buffers
[shader
],
1235 si_const_and_shader_buffer_descriptors(sctx
, shader
),
1236 si_get_constbuf_slot(slot
),
1237 &cbuf
->buffer
, &cbuf
->buffer_offset
, &cbuf
->buffer_size
);
1240 /* SHADER BUFFERS */
1242 static void si_set_shader_buffers(struct pipe_context
*ctx
,
1243 enum pipe_shader_type shader
,
1244 unsigned start_slot
, unsigned count
,
1245 const struct pipe_shader_buffer
*sbuffers
)
1247 struct si_context
*sctx
= (struct si_context
*)ctx
;
1248 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1249 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1252 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1254 for (i
= 0; i
< count
; ++i
) {
1255 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1256 struct r600_resource
*buf
;
1257 unsigned slot
= si_get_shaderbuf_slot(start_slot
+ i
);
1258 uint32_t *desc
= descs
->list
+ slot
* 4;
1261 if (!sbuffer
|| !sbuffer
->buffer
) {
1262 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1263 memset(desc
, 0, sizeof(uint32_t) * 4);
1264 buffers
->enabled_mask
&= ~(1u << slot
);
1265 sctx
->descriptors_dirty
|=
1266 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1270 buf
= (struct r600_resource
*)sbuffer
->buffer
;
1271 va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1274 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1276 desc
[2] = sbuffer
->buffer_size
;
1277 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1278 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1279 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1280 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1281 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1282 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1284 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1285 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
, buf
,
1286 buffers
->shader_usage
,
1287 buffers
->priority
, true);
1288 buf
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1290 buffers
->enabled_mask
|= 1u << slot
;
1291 sctx
->descriptors_dirty
|=
1292 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1294 util_range_add(&buf
->valid_buffer_range
, sbuffer
->buffer_offset
,
1295 sbuffer
->buffer_offset
+ sbuffer
->buffer_size
);
1299 void si_get_shader_buffers(struct si_context
*sctx
,
1300 enum pipe_shader_type shader
,
1301 uint start_slot
, uint count
,
1302 struct pipe_shader_buffer
*sbuf
)
1304 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1305 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1307 for (unsigned i
= 0; i
< count
; ++i
) {
1308 si_get_buffer_from_descriptors(
1310 si_get_shaderbuf_slot(start_slot
+ i
),
1311 &sbuf
[i
].buffer
, &sbuf
[i
].buffer_offset
,
1312 &sbuf
[i
].buffer_size
);
1318 void si_set_ring_buffer(struct pipe_context
*ctx
, uint slot
,
1319 struct pipe_resource
*buffer
,
1320 unsigned stride
, unsigned num_records
,
1321 bool add_tid
, bool swizzle
,
1322 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1324 struct si_context
*sctx
= (struct si_context
*)ctx
;
1325 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1326 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1328 /* The stride field in the resource descriptor has 14 bits */
1329 assert(stride
< (1 << 14));
1331 assert(slot
< descs
->num_elements
);
1332 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1337 va
= r600_resource(buffer
)->gpu_address
+ offset
;
1339 switch (element_size
) {
1341 assert(!"Unsupported ring buffer element size");
1357 switch (index_stride
) {
1359 assert(!"Unsupported ring buffer index stride");
1375 if (sctx
->b
.chip_class
>= VI
&& stride
)
1376 num_records
*= stride
;
1378 /* Set the descriptor. */
1379 uint32_t *desc
= descs
->list
+ slot
*4;
1381 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1382 S_008F04_STRIDE(stride
) |
1383 S_008F04_SWIZZLE_ENABLE(swizzle
);
1384 desc
[2] = num_records
;
1385 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1386 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1387 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1388 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1389 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1390 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1391 S_008F0C_INDEX_STRIDE(index_stride
) |
1392 S_008F0C_ADD_TID_ENABLE(add_tid
);
1394 if (sctx
->b
.chip_class
>= GFX9
)
1395 assert(!swizzle
|| element_size
== 1); /* always 4 bytes on GFX9 */
1397 desc
[3] |= S_008F0C_ELEMENT_SIZE(element_size
);
1399 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1400 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1401 (struct r600_resource
*)buffer
,
1402 buffers
->shader_usage
, buffers
->priority
);
1403 buffers
->enabled_mask
|= 1u << slot
;
1405 /* Clear the descriptor. */
1406 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1407 buffers
->enabled_mask
&= ~(1u << slot
);
1410 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1413 static void si_desc_reset_buffer_offset(struct pipe_context
*ctx
,
1414 uint32_t *desc
, uint64_t old_buf_va
,
1415 struct pipe_resource
*new_buf
)
1417 /* Retrieve the buffer offset from the descriptor. */
1418 uint64_t old_desc_va
= si_desc_extract_buffer_address(desc
);
1420 assert(old_buf_va
<= old_desc_va
);
1421 uint64_t offset_within_buffer
= old_desc_va
- old_buf_va
;
1423 /* Update the descriptor. */
1424 si_set_buf_desc_address(r600_resource(new_buf
), offset_within_buffer
,
1428 /* INTERNAL CONST BUFFERS */
1430 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
1431 const struct pipe_poly_stipple
*state
)
1433 struct si_context
*sctx
= (struct si_context
*)ctx
;
1434 struct pipe_constant_buffer cb
= {};
1435 unsigned stipple
[32];
1438 for (i
= 0; i
< 32; i
++)
1439 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1441 cb
.user_buffer
= stipple
;
1442 cb
.buffer_size
= sizeof(stipple
);
1444 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1447 /* TEXTURE METADATA ENABLE/DISABLE */
1450 si_resident_handles_update_needs_color_decompress(struct si_context
*sctx
)
1452 util_dynarray_clear(&sctx
->resident_tex_needs_color_decompress
);
1453 util_dynarray_clear(&sctx
->resident_img_needs_color_decompress
);
1455 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1456 struct si_texture_handle
*, tex_handle
) {
1457 struct pipe_resource
*res
= (*tex_handle
)->view
->texture
;
1458 struct r600_texture
*rtex
;
1460 if (!res
|| res
->target
== PIPE_BUFFER
)
1463 rtex
= (struct r600_texture
*)res
;
1464 if (!color_needs_decompression(rtex
))
1467 util_dynarray_append(&sctx
->resident_tex_needs_color_decompress
,
1468 struct si_texture_handle
*, *tex_handle
);
1471 util_dynarray_foreach(&sctx
->resident_img_handles
,
1472 struct si_image_handle
*, img_handle
) {
1473 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1474 struct pipe_resource
*res
= view
->resource
;
1475 struct r600_texture
*rtex
;
1477 if (!res
|| res
->target
== PIPE_BUFFER
)
1480 rtex
= (struct r600_texture
*)res
;
1481 if (!color_needs_decompression(rtex
))
1484 util_dynarray_append(&sctx
->resident_img_needs_color_decompress
,
1485 struct si_image_handle
*, *img_handle
);
1489 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1490 * while the texture is bound, possibly by a different context. In that case,
1491 * call this function to update needs_*_decompress_masks.
1493 void si_update_needs_color_decompress_masks(struct si_context
*sctx
)
1495 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1496 si_samplers_update_needs_color_decompress_mask(&sctx
->samplers
[i
]);
1497 si_images_update_needs_color_decompress_mask(&sctx
->images
[i
]);
1498 si_update_shader_needs_decompress_mask(sctx
, i
);
1501 si_resident_handles_update_needs_color_decompress(sctx
);
1504 /* BUFFER DISCARD/INVALIDATION */
1506 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1507 static void si_reset_buffer_resources(struct si_context
*sctx
,
1508 struct si_buffer_resources
*buffers
,
1509 unsigned descriptors_idx
,
1511 struct pipe_resource
*buf
,
1513 enum radeon_bo_usage usage
,
1514 enum radeon_bo_priority priority
)
1516 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1517 unsigned mask
= buffers
->enabled_mask
& slot_mask
;
1520 unsigned i
= u_bit_scan(&mask
);
1521 if (buffers
->buffers
[i
] == buf
) {
1522 si_desc_reset_buffer_offset(&sctx
->b
.b
,
1525 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1527 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1528 (struct r600_resource
*)buf
,
1529 usage
, priority
, true);
1534 static void si_rebind_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
,
1537 struct si_context
*sctx
= (struct si_context
*)ctx
;
1538 struct r600_resource
*rbuffer
= r600_resource(buf
);
1540 unsigned num_elems
= sctx
->vertex_elements
?
1541 sctx
->vertex_elements
->count
: 0;
1543 /* We changed the buffer, now we need to bind it where the old one
1544 * was bound. This consists of 2 things:
1545 * 1) Updating the resource descriptor and dirtying it.
1546 * 2) Adding a relocation to the CS, so that it's usable.
1549 /* Vertex buffers. */
1550 if (rbuffer
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
1551 for (i
= 0; i
< num_elems
; i
++) {
1552 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1554 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1556 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1559 if (sctx
->vertex_buffer
[vb
].buffer
.resource
== buf
) {
1560 sctx
->vertex_buffers_dirty
= true;
1566 /* Streamout buffers. (other internal buffers can't be invalidated) */
1567 if (rbuffer
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
1568 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1569 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1570 struct si_descriptors
*descs
=
1571 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1573 if (buffers
->buffers
[i
] != buf
)
1576 si_desc_reset_buffer_offset(ctx
, descs
->list
+ i
*4,
1578 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1580 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1581 rbuffer
, buffers
->shader_usage
,
1582 RADEON_PRIO_SHADER_RW_BUFFER
,
1585 /* Update the streamout state. */
1586 if (sctx
->streamout
.begin_emitted
)
1587 si_emit_streamout_end(sctx
);
1588 sctx
->streamout
.append_bitmask
=
1589 sctx
->streamout
.enabled_mask
;
1590 si_streamout_buffers_dirty(sctx
);
1594 /* Constant and shader buffers. */
1595 if (rbuffer
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1596 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1597 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1598 si_const_and_shader_buffer_descriptors_idx(shader
),
1599 u_bit_consecutive(SI_NUM_SHADER_BUFFERS
, SI_NUM_CONST_BUFFERS
),
1601 sctx
->const_and_shader_buffers
[shader
].shader_usage_constbuf
,
1602 sctx
->const_and_shader_buffers
[shader
].priority_constbuf
);
1605 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
1606 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1607 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1608 si_const_and_shader_buffer_descriptors_idx(shader
),
1609 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
),
1611 sctx
->const_and_shader_buffers
[shader
].shader_usage
,
1612 sctx
->const_and_shader_buffers
[shader
].priority
);
1615 if (rbuffer
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
1616 /* Texture buffers - update bindings. */
1617 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1618 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1619 struct si_descriptors
*descs
=
1620 si_sampler_and_image_descriptors(sctx
, shader
);
1621 unsigned mask
= samplers
->enabled_mask
;
1624 unsigned i
= u_bit_scan(&mask
);
1625 if (samplers
->views
[i
]->texture
== buf
) {
1626 unsigned desc_slot
= si_get_sampler_slot(i
);
1628 si_desc_reset_buffer_offset(ctx
,
1632 sctx
->descriptors_dirty
|=
1633 1u << si_sampler_and_image_descriptors_idx(shader
);
1635 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1636 rbuffer
, RADEON_USAGE_READ
,
1637 RADEON_PRIO_SAMPLER_BUFFER
,
1645 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
1646 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1647 struct si_images
*images
= &sctx
->images
[shader
];
1648 struct si_descriptors
*descs
=
1649 si_sampler_and_image_descriptors(sctx
, shader
);
1650 unsigned mask
= images
->enabled_mask
;
1653 unsigned i
= u_bit_scan(&mask
);
1655 if (images
->views
[i
].resource
== buf
) {
1656 unsigned desc_slot
= si_get_image_slot(i
);
1658 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1659 si_mark_image_range_valid(&images
->views
[i
]);
1661 si_desc_reset_buffer_offset(
1662 ctx
, descs
->list
+ desc_slot
* 8 + 4,
1664 sctx
->descriptors_dirty
|=
1665 1u << si_sampler_and_image_descriptors_idx(shader
);
1667 radeon_add_to_buffer_list_check_mem(
1668 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1669 RADEON_USAGE_READWRITE
,
1670 RADEON_PRIO_SAMPLER_BUFFER
, true);
1676 /* Bindless texture handles */
1677 if (rbuffer
->texture_handle_allocated
) {
1678 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1680 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1681 struct si_texture_handle
*, tex_handle
) {
1682 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
1683 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1685 if (view
->texture
== buf
) {
1686 si_set_buf_desc_address(rbuffer
,
1689 desc_slot
* 16 + 4);
1691 (*tex_handle
)->desc_dirty
= true;
1692 sctx
->bindless_descriptors_dirty
= true;
1694 radeon_add_to_buffer_list_check_mem(
1695 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1697 RADEON_PRIO_SAMPLER_BUFFER
, true);
1702 /* Bindless image handles */
1703 if (rbuffer
->image_handle_allocated
) {
1704 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1706 util_dynarray_foreach(&sctx
->resident_img_handles
,
1707 struct si_image_handle
*, img_handle
) {
1708 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1709 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1711 if (view
->resource
== buf
) {
1712 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
1713 si_mark_image_range_valid(view
);
1715 si_set_buf_desc_address(rbuffer
,
1718 desc_slot
* 16 + 4);
1720 (*img_handle
)->desc_dirty
= true;
1721 sctx
->bindless_descriptors_dirty
= true;
1723 radeon_add_to_buffer_list_check_mem(
1724 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1725 RADEON_USAGE_READWRITE
,
1726 RADEON_PRIO_SAMPLER_BUFFER
, true);
1732 /* Reallocate a buffer a update all resource bindings where the buffer is
1735 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
1736 * idle by discarding its contents. Apps usually tell us when to do this using
1737 * map_buffer flags, for example.
1739 static void si_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
1741 struct si_context
*sctx
= (struct si_context
*)ctx
;
1742 struct r600_resource
*rbuffer
= r600_resource(buf
);
1743 uint64_t old_va
= rbuffer
->gpu_address
;
1745 /* Reallocate the buffer in the same pipe_resource. */
1746 si_alloc_resource(sctx
->screen
, rbuffer
);
1748 si_rebind_buffer(ctx
, buf
, old_va
);
1751 static void si_upload_bindless_descriptor(struct si_context
*sctx
,
1753 unsigned num_dwords
)
1755 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1756 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1757 unsigned desc_slot_offset
= desc_slot
* 16;
1761 data
= desc
->list
+ desc_slot_offset
;
1762 va
= desc
->gpu_address
+ desc_slot_offset
* 4;
1764 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + num_dwords
, 0));
1765 radeon_emit(cs
, S_370_DST_SEL(V_370_TC_L2
) |
1766 S_370_WR_CONFIRM(1) |
1767 S_370_ENGINE_SEL(V_370_ME
));
1768 radeon_emit(cs
, va
);
1769 radeon_emit(cs
, va
>> 32);
1770 radeon_emit_array(cs
, data
, num_dwords
);
1773 static void si_upload_bindless_descriptors(struct si_context
*sctx
)
1775 if (!sctx
->bindless_descriptors_dirty
)
1778 /* Wait for graphics/compute to be idle before updating the resident
1779 * descriptors directly in memory, in case the GPU is using them.
1781 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
1782 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1783 si_emit_cache_flush(sctx
);
1785 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1786 struct si_texture_handle
*, tex_handle
) {
1787 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1789 if (!(*tex_handle
)->desc_dirty
)
1792 si_upload_bindless_descriptor(sctx
, desc_slot
, 16);
1793 (*tex_handle
)->desc_dirty
= false;
1796 util_dynarray_foreach(&sctx
->resident_img_handles
,
1797 struct si_image_handle
*, img_handle
) {
1798 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1800 if (!(*img_handle
)->desc_dirty
)
1803 si_upload_bindless_descriptor(sctx
, desc_slot
, 8);
1804 (*img_handle
)->desc_dirty
= false;
1807 /* Invalidate L1 because it doesn't know that L2 changed. */
1808 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
;
1809 si_emit_cache_flush(sctx
);
1811 sctx
->bindless_descriptors_dirty
= false;
1814 /* Update mutable image descriptor fields of all resident textures. */
1815 static void si_update_bindless_texture_descriptor(struct si_context
*sctx
,
1816 struct si_texture_handle
*tex_handle
)
1818 struct si_sampler_view
*sview
= (struct si_sampler_view
*)tex_handle
->view
;
1819 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1820 unsigned desc_slot_offset
= tex_handle
->desc_slot
* 16;
1821 uint32_t desc_list
[16];
1823 if (sview
->base
.texture
->target
== PIPE_BUFFER
)
1826 memcpy(desc_list
, desc
->list
+ desc_slot_offset
, sizeof(desc_list
));
1827 si_set_sampler_view_desc(sctx
, sview
, &tex_handle
->sstate
,
1828 desc
->list
+ desc_slot_offset
);
1830 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1831 sizeof(desc_list
))) {
1832 tex_handle
->desc_dirty
= true;
1833 sctx
->bindless_descriptors_dirty
= true;
1837 static void si_update_bindless_image_descriptor(struct si_context
*sctx
,
1838 struct si_image_handle
*img_handle
)
1840 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1841 unsigned desc_slot_offset
= img_handle
->desc_slot
* 16;
1842 struct pipe_image_view
*view
= &img_handle
->view
;
1843 uint32_t desc_list
[8];
1845 if (view
->resource
->target
== PIPE_BUFFER
)
1848 memcpy(desc_list
, desc
->list
+ desc_slot_offset
,
1850 si_set_shader_image_desc(sctx
, view
, true,
1851 desc
->list
+ desc_slot_offset
);
1853 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1854 sizeof(desc_list
))) {
1855 img_handle
->desc_dirty
= true;
1856 sctx
->bindless_descriptors_dirty
= true;
1860 static void si_update_all_resident_texture_descriptors(struct si_context
*sctx
)
1862 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1863 struct si_texture_handle
*, tex_handle
) {
1864 si_update_bindless_texture_descriptor(sctx
, *tex_handle
);
1867 util_dynarray_foreach(&sctx
->resident_img_handles
,
1868 struct si_image_handle
*, img_handle
) {
1869 si_update_bindless_image_descriptor(sctx
, *img_handle
);
1872 si_upload_bindless_descriptors(sctx
);
1875 /* Update mutable image descriptor fields of all bound textures. */
1876 void si_update_all_texture_descriptors(struct si_context
*sctx
)
1880 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1881 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1882 struct si_images
*images
= &sctx
->images
[shader
];
1886 mask
= images
->enabled_mask
;
1888 unsigned i
= u_bit_scan(&mask
);
1889 struct pipe_image_view
*view
= &images
->views
[i
];
1891 if (!view
->resource
||
1892 view
->resource
->target
== PIPE_BUFFER
)
1895 si_set_shader_image(sctx
, shader
, i
, view
, true);
1898 /* Sampler views. */
1899 mask
= samplers
->enabled_mask
;
1901 unsigned i
= u_bit_scan(&mask
);
1902 struct pipe_sampler_view
*view
= samplers
->views
[i
];
1906 view
->texture
->target
== PIPE_BUFFER
)
1909 si_set_sampler_view(sctx
, shader
, i
,
1910 samplers
->views
[i
], true);
1913 si_update_shader_needs_decompress_mask(sctx
, shader
);
1916 si_update_all_resident_texture_descriptors(sctx
);
1919 /* SHADER USER DATA */
1921 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
,
1924 sctx
->shader_pointers_dirty
|=
1925 u_bit_consecutive(SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
,
1926 SI_NUM_SHADER_DESCS
);
1928 if (shader
== PIPE_SHADER_VERTEX
)
1929 sctx
->vertex_buffer_pointer_dirty
= sctx
->vertex_buffers
.buffer
!= NULL
;
1931 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1934 static void si_shader_pointers_begin_new_cs(struct si_context
*sctx
)
1936 sctx
->shader_pointers_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
1937 sctx
->vertex_buffer_pointer_dirty
= sctx
->vertex_buffers
.buffer
!= NULL
;
1938 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1939 sctx
->graphics_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
1940 sctx
->compute_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
1943 /* Set a base register address for user data constants in the given shader.
1944 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1946 static void si_set_user_data_base(struct si_context
*sctx
,
1947 unsigned shader
, uint32_t new_base
)
1949 uint32_t *base
= &sctx
->shader_pointers
.sh_base
[shader
];
1951 if (*base
!= new_base
) {
1955 si_mark_shader_pointers_dirty(sctx
, shader
);
1957 if (shader
== PIPE_SHADER_VERTEX
)
1958 sctx
->last_vs_state
= ~0;
1963 /* This must be called when these shaders are changed from non-NULL to NULL
1966 * - tessellation control shader
1967 * - tessellation evaluation shader
1969 void si_shader_change_notify(struct si_context
*sctx
)
1971 /* VS can be bound as VS, ES, or LS. */
1972 if (sctx
->tes_shader
.cso
) {
1973 if (sctx
->b
.chip_class
>= GFX9
) {
1974 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1975 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
1977 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1978 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
1980 } else if (sctx
->gs_shader
.cso
) {
1981 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1982 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1984 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1985 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1988 /* TES can be bound as ES, VS, or not bound. */
1989 if (sctx
->tes_shader
.cso
) {
1990 if (sctx
->gs_shader
.cso
)
1991 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
1992 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1994 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
1995 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1997 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
2001 static void si_emit_shader_pointer_head(struct radeon_winsys_cs
*cs
,
2002 struct si_descriptors
*desc
,
2004 unsigned pointer_count
)
2006 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* (HAVE_32BIT_POINTERS
? 1 : 2), 0));
2007 radeon_emit(cs
, (sh_base
+ desc
->shader_userdata_offset
- SI_SH_REG_OFFSET
) >> 2);
2010 static void si_emit_shader_pointer_body(struct si_screen
*sscreen
,
2011 struct radeon_winsys_cs
*cs
,
2012 struct si_descriptors
*desc
)
2014 uint64_t va
= desc
->gpu_address
;
2016 radeon_emit(cs
, va
);
2018 if (HAVE_32BIT_POINTERS
)
2019 assert((va
>> 32) == sscreen
->info
.address32_hi
);
2021 radeon_emit(cs
, va
>> 32);
2024 static void si_emit_shader_pointer(struct si_context
*sctx
,
2025 struct si_descriptors
*desc
,
2028 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2030 si_emit_shader_pointer_head(cs
, desc
, sh_base
, 1);
2031 si_emit_shader_pointer_body(sctx
->screen
, cs
, desc
);
2034 static void si_emit_consecutive_shader_pointers(struct si_context
*sctx
,
2035 unsigned pointer_mask
,
2041 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2042 unsigned mask
= sctx
->shader_pointers_dirty
& pointer_mask
;
2046 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
2048 struct si_descriptors
*descs
= &sctx
->descriptors
[start
];
2050 si_emit_shader_pointer_head(cs
, descs
, sh_base
, count
);
2051 for (int i
= 0; i
< count
; i
++)
2052 si_emit_shader_pointer_body(sctx
->screen
, cs
, descs
+ i
);
2056 static void si_emit_disjoint_shader_pointers(struct si_context
*sctx
,
2057 unsigned pointer_mask
,
2063 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2064 unsigned mask
= sctx
->shader_pointers_dirty
& pointer_mask
;
2067 struct si_descriptors
*descs
= &sctx
->descriptors
[u_bit_scan(&mask
)];
2069 si_emit_shader_pointer_head(cs
, descs
, sh_base
, 1);
2070 si_emit_shader_pointer_body(sctx
->screen
, cs
, descs
);
2074 static void si_emit_global_shader_pointers(struct si_context
*sctx
,
2075 struct si_descriptors
*descs
)
2077 if (sctx
->b
.chip_class
== GFX9
) {
2078 /* Broadcast it to all shader stages. */
2079 si_emit_shader_pointer(sctx
, descs
,
2080 R_00B530_SPI_SHADER_USER_DATA_COMMON_0
);
2084 si_emit_shader_pointer(sctx
, descs
,
2085 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2086 si_emit_shader_pointer(sctx
, descs
,
2087 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2088 si_emit_shader_pointer(sctx
, descs
,
2089 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2090 si_emit_shader_pointer(sctx
, descs
,
2091 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2092 si_emit_shader_pointer(sctx
, descs
,
2093 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2094 si_emit_shader_pointer(sctx
, descs
,
2095 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2098 void si_emit_graphics_shader_pointers(struct si_context
*sctx
,
2099 struct r600_atom
*atom
)
2101 uint32_t *sh_base
= sctx
->shader_pointers
.sh_base
;
2103 if (sctx
->shader_pointers_dirty
& (1 << SI_DESCS_RW_BUFFERS
)) {
2104 si_emit_global_shader_pointers(sctx
,
2105 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2108 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(VERTEX
),
2109 sh_base
[PIPE_SHADER_VERTEX
]);
2110 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_EVAL
),
2111 sh_base
[PIPE_SHADER_TESS_EVAL
]);
2112 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(FRAGMENT
),
2113 sh_base
[PIPE_SHADER_FRAGMENT
]);
2114 if (HAVE_32BIT_POINTERS
|| sctx
->b
.chip_class
<= VI
) {
2115 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_CTRL
),
2116 sh_base
[PIPE_SHADER_TESS_CTRL
]);
2117 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(GEOMETRY
),
2118 sh_base
[PIPE_SHADER_GEOMETRY
]);
2120 si_emit_disjoint_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(TESS_CTRL
),
2121 sh_base
[PIPE_SHADER_TESS_CTRL
]);
2122 si_emit_disjoint_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(GEOMETRY
),
2123 sh_base
[PIPE_SHADER_GEOMETRY
]);
2126 sctx
->shader_pointers_dirty
&=
2127 ~u_bit_consecutive(SI_DESCS_RW_BUFFERS
, SI_DESCS_FIRST_COMPUTE
);
2129 if (sctx
->vertex_buffer_pointer_dirty
) {
2130 si_emit_shader_pointer(sctx
, &sctx
->vertex_buffers
,
2131 sh_base
[PIPE_SHADER_VERTEX
]);
2132 sctx
->vertex_buffer_pointer_dirty
= false;
2135 if (sctx
->graphics_bindless_pointer_dirty
) {
2136 si_emit_global_shader_pointers(sctx
,
2137 &sctx
->bindless_descriptors
);
2138 sctx
->graphics_bindless_pointer_dirty
= false;
2142 void si_emit_compute_shader_pointers(struct si_context
*sctx
)
2144 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
2146 si_emit_consecutive_shader_pointers(sctx
, SI_DESCS_SHADER_MASK(COMPUTE
),
2147 R_00B900_COMPUTE_USER_DATA_0
);
2148 sctx
->shader_pointers_dirty
&= ~SI_DESCS_SHADER_MASK(COMPUTE
);
2150 if (sctx
->compute_bindless_pointer_dirty
) {
2151 si_emit_shader_pointer(sctx
, &sctx
->bindless_descriptors
, base
);
2152 sctx
->compute_bindless_pointer_dirty
= false;
2158 static void si_init_bindless_descriptors(struct si_context
*sctx
,
2159 struct si_descriptors
*desc
,
2160 short shader_userdata_rel_index
,
2161 unsigned num_elements
)
2163 MAYBE_UNUSED
unsigned desc_slot
;
2165 si_init_descriptors(desc
, shader_userdata_rel_index
, 16, num_elements
);
2166 sctx
->bindless_descriptors
.num_active_slots
= num_elements
;
2168 /* The first bindless descriptor is stored at slot 1, because 0 is not
2169 * considered to be a valid handle.
2171 sctx
->num_bindless_descriptors
= 1;
2173 /* Track which bindless slots are used (or not). */
2174 util_idalloc_init(&sctx
->bindless_used_slots
);
2175 util_idalloc_resize(&sctx
->bindless_used_slots
, num_elements
);
2177 /* Reserve slot 0 because it's an invalid handle for bindless. */
2178 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2179 assert(desc_slot
== 0);
2182 static void si_release_bindless_descriptors(struct si_context
*sctx
)
2184 si_release_descriptors(&sctx
->bindless_descriptors
);
2185 util_idalloc_fini(&sctx
->bindless_used_slots
);
2188 static unsigned si_get_first_free_bindless_slot(struct si_context
*sctx
)
2190 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2193 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2194 if (desc_slot
>= desc
->num_elements
) {
2195 /* The array of bindless descriptors is full, resize it. */
2196 unsigned slot_size
= desc
->element_dw_size
* 4;
2197 unsigned new_num_elements
= desc
->num_elements
* 2;
2199 desc
->list
= REALLOC(desc
->list
, desc
->num_elements
* slot_size
,
2200 new_num_elements
* slot_size
);
2201 desc
->num_elements
= new_num_elements
;
2202 desc
->num_active_slots
= new_num_elements
;
2210 si_create_bindless_descriptor(struct si_context
*sctx
, uint32_t *desc_list
,
2213 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2214 unsigned desc_slot
, desc_slot_offset
;
2216 /* Find a free slot. */
2217 desc_slot
= si_get_first_free_bindless_slot(sctx
);
2219 /* For simplicity, sampler and image bindless descriptors use fixed
2220 * 16-dword slots for now. Image descriptors only need 8-dword but this
2221 * doesn't really matter because no real apps use image handles.
2223 desc_slot_offset
= desc_slot
* 16;
2225 /* Copy the descriptor into the array. */
2226 memcpy(desc
->list
+ desc_slot_offset
, desc_list
, size
);
2228 /* Re-upload the whole array of bindless descriptors into a new buffer.
2230 if (!si_upload_descriptors(sctx
, desc
))
2233 /* Make sure to re-emit the shader pointers for all stages. */
2234 sctx
->graphics_bindless_pointer_dirty
= true;
2235 sctx
->compute_bindless_pointer_dirty
= true;
2240 static void si_update_bindless_buffer_descriptor(struct si_context
*sctx
,
2242 struct pipe_resource
*resource
,
2246 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2247 struct r600_resource
*buf
= r600_resource(resource
);
2248 unsigned desc_slot_offset
= desc_slot
* 16;
2249 uint32_t *desc_list
= desc
->list
+ desc_slot_offset
+ 4;
2250 uint64_t old_desc_va
;
2252 assert(resource
->target
== PIPE_BUFFER
);
2254 /* Retrieve the old buffer addr from the descriptor. */
2255 old_desc_va
= si_desc_extract_buffer_address(desc_list
);
2257 if (old_desc_va
!= buf
->gpu_address
+ offset
) {
2258 /* The buffer has been invalidated when the handle wasn't
2259 * resident, update the descriptor and the dirty flag.
2261 si_set_buf_desc_address(buf
, offset
, &desc_list
[0]);
2267 static uint64_t si_create_texture_handle(struct pipe_context
*ctx
,
2268 struct pipe_sampler_view
*view
,
2269 const struct pipe_sampler_state
*state
)
2271 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
2272 struct si_context
*sctx
= (struct si_context
*)ctx
;
2273 struct si_texture_handle
*tex_handle
;
2274 struct si_sampler_state
*sstate
;
2275 uint32_t desc_list
[16];
2278 tex_handle
= CALLOC_STRUCT(si_texture_handle
);
2282 memset(desc_list
, 0, sizeof(desc_list
));
2283 si_init_descriptor_list(&desc_list
[0], 16, 1, null_texture_descriptor
);
2285 sstate
= ctx
->create_sampler_state(ctx
, state
);
2291 si_set_sampler_view_desc(sctx
, sview
, sstate
, &desc_list
[0]);
2292 memcpy(&tex_handle
->sstate
, sstate
, sizeof(*sstate
));
2293 ctx
->delete_sampler_state(ctx
, sstate
);
2295 tex_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2297 if (!tex_handle
->desc_slot
) {
2302 handle
= tex_handle
->desc_slot
;
2304 if (!_mesa_hash_table_insert(sctx
->tex_handles
,
2305 (void *)(uintptr_t)handle
,
2311 pipe_sampler_view_reference(&tex_handle
->view
, view
);
2313 r600_resource(sview
->base
.texture
)->texture_handle_allocated
= true;
2318 static void si_delete_texture_handle(struct pipe_context
*ctx
, uint64_t handle
)
2320 struct si_context
*sctx
= (struct si_context
*)ctx
;
2321 struct si_texture_handle
*tex_handle
;
2322 struct hash_entry
*entry
;
2324 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2325 (void *)(uintptr_t)handle
);
2329 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2331 /* Allow this descriptor slot to be re-used. */
2332 util_idalloc_free(&sctx
->bindless_used_slots
, tex_handle
->desc_slot
);
2334 pipe_sampler_view_reference(&tex_handle
->view
, NULL
);
2335 _mesa_hash_table_remove(sctx
->tex_handles
, entry
);
2339 static void si_make_texture_handle_resident(struct pipe_context
*ctx
,
2340 uint64_t handle
, bool resident
)
2342 struct si_context
*sctx
= (struct si_context
*)ctx
;
2343 struct si_texture_handle
*tex_handle
;
2344 struct si_sampler_view
*sview
;
2345 struct hash_entry
*entry
;
2347 entry
= _mesa_hash_table_search(sctx
->tex_handles
,
2348 (void *)(uintptr_t)handle
);
2352 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2353 sview
= (struct si_sampler_view
*)tex_handle
->view
;
2356 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2357 struct r600_texture
*rtex
=
2358 (struct r600_texture
*)sview
->base
.texture
;
2360 if (depth_needs_decompression(rtex
)) {
2361 util_dynarray_append(
2362 &sctx
->resident_tex_needs_depth_decompress
,
2363 struct si_texture_handle
*,
2367 if (color_needs_decompression(rtex
)) {
2368 util_dynarray_append(
2369 &sctx
->resident_tex_needs_color_decompress
,
2370 struct si_texture_handle
*,
2374 if (rtex
->dcc_offset
&&
2375 p_atomic_read(&rtex
->framebuffers_bound
))
2376 sctx
->need_check_render_feedback
= true;
2378 si_update_bindless_texture_descriptor(sctx
, tex_handle
);
2380 si_update_bindless_buffer_descriptor(sctx
,
2381 tex_handle
->desc_slot
,
2382 sview
->base
.texture
,
2383 sview
->base
.u
.buf
.offset
,
2384 &tex_handle
->desc_dirty
);
2387 /* Re-upload the descriptor if it has been updated while it
2390 if (tex_handle
->desc_dirty
)
2391 sctx
->bindless_descriptors_dirty
= true;
2393 /* Add the texture handle to the per-context list. */
2394 util_dynarray_append(&sctx
->resident_tex_handles
,
2395 struct si_texture_handle
*, tex_handle
);
2397 /* Add the buffers to the current CS in case si_begin_new_cs()
2398 * is not going to be called.
2400 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2402 sview
->is_stencil_sampler
, false);
2404 /* Remove the texture handle from the per-context list. */
2405 util_dynarray_delete_unordered(&sctx
->resident_tex_handles
,
2406 struct si_texture_handle
*,
2409 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2410 util_dynarray_delete_unordered(
2411 &sctx
->resident_tex_needs_depth_decompress
,
2412 struct si_texture_handle
*, tex_handle
);
2414 util_dynarray_delete_unordered(
2415 &sctx
->resident_tex_needs_color_decompress
,
2416 struct si_texture_handle
*, tex_handle
);
2421 static uint64_t si_create_image_handle(struct pipe_context
*ctx
,
2422 const struct pipe_image_view
*view
)
2424 struct si_context
*sctx
= (struct si_context
*)ctx
;
2425 struct si_image_handle
*img_handle
;
2426 uint32_t desc_list
[8];
2429 if (!view
|| !view
->resource
)
2432 img_handle
= CALLOC_STRUCT(si_image_handle
);
2436 memset(desc_list
, 0, sizeof(desc_list
));
2437 si_init_descriptor_list(&desc_list
[0], 8, 1, null_image_descriptor
);
2439 si_set_shader_image_desc(sctx
, view
, false, &desc_list
[0]);
2441 img_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2443 if (!img_handle
->desc_slot
) {
2448 handle
= img_handle
->desc_slot
;
2450 if (!_mesa_hash_table_insert(sctx
->img_handles
,
2451 (void *)(uintptr_t)handle
,
2457 util_copy_image_view(&img_handle
->view
, view
);
2459 r600_resource(view
->resource
)->image_handle_allocated
= true;
2464 static void si_delete_image_handle(struct pipe_context
*ctx
, uint64_t handle
)
2466 struct si_context
*sctx
= (struct si_context
*)ctx
;
2467 struct si_image_handle
*img_handle
;
2468 struct hash_entry
*entry
;
2470 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2471 (void *)(uintptr_t)handle
);
2475 img_handle
= (struct si_image_handle
*)entry
->data
;
2477 util_copy_image_view(&img_handle
->view
, NULL
);
2478 _mesa_hash_table_remove(sctx
->img_handles
, entry
);
2482 static void si_make_image_handle_resident(struct pipe_context
*ctx
,
2483 uint64_t handle
, unsigned access
,
2486 struct si_context
*sctx
= (struct si_context
*)ctx
;
2487 struct si_image_handle
*img_handle
;
2488 struct pipe_image_view
*view
;
2489 struct r600_resource
*res
;
2490 struct hash_entry
*entry
;
2492 entry
= _mesa_hash_table_search(sctx
->img_handles
,
2493 (void *)(uintptr_t)handle
);
2497 img_handle
= (struct si_image_handle
*)entry
->data
;
2498 view
= &img_handle
->view
;
2499 res
= (struct r600_resource
*)view
->resource
;
2502 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2503 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
2504 unsigned level
= view
->u
.tex
.level
;
2506 if (color_needs_decompression(rtex
)) {
2507 util_dynarray_append(
2508 &sctx
->resident_img_needs_color_decompress
,
2509 struct si_image_handle
*,
2513 if (vi_dcc_enabled(rtex
, level
) &&
2514 p_atomic_read(&rtex
->framebuffers_bound
))
2515 sctx
->need_check_render_feedback
= true;
2517 si_update_bindless_image_descriptor(sctx
, img_handle
);
2519 si_update_bindless_buffer_descriptor(sctx
,
2520 img_handle
->desc_slot
,
2523 &img_handle
->desc_dirty
);
2526 /* Re-upload the descriptor if it has been updated while it
2529 if (img_handle
->desc_dirty
)
2530 sctx
->bindless_descriptors_dirty
= true;
2532 /* Add the image handle to the per-context list. */
2533 util_dynarray_append(&sctx
->resident_img_handles
,
2534 struct si_image_handle
*, img_handle
);
2536 /* Add the buffers to the current CS in case si_begin_new_cs()
2537 * is not going to be called.
2539 si_sampler_view_add_buffer(sctx
, view
->resource
,
2540 (access
& PIPE_IMAGE_ACCESS_WRITE
) ?
2541 RADEON_USAGE_READWRITE
:
2542 RADEON_USAGE_READ
, false, false);
2544 /* Remove the image handle from the per-context list. */
2545 util_dynarray_delete_unordered(&sctx
->resident_img_handles
,
2546 struct si_image_handle
*,
2549 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2550 util_dynarray_delete_unordered(
2551 &sctx
->resident_img_needs_color_decompress
,
2552 struct si_image_handle
*,
2559 void si_all_resident_buffers_begin_new_cs(struct si_context
*sctx
)
2561 unsigned num_resident_tex_handles
, num_resident_img_handles
;
2563 num_resident_tex_handles
= sctx
->resident_tex_handles
.size
/
2564 sizeof(struct si_texture_handle
*);
2565 num_resident_img_handles
= sctx
->resident_img_handles
.size
/
2566 sizeof(struct si_image_handle
*);
2568 /* Add all resident texture handles. */
2569 util_dynarray_foreach(&sctx
->resident_tex_handles
,
2570 struct si_texture_handle
*, tex_handle
) {
2571 struct si_sampler_view
*sview
=
2572 (struct si_sampler_view
*)(*tex_handle
)->view
;
2574 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2576 sview
->is_stencil_sampler
, false);
2579 /* Add all resident image handles. */
2580 util_dynarray_foreach(&sctx
->resident_img_handles
,
2581 struct si_image_handle
*, img_handle
) {
2582 struct pipe_image_view
*view
= &(*img_handle
)->view
;
2584 si_sampler_view_add_buffer(sctx
, view
->resource
,
2585 RADEON_USAGE_READWRITE
,
2589 sctx
->b
.num_resident_handles
+= num_resident_tex_handles
+
2590 num_resident_img_handles
;
2593 /* INIT/DEINIT/UPLOAD */
2595 void si_init_all_descriptors(struct si_context
*sctx
)
2599 #if !HAVE_32BIT_POINTERS
2600 STATIC_ASSERT(GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES
% 2 == 0);
2603 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2604 bool is_2nd
= sctx
->b
.chip_class
>= GFX9
&&
2605 (i
== PIPE_SHADER_TESS_CTRL
||
2606 i
== PIPE_SHADER_GEOMETRY
);
2607 unsigned num_sampler_slots
= SI_NUM_IMAGES
/ 2 + SI_NUM_SAMPLERS
;
2608 unsigned num_buffer_slots
= SI_NUM_SHADER_BUFFERS
+ SI_NUM_CONST_BUFFERS
;
2610 struct si_descriptors
*desc
;
2613 if (i
== PIPE_SHADER_TESS_CTRL
) {
2614 rel_dw_offset
= (R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
-
2615 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2616 } else { /* PIPE_SHADER_GEOMETRY */
2617 rel_dw_offset
= (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
-
2618 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2621 rel_dw_offset
= SI_SGPR_CONST_AND_SHADER_BUFFERS
;
2623 desc
= si_const_and_shader_buffer_descriptors(sctx
, i
);
2624 si_init_buffer_resources(&sctx
->const_and_shader_buffers
[i
], desc
,
2625 num_buffer_slots
, rel_dw_offset
,
2626 RADEON_USAGE_READWRITE
,
2628 RADEON_PRIO_SHADER_RW_BUFFER
,
2629 RADEON_PRIO_CONST_BUFFER
);
2630 desc
->slot_index_to_bind_directly
= si_get_constbuf_slot(0);
2633 #if HAVE_32BIT_POINTERS
2634 if (i
== PIPE_SHADER_TESS_CTRL
) {
2635 rel_dw_offset
= (R_00B40C_SPI_SHADER_USER_DATA_ADDR_HI_HS
-
2636 R_00B430_SPI_SHADER_USER_DATA_LS_0
) / 4;
2637 } else { /* PIPE_SHADER_GEOMETRY */
2638 rel_dw_offset
= (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS
-
2639 R_00B330_SPI_SHADER_USER_DATA_ES_0
) / 4;
2642 rel_dw_offset
= GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES
;
2645 rel_dw_offset
= SI_SGPR_SAMPLERS_AND_IMAGES
;
2648 desc
= si_sampler_and_image_descriptors(sctx
, i
);
2649 si_init_descriptors(desc
, rel_dw_offset
, 16, num_sampler_slots
);
2652 for (j
= 0; j
< SI_NUM_IMAGES
; j
++)
2653 memcpy(desc
->list
+ j
* 8, null_image_descriptor
, 8 * 4);
2654 for (; j
< SI_NUM_IMAGES
+ SI_NUM_SAMPLERS
* 2; j
++)
2655 memcpy(desc
->list
+ j
* 8, null_texture_descriptor
, 8 * 4);
2658 si_init_buffer_resources(&sctx
->rw_buffers
,
2659 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
2660 SI_NUM_RW_BUFFERS
, SI_SGPR_RW_BUFFERS
,
2661 /* The second set of usage/priority is used by
2662 * const buffers in RW buffer slots. */
2663 RADEON_USAGE_READWRITE
, RADEON_USAGE_READ
,
2664 RADEON_PRIO_SHADER_RINGS
, RADEON_PRIO_CONST_BUFFER
);
2665 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
= SI_NUM_RW_BUFFERS
;
2667 si_init_descriptors(&sctx
->vertex_buffers
, SI_SGPR_VERTEX_BUFFERS
,
2668 4, SI_NUM_VERTEX_BUFFERS
);
2669 FREE(sctx
->vertex_buffers
.list
); /* not used */
2670 sctx
->vertex_buffers
.list
= NULL
;
2672 /* Initialize an array of 1024 bindless descriptors, when the limit is
2673 * reached, just make it larger and re-upload the whole array.
2675 si_init_bindless_descriptors(sctx
, &sctx
->bindless_descriptors
,
2676 SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
,
2679 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2681 /* Set pipe_context functions. */
2682 sctx
->b
.b
.bind_sampler_states
= si_bind_sampler_states
;
2683 sctx
->b
.b
.set_shader_images
= si_set_shader_images
;
2684 sctx
->b
.b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
2685 sctx
->b
.b
.set_polygon_stipple
= si_set_polygon_stipple
;
2686 sctx
->b
.b
.set_shader_buffers
= si_set_shader_buffers
;
2687 sctx
->b
.b
.set_sampler_views
= si_set_sampler_views
;
2688 sctx
->b
.b
.create_texture_handle
= si_create_texture_handle
;
2689 sctx
->b
.b
.delete_texture_handle
= si_delete_texture_handle
;
2690 sctx
->b
.b
.make_texture_handle_resident
= si_make_texture_handle_resident
;
2691 sctx
->b
.b
.create_image_handle
= si_create_image_handle
;
2692 sctx
->b
.b
.delete_image_handle
= si_delete_image_handle
;
2693 sctx
->b
.b
.make_image_handle_resident
= si_make_image_handle_resident
;
2694 sctx
->b
.invalidate_buffer
= si_invalidate_buffer
;
2695 sctx
->b
.rebind_buffer
= si_rebind_buffer
;
2697 /* Shader user data. */
2698 si_init_atom(sctx
, &sctx
->shader_pointers
.atom
, &sctx
->atoms
.s
.shader_pointers
,
2699 si_emit_graphics_shader_pointers
);
2701 /* Set default and immutable mappings. */
2702 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2704 if (sctx
->b
.chip_class
>= GFX9
) {
2705 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2706 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2707 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2708 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2710 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2711 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2712 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2713 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2715 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2718 static bool si_upload_shader_descriptors(struct si_context
*sctx
, unsigned mask
)
2720 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2722 /* Assume nothing will go wrong: */
2723 sctx
->shader_pointers_dirty
|= dirty
;
2726 unsigned i
= u_bit_scan(&dirty
);
2728 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
]))
2732 sctx
->descriptors_dirty
&= ~mask
;
2734 si_upload_bindless_descriptors(sctx
);
2739 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
2741 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
2742 return si_upload_shader_descriptors(sctx
, mask
);
2745 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
2747 /* Does not update rw_buffers as that is not needed for compute shaders
2748 * and the input buffer is using the same SGPR's anyway.
2750 const unsigned mask
= u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
,
2751 SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
2752 return si_upload_shader_descriptors(sctx
, mask
);
2755 void si_release_all_descriptors(struct si_context
*sctx
)
2759 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2760 si_release_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2761 si_const_and_shader_buffer_descriptors(sctx
, i
));
2762 si_release_sampler_views(&sctx
->samplers
[i
]);
2763 si_release_image_views(&sctx
->images
[i
]);
2765 si_release_buffer_resources(&sctx
->rw_buffers
,
2766 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2767 for (i
= 0; i
< SI_NUM_VERTEX_BUFFERS
; i
++)
2768 pipe_vertex_buffer_unreference(&sctx
->vertex_buffer
[i
]);
2770 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2771 si_release_descriptors(&sctx
->descriptors
[i
]);
2773 sctx
->vertex_buffers
.list
= NULL
; /* points into a mapped buffer */
2774 si_release_descriptors(&sctx
->vertex_buffers
);
2775 si_release_bindless_descriptors(sctx
);
2778 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
2782 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2783 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2784 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
]);
2785 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
2787 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2788 si_vertex_buffers_begin_new_cs(sctx
);
2790 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2791 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
2792 si_descriptors_begin_new_cs(sctx
, &sctx
->bindless_descriptors
);
2794 si_shader_pointers_begin_new_cs(sctx
);
2797 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
2798 uint64_t new_active_mask
)
2800 struct si_descriptors
*desc
= &sctx
->descriptors
[desc_idx
];
2802 /* Ignore no-op updates and updates that disable all slots. */
2803 if (!new_active_mask
||
2804 new_active_mask
== u_bit_consecutive64(desc
->first_active_slot
,
2805 desc
->num_active_slots
))
2809 u_bit_scan_consecutive_range64(&new_active_mask
, &first
, &count
);
2810 assert(new_active_mask
== 0);
2812 /* Upload/dump descriptors if slots are being enabled. */
2813 if (first
< desc
->first_active_slot
||
2814 first
+ count
> desc
->first_active_slot
+ desc
->num_active_slots
)
2815 sctx
->descriptors_dirty
|= 1u << desc_idx
;
2817 desc
->first_active_slot
= first
;
2818 desc
->num_active_slots
= count
;
2821 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
2822 struct si_shader_selector
*sel
)
2827 si_set_active_descriptors(sctx
,
2828 si_const_and_shader_buffer_descriptors_idx(sel
->type
),
2829 sel
->active_const_and_shader_buffers
);
2830 si_set_active_descriptors(sctx
,
2831 si_sampler_and_image_descriptors_idx(sel
->type
),
2832 sel
->active_samplers_and_images
);