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gallium: change pipe_image_view::first_element/last_element -> offset/size
[mesa.git] / src / gallium / drivers / radeonsi / si_descriptors.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Marek Olšák <marek.olsak@amd.com>
25 */
26
27 /* Resource binding slots and sampler states (each described with 8 or
28 * 4 dwords) are stored in lists in memory which is accessed by shaders
29 * using scalar load instructions.
30 *
31 * This file is responsible for managing such lists. It keeps a copy of all
32 * descriptors in CPU memory and re-uploads a whole list if some slots have
33 * been changed.
34 *
35 * This code is also reponsible for updating shader pointers to those lists.
36 *
37 * Note that CP DMA can't be used for updating the lists, because a GPU hang
38 * could leave the list in a mid-IB state and the next IB would get wrong
39 * descriptors and the whole context would be unusable at that point.
40 * (Note: The register shadowing can't be used due to the same reason)
41 *
42 * Also, uploading descriptors to newly allocated memory doesn't require
43 * a KCACHE flush.
44 *
45 *
46 * Possible scenarios for one 16 dword image+sampler slot:
47 *
48 * | Image | w/ FMASK | Buffer | NULL
49 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
50 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
51 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
52 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
53 *
54 * FMASK implies MSAA, therefore no sampler state.
55 * Sampler states are never unbound except when FMASK is bound.
56 */
57
58 #include "radeon/r600_cs.h"
59 #include "si_pipe.h"
60 #include "si_shader.h"
61 #include "sid.h"
62
63 #include "util/u_format.h"
64 #include "util/u_math.h"
65 #include "util/u_memory.h"
66 #include "util/u_suballoc.h"
67 #include "util/u_upload_mgr.h"
68
69
70 /* NULL image and buffer descriptor for textures (alpha = 1) and images
71 * (alpha = 0).
72 *
73 * For images, all fields must be zero except for the swizzle, which
74 * supports arbitrary combinations of 0s and 1s. The texture type must be
75 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
76 *
77 * For buffers, all fields must be zero. If they are not, the hw hangs.
78 *
79 * This is the only reason why the buffer descriptor must be in words [4:7].
80 */
81 static uint32_t null_texture_descriptor[8] = {
82 0,
83 0,
84 0,
85 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1) |
86 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
87 /* the rest must contain zeros, which is also used by the buffer
88 * descriptor */
89 };
90
91 static uint32_t null_image_descriptor[8] = {
92 0,
93 0,
94 0,
95 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
96 /* the rest must contain zeros, which is also used by the buffer
97 * descriptor */
98 };
99
100 static void si_init_descriptors(struct si_descriptors *desc,
101 unsigned shader_userdata_index,
102 unsigned element_dw_size,
103 unsigned num_elements,
104 const uint32_t *null_descriptor,
105 unsigned *ce_offset)
106 {
107 int i;
108
109 assert(num_elements <= sizeof(desc->dirty_mask)*8);
110
111 desc->list = CALLOC(num_elements, element_dw_size * 4);
112 desc->element_dw_size = element_dw_size;
113 desc->num_elements = num_elements;
114 desc->dirty_mask = num_elements == 32 ? ~0u : (1u << num_elements) - 1;
115 desc->shader_userdata_offset = shader_userdata_index * 4;
116
117 if (ce_offset) {
118 desc->ce_offset = *ce_offset;
119
120 /* make sure that ce_offset stays 32 byte aligned */
121 *ce_offset += align(element_dw_size * num_elements * 4, 32);
122 }
123
124 /* Initialize the array to NULL descriptors if the element size is 8. */
125 if (null_descriptor) {
126 assert(element_dw_size % 8 == 0);
127 for (i = 0; i < num_elements * element_dw_size / 8; i++)
128 memcpy(desc->list + i * 8, null_descriptor,
129 8 * 4);
130 }
131 }
132
133 static void si_release_descriptors(struct si_descriptors *desc)
134 {
135 r600_resource_reference(&desc->buffer, NULL);
136 FREE(desc->list);
137 }
138
139 static bool si_ce_upload(struct si_context *sctx, unsigned ce_offset, unsigned size,
140 unsigned *out_offset, struct r600_resource **out_buf) {
141 uint64_t va;
142
143 u_suballocator_alloc(sctx->ce_suballocator, size, 64, out_offset,
144 (struct pipe_resource**)out_buf);
145 if (!out_buf)
146 return false;
147
148 va = (*out_buf)->gpu_address + *out_offset;
149
150 radeon_emit(sctx->ce_ib, PKT3(PKT3_DUMP_CONST_RAM, 3, 0));
151 radeon_emit(sctx->ce_ib, ce_offset);
152 radeon_emit(sctx->ce_ib, size / 4);
153 radeon_emit(sctx->ce_ib, va);
154 radeon_emit(sctx->ce_ib, va >> 32);
155
156 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, *out_buf,
157 RADEON_USAGE_READWRITE, RADEON_PRIO_DESCRIPTORS);
158
159 sctx->ce_need_synchronization = true;
160 return true;
161 }
162
163 static void si_ce_reinitialize_descriptors(struct si_context *sctx,
164 struct si_descriptors *desc)
165 {
166 if (desc->buffer) {
167 struct r600_resource *buffer = (struct r600_resource*)desc->buffer;
168 unsigned list_size = desc->num_elements * desc->element_dw_size * 4;
169 uint64_t va = buffer->gpu_address + desc->buffer_offset;
170 struct radeon_winsys_cs *ib = sctx->ce_preamble_ib;
171
172 if (!ib)
173 ib = sctx->ce_ib;
174
175 list_size = align(list_size, 32);
176
177 radeon_emit(ib, PKT3(PKT3_LOAD_CONST_RAM, 3, 0));
178 radeon_emit(ib, va);
179 radeon_emit(ib, va >> 32);
180 radeon_emit(ib, list_size / 4);
181 radeon_emit(ib, desc->ce_offset);
182
183 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
184 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
185 }
186 desc->ce_ram_dirty = false;
187 }
188
189 void si_ce_reinitialize_all_descriptors(struct si_context *sctx)
190 {
191 int i;
192
193 for (i = 0; i < SI_NUM_DESCS; ++i)
194 si_ce_reinitialize_descriptors(sctx, &sctx->descriptors[i]);
195 }
196
197 void si_ce_enable_loads(struct radeon_winsys_cs *ib)
198 {
199 radeon_emit(ib, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
200 radeon_emit(ib, CONTEXT_CONTROL_LOAD_ENABLE(1) |
201 CONTEXT_CONTROL_LOAD_CE_RAM(1));
202 radeon_emit(ib, CONTEXT_CONTROL_SHADOW_ENABLE(1));
203 }
204
205 static bool si_upload_descriptors(struct si_context *sctx,
206 struct si_descriptors *desc,
207 struct r600_atom * atom)
208 {
209 unsigned list_size = desc->num_elements * desc->element_dw_size * 4;
210
211 if (!desc->dirty_mask)
212 return true;
213
214 if (sctx->ce_ib) {
215 uint32_t const* list = (uint32_t const*)desc->list;
216
217 if (desc->ce_ram_dirty)
218 si_ce_reinitialize_descriptors(sctx, desc);
219
220 while(desc->dirty_mask) {
221 int begin, count;
222 u_bit_scan_consecutive_range(&desc->dirty_mask, &begin,
223 &count);
224
225 begin *= desc->element_dw_size;
226 count *= desc->element_dw_size;
227
228 radeon_emit(sctx->ce_ib,
229 PKT3(PKT3_WRITE_CONST_RAM, count, 0));
230 radeon_emit(sctx->ce_ib, desc->ce_offset + begin * 4);
231 radeon_emit_array(sctx->ce_ib, list + begin, count);
232 }
233
234 if (!si_ce_upload(sctx, desc->ce_offset, list_size,
235 &desc->buffer_offset, &desc->buffer))
236 return false;
237 } else {
238 void *ptr;
239
240 u_upload_alloc(sctx->b.uploader, 0, list_size, 256,
241 &desc->buffer_offset,
242 (struct pipe_resource**)&desc->buffer, &ptr);
243 if (!desc->buffer)
244 return false; /* skip the draw call */
245
246 util_memcpy_cpu_to_le32(ptr, desc->list, list_size);
247
248 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
249 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
250 }
251 desc->pointer_dirty = true;
252 desc->dirty_mask = 0;
253
254 if (atom)
255 si_mark_atom_dirty(sctx, atom);
256
257 return true;
258 }
259
260 static void
261 si_descriptors_begin_new_cs(struct si_context *sctx, struct si_descriptors *desc)
262 {
263 desc->ce_ram_dirty = true;
264
265 if (!desc->buffer)
266 return;
267
268 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
269 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
270 }
271
272 /* SAMPLER VIEWS */
273
274 static unsigned
275 si_sampler_descriptors_idx(unsigned shader)
276 {
277 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
278 SI_SHADER_DESCS_SAMPLERS;
279 }
280
281 static struct si_descriptors *
282 si_sampler_descriptors(struct si_context *sctx, unsigned shader)
283 {
284 return &sctx->descriptors[si_sampler_descriptors_idx(shader)];
285 }
286
287 static void si_release_sampler_views(struct si_sampler_views *views)
288 {
289 int i;
290
291 for (i = 0; i < ARRAY_SIZE(views->views); i++) {
292 pipe_sampler_view_reference(&views->views[i], NULL);
293 }
294 }
295
296 static void si_sampler_view_add_buffer(struct si_context *sctx,
297 struct pipe_resource *resource,
298 enum radeon_bo_usage usage,
299 bool is_stencil_sampler,
300 bool check_mem)
301 {
302 struct r600_resource *rres;
303 struct r600_texture *rtex;
304 enum radeon_bo_priority priority;
305
306 if (!resource)
307 return;
308
309 if (resource->target != PIPE_BUFFER) {
310 struct r600_texture *tex = (struct r600_texture*)resource;
311
312 if (tex->is_depth && !r600_can_sample_zs(tex, is_stencil_sampler))
313 resource = &tex->flushed_depth_texture->resource.b.b;
314 }
315
316 rres = (struct r600_resource*)resource;
317 priority = r600_get_sampler_view_priority(rres);
318
319 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
320 rres, usage, priority,
321 check_mem);
322
323 if (resource->target == PIPE_BUFFER)
324 return;
325
326 /* Now add separate DCC if it's present. */
327 rtex = (struct r600_texture*)resource;
328 if (!rtex->dcc_separate_buffer)
329 return;
330
331 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
332 rtex->dcc_separate_buffer, usage,
333 RADEON_PRIO_DCC, check_mem);
334 }
335
336 static void si_sampler_views_begin_new_cs(struct si_context *sctx,
337 struct si_sampler_views *views)
338 {
339 unsigned mask = views->enabled_mask;
340
341 /* Add buffers to the CS. */
342 while (mask) {
343 int i = u_bit_scan(&mask);
344 struct si_sampler_view *sview = (struct si_sampler_view *)views->views[i];
345
346 si_sampler_view_add_buffer(sctx, sview->base.texture,
347 RADEON_USAGE_READ,
348 sview->is_stencil_sampler, false);
349 }
350 }
351
352 /* Set texture descriptor fields that can be changed by reallocations.
353 *
354 * \param tex texture
355 * \param base_level_info information of the level of BASE_ADDRESS
356 * \param base_level the level of BASE_ADDRESS
357 * \param first_level pipe_sampler_view.u.tex.first_level
358 * \param block_width util_format_get_blockwidth()
359 * \param is_stencil select between separate Z & Stencil
360 * \param state descriptor to update
361 */
362 void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
363 const struct radeon_surf_level *base_level_info,
364 unsigned base_level, unsigned first_level,
365 unsigned block_width, bool is_stencil,
366 uint32_t *state)
367 {
368 uint64_t va;
369 unsigned pitch = base_level_info->nblk_x * block_width;
370
371 if (tex->is_depth && !r600_can_sample_zs(tex, is_stencil)) {
372 tex = tex->flushed_depth_texture;
373 is_stencil = false;
374 }
375
376 va = tex->resource.gpu_address + base_level_info->offset;
377
378 state[1] &= C_008F14_BASE_ADDRESS_HI;
379 state[3] &= C_008F1C_TILING_INDEX;
380 state[4] &= C_008F20_PITCH;
381 state[6] &= C_008F28_COMPRESSION_EN;
382
383 state[0] = va >> 8;
384 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
385 state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(tex, base_level,
386 is_stencil));
387 state[4] |= S_008F20_PITCH(pitch - 1);
388
389 if (tex->dcc_offset && tex->surface.level[first_level].dcc_enabled) {
390 state[6] |= S_008F28_COMPRESSION_EN(1);
391 state[7] = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
392 tex->dcc_offset +
393 base_level_info->dcc_offset) >> 8;
394 }
395 }
396
397 static void si_set_sampler_view(struct si_context *sctx,
398 unsigned shader,
399 unsigned slot, struct pipe_sampler_view *view,
400 bool disallow_early_out)
401 {
402 struct si_sampler_views *views = &sctx->samplers[shader].views;
403 struct si_sampler_view *rview = (struct si_sampler_view*)view;
404 struct si_descriptors *descs = si_sampler_descriptors(sctx, shader);
405
406 if (views->views[slot] == view && !disallow_early_out)
407 return;
408
409 if (view) {
410 struct r600_texture *rtex = (struct r600_texture *)view->texture;
411 uint32_t *desc = descs->list + slot * 16;
412
413 si_sampler_view_add_buffer(sctx, view->texture,
414 RADEON_USAGE_READ,
415 rview->is_stencil_sampler, true);
416
417 pipe_sampler_view_reference(&views->views[slot], view);
418 memcpy(desc, rview->state, 8*4);
419
420 if (view->texture && view->texture->target != PIPE_BUFFER) {
421 bool is_separate_stencil =
422 rtex->db_compatible &&
423 rview->is_stencil_sampler;
424
425 si_set_mutable_tex_desc_fields(rtex,
426 rview->base_level_info,
427 rview->base_level,
428 rview->base.u.tex.first_level,
429 rview->block_width,
430 is_separate_stencil,
431 desc);
432 }
433
434 if (view->texture && view->texture->target != PIPE_BUFFER &&
435 rtex->fmask.size) {
436 memcpy(desc + 8,
437 rview->fmask_state, 8*4);
438 } else {
439 /* Disable FMASK and bind sampler state in [12:15]. */
440 memcpy(desc + 8,
441 null_texture_descriptor, 4*4);
442
443 if (views->sampler_states[slot])
444 memcpy(desc + 12,
445 views->sampler_states[slot], 4*4);
446 }
447
448 views->enabled_mask |= 1u << slot;
449 } else {
450 pipe_sampler_view_reference(&views->views[slot], NULL);
451 memcpy(descs->list + slot*16, null_texture_descriptor, 8*4);
452 /* Only clear the lower dwords of FMASK. */
453 memcpy(descs->list + slot*16 + 8, null_texture_descriptor, 4*4);
454 views->enabled_mask &= ~(1u << slot);
455 }
456
457 descs->dirty_mask |= 1u << slot;
458 sctx->descriptors_dirty |= 1u << si_sampler_descriptors_idx(shader);
459 }
460
461 static bool is_compressed_colortex(struct r600_texture *rtex)
462 {
463 return rtex->cmask.size || rtex->fmask.size ||
464 (rtex->dcc_offset && rtex->dirty_level_mask);
465 }
466
467 static void si_set_sampler_views(struct pipe_context *ctx,
468 unsigned shader, unsigned start,
469 unsigned count,
470 struct pipe_sampler_view **views)
471 {
472 struct si_context *sctx = (struct si_context *)ctx;
473 struct si_textures_info *samplers = &sctx->samplers[shader];
474 int i;
475
476 if (!count || shader >= SI_NUM_SHADERS)
477 return;
478
479 for (i = 0; i < count; i++) {
480 unsigned slot = start + i;
481
482 if (!views || !views[i]) {
483 samplers->depth_texture_mask &= ~(1u << slot);
484 samplers->compressed_colortex_mask &= ~(1u << slot);
485 si_set_sampler_view(sctx, shader, slot, NULL, false);
486 continue;
487 }
488
489 si_set_sampler_view(sctx, shader, slot, views[i], false);
490
491 if (views[i]->texture && views[i]->texture->target != PIPE_BUFFER) {
492 struct r600_texture *rtex =
493 (struct r600_texture*)views[i]->texture;
494
495 if (rtex->db_compatible) {
496 samplers->depth_texture_mask |= 1u << slot;
497 } else {
498 samplers->depth_texture_mask &= ~(1u << slot);
499 }
500 if (is_compressed_colortex(rtex)) {
501 samplers->compressed_colortex_mask |= 1u << slot;
502 } else {
503 samplers->compressed_colortex_mask &= ~(1u << slot);
504 }
505
506 if (rtex->dcc_offset &&
507 p_atomic_read(&rtex->framebuffers_bound))
508 sctx->need_check_render_feedback = true;
509 } else {
510 samplers->depth_texture_mask &= ~(1u << slot);
511 samplers->compressed_colortex_mask &= ~(1u << slot);
512 }
513 }
514 }
515
516 static void
517 si_samplers_update_compressed_colortex_mask(struct si_textures_info *samplers)
518 {
519 unsigned mask = samplers->views.enabled_mask;
520
521 while (mask) {
522 int i = u_bit_scan(&mask);
523 struct pipe_resource *res = samplers->views.views[i]->texture;
524
525 if (res && res->target != PIPE_BUFFER) {
526 struct r600_texture *rtex = (struct r600_texture *)res;
527
528 if (is_compressed_colortex(rtex)) {
529 samplers->compressed_colortex_mask |= 1u << i;
530 } else {
531 samplers->compressed_colortex_mask &= ~(1u << i);
532 }
533 }
534 }
535 }
536
537 /* IMAGE VIEWS */
538
539 static unsigned
540 si_image_descriptors_idx(unsigned shader)
541 {
542 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
543 SI_SHADER_DESCS_IMAGES;
544 }
545
546 static struct si_descriptors*
547 si_image_descriptors(struct si_context *sctx, unsigned shader)
548 {
549 return &sctx->descriptors[si_image_descriptors_idx(shader)];
550 }
551
552 static void
553 si_release_image_views(struct si_images_info *images)
554 {
555 unsigned i;
556
557 for (i = 0; i < SI_NUM_IMAGES; ++i) {
558 struct pipe_image_view *view = &images->views[i];
559
560 pipe_resource_reference(&view->resource, NULL);
561 }
562 }
563
564 static void
565 si_image_views_begin_new_cs(struct si_context *sctx, struct si_images_info *images)
566 {
567 uint mask = images->enabled_mask;
568
569 /* Add buffers to the CS. */
570 while (mask) {
571 int i = u_bit_scan(&mask);
572 struct pipe_image_view *view = &images->views[i];
573
574 assert(view->resource);
575
576 si_sampler_view_add_buffer(sctx, view->resource,
577 RADEON_USAGE_READWRITE, false, false);
578 }
579 }
580
581 static void
582 si_disable_shader_image(struct si_context *ctx, unsigned shader, unsigned slot)
583 {
584 struct si_images_info *images = &ctx->images[shader];
585
586 if (images->enabled_mask & (1u << slot)) {
587 struct si_descriptors *descs = si_image_descriptors(ctx, shader);
588
589 pipe_resource_reference(&images->views[slot].resource, NULL);
590 images->compressed_colortex_mask &= ~(1 << slot);
591
592 memcpy(descs->list + slot*8, null_image_descriptor, 8*4);
593 images->enabled_mask &= ~(1u << slot);
594 descs->dirty_mask |= 1u << slot;
595 ctx->descriptors_dirty |= 1u << si_image_descriptors_idx(shader);
596 }
597 }
598
599 static void
600 si_mark_image_range_valid(const struct pipe_image_view *view)
601 {
602 struct r600_resource *res = (struct r600_resource *)view->resource;
603
604 assert(res && res->b.b.target == PIPE_BUFFER);
605
606 util_range_add(&res->valid_buffer_range,
607 view->u.buf.offset,
608 view->u.buf.offset + view->u.buf.size);
609 }
610
611 static void si_set_shader_image(struct si_context *ctx,
612 unsigned shader,
613 unsigned slot, const struct pipe_image_view *view)
614 {
615 struct si_screen *screen = ctx->screen;
616 struct si_images_info *images = &ctx->images[shader];
617 struct si_descriptors *descs = si_image_descriptors(ctx, shader);
618 struct r600_resource *res;
619
620 if (!view || !view->resource) {
621 si_disable_shader_image(ctx, shader, slot);
622 return;
623 }
624
625 res = (struct r600_resource *)view->resource;
626
627 if (&images->views[slot] != view)
628 util_copy_image_view(&images->views[slot], view);
629
630 si_sampler_view_add_buffer(ctx, &res->b.b,
631 RADEON_USAGE_READWRITE, false, true);
632
633 if (res->b.b.target == PIPE_BUFFER) {
634 if (view->access & PIPE_IMAGE_ACCESS_WRITE)
635 si_mark_image_range_valid(view);
636
637 si_make_buffer_descriptor(screen, res,
638 view->format,
639 view->u.buf.offset,
640 view->u.buf.size,
641 descs->list + slot * 8);
642 images->compressed_colortex_mask &= ~(1 << slot);
643 } else {
644 static const unsigned char swizzle[4] = { 0, 1, 2, 3 };
645 struct r600_texture *tex = (struct r600_texture *)res;
646 unsigned level = view->u.tex.level;
647 unsigned width, height, depth;
648 uint32_t *desc = descs->list + slot * 8;
649 bool uses_dcc = tex->dcc_offset &&
650 tex->surface.level[level].dcc_enabled;
651
652 assert(!tex->is_depth);
653 assert(tex->fmask.size == 0);
654
655 if (uses_dcc &&
656 view->access & PIPE_IMAGE_ACCESS_WRITE) {
657 /* If DCC can't be disabled, at least decompress it.
658 * The decompression is relatively cheap if the surface
659 * has been decompressed already.
660 */
661 if (r600_texture_disable_dcc(&ctx->b, tex))
662 uses_dcc = false;
663 else
664 ctx->b.decompress_dcc(&ctx->b.b, tex);
665 }
666
667 if (is_compressed_colortex(tex)) {
668 images->compressed_colortex_mask |= 1 << slot;
669 } else {
670 images->compressed_colortex_mask &= ~(1 << slot);
671 }
672
673 if (uses_dcc &&
674 p_atomic_read(&tex->framebuffers_bound))
675 ctx->need_check_render_feedback = true;
676
677 /* Always force the base level to the selected level.
678 *
679 * This is required for 3D textures, where otherwise
680 * selecting a single slice for non-layered bindings
681 * fails. It doesn't hurt the other targets.
682 */
683 width = u_minify(res->b.b.width0, level);
684 height = u_minify(res->b.b.height0, level);
685 depth = u_minify(res->b.b.depth0, level);
686
687 si_make_texture_descriptor(screen, tex,
688 false, res->b.b.target,
689 view->format, swizzle,
690 0, 0,
691 view->u.tex.first_layer,
692 view->u.tex.last_layer,
693 width, height, depth,
694 desc, NULL);
695 si_set_mutable_tex_desc_fields(tex, &tex->surface.level[level],
696 level, level,
697 util_format_get_blockwidth(view->format),
698 false, desc);
699 }
700
701 images->enabled_mask |= 1u << slot;
702 descs->dirty_mask |= 1u << slot;
703 ctx->descriptors_dirty |= 1u << si_image_descriptors_idx(shader);
704 }
705
706 static void
707 si_set_shader_images(struct pipe_context *pipe, unsigned shader,
708 unsigned start_slot, unsigned count,
709 const struct pipe_image_view *views)
710 {
711 struct si_context *ctx = (struct si_context *)pipe;
712 unsigned i, slot;
713
714 assert(shader < SI_NUM_SHADERS);
715
716 if (!count)
717 return;
718
719 assert(start_slot + count <= SI_NUM_IMAGES);
720
721 if (views) {
722 for (i = 0, slot = start_slot; i < count; ++i, ++slot)
723 si_set_shader_image(ctx, shader, slot, &views[i]);
724 } else {
725 for (i = 0, slot = start_slot; i < count; ++i, ++slot)
726 si_set_shader_image(ctx, shader, slot, NULL);
727 }
728 }
729
730 static void
731 si_images_update_compressed_colortex_mask(struct si_images_info *images)
732 {
733 unsigned mask = images->enabled_mask;
734
735 while (mask) {
736 int i = u_bit_scan(&mask);
737 struct pipe_resource *res = images->views[i].resource;
738
739 if (res && res->target != PIPE_BUFFER) {
740 struct r600_texture *rtex = (struct r600_texture *)res;
741
742 if (is_compressed_colortex(rtex)) {
743 images->compressed_colortex_mask |= 1 << i;
744 } else {
745 images->compressed_colortex_mask &= ~(1 << i);
746 }
747 }
748 }
749 }
750
751 /* SAMPLER STATES */
752
753 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
754 unsigned start, unsigned count, void **states)
755 {
756 struct si_context *sctx = (struct si_context *)ctx;
757 struct si_textures_info *samplers = &sctx->samplers[shader];
758 struct si_descriptors *desc = si_sampler_descriptors(sctx, shader);
759 struct si_sampler_state **sstates = (struct si_sampler_state**)states;
760 int i;
761
762 if (!count || shader >= SI_NUM_SHADERS)
763 return;
764
765 for (i = 0; i < count; i++) {
766 unsigned slot = start + i;
767
768 if (!sstates[i] ||
769 sstates[i] == samplers->views.sampler_states[slot])
770 continue;
771
772 samplers->views.sampler_states[slot] = sstates[i];
773
774 /* If FMASK is bound, don't overwrite it.
775 * The sampler state will be set after FMASK is unbound.
776 */
777 if (samplers->views.views[i] &&
778 samplers->views.views[i]->texture &&
779 samplers->views.views[i]->texture->target != PIPE_BUFFER &&
780 ((struct r600_texture*)samplers->views.views[i]->texture)->fmask.size)
781 continue;
782
783 memcpy(desc->list + slot * 16 + 12, sstates[i]->val, 4*4);
784 desc->dirty_mask |= 1u << slot;
785 sctx->descriptors_dirty |= 1u << si_sampler_descriptors_idx(shader);
786 }
787 }
788
789 /* BUFFER RESOURCES */
790
791 static void si_init_buffer_resources(struct si_buffer_resources *buffers,
792 struct si_descriptors *descs,
793 unsigned num_buffers,
794 unsigned shader_userdata_index,
795 enum radeon_bo_usage shader_usage,
796 enum radeon_bo_priority priority,
797 unsigned *ce_offset)
798 {
799 buffers->shader_usage = shader_usage;
800 buffers->priority = priority;
801 buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource*));
802
803 si_init_descriptors(descs, shader_userdata_index, 4,
804 num_buffers, NULL, ce_offset);
805 }
806
807 static void si_release_buffer_resources(struct si_buffer_resources *buffers,
808 struct si_descriptors *descs)
809 {
810 int i;
811
812 for (i = 0; i < descs->num_elements; i++) {
813 pipe_resource_reference(&buffers->buffers[i], NULL);
814 }
815
816 FREE(buffers->buffers);
817 }
818
819 static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
820 struct si_buffer_resources *buffers)
821 {
822 unsigned mask = buffers->enabled_mask;
823
824 /* Add buffers to the CS. */
825 while (mask) {
826 int i = u_bit_scan(&mask);
827
828 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
829 (struct r600_resource*)buffers->buffers[i],
830 buffers->shader_usage, buffers->priority);
831 }
832 }
833
834 /* VERTEX BUFFERS */
835
836 static void si_vertex_buffers_begin_new_cs(struct si_context *sctx)
837 {
838 struct si_descriptors *desc = &sctx->vertex_buffers;
839 int count = sctx->vertex_elements ? sctx->vertex_elements->count : 0;
840 int i;
841
842 for (i = 0; i < count; i++) {
843 int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
844
845 if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
846 continue;
847 if (!sctx->vertex_buffer[vb].buffer)
848 continue;
849
850 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
851 (struct r600_resource*)sctx->vertex_buffer[vb].buffer,
852 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
853 }
854
855 if (!desc->buffer)
856 return;
857 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
858 desc->buffer, RADEON_USAGE_READ,
859 RADEON_PRIO_DESCRIPTORS);
860 }
861
862 bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
863 {
864 struct si_descriptors *desc = &sctx->vertex_buffers;
865 bool bound[SI_NUM_VERTEX_BUFFERS] = {};
866 unsigned i, count = sctx->vertex_elements->count;
867 uint64_t va;
868 uint32_t *ptr;
869
870 if (!sctx->vertex_buffers_dirty)
871 return true;
872 if (!count || !sctx->vertex_elements)
873 return true;
874
875 /* Vertex buffer descriptors are the only ones which are uploaded
876 * directly through a staging buffer and don't go through
877 * the fine-grained upload path.
878 */
879 u_upload_alloc(sctx->b.uploader, 0, count * 16, 256, &desc->buffer_offset,
880 (struct pipe_resource**)&desc->buffer, (void**)&ptr);
881 if (!desc->buffer)
882 return false;
883
884 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
885 desc->buffer, RADEON_USAGE_READ,
886 RADEON_PRIO_DESCRIPTORS);
887
888 assert(count <= SI_NUM_VERTEX_BUFFERS);
889
890 for (i = 0; i < count; i++) {
891 struct pipe_vertex_element *ve = &sctx->vertex_elements->elements[i];
892 struct pipe_vertex_buffer *vb;
893 struct r600_resource *rbuffer;
894 unsigned offset;
895 uint32_t *desc = &ptr[i*4];
896
897 if (ve->vertex_buffer_index >= ARRAY_SIZE(sctx->vertex_buffer)) {
898 memset(desc, 0, 16);
899 continue;
900 }
901
902 vb = &sctx->vertex_buffer[ve->vertex_buffer_index];
903 rbuffer = (struct r600_resource*)vb->buffer;
904 if (!rbuffer) {
905 memset(desc, 0, 16);
906 continue;
907 }
908
909 offset = vb->buffer_offset + ve->src_offset;
910 va = rbuffer->gpu_address + offset;
911
912 /* Fill in T# buffer resource description */
913 desc[0] = va;
914 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
915 S_008F04_STRIDE(vb->stride);
916
917 if (sctx->b.chip_class <= CIK && vb->stride)
918 /* Round up by rounding down and adding 1 */
919 desc[2] = (vb->buffer->width0 - offset -
920 sctx->vertex_elements->format_size[i]) /
921 vb->stride + 1;
922 else
923 desc[2] = vb->buffer->width0 - offset;
924
925 desc[3] = sctx->vertex_elements->rsrc_word3[i];
926
927 if (!bound[ve->vertex_buffer_index]) {
928 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
929 (struct r600_resource*)vb->buffer,
930 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
931 bound[ve->vertex_buffer_index] = true;
932 }
933 }
934
935 /* Don't flush the const cache. It would have a very negative effect
936 * on performance (confirmed by testing). New descriptors are always
937 * uploaded to a fresh new buffer, so I don't think flushing the const
938 * cache is needed. */
939 desc->pointer_dirty = true;
940 si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
941 sctx->vertex_buffers_dirty = false;
942 return true;
943 }
944
945
946 /* CONSTANT BUFFERS */
947
948 static unsigned
949 si_const_buffer_descriptors_idx(unsigned shader)
950 {
951 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
952 SI_SHADER_DESCS_CONST_BUFFERS;
953 }
954
955 static struct si_descriptors *
956 si_const_buffer_descriptors(struct si_context *sctx, unsigned shader)
957 {
958 return &sctx->descriptors[si_const_buffer_descriptors_idx(shader)];
959 }
960
961 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
962 const uint8_t *ptr, unsigned size, uint32_t *const_offset)
963 {
964 void *tmp;
965
966 u_upload_alloc(sctx->b.uploader, 0, size, 256, const_offset,
967 (struct pipe_resource**)rbuffer, &tmp);
968 if (*rbuffer)
969 util_memcpy_cpu_to_le32(tmp, ptr, size);
970 }
971
972 static void si_set_constant_buffer(struct si_context *sctx,
973 struct si_buffer_resources *buffers,
974 unsigned descriptors_idx,
975 uint slot, const struct pipe_constant_buffer *input)
976 {
977 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
978 assert(slot < descs->num_elements);
979 pipe_resource_reference(&buffers->buffers[slot], NULL);
980
981 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
982 * with a NULL buffer). We need to use a dummy buffer instead. */
983 if (sctx->b.chip_class == CIK &&
984 (!input || (!input->buffer && !input->user_buffer)))
985 input = &sctx->null_const_buf;
986
987 if (input && (input->buffer || input->user_buffer)) {
988 struct pipe_resource *buffer = NULL;
989 uint64_t va;
990
991 /* Upload the user buffer if needed. */
992 if (input->user_buffer) {
993 unsigned buffer_offset;
994
995 si_upload_const_buffer(sctx,
996 (struct r600_resource**)&buffer, input->user_buffer,
997 input->buffer_size, &buffer_offset);
998 if (!buffer) {
999 /* Just unbind on failure. */
1000 si_set_constant_buffer(sctx, buffers, descriptors_idx, slot, NULL);
1001 return;
1002 }
1003 va = r600_resource(buffer)->gpu_address + buffer_offset;
1004 } else {
1005 pipe_resource_reference(&buffer, input->buffer);
1006 va = r600_resource(buffer)->gpu_address + input->buffer_offset;
1007 }
1008
1009 /* Set the descriptor. */
1010 uint32_t *desc = descs->list + slot*4;
1011 desc[0] = va;
1012 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1013 S_008F04_STRIDE(0);
1014 desc[2] = input->buffer_size;
1015 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1016 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1017 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1018 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1019 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1020 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1021
1022 buffers->buffers[slot] = buffer;
1023 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1024 (struct r600_resource*)buffer,
1025 buffers->shader_usage,
1026 buffers->priority, true);
1027 buffers->enabled_mask |= 1u << slot;
1028 } else {
1029 /* Clear the descriptor. */
1030 memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4);
1031 buffers->enabled_mask &= ~(1u << slot);
1032 }
1033
1034 descs->dirty_mask |= 1u << slot;
1035 sctx->descriptors_dirty |= 1u << descriptors_idx;
1036 }
1037
1038 void si_set_rw_buffer(struct si_context *sctx,
1039 uint slot, const struct pipe_constant_buffer *input)
1040 {
1041 si_set_constant_buffer(sctx, &sctx->rw_buffers,
1042 SI_DESCS_RW_BUFFERS, slot, input);
1043 }
1044
1045 static void si_pipe_set_constant_buffer(struct pipe_context *ctx,
1046 uint shader, uint slot,
1047 const struct pipe_constant_buffer *input)
1048 {
1049 struct si_context *sctx = (struct si_context *)ctx;
1050
1051 if (shader >= SI_NUM_SHADERS)
1052 return;
1053
1054 si_set_constant_buffer(sctx, &sctx->const_buffers[shader],
1055 si_const_buffer_descriptors_idx(shader),
1056 slot, input);
1057 }
1058
1059 /* SHADER BUFFERS */
1060
1061 static unsigned
1062 si_shader_buffer_descriptors_idx(unsigned shader)
1063 {
1064 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
1065 SI_SHADER_DESCS_SHADER_BUFFERS;
1066 }
1067
1068 static struct si_descriptors *
1069 si_shader_buffer_descriptors(struct si_context *sctx, unsigned shader)
1070 {
1071 return &sctx->descriptors[si_shader_buffer_descriptors_idx(shader)];
1072 }
1073
1074 static void si_set_shader_buffers(struct pipe_context *ctx, unsigned shader,
1075 unsigned start_slot, unsigned count,
1076 const struct pipe_shader_buffer *sbuffers)
1077 {
1078 struct si_context *sctx = (struct si_context *)ctx;
1079 struct si_buffer_resources *buffers = &sctx->shader_buffers[shader];
1080 struct si_descriptors *descs = si_shader_buffer_descriptors(sctx, shader);
1081 unsigned i;
1082
1083 assert(start_slot + count <= SI_NUM_SHADER_BUFFERS);
1084
1085 for (i = 0; i < count; ++i) {
1086 const struct pipe_shader_buffer *sbuffer = sbuffers ? &sbuffers[i] : NULL;
1087 struct r600_resource *buf;
1088 unsigned slot = start_slot + i;
1089 uint32_t *desc = descs->list + slot * 4;
1090 uint64_t va;
1091
1092 if (!sbuffer || !sbuffer->buffer) {
1093 pipe_resource_reference(&buffers->buffers[slot], NULL);
1094 memset(desc, 0, sizeof(uint32_t) * 4);
1095 buffers->enabled_mask &= ~(1u << slot);
1096 descs->dirty_mask |= 1u << slot;
1097 sctx->descriptors_dirty |=
1098 1u << si_shader_buffer_descriptors_idx(shader);
1099 continue;
1100 }
1101
1102 buf = (struct r600_resource *)sbuffer->buffer;
1103 va = buf->gpu_address + sbuffer->buffer_offset;
1104
1105 desc[0] = va;
1106 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1107 S_008F04_STRIDE(0);
1108 desc[2] = sbuffer->buffer_size;
1109 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1110 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1111 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1112 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1113 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1114 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1115
1116 pipe_resource_reference(&buffers->buffers[slot], &buf->b.b);
1117 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx, buf,
1118 buffers->shader_usage,
1119 buffers->priority, true);
1120 buffers->enabled_mask |= 1u << slot;
1121 descs->dirty_mask |= 1u << slot;
1122 sctx->descriptors_dirty |=
1123 1u << si_shader_buffer_descriptors_idx(shader);
1124 }
1125 }
1126
1127 /* RING BUFFERS */
1128
1129 void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
1130 struct pipe_resource *buffer,
1131 unsigned stride, unsigned num_records,
1132 bool add_tid, bool swizzle,
1133 unsigned element_size, unsigned index_stride, uint64_t offset)
1134 {
1135 struct si_context *sctx = (struct si_context *)ctx;
1136 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1137 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1138
1139 /* The stride field in the resource descriptor has 14 bits */
1140 assert(stride < (1 << 14));
1141
1142 assert(slot < descs->num_elements);
1143 pipe_resource_reference(&buffers->buffers[slot], NULL);
1144
1145 if (buffer) {
1146 uint64_t va;
1147
1148 va = r600_resource(buffer)->gpu_address + offset;
1149
1150 switch (element_size) {
1151 default:
1152 assert(!"Unsupported ring buffer element size");
1153 case 0:
1154 case 2:
1155 element_size = 0;
1156 break;
1157 case 4:
1158 element_size = 1;
1159 break;
1160 case 8:
1161 element_size = 2;
1162 break;
1163 case 16:
1164 element_size = 3;
1165 break;
1166 }
1167
1168 switch (index_stride) {
1169 default:
1170 assert(!"Unsupported ring buffer index stride");
1171 case 0:
1172 case 8:
1173 index_stride = 0;
1174 break;
1175 case 16:
1176 index_stride = 1;
1177 break;
1178 case 32:
1179 index_stride = 2;
1180 break;
1181 case 64:
1182 index_stride = 3;
1183 break;
1184 }
1185
1186 if (sctx->b.chip_class >= VI && stride)
1187 num_records *= stride;
1188
1189 /* Set the descriptor. */
1190 uint32_t *desc = descs->list + slot*4;
1191 desc[0] = va;
1192 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1193 S_008F04_STRIDE(stride) |
1194 S_008F04_SWIZZLE_ENABLE(swizzle);
1195 desc[2] = num_records;
1196 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1197 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1198 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1199 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1200 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1201 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1202 S_008F0C_ELEMENT_SIZE(element_size) |
1203 S_008F0C_INDEX_STRIDE(index_stride) |
1204 S_008F0C_ADD_TID_ENABLE(add_tid);
1205
1206 pipe_resource_reference(&buffers->buffers[slot], buffer);
1207 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1208 (struct r600_resource*)buffer,
1209 buffers->shader_usage, buffers->priority);
1210 buffers->enabled_mask |= 1u << slot;
1211 } else {
1212 /* Clear the descriptor. */
1213 memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4);
1214 buffers->enabled_mask &= ~(1u << slot);
1215 }
1216
1217 descs->dirty_mask |= 1u << slot;
1218 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1219 }
1220
1221 /* STREAMOUT BUFFERS */
1222
1223 static void si_set_streamout_targets(struct pipe_context *ctx,
1224 unsigned num_targets,
1225 struct pipe_stream_output_target **targets,
1226 const unsigned *offsets)
1227 {
1228 struct si_context *sctx = (struct si_context *)ctx;
1229 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1230 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1231 unsigned old_num_targets = sctx->b.streamout.num_targets;
1232 unsigned i, bufidx;
1233
1234 /* We are going to unbind the buffers. Mark which caches need to be flushed. */
1235 if (sctx->b.streamout.num_targets && sctx->b.streamout.begin_emitted) {
1236 /* Since streamout uses vector writes which go through TC L2
1237 * and most other clients can use TC L2 as well, we don't need
1238 * to flush it.
1239 *
1240 * The only cases which requires flushing it is VGT DMA index
1241 * fetching (on <= CIK) and indirect draw data, which are rare
1242 * cases. Thus, flag the TC L2 dirtiness in the resource and
1243 * handle it at draw call time.
1244 */
1245 for (i = 0; i < sctx->b.streamout.num_targets; i++)
1246 if (sctx->b.streamout.targets[i])
1247 r600_resource(sctx->b.streamout.targets[i]->b.buffer)->TC_L2_dirty = true;
1248
1249 /* Invalidate the scalar cache in case a streamout buffer is
1250 * going to be used as a constant buffer.
1251 *
1252 * Invalidate TC L1, because streamout bypasses it (done by
1253 * setting GLC=1 in the store instruction), but it can contain
1254 * outdated data of streamout buffers.
1255 *
1256 * VS_PARTIAL_FLUSH is required if the buffers are going to be
1257 * used as an input immediately.
1258 */
1259 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
1260 SI_CONTEXT_INV_VMEM_L1 |
1261 SI_CONTEXT_VS_PARTIAL_FLUSH;
1262 }
1263
1264 /* All readers of the streamout targets need to be finished before we can
1265 * start writing to the targets.
1266 */
1267 if (num_targets)
1268 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
1269 SI_CONTEXT_CS_PARTIAL_FLUSH;
1270
1271 /* Streamout buffers must be bound in 2 places:
1272 * 1) in VGT by setting the VGT_STRMOUT registers
1273 * 2) as shader resources
1274 */
1275
1276 /* Set the VGT regs. */
1277 r600_set_streamout_targets(ctx, num_targets, targets, offsets);
1278
1279 /* Set the shader resources.*/
1280 for (i = 0; i < num_targets; i++) {
1281 bufidx = SI_VS_STREAMOUT_BUF0 + i;
1282
1283 if (targets[i]) {
1284 struct pipe_resource *buffer = targets[i]->buffer;
1285 uint64_t va = r600_resource(buffer)->gpu_address;
1286
1287 /* Set the descriptor.
1288 *
1289 * On VI, the format must be non-INVALID, otherwise
1290 * the buffer will be considered not bound and store
1291 * instructions will be no-ops.
1292 */
1293 uint32_t *desc = descs->list + bufidx*4;
1294 desc[0] = va;
1295 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1296 desc[2] = 0xffffffff;
1297 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1298 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1299 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1300 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1301 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1302
1303 /* Set the resource. */
1304 pipe_resource_reference(&buffers->buffers[bufidx],
1305 buffer);
1306 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1307 (struct r600_resource*)buffer,
1308 buffers->shader_usage,
1309 RADEON_PRIO_SHADER_RW_BUFFER,
1310 true);
1311 buffers->enabled_mask |= 1u << bufidx;
1312 } else {
1313 /* Clear the descriptor and unset the resource. */
1314 memset(descs->list + bufidx*4, 0,
1315 sizeof(uint32_t) * 4);
1316 pipe_resource_reference(&buffers->buffers[bufidx],
1317 NULL);
1318 buffers->enabled_mask &= ~(1u << bufidx);
1319 }
1320 descs->dirty_mask |= 1u << bufidx;
1321 }
1322 for (; i < old_num_targets; i++) {
1323 bufidx = SI_VS_STREAMOUT_BUF0 + i;
1324 /* Clear the descriptor and unset the resource. */
1325 memset(descs->list + bufidx*4, 0, sizeof(uint32_t) * 4);
1326 pipe_resource_reference(&buffers->buffers[bufidx], NULL);
1327 buffers->enabled_mask &= ~(1u << bufidx);
1328 descs->dirty_mask |= 1u << bufidx;
1329 }
1330
1331 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1332 }
1333
1334 static void si_desc_reset_buffer_offset(struct pipe_context *ctx,
1335 uint32_t *desc, uint64_t old_buf_va,
1336 struct pipe_resource *new_buf)
1337 {
1338 /* Retrieve the buffer offset from the descriptor. */
1339 uint64_t old_desc_va =
1340 desc[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc[1]) << 32);
1341
1342 assert(old_buf_va <= old_desc_va);
1343 uint64_t offset_within_buffer = old_desc_va - old_buf_va;
1344
1345 /* Update the descriptor. */
1346 uint64_t va = r600_resource(new_buf)->gpu_address + offset_within_buffer;
1347
1348 desc[0] = va;
1349 desc[1] = (desc[1] & C_008F04_BASE_ADDRESS_HI) |
1350 S_008F04_BASE_ADDRESS_HI(va >> 32);
1351 }
1352
1353 /* INTERNAL CONST BUFFERS */
1354
1355 static void si_set_polygon_stipple(struct pipe_context *ctx,
1356 const struct pipe_poly_stipple *state)
1357 {
1358 struct si_context *sctx = (struct si_context *)ctx;
1359 struct pipe_constant_buffer cb = {};
1360 unsigned stipple[32];
1361 int i;
1362
1363 for (i = 0; i < 32; i++)
1364 stipple[i] = util_bitreverse(state->stipple[i]);
1365
1366 cb.user_buffer = stipple;
1367 cb.buffer_size = sizeof(stipple);
1368
1369 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE, &cb);
1370 }
1371
1372 /* TEXTURE METADATA ENABLE/DISABLE */
1373
1374 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1375 * while the texture is bound, possibly by a different context. In that case,
1376 * call this function to update compressed_colortex_masks.
1377 */
1378 void si_update_compressed_colortex_masks(struct si_context *sctx)
1379 {
1380 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
1381 si_samplers_update_compressed_colortex_mask(&sctx->samplers[i]);
1382 si_images_update_compressed_colortex_mask(&sctx->images[i]);
1383 }
1384 }
1385
1386 /* BUFFER DISCARD/INVALIDATION */
1387
1388 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1389 static void si_reset_buffer_resources(struct si_context *sctx,
1390 struct si_buffer_resources *buffers,
1391 unsigned descriptors_idx,
1392 struct pipe_resource *buf,
1393 uint64_t old_va)
1394 {
1395 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
1396 unsigned mask = buffers->enabled_mask;
1397
1398 while (mask) {
1399 unsigned i = u_bit_scan(&mask);
1400 if (buffers->buffers[i] == buf) {
1401 si_desc_reset_buffer_offset(&sctx->b.b,
1402 descs->list + i*4,
1403 old_va, buf);
1404 descs->dirty_mask |= 1u << i;
1405 sctx->descriptors_dirty |= 1u << descriptors_idx;
1406
1407 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1408 (struct r600_resource *)buf,
1409 buffers->shader_usage,
1410 buffers->priority, true);
1411 }
1412 }
1413 }
1414
1415 /* Reallocate a buffer a update all resource bindings where the buffer is
1416 * bound.
1417 *
1418 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
1419 * idle by discarding its contents. Apps usually tell us when to do this using
1420 * map_buffer flags, for example.
1421 */
1422 static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
1423 {
1424 struct si_context *sctx = (struct si_context*)ctx;
1425 struct r600_resource *rbuffer = r600_resource(buf);
1426 unsigned i, shader, alignment = rbuffer->buf->alignment;
1427 uint64_t old_va = rbuffer->gpu_address;
1428 unsigned num_elems = sctx->vertex_elements ?
1429 sctx->vertex_elements->count : 0;
1430 struct si_sampler_view *view;
1431
1432 /* Reallocate the buffer in the same pipe_resource. */
1433 r600_init_resource(&sctx->screen->b, rbuffer, rbuffer->b.b.width0,
1434 alignment);
1435
1436 /* We changed the buffer, now we need to bind it where the old one
1437 * was bound. This consists of 2 things:
1438 * 1) Updating the resource descriptor and dirtying it.
1439 * 2) Adding a relocation to the CS, so that it's usable.
1440 */
1441
1442 /* Vertex buffers. */
1443 for (i = 0; i < num_elems; i++) {
1444 int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
1445
1446 if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
1447 continue;
1448 if (!sctx->vertex_buffer[vb].buffer)
1449 continue;
1450
1451 if (sctx->vertex_buffer[vb].buffer == buf) {
1452 sctx->vertex_buffers_dirty = true;
1453 break;
1454 }
1455 }
1456
1457 /* Streamout buffers. (other internal buffers can't be invalidated) */
1458 for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) {
1459 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1460 struct si_descriptors *descs =
1461 &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1462
1463 if (buffers->buffers[i] != buf)
1464 continue;
1465
1466 si_desc_reset_buffer_offset(ctx, descs->list + i*4,
1467 old_va, buf);
1468 descs->dirty_mask |= 1u << i;
1469 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1470
1471 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1472 rbuffer, buffers->shader_usage,
1473 RADEON_PRIO_SHADER_RW_BUFFER,
1474 true);
1475
1476 /* Update the streamout state. */
1477 if (sctx->b.streamout.begin_emitted)
1478 r600_emit_streamout_end(&sctx->b);
1479 sctx->b.streamout.append_bitmask =
1480 sctx->b.streamout.enabled_mask;
1481 r600_streamout_buffers_dirty(&sctx->b);
1482 }
1483
1484 /* Constant and shader buffers. */
1485 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1486 si_reset_buffer_resources(sctx, &sctx->const_buffers[shader],
1487 si_const_buffer_descriptors_idx(shader),
1488 buf, old_va);
1489 si_reset_buffer_resources(sctx, &sctx->shader_buffers[shader],
1490 si_shader_buffer_descriptors_idx(shader),
1491 buf, old_va);
1492 }
1493
1494 /* Texture buffers - update virtual addresses in sampler view descriptors. */
1495 LIST_FOR_EACH_ENTRY(view, &sctx->b.texture_buffers, list) {
1496 if (view->base.texture == buf) {
1497 si_desc_reset_buffer_offset(ctx, &view->state[4], old_va, buf);
1498 }
1499 }
1500 /* Texture buffers - update bindings. */
1501 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1502 struct si_sampler_views *views = &sctx->samplers[shader].views;
1503 struct si_descriptors *descs =
1504 si_sampler_descriptors(sctx, shader);
1505 unsigned mask = views->enabled_mask;
1506
1507 while (mask) {
1508 unsigned i = u_bit_scan(&mask);
1509 if (views->views[i]->texture == buf) {
1510 si_desc_reset_buffer_offset(ctx,
1511 descs->list +
1512 i * 16 + 4,
1513 old_va, buf);
1514 descs->dirty_mask |= 1u << i;
1515 sctx->descriptors_dirty |=
1516 1u << si_sampler_descriptors_idx(shader);
1517
1518 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1519 rbuffer, RADEON_USAGE_READ,
1520 RADEON_PRIO_SAMPLER_BUFFER,
1521 true);
1522 }
1523 }
1524 }
1525
1526 /* Shader images */
1527 for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
1528 struct si_images_info *images = &sctx->images[shader];
1529 struct si_descriptors *descs =
1530 si_image_descriptors(sctx, shader);
1531 unsigned mask = images->enabled_mask;
1532
1533 while (mask) {
1534 unsigned i = u_bit_scan(&mask);
1535
1536 if (images->views[i].resource == buf) {
1537 if (images->views[i].access & PIPE_IMAGE_ACCESS_WRITE)
1538 si_mark_image_range_valid(&images->views[i]);
1539
1540 si_desc_reset_buffer_offset(
1541 ctx, descs->list + i * 8 + 4,
1542 old_va, buf);
1543 descs->dirty_mask |= 1u << i;
1544 sctx->descriptors_dirty |=
1545 1u << si_image_descriptors_idx(shader);
1546
1547 radeon_add_to_buffer_list_check_mem(
1548 &sctx->b, &sctx->b.gfx, rbuffer,
1549 RADEON_USAGE_READWRITE,
1550 RADEON_PRIO_SAMPLER_BUFFER, true);
1551 }
1552 }
1553 }
1554 }
1555
1556 /* Update mutable image descriptor fields of all bound textures. */
1557 void si_update_all_texture_descriptors(struct si_context *sctx)
1558 {
1559 unsigned shader;
1560
1561 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1562 struct si_sampler_views *samplers = &sctx->samplers[shader].views;
1563 struct si_images_info *images = &sctx->images[shader];
1564 unsigned mask;
1565
1566 /* Images. */
1567 mask = images->enabled_mask;
1568 while (mask) {
1569 unsigned i = u_bit_scan(&mask);
1570 struct pipe_image_view *view = &images->views[i];
1571
1572 if (!view->resource ||
1573 view->resource->target == PIPE_BUFFER)
1574 continue;
1575
1576 si_set_shader_image(sctx, shader, i, view);
1577 }
1578
1579 /* Sampler views. */
1580 mask = samplers->enabled_mask;
1581 while (mask) {
1582 unsigned i = u_bit_scan(&mask);
1583 struct pipe_sampler_view *view = samplers->views[i];
1584
1585 if (!view ||
1586 !view->texture ||
1587 view->texture->target == PIPE_BUFFER)
1588 continue;
1589
1590 si_set_sampler_view(sctx, shader, i,
1591 samplers->views[i], true);
1592 }
1593 }
1594 }
1595
1596 /* SHADER USER DATA */
1597
1598 static void si_mark_shader_pointers_dirty(struct si_context *sctx,
1599 unsigned shader)
1600 {
1601 struct si_descriptors *descs =
1602 &sctx->descriptors[SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS];
1603
1604 for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs)
1605 descs->pointer_dirty = true;
1606
1607 if (shader == PIPE_SHADER_VERTEX)
1608 sctx->vertex_buffers.pointer_dirty = true;
1609
1610 si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
1611 }
1612
1613 static void si_shader_userdata_begin_new_cs(struct si_context *sctx)
1614 {
1615 int i;
1616
1617 for (i = 0; i < SI_NUM_SHADERS; i++) {
1618 si_mark_shader_pointers_dirty(sctx, i);
1619 }
1620 sctx->descriptors[SI_DESCS_RW_BUFFERS].pointer_dirty = true;
1621 }
1622
1623 /* Set a base register address for user data constants in the given shader.
1624 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1625 */
1626 static void si_set_user_data_base(struct si_context *sctx,
1627 unsigned shader, uint32_t new_base)
1628 {
1629 uint32_t *base = &sctx->shader_userdata.sh_base[shader];
1630
1631 if (*base != new_base) {
1632 *base = new_base;
1633
1634 if (new_base)
1635 si_mark_shader_pointers_dirty(sctx, shader);
1636 }
1637 }
1638
1639 /* This must be called when these shaders are changed from non-NULL to NULL
1640 * and vice versa:
1641 * - geometry shader
1642 * - tessellation control shader
1643 * - tessellation evaluation shader
1644 */
1645 void si_shader_change_notify(struct si_context *sctx)
1646 {
1647 /* VS can be bound as VS, ES, or LS. */
1648 if (sctx->tes_shader.cso)
1649 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1650 R_00B530_SPI_SHADER_USER_DATA_LS_0);
1651 else if (sctx->gs_shader.cso)
1652 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1653 R_00B330_SPI_SHADER_USER_DATA_ES_0);
1654 else
1655 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1656 R_00B130_SPI_SHADER_USER_DATA_VS_0);
1657
1658 /* TES can be bound as ES, VS, or not bound. */
1659 if (sctx->tes_shader.cso) {
1660 if (sctx->gs_shader.cso)
1661 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
1662 R_00B330_SPI_SHADER_USER_DATA_ES_0);
1663 else
1664 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
1665 R_00B130_SPI_SHADER_USER_DATA_VS_0);
1666 } else {
1667 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, 0);
1668 }
1669 }
1670
1671 static void si_emit_shader_pointer(struct si_context *sctx,
1672 struct si_descriptors *desc,
1673 unsigned sh_base, bool keep_dirty)
1674 {
1675 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1676 uint64_t va;
1677
1678 if (!desc->pointer_dirty || !desc->buffer)
1679 return;
1680
1681 va = desc->buffer->gpu_address +
1682 desc->buffer_offset;
1683
1684 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0));
1685 radeon_emit(cs, (sh_base + desc->shader_userdata_offset - SI_SH_REG_OFFSET) >> 2);
1686 radeon_emit(cs, va);
1687 radeon_emit(cs, va >> 32);
1688
1689 desc->pointer_dirty = keep_dirty;
1690 }
1691
1692 void si_emit_graphics_shader_userdata(struct si_context *sctx,
1693 struct r600_atom *atom)
1694 {
1695 unsigned shader;
1696 uint32_t *sh_base = sctx->shader_userdata.sh_base;
1697 struct si_descriptors *descs;
1698
1699 descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1700
1701 if (descs->pointer_dirty) {
1702 si_emit_shader_pointer(sctx, descs,
1703 R_00B030_SPI_SHADER_USER_DATA_PS_0, true);
1704 si_emit_shader_pointer(sctx, descs,
1705 R_00B130_SPI_SHADER_USER_DATA_VS_0, true);
1706 si_emit_shader_pointer(sctx, descs,
1707 R_00B230_SPI_SHADER_USER_DATA_GS_0, true);
1708 si_emit_shader_pointer(sctx, descs,
1709 R_00B330_SPI_SHADER_USER_DATA_ES_0, true);
1710 si_emit_shader_pointer(sctx, descs,
1711 R_00B430_SPI_SHADER_USER_DATA_HS_0, true);
1712 descs->pointer_dirty = false;
1713 }
1714
1715 descs = &sctx->descriptors[SI_DESCS_FIRST_SHADER];
1716
1717 for (shader = 0; shader < SI_NUM_GRAPHICS_SHADERS; shader++) {
1718 unsigned base = sh_base[shader];
1719 unsigned i;
1720
1721 if (!base)
1722 continue;
1723
1724 for (i = 0; i < SI_NUM_SHADER_DESCS; i++, descs++)
1725 si_emit_shader_pointer(sctx, descs, base, false);
1726 }
1727 si_emit_shader_pointer(sctx, &sctx->vertex_buffers, sh_base[PIPE_SHADER_VERTEX], false);
1728 }
1729
1730 void si_emit_compute_shader_userdata(struct si_context *sctx)
1731 {
1732 unsigned base = R_00B900_COMPUTE_USER_DATA_0;
1733 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_FIRST_COMPUTE];
1734
1735 for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs)
1736 si_emit_shader_pointer(sctx, descs, base, false);
1737 }
1738
1739 /* INIT/DEINIT/UPLOAD */
1740
1741 void si_init_all_descriptors(struct si_context *sctx)
1742 {
1743 int i;
1744 unsigned ce_offset = 0;
1745
1746 for (i = 0; i < SI_NUM_SHADERS; i++) {
1747 si_init_buffer_resources(&sctx->const_buffers[i],
1748 si_const_buffer_descriptors(sctx, i),
1749 SI_NUM_CONST_BUFFERS, SI_SGPR_CONST_BUFFERS,
1750 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER,
1751 &ce_offset);
1752 si_init_buffer_resources(&sctx->shader_buffers[i],
1753 si_shader_buffer_descriptors(sctx, i),
1754 SI_NUM_SHADER_BUFFERS, SI_SGPR_SHADER_BUFFERS,
1755 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RW_BUFFER,
1756 &ce_offset);
1757
1758 si_init_descriptors(si_sampler_descriptors(sctx, i),
1759 SI_SGPR_SAMPLERS, 16, SI_NUM_SAMPLERS,
1760 null_texture_descriptor, &ce_offset);
1761
1762 si_init_descriptors(si_image_descriptors(sctx, i),
1763 SI_SGPR_IMAGES, 8, SI_NUM_IMAGES,
1764 null_image_descriptor, &ce_offset);
1765 }
1766
1767 si_init_buffer_resources(&sctx->rw_buffers,
1768 &sctx->descriptors[SI_DESCS_RW_BUFFERS],
1769 SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS,
1770 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS,
1771 &ce_offset);
1772 si_init_descriptors(&sctx->vertex_buffers, SI_SGPR_VERTEX_BUFFERS,
1773 4, SI_NUM_VERTEX_BUFFERS, NULL, NULL);
1774
1775 sctx->descriptors_dirty = u_bit_consecutive(0, SI_NUM_DESCS);
1776
1777 assert(ce_offset <= 32768);
1778
1779 /* Set pipe_context functions. */
1780 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
1781 sctx->b.b.set_shader_images = si_set_shader_images;
1782 sctx->b.b.set_constant_buffer = si_pipe_set_constant_buffer;
1783 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
1784 sctx->b.b.set_shader_buffers = si_set_shader_buffers;
1785 sctx->b.b.set_sampler_views = si_set_sampler_views;
1786 sctx->b.b.set_stream_output_targets = si_set_streamout_targets;
1787 sctx->b.invalidate_buffer = si_invalidate_buffer;
1788
1789 /* Shader user data. */
1790 si_init_atom(sctx, &sctx->shader_userdata.atom, &sctx->atoms.s.shader_userdata,
1791 si_emit_graphics_shader_userdata);
1792
1793 /* Set default and immutable mappings. */
1794 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
1795 si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, R_00B430_SPI_SHADER_USER_DATA_HS_0);
1796 si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, R_00B230_SPI_SHADER_USER_DATA_GS_0);
1797 si_set_user_data_base(sctx, PIPE_SHADER_FRAGMENT, R_00B030_SPI_SHADER_USER_DATA_PS_0);
1798 }
1799
1800 bool si_upload_graphics_shader_descriptors(struct si_context *sctx)
1801 {
1802 const unsigned mask = u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE);
1803 unsigned dirty = sctx->descriptors_dirty & mask;
1804
1805 while (dirty) {
1806 unsigned i = u_bit_scan(&dirty);
1807
1808 if (!si_upload_descriptors(sctx, &sctx->descriptors[i],
1809 &sctx->shader_userdata.atom))
1810 return false;
1811 }
1812
1813 sctx->descriptors_dirty &= ~mask;
1814 return true;
1815 }
1816
1817 bool si_upload_compute_shader_descriptors(struct si_context *sctx)
1818 {
1819 /* Does not update rw_buffers as that is not needed for compute shaders
1820 * and the input buffer is using the same SGPR's anyway.
1821 */
1822 const unsigned mask = u_bit_consecutive(SI_DESCS_FIRST_COMPUTE,
1823 SI_NUM_DESCS - SI_DESCS_FIRST_COMPUTE);
1824 unsigned dirty = sctx->descriptors_dirty & mask;
1825
1826 while (dirty) {
1827 unsigned i = u_bit_scan(&dirty);
1828
1829 if (!si_upload_descriptors(sctx, &sctx->descriptors[i], NULL))
1830 return false;
1831 }
1832
1833 sctx->descriptors_dirty &= ~mask;
1834
1835 return true;
1836 }
1837
1838 void si_release_all_descriptors(struct si_context *sctx)
1839 {
1840 int i;
1841
1842 for (i = 0; i < SI_NUM_SHADERS; i++) {
1843 si_release_buffer_resources(&sctx->const_buffers[i],
1844 si_const_buffer_descriptors(sctx, i));
1845 si_release_buffer_resources(&sctx->shader_buffers[i],
1846 si_shader_buffer_descriptors(sctx, i));
1847 si_release_sampler_views(&sctx->samplers[i].views);
1848 si_release_image_views(&sctx->images[i]);
1849 }
1850 si_release_buffer_resources(&sctx->rw_buffers,
1851 &sctx->descriptors[SI_DESCS_RW_BUFFERS]);
1852
1853 for (i = 0; i < SI_NUM_DESCS; ++i)
1854 si_release_descriptors(&sctx->descriptors[i]);
1855 si_release_descriptors(&sctx->vertex_buffers);
1856 }
1857
1858 void si_all_descriptors_begin_new_cs(struct si_context *sctx)
1859 {
1860 int i;
1861
1862 for (i = 0; i < SI_NUM_SHADERS; i++) {
1863 si_buffer_resources_begin_new_cs(sctx, &sctx->const_buffers[i]);
1864 si_buffer_resources_begin_new_cs(sctx, &sctx->shader_buffers[i]);
1865 si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i].views);
1866 si_image_views_begin_new_cs(sctx, &sctx->images[i]);
1867 }
1868 si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers);
1869 si_vertex_buffers_begin_new_cs(sctx);
1870
1871 for (i = 0; i < SI_NUM_DESCS; ++i)
1872 si_descriptors_begin_new_cs(sctx, &sctx->descriptors[i]);
1873
1874 si_shader_userdata_begin_new_cs(sctx);
1875 }