2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Marek Olšák <marek.olsak@amd.com>
27 /* Resource binding slots and sampler states (each described with 8 or
28 * 4 dwords) are stored in lists in memory which is accessed by shaders
29 * using scalar load instructions.
31 * This file is responsible for managing such lists. It keeps a copy of all
32 * descriptors in CPU memory and re-uploads a whole list if some slots have
35 * This code is also reponsible for updating shader pointers to those lists.
37 * Note that CP DMA can't be used for updating the lists, because a GPU hang
38 * could leave the list in a mid-IB state and the next IB would get wrong
39 * descriptors and the whole context would be unusable at that point.
40 * (Note: The register shadowing can't be used due to the same reason)
42 * Also, uploading descriptors to newly allocated memory doesn't require
46 * Possible scenarios for one 16 dword image+sampler slot:
48 * | Image | w/ FMASK | Buffer | NULL
49 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
50 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
51 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
52 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
54 * FMASK implies MSAA, therefore no sampler state.
55 * Sampler states are never unbound except when FMASK is bound.
58 #include "radeon/r600_cs.h"
63 #include "util/hash_table.h"
64 #include "util/u_format.h"
65 #include "util/u_memory.h"
66 #include "util/u_upload_mgr.h"
69 /* NULL image and buffer descriptor for textures (alpha = 1) and images
72 * For images, all fields must be zero except for the swizzle, which
73 * supports arbitrary combinations of 0s and 1s. The texture type must be
74 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
76 * For buffers, all fields must be zero. If they are not, the hw hangs.
78 * This is the only reason why the buffer descriptor must be in words [4:7].
80 static uint32_t null_texture_descriptor
[8] = {
84 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) |
85 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
86 /* the rest must contain zeros, which is also used by the buffer
90 static uint32_t null_image_descriptor
[8] = {
94 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
95 /* the rest must contain zeros, which is also used by the buffer
99 static void si_init_descriptor_list(uint32_t *desc_list
,
100 unsigned element_dw_size
,
101 unsigned num_elements
,
102 const uint32_t *null_descriptor
)
106 /* Initialize the array to NULL descriptors if the element size is 8. */
107 if (null_descriptor
) {
108 assert(element_dw_size
% 8 == 0);
109 for (i
= 0; i
< num_elements
* element_dw_size
/ 8; i
++)
110 memcpy(desc_list
+ i
* 8, null_descriptor
, 8 * 4);
114 static void si_init_descriptors(struct si_context
*sctx
,
115 struct si_descriptors
*desc
,
116 unsigned shader_userdata_index
,
117 unsigned element_dw_size
,
118 unsigned num_elements
,
119 unsigned first_ce_slot
,
120 unsigned num_ce_slots
,
123 assert(num_elements
<= sizeof(desc
->dirty_mask
)*8);
125 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
126 desc
->element_dw_size
= element_dw_size
;
127 desc
->num_elements
= num_elements
;
128 desc
->first_ce_slot
= sctx
->ce_ib
? first_ce_slot
: 0;
129 desc
->num_ce_slots
= sctx
->ce_ib
? num_ce_slots
: 0;
130 desc
->dirty_mask
= u_bit_consecutive64(0, num_elements
);
131 desc
->shader_userdata_offset
= shader_userdata_index
* 4;
133 if (desc
->num_ce_slots
) {
134 desc
->uses_ce
= true;
135 desc
->ce_offset
= *ce_offset
;
137 *ce_offset
+= element_dw_size
* desc
->num_ce_slots
* 4;
141 static void si_release_descriptors(struct si_descriptors
*desc
)
143 r600_resource_reference(&desc
->buffer
, NULL
);
147 static bool si_ce_upload(struct si_context
*sctx
, unsigned ce_offset
, unsigned size
,
148 unsigned *out_offset
, struct r600_resource
**out_buf
)
152 u_suballocator_alloc(sctx
->ce_suballocator
, size
,
153 si_optimal_tcc_alignment(sctx
, size
),
155 (struct pipe_resource
**)out_buf
);
159 va
= (*out_buf
)->gpu_address
+ *out_offset
;
161 radeon_emit(sctx
->ce_ib
, PKT3(PKT3_DUMP_CONST_RAM
, 3, 0));
162 radeon_emit(sctx
->ce_ib
, ce_offset
);
163 radeon_emit(sctx
->ce_ib
, size
/ 4);
164 radeon_emit(sctx
->ce_ib
, va
);
165 radeon_emit(sctx
->ce_ib
, va
>> 32);
167 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, *out_buf
,
168 RADEON_USAGE_READWRITE
, RADEON_PRIO_DESCRIPTORS
);
170 sctx
->ce_need_synchronization
= true;
174 void si_ce_save_all_descriptors_at_ib_end(struct si_context
* sctx
)
176 bool success
= si_ce_upload(sctx
, 0, sctx
->total_ce_ram_allocated
,
177 &sctx
->ce_ram_saved_offset
,
178 &sctx
->ce_ram_saved_buffer
);
183 void si_ce_restore_all_descriptors_at_ib_start(struct si_context
*sctx
)
185 if (!sctx
->ce_ram_saved_buffer
)
188 struct radeon_winsys_cs
*ib
= sctx
->ce_preamble_ib
;
192 uint64_t va
= sctx
->ce_ram_saved_buffer
->gpu_address
+
193 sctx
->ce_ram_saved_offset
;
195 radeon_emit(ib
, PKT3(PKT3_LOAD_CONST_RAM
, 3, 0));
197 radeon_emit(ib
, va
>> 32);
198 radeon_emit(ib
, sctx
->total_ce_ram_allocated
/ 4);
201 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
202 sctx
->ce_ram_saved_buffer
,
203 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
206 void si_ce_enable_loads(struct radeon_winsys_cs
*ib
)
208 radeon_emit(ib
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
209 radeon_emit(ib
, CONTEXT_CONTROL_LOAD_ENABLE(1) |
210 CONTEXT_CONTROL_LOAD_CE_RAM(1));
211 radeon_emit(ib
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
214 static bool si_upload_descriptors(struct si_context
*sctx
,
215 struct si_descriptors
*desc
,
216 struct r600_atom
* atom
)
218 unsigned slot_size
= desc
->element_dw_size
* 4;
219 unsigned first_slot_offset
= desc
->first_active_slot
* slot_size
;
220 unsigned upload_size
= desc
->num_active_slots
* slot_size
;
222 /* Skip the upload if no shader is using the descriptors. dirty_mask
223 * will stay dirty and the descriptors will be uploaded when there is
224 * a shader using them.
230 const uint32_t *list
= desc
->list
+
231 desc
->first_ce_slot
* desc
->element_dw_size
;
232 uint64_t mask
= (desc
->dirty_mask
>> desc
->first_ce_slot
) &
233 u_bit_consecutive64(0, desc
->num_ce_slots
);
238 u_bit_scan_consecutive_range64(&mask
, &begin
, &count
);
240 begin
*= desc
->element_dw_size
;
241 count
*= desc
->element_dw_size
;
243 radeon_emit(sctx
->ce_ib
,
244 PKT3(PKT3_WRITE_CONST_RAM
, count
, 0));
245 radeon_emit(sctx
->ce_ib
, desc
->ce_offset
+ begin
* 4);
246 radeon_emit_array(sctx
->ce_ib
, list
+ begin
, count
);
249 if (!si_ce_upload(sctx
,
251 (first_slot_offset
- desc
->first_ce_slot
* slot_size
),
252 upload_size
, (unsigned*)&desc
->buffer_offset
,
258 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, upload_size
,
259 si_optimal_tcc_alignment(sctx
, upload_size
),
260 (unsigned*)&desc
->buffer_offset
,
261 (struct pipe_resource
**)&desc
->buffer
,
264 return false; /* skip the draw call */
266 util_memcpy_cpu_to_le32(ptr
, (char*)desc
->list
+ first_slot_offset
,
268 desc
->gpu_list
= ptr
- first_slot_offset
/ 4;
270 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
271 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
274 /* The shader pointer should point to slot 0. */
275 desc
->buffer_offset
-= first_slot_offset
;
277 desc
->dirty_mask
= 0;
280 si_mark_atom_dirty(sctx
, atom
);
286 si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
291 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
292 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
298 si_sampler_and_image_descriptors_idx(unsigned shader
)
300 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
301 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
;
304 static struct si_descriptors
*
305 si_sampler_and_image_descriptors(struct si_context
*sctx
, unsigned shader
)
307 return &sctx
->descriptors
[si_sampler_and_image_descriptors_idx(shader
)];
310 static void si_release_sampler_views(struct si_sampler_views
*views
)
314 for (i
= 0; i
< ARRAY_SIZE(views
->views
); i
++) {
315 pipe_sampler_view_reference(&views
->views
[i
], NULL
);
319 static void si_sampler_view_add_buffer(struct si_context
*sctx
,
320 struct pipe_resource
*resource
,
321 enum radeon_bo_usage usage
,
322 bool is_stencil_sampler
,
325 struct r600_resource
*rres
;
326 struct r600_texture
*rtex
;
327 enum radeon_bo_priority priority
;
332 if (resource
->target
!= PIPE_BUFFER
) {
333 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
335 if (tex
->is_depth
&& !r600_can_sample_zs(tex
, is_stencil_sampler
))
336 resource
= &tex
->flushed_depth_texture
->resource
.b
.b
;
339 rres
= (struct r600_resource
*)resource
;
340 priority
= r600_get_sampler_view_priority(rres
);
342 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
343 rres
, usage
, priority
,
346 if (resource
->target
== PIPE_BUFFER
)
349 /* Now add separate DCC or HTILE. */
350 rtex
= (struct r600_texture
*)resource
;
351 if (rtex
->dcc_separate_buffer
) {
352 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
353 rtex
->dcc_separate_buffer
, usage
,
354 RADEON_PRIO_DCC
, check_mem
);
358 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
,
359 struct si_sampler_views
*views
)
361 unsigned mask
= views
->enabled_mask
;
363 /* Add buffers to the CS. */
365 int i
= u_bit_scan(&mask
);
366 struct si_sampler_view
*sview
= (struct si_sampler_view
*)views
->views
[i
];
368 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
370 sview
->is_stencil_sampler
, false);
374 /* Set buffer descriptor fields that can be changed by reallocations. */
375 static void si_set_buf_desc_address(struct r600_resource
*buf
,
376 uint64_t offset
, uint32_t *state
)
378 uint64_t va
= buf
->gpu_address
+ offset
;
381 state
[1] &= C_008F04_BASE_ADDRESS_HI
;
382 state
[1] |= S_008F04_BASE_ADDRESS_HI(va
>> 32);
385 /* Set texture descriptor fields that can be changed by reallocations.
388 * \param base_level_info information of the level of BASE_ADDRESS
389 * \param base_level the level of BASE_ADDRESS
390 * \param first_level pipe_sampler_view.u.tex.first_level
391 * \param block_width util_format_get_blockwidth()
392 * \param is_stencil select between separate Z & Stencil
393 * \param state descriptor to update
395 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
396 struct r600_texture
*tex
,
397 const struct legacy_surf_level
*base_level_info
,
398 unsigned base_level
, unsigned first_level
,
399 unsigned block_width
, bool is_stencil
,
402 uint64_t va
, meta_va
= 0;
404 if (tex
->is_depth
&& !r600_can_sample_zs(tex
, is_stencil
)) {
405 tex
= tex
->flushed_depth_texture
;
409 va
= tex
->resource
.gpu_address
;
411 if (sscreen
->b
.chip_class
>= GFX9
) {
412 /* Only stencil_offset needs to be added here. */
414 va
+= tex
->surface
.u
.gfx9
.stencil_offset
;
416 va
+= tex
->surface
.u
.gfx9
.surf_offset
;
418 va
+= base_level_info
->offset
;
422 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
423 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
425 if (sscreen
->b
.chip_class
>= VI
) {
426 state
[6] &= C_008F28_COMPRESSION_EN
;
429 if (vi_dcc_enabled(tex
, first_level
)) {
430 meta_va
= (!tex
->dcc_separate_buffer
? tex
->resource
.gpu_address
: 0) +
433 if (sscreen
->b
.chip_class
<= VI
)
434 meta_va
+= base_level_info
->dcc_offset
;
435 } else if (tex
->tc_compatible_htile
) {
436 meta_va
= tex
->resource
.gpu_address
+ tex
->htile_offset
;
440 state
[6] |= S_008F28_COMPRESSION_EN(1);
441 state
[7] = meta_va
>> 8;
445 if (sscreen
->b
.chip_class
>= GFX9
) {
446 state
[3] &= C_008F1C_SW_MODE
;
447 state
[4] &= C_008F20_PITCH_GFX9
;
450 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
451 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.stencil
.epitch
);
453 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
454 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.surf
.epitch
);
457 state
[5] &= C_008F24_META_DATA_ADDRESS
&
458 C_008F24_META_PIPE_ALIGNED
&
459 C_008F24_META_RB_ALIGNED
;
461 struct gfx9_surf_meta_flags meta
;
464 meta
= tex
->surface
.u
.gfx9
.dcc
;
466 meta
= tex
->surface
.u
.gfx9
.htile
;
468 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
469 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
470 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
474 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
475 unsigned index
= si_tile_mode_index(tex
, base_level
, is_stencil
);
477 state
[3] &= C_008F1C_TILING_INDEX
;
478 state
[3] |= S_008F1C_TILING_INDEX(index
);
479 state
[4] &= C_008F20_PITCH_GFX6
;
480 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
484 static void si_set_sampler_view_desc(struct si_context
*sctx
,
485 struct si_sampler_view
*sview
,
486 struct si_sampler_state
*sstate
,
489 struct pipe_sampler_view
*view
= &sview
->base
;
490 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
491 bool is_buffer
= rtex
->resource
.b
.b
.target
== PIPE_BUFFER
;
493 if (unlikely(!is_buffer
&& sview
->dcc_incompatible
)) {
494 if (vi_dcc_enabled(rtex
, view
->u
.tex
.first_level
))
495 if (!r600_texture_disable_dcc(&sctx
->b
, rtex
))
496 sctx
->b
.decompress_dcc(&sctx
->b
.b
, rtex
);
498 sview
->dcc_incompatible
= false;
501 assert(rtex
); /* views with texture == NULL aren't supported */
502 memcpy(desc
, sview
->state
, 8*4);
505 si_set_buf_desc_address(&rtex
->resource
,
506 sview
->base
.u
.buf
.offset
,
509 bool is_separate_stencil
= rtex
->db_compatible
&&
510 sview
->is_stencil_sampler
;
512 si_set_mutable_tex_desc_fields(sctx
->screen
, rtex
,
513 sview
->base_level_info
,
515 sview
->base
.u
.tex
.first_level
,
521 if (!is_buffer
&& rtex
->fmask
.size
) {
522 memcpy(desc
+ 8, sview
->fmask_state
, 8*4);
524 /* Disable FMASK and bind sampler state in [12:15]. */
525 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
528 memcpy(desc
+ 12, sstate
->val
, 4*4);
532 static void si_set_sampler_view(struct si_context
*sctx
,
534 unsigned slot
, struct pipe_sampler_view
*view
,
535 bool disallow_early_out
)
537 struct si_sampler_views
*views
= &sctx
->samplers
[shader
].views
;
538 struct si_sampler_view
*rview
= (struct si_sampler_view
*)view
;
539 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
540 unsigned desc_slot
= si_get_sampler_slot(slot
);
541 uint32_t *desc
= descs
->list
+ desc_slot
* 16;
543 if (views
->views
[slot
] == view
&& !disallow_early_out
)
547 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
549 si_set_sampler_view_desc(sctx
, rview
,
550 views
->sampler_states
[slot
], desc
);
552 if (rtex
->resource
.b
.b
.target
== PIPE_BUFFER
)
553 rtex
->resource
.bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
555 pipe_sampler_view_reference(&views
->views
[slot
], view
);
556 views
->enabled_mask
|= 1u << slot
;
558 /* Since this can flush, it must be done after enabled_mask is
560 si_sampler_view_add_buffer(sctx
, view
->texture
,
562 rview
->is_stencil_sampler
, true);
564 pipe_sampler_view_reference(&views
->views
[slot
], NULL
);
565 memcpy(desc
, null_texture_descriptor
, 8*4);
566 /* Only clear the lower dwords of FMASK. */
567 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
568 /* Re-set the sampler state if we are transitioning from FMASK. */
569 if (views
->sampler_states
[slot
])
571 views
->sampler_states
[slot
]->val
, 4*4);
573 views
->enabled_mask
&= ~(1u << slot
);
576 descs
->dirty_mask
|= 1ull << desc_slot
;
577 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
580 static bool color_needs_decompression(struct r600_texture
*rtex
)
582 return rtex
->fmask
.size
||
583 (rtex
->dirty_level_mask
&&
584 (rtex
->cmask
.size
|| rtex
->dcc_offset
));
587 static bool depth_needs_decompression(struct r600_texture
*rtex
,
588 struct si_sampler_view
*sview
)
590 return rtex
->db_compatible
&&
591 (!rtex
->tc_compatible_htile
||
592 !r600_can_sample_zs(rtex
, sview
->is_stencil_sampler
));
595 static void si_update_shader_needs_decompress_mask(struct si_context
*sctx
,
598 struct si_textures_info
*samplers
= &sctx
->samplers
[shader
];
599 unsigned shader_bit
= 1 << shader
;
601 if (samplers
->needs_depth_decompress_mask
||
602 samplers
->needs_color_decompress_mask
||
603 sctx
->images
[shader
].needs_color_decompress_mask
)
604 sctx
->shader_needs_decompress_mask
|= shader_bit
;
606 sctx
->shader_needs_decompress_mask
&= ~shader_bit
;
609 static void si_set_sampler_views(struct pipe_context
*ctx
,
610 enum pipe_shader_type shader
, unsigned start
,
612 struct pipe_sampler_view
**views
)
614 struct si_context
*sctx
= (struct si_context
*)ctx
;
615 struct si_textures_info
*samplers
= &sctx
->samplers
[shader
];
618 if (!count
|| shader
>= SI_NUM_SHADERS
)
621 for (i
= 0; i
< count
; i
++) {
622 unsigned slot
= start
+ i
;
624 if (!views
|| !views
[i
]) {
625 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
626 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
627 si_set_sampler_view(sctx
, shader
, slot
, NULL
, false);
631 si_set_sampler_view(sctx
, shader
, slot
, views
[i
], false);
633 if (views
[i
]->texture
&& views
[i
]->texture
->target
!= PIPE_BUFFER
) {
634 struct r600_texture
*rtex
=
635 (struct r600_texture
*)views
[i
]->texture
;
636 struct si_sampler_view
*rview
= (struct si_sampler_view
*)views
[i
];
638 if (depth_needs_decompression(rtex
, rview
)) {
639 samplers
->needs_depth_decompress_mask
|= 1u << slot
;
641 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
643 if (color_needs_decompression(rtex
)) {
644 samplers
->needs_color_decompress_mask
|= 1u << slot
;
646 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
649 if (rtex
->dcc_offset
&&
650 p_atomic_read(&rtex
->framebuffers_bound
))
651 sctx
->need_check_render_feedback
= true;
653 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
654 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
658 si_update_shader_needs_decompress_mask(sctx
, shader
);
662 si_samplers_update_needs_color_decompress_mask(struct si_textures_info
*samplers
)
664 unsigned mask
= samplers
->views
.enabled_mask
;
667 int i
= u_bit_scan(&mask
);
668 struct pipe_resource
*res
= samplers
->views
.views
[i
]->texture
;
670 if (res
&& res
->target
!= PIPE_BUFFER
) {
671 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
673 if (color_needs_decompression(rtex
)) {
674 samplers
->needs_color_decompress_mask
|= 1u << i
;
676 samplers
->needs_color_decompress_mask
&= ~(1u << i
);
685 si_release_image_views(struct si_images_info
*images
)
689 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
690 struct pipe_image_view
*view
= &images
->views
[i
];
692 pipe_resource_reference(&view
->resource
, NULL
);
697 si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images_info
*images
)
699 uint mask
= images
->enabled_mask
;
701 /* Add buffers to the CS. */
703 int i
= u_bit_scan(&mask
);
704 struct pipe_image_view
*view
= &images
->views
[i
];
706 assert(view
->resource
);
708 si_sampler_view_add_buffer(sctx
, view
->resource
,
709 RADEON_USAGE_READWRITE
, false, false);
714 si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
716 struct si_images_info
*images
= &ctx
->images
[shader
];
718 if (images
->enabled_mask
& (1u << slot
)) {
719 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
720 unsigned desc_slot
= si_get_image_slot(slot
);
722 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
723 images
->needs_color_decompress_mask
&= ~(1 << slot
);
725 memcpy(descs
->list
+ desc_slot
*8, null_image_descriptor
, 8*4);
726 images
->enabled_mask
&= ~(1u << slot
);
727 /* two 8-byte images share one 16-byte slot */
728 descs
->dirty_mask
|= 1u << (desc_slot
/ 2);
729 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
734 si_mark_image_range_valid(const struct pipe_image_view
*view
)
736 struct r600_resource
*res
= (struct r600_resource
*)view
->resource
;
738 assert(res
&& res
->b
.b
.target
== PIPE_BUFFER
);
740 util_range_add(&res
->valid_buffer_range
,
742 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
745 static void si_set_shader_image_desc(struct si_context
*ctx
,
746 const struct pipe_image_view
*view
,
747 bool skip_decompress
,
750 struct si_screen
*screen
= ctx
->screen
;
751 struct r600_resource
*res
;
753 res
= (struct r600_resource
*)view
->resource
;
755 if (res
->b
.b
.target
== PIPE_BUFFER
) {
756 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
757 si_mark_image_range_valid(view
);
759 si_make_buffer_descriptor(screen
, res
,
762 view
->u
.buf
.size
, desc
);
763 si_set_buf_desc_address(res
, view
->u
.buf
.offset
, desc
+ 4);
765 static const unsigned char swizzle
[4] = { 0, 1, 2, 3 };
766 struct r600_texture
*tex
= (struct r600_texture
*)res
;
767 unsigned level
= view
->u
.tex
.level
;
768 unsigned width
, height
, depth
, hw_level
;
769 bool uses_dcc
= vi_dcc_enabled(tex
, level
);
771 assert(!tex
->is_depth
);
772 assert(tex
->fmask
.size
== 0);
774 if (uses_dcc
&& !skip_decompress
&&
775 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
||
776 !vi_dcc_formats_compatible(res
->b
.b
.format
, view
->format
))) {
777 /* If DCC can't be disabled, at least decompress it.
778 * The decompression is relatively cheap if the surface
779 * has been decompressed already.
781 if (!r600_texture_disable_dcc(&ctx
->b
, tex
))
782 ctx
->b
.decompress_dcc(&ctx
->b
.b
, tex
);
785 if (ctx
->b
.chip_class
>= GFX9
) {
786 /* Always set the base address. The swizzle modes don't
787 * allow setting mipmap level offsets as the base.
789 width
= res
->b
.b
.width0
;
790 height
= res
->b
.b
.height0
;
791 depth
= res
->b
.b
.depth0
;
794 /* Always force the base level to the selected level.
796 * This is required for 3D textures, where otherwise
797 * selecting a single slice for non-layered bindings
798 * fails. It doesn't hurt the other targets.
800 width
= u_minify(res
->b
.b
.width0
, level
);
801 height
= u_minify(res
->b
.b
.height0
, level
);
802 depth
= u_minify(res
->b
.b
.depth0
, level
);
806 si_make_texture_descriptor(screen
, tex
,
807 false, res
->b
.b
.target
,
808 view
->format
, swizzle
,
810 view
->u
.tex
.first_layer
,
811 view
->u
.tex
.last_layer
,
812 width
, height
, depth
,
814 si_set_mutable_tex_desc_fields(screen
, tex
,
815 &tex
->surface
.u
.legacy
.level
[level
],
817 util_format_get_blockwidth(view
->format
),
822 static void si_set_shader_image(struct si_context
*ctx
,
824 unsigned slot
, const struct pipe_image_view
*view
,
825 bool skip_decompress
)
827 struct si_images_info
*images
= &ctx
->images
[shader
];
828 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
829 struct r600_resource
*res
;
830 unsigned desc_slot
= si_get_image_slot(slot
);
831 uint32_t *desc
= descs
->list
+ desc_slot
* 8;
833 if (!view
|| !view
->resource
) {
834 si_disable_shader_image(ctx
, shader
, slot
);
838 res
= (struct r600_resource
*)view
->resource
;
840 if (&images
->views
[slot
] != view
)
841 util_copy_image_view(&images
->views
[slot
], view
);
843 si_set_shader_image_desc(ctx
, view
, skip_decompress
, desc
);
845 if (res
->b
.b
.target
== PIPE_BUFFER
) {
846 images
->needs_color_decompress_mask
&= ~(1 << slot
);
847 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
849 struct r600_texture
*tex
= (struct r600_texture
*)res
;
850 unsigned level
= view
->u
.tex
.level
;
852 if (color_needs_decompression(tex
)) {
853 images
->needs_color_decompress_mask
|= 1 << slot
;
855 images
->needs_color_decompress_mask
&= ~(1 << slot
);
858 if (vi_dcc_enabled(tex
, level
) &&
859 p_atomic_read(&tex
->framebuffers_bound
))
860 ctx
->need_check_render_feedback
= true;
863 images
->enabled_mask
|= 1u << slot
;
864 /* two 8-byte images share one 16-byte slot */
865 descs
->dirty_mask
|= 1u << (desc_slot
/ 2);
866 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
868 /* Since this can flush, it must be done after enabled_mask is updated. */
869 si_sampler_view_add_buffer(ctx
, &res
->b
.b
,
870 RADEON_USAGE_READWRITE
, false, true);
874 si_set_shader_images(struct pipe_context
*pipe
,
875 enum pipe_shader_type shader
,
876 unsigned start_slot
, unsigned count
,
877 const struct pipe_image_view
*views
)
879 struct si_context
*ctx
= (struct si_context
*)pipe
;
882 assert(shader
< SI_NUM_SHADERS
);
887 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
890 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
891 si_set_shader_image(ctx
, shader
, slot
, &views
[i
], false);
893 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
894 si_set_shader_image(ctx
, shader
, slot
, NULL
, false);
897 si_update_shader_needs_decompress_mask(ctx
, shader
);
901 si_images_update_needs_color_decompress_mask(struct si_images_info
*images
)
903 unsigned mask
= images
->enabled_mask
;
906 int i
= u_bit_scan(&mask
);
907 struct pipe_resource
*res
= images
->views
[i
].resource
;
909 if (res
&& res
->target
!= PIPE_BUFFER
) {
910 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
912 if (color_needs_decompression(rtex
)) {
913 images
->needs_color_decompress_mask
|= 1 << i
;
915 images
->needs_color_decompress_mask
&= ~(1 << i
);
923 static void si_bind_sampler_states(struct pipe_context
*ctx
,
924 enum pipe_shader_type shader
,
925 unsigned start
, unsigned count
, void **states
)
927 struct si_context
*sctx
= (struct si_context
*)ctx
;
928 struct si_textures_info
*samplers
= &sctx
->samplers
[shader
];
929 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, shader
);
930 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
933 if (!count
|| shader
>= SI_NUM_SHADERS
)
936 for (i
= 0; i
< count
; i
++) {
937 unsigned slot
= start
+ i
;
938 unsigned desc_slot
= si_get_sampler_slot(slot
);
941 sstates
[i
] == samplers
->views
.sampler_states
[slot
])
945 assert(sstates
[i
]->magic
== SI_SAMPLER_STATE_MAGIC
);
947 samplers
->views
.sampler_states
[slot
] = sstates
[i
];
949 /* If FMASK is bound, don't overwrite it.
950 * The sampler state will be set after FMASK is unbound.
952 if (samplers
->views
.views
[slot
] &&
953 samplers
->views
.views
[slot
]->texture
&&
954 samplers
->views
.views
[slot
]->texture
->target
!= PIPE_BUFFER
&&
955 ((struct r600_texture
*)samplers
->views
.views
[slot
]->texture
)->fmask
.size
)
958 memcpy(desc
->list
+ desc_slot
* 16 + 12, sstates
[i
]->val
, 4*4);
959 desc
->dirty_mask
|= 1ull << desc_slot
;
960 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
964 /* BUFFER RESOURCES */
966 static void si_init_buffer_resources(struct si_context
*sctx
,
967 struct si_buffer_resources
*buffers
,
968 struct si_descriptors
*descs
,
969 unsigned num_buffers
,
970 unsigned first_ce_slot
,
971 unsigned num_ce_slots
,
972 unsigned shader_userdata_index
,
973 enum radeon_bo_usage shader_usage
,
974 enum radeon_bo_usage shader_usage_constbuf
,
975 enum radeon_bo_priority priority
,
976 enum radeon_bo_priority priority_constbuf
,
979 buffers
->shader_usage
= shader_usage
;
980 buffers
->shader_usage_constbuf
= shader_usage_constbuf
;
981 buffers
->priority
= priority
;
982 buffers
->priority_constbuf
= priority_constbuf
;
983 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
985 si_init_descriptors(sctx
, descs
, shader_userdata_index
, 4, num_buffers
,
986 first_ce_slot
, num_ce_slots
, ce_offset
);
989 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
990 struct si_descriptors
*descs
)
994 for (i
= 0; i
< descs
->num_elements
; i
++) {
995 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
998 FREE(buffers
->buffers
);
1001 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
1002 struct si_buffer_resources
*buffers
)
1004 unsigned mask
= buffers
->enabled_mask
;
1006 /* Add buffers to the CS. */
1008 int i
= u_bit_scan(&mask
);
1010 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1011 r600_resource(buffers
->buffers
[i
]),
1012 i
< SI_NUM_SHADER_BUFFERS
? buffers
->shader_usage
:
1013 buffers
->shader_usage_constbuf
,
1014 i
< SI_NUM_SHADER_BUFFERS
? buffers
->priority
:
1015 buffers
->priority_constbuf
);
1019 static void si_get_buffer_from_descriptors(struct si_buffer_resources
*buffers
,
1020 struct si_descriptors
*descs
,
1021 unsigned idx
, struct pipe_resource
**buf
,
1022 unsigned *offset
, unsigned *size
)
1024 pipe_resource_reference(buf
, buffers
->buffers
[idx
]);
1026 struct r600_resource
*res
= r600_resource(*buf
);
1027 const uint32_t *desc
= descs
->list
+ idx
* 4;
1032 assert(G_008F04_STRIDE(desc
[1]) == 0);
1033 va
= ((uint64_t)desc
[1] << 32) | desc
[0];
1035 assert(va
>= res
->gpu_address
&& va
+ *size
<= res
->gpu_address
+ res
->bo_size
);
1036 *offset
= va
- res
->gpu_address
;
1040 /* VERTEX BUFFERS */
1042 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
1044 struct si_descriptors
*desc
= &sctx
->vertex_buffers
;
1045 int count
= sctx
->vertex_elements
? sctx
->vertex_elements
->count
: 0;
1048 for (i
= 0; i
< count
; i
++) {
1049 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1051 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1053 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1056 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1057 (struct r600_resource
*)sctx
->vertex_buffer
[vb
].buffer
.resource
,
1058 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1063 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1064 desc
->buffer
, RADEON_USAGE_READ
,
1065 RADEON_PRIO_DESCRIPTORS
);
1068 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
1070 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
1071 struct si_descriptors
*desc
= &sctx
->vertex_buffers
;
1073 unsigned desc_list_byte_size
;
1074 unsigned first_vb_use_mask
;
1078 if (!sctx
->vertex_buffers_dirty
|| !velems
)
1081 count
= velems
->count
;
1086 desc_list_byte_size
= velems
->desc_list_byte_size
;
1087 first_vb_use_mask
= velems
->first_vb_use_mask
;
1089 /* Vertex buffer descriptors are the only ones which are uploaded
1090 * directly through a staging buffer and don't go through
1091 * the fine-grained upload path.
1093 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0,
1094 desc_list_byte_size
,
1095 si_optimal_tcc_alignment(sctx
, desc_list_byte_size
),
1096 (unsigned*)&desc
->buffer_offset
,
1097 (struct pipe_resource
**)&desc
->buffer
, (void**)&ptr
);
1101 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1102 desc
->buffer
, RADEON_USAGE_READ
,
1103 RADEON_PRIO_DESCRIPTORS
);
1105 assert(count
<= SI_MAX_ATTRIBS
);
1107 for (i
= 0; i
< count
; i
++) {
1108 struct pipe_vertex_buffer
*vb
;
1109 struct r600_resource
*rbuffer
;
1111 unsigned vbo_index
= velems
->vertex_buffer_index
[i
];
1112 uint32_t *desc
= &ptr
[i
*4];
1114 vb
= &sctx
->vertex_buffer
[vbo_index
];
1115 rbuffer
= (struct r600_resource
*)vb
->buffer
.resource
;
1117 memset(desc
, 0, 16);
1121 offset
= vb
->buffer_offset
+ velems
->src_offset
[i
];
1122 va
= rbuffer
->gpu_address
+ offset
;
1124 /* Fill in T# buffer resource description */
1126 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1127 S_008F04_STRIDE(vb
->stride
);
1129 if (sctx
->b
.chip_class
!= VI
&& vb
->stride
) {
1130 /* Round up by rounding down and adding 1 */
1131 desc
[2] = (vb
->buffer
.resource
->width0
- offset
-
1132 velems
->format_size
[i
]) /
1135 desc
[2] = vb
->buffer
.resource
->width0
- offset
;
1138 desc
[3] = velems
->rsrc_word3
[i
];
1140 if (first_vb_use_mask
& (1 << i
)) {
1141 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1142 (struct r600_resource
*)vb
->buffer
.resource
,
1143 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1147 /* Don't flush the const cache. It would have a very negative effect
1148 * on performance (confirmed by testing). New descriptors are always
1149 * uploaded to a fresh new buffer, so I don't think flushing the const
1150 * cache is needed. */
1151 si_mark_atom_dirty(sctx
, &sctx
->shader_userdata
.atom
);
1152 if (sctx
->b
.chip_class
>= CIK
)
1153 si_mark_atom_dirty(sctx
, &sctx
->prefetch_L2
);
1154 sctx
->vertex_buffers_dirty
= false;
1155 sctx
->vertex_buffer_pointer_dirty
= true;
1160 /* CONSTANT BUFFERS */
1163 si_const_and_shader_buffer_descriptors_idx(unsigned shader
)
1165 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
1166 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
;
1169 static struct si_descriptors
*
1170 si_const_and_shader_buffer_descriptors(struct si_context
*sctx
, unsigned shader
)
1172 return &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(shader
)];
1175 void si_upload_const_buffer(struct si_context
*sctx
, struct r600_resource
**rbuffer
,
1176 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
)
1180 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, size
,
1181 si_optimal_tcc_alignment(sctx
, size
),
1183 (struct pipe_resource
**)rbuffer
, &tmp
);
1185 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
1188 static void si_set_constant_buffer(struct si_context
*sctx
,
1189 struct si_buffer_resources
*buffers
,
1190 unsigned descriptors_idx
,
1191 uint slot
, const struct pipe_constant_buffer
*input
)
1193 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1194 assert(slot
< descs
->num_elements
);
1195 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1197 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1198 * with a NULL buffer). We need to use a dummy buffer instead. */
1199 if (sctx
->b
.chip_class
== CIK
&&
1200 (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
1201 input
= &sctx
->null_const_buf
;
1203 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1204 struct pipe_resource
*buffer
= NULL
;
1207 /* Upload the user buffer if needed. */
1208 if (input
->user_buffer
) {
1209 unsigned buffer_offset
;
1211 si_upload_const_buffer(sctx
,
1212 (struct r600_resource
**)&buffer
, input
->user_buffer
,
1213 input
->buffer_size
, &buffer_offset
);
1215 /* Just unbind on failure. */
1216 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1219 va
= r600_resource(buffer
)->gpu_address
+ buffer_offset
;
1221 pipe_resource_reference(&buffer
, input
->buffer
);
1222 va
= r600_resource(buffer
)->gpu_address
+ input
->buffer_offset
;
1223 /* Only track usage for non-user buffers. */
1224 r600_resource(buffer
)->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
1227 /* Set the descriptor. */
1228 uint32_t *desc
= descs
->list
+ slot
*4;
1230 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1232 desc
[2] = input
->buffer_size
;
1233 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1234 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1235 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1236 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1237 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1238 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1240 buffers
->buffers
[slot
] = buffer
;
1241 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1242 (struct r600_resource
*)buffer
,
1243 buffers
->shader_usage_constbuf
,
1244 buffers
->priority_constbuf
, true);
1245 buffers
->enabled_mask
|= 1u << slot
;
1247 /* Clear the descriptor. */
1248 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1249 buffers
->enabled_mask
&= ~(1u << slot
);
1252 descs
->dirty_mask
|= 1u << slot
;
1253 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1256 void si_set_rw_buffer(struct si_context
*sctx
,
1257 uint slot
, const struct pipe_constant_buffer
*input
)
1259 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
,
1260 SI_DESCS_RW_BUFFERS
, slot
, input
);
1263 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
,
1264 enum pipe_shader_type shader
, uint slot
,
1265 const struct pipe_constant_buffer
*input
)
1267 struct si_context
*sctx
= (struct si_context
*)ctx
;
1269 if (shader
>= SI_NUM_SHADERS
)
1272 slot
= si_get_constbuf_slot(slot
);
1273 si_set_constant_buffer(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1274 si_const_and_shader_buffer_descriptors_idx(shader
),
1278 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
1279 uint slot
, struct pipe_constant_buffer
*cbuf
)
1281 cbuf
->user_buffer
= NULL
;
1282 si_get_buffer_from_descriptors(
1283 &sctx
->const_and_shader_buffers
[shader
],
1284 si_const_and_shader_buffer_descriptors(sctx
, shader
),
1285 si_get_constbuf_slot(slot
),
1286 &cbuf
->buffer
, &cbuf
->buffer_offset
, &cbuf
->buffer_size
);
1289 /* SHADER BUFFERS */
1291 static void si_set_shader_buffers(struct pipe_context
*ctx
,
1292 enum pipe_shader_type shader
,
1293 unsigned start_slot
, unsigned count
,
1294 const struct pipe_shader_buffer
*sbuffers
)
1296 struct si_context
*sctx
= (struct si_context
*)ctx
;
1297 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1298 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1301 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1303 for (i
= 0; i
< count
; ++i
) {
1304 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1305 struct r600_resource
*buf
;
1306 unsigned slot
= si_get_shaderbuf_slot(start_slot
+ i
);
1307 uint32_t *desc
= descs
->list
+ slot
* 4;
1310 if (!sbuffer
|| !sbuffer
->buffer
) {
1311 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1312 memset(desc
, 0, sizeof(uint32_t) * 4);
1313 buffers
->enabled_mask
&= ~(1u << slot
);
1314 descs
->dirty_mask
|= 1u << slot
;
1315 sctx
->descriptors_dirty
|=
1316 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1320 buf
= (struct r600_resource
*)sbuffer
->buffer
;
1321 va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1324 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1326 desc
[2] = sbuffer
->buffer_size
;
1327 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1328 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1329 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1330 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1331 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1332 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1334 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1335 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
, buf
,
1336 buffers
->shader_usage
,
1337 buffers
->priority
, true);
1338 buf
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1340 buffers
->enabled_mask
|= 1u << slot
;
1341 descs
->dirty_mask
|= 1u << slot
;
1342 sctx
->descriptors_dirty
|=
1343 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1345 util_range_add(&buf
->valid_buffer_range
, sbuffer
->buffer_offset
,
1346 sbuffer
->buffer_offset
+ sbuffer
->buffer_size
);
1350 void si_get_shader_buffers(struct si_context
*sctx
,
1351 enum pipe_shader_type shader
,
1352 uint start_slot
, uint count
,
1353 struct pipe_shader_buffer
*sbuf
)
1355 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1356 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1358 for (unsigned i
= 0; i
< count
; ++i
) {
1359 si_get_buffer_from_descriptors(
1361 si_get_shaderbuf_slot(start_slot
+ i
),
1362 &sbuf
[i
].buffer
, &sbuf
[i
].buffer_offset
,
1363 &sbuf
[i
].buffer_size
);
1369 void si_set_ring_buffer(struct pipe_context
*ctx
, uint slot
,
1370 struct pipe_resource
*buffer
,
1371 unsigned stride
, unsigned num_records
,
1372 bool add_tid
, bool swizzle
,
1373 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1375 struct si_context
*sctx
= (struct si_context
*)ctx
;
1376 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1377 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1379 /* The stride field in the resource descriptor has 14 bits */
1380 assert(stride
< (1 << 14));
1382 assert(slot
< descs
->num_elements
);
1383 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1388 va
= r600_resource(buffer
)->gpu_address
+ offset
;
1390 switch (element_size
) {
1392 assert(!"Unsupported ring buffer element size");
1408 switch (index_stride
) {
1410 assert(!"Unsupported ring buffer index stride");
1426 if (sctx
->b
.chip_class
>= VI
&& stride
)
1427 num_records
*= stride
;
1429 /* Set the descriptor. */
1430 uint32_t *desc
= descs
->list
+ slot
*4;
1432 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1433 S_008F04_STRIDE(stride
) |
1434 S_008F04_SWIZZLE_ENABLE(swizzle
);
1435 desc
[2] = num_records
;
1436 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1437 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1438 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1439 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1440 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1441 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1442 S_008F0C_INDEX_STRIDE(index_stride
) |
1443 S_008F0C_ADD_TID_ENABLE(add_tid
);
1445 if (sctx
->b
.chip_class
>= GFX9
)
1446 assert(!swizzle
|| element_size
== 1); /* always 4 bytes on GFX9 */
1448 desc
[3] |= S_008F0C_ELEMENT_SIZE(element_size
);
1450 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1451 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1452 (struct r600_resource
*)buffer
,
1453 buffers
->shader_usage
, buffers
->priority
);
1454 buffers
->enabled_mask
|= 1u << slot
;
1456 /* Clear the descriptor. */
1457 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1458 buffers
->enabled_mask
&= ~(1u << slot
);
1461 descs
->dirty_mask
|= 1u << slot
;
1462 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1465 /* STREAMOUT BUFFERS */
1467 static void si_set_streamout_targets(struct pipe_context
*ctx
,
1468 unsigned num_targets
,
1469 struct pipe_stream_output_target
**targets
,
1470 const unsigned *offsets
)
1472 struct si_context
*sctx
= (struct si_context
*)ctx
;
1473 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1474 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1475 unsigned old_num_targets
= sctx
->b
.streamout
.num_targets
;
1478 /* We are going to unbind the buffers. Mark which caches need to be flushed. */
1479 if (sctx
->b
.streamout
.num_targets
&& sctx
->b
.streamout
.begin_emitted
) {
1480 /* Since streamout uses vector writes which go through TC L2
1481 * and most other clients can use TC L2 as well, we don't need
1484 * The only cases which requires flushing it is VGT DMA index
1485 * fetching (on <= CIK) and indirect draw data, which are rare
1486 * cases. Thus, flag the TC L2 dirtiness in the resource and
1487 * handle it at draw call time.
1489 for (i
= 0; i
< sctx
->b
.streamout
.num_targets
; i
++)
1490 if (sctx
->b
.streamout
.targets
[i
])
1491 r600_resource(sctx
->b
.streamout
.targets
[i
]->b
.buffer
)->TC_L2_dirty
= true;
1493 /* Invalidate the scalar cache in case a streamout buffer is
1494 * going to be used as a constant buffer.
1496 * Invalidate TC L1, because streamout bypasses it (done by
1497 * setting GLC=1 in the store instruction), but it can contain
1498 * outdated data of streamout buffers.
1500 * VS_PARTIAL_FLUSH is required if the buffers are going to be
1501 * used as an input immediately.
1503 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
|
1504 SI_CONTEXT_INV_VMEM_L1
|
1505 SI_CONTEXT_VS_PARTIAL_FLUSH
;
1508 /* All readers of the streamout targets need to be finished before we can
1509 * start writing to the targets.
1512 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
1513 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1515 /* Streamout buffers must be bound in 2 places:
1516 * 1) in VGT by setting the VGT_STRMOUT registers
1517 * 2) as shader resources
1520 /* Set the VGT regs. */
1521 r600_set_streamout_targets(ctx
, num_targets
, targets
, offsets
);
1523 /* Set the shader resources.*/
1524 for (i
= 0; i
< num_targets
; i
++) {
1525 bufidx
= SI_VS_STREAMOUT_BUF0
+ i
;
1528 struct pipe_resource
*buffer
= targets
[i
]->buffer
;
1529 uint64_t va
= r600_resource(buffer
)->gpu_address
;
1531 /* Set the descriptor.
1533 * On VI, the format must be non-INVALID, otherwise
1534 * the buffer will be considered not bound and store
1535 * instructions will be no-ops.
1537 uint32_t *desc
= descs
->list
+ bufidx
*4;
1539 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
1540 desc
[2] = 0xffffffff;
1541 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1542 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1543 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1544 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1545 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1547 /* Set the resource. */
1548 pipe_resource_reference(&buffers
->buffers
[bufidx
],
1550 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1551 (struct r600_resource
*)buffer
,
1552 buffers
->shader_usage
,
1553 RADEON_PRIO_SHADER_RW_BUFFER
,
1555 r600_resource(buffer
)->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
1557 buffers
->enabled_mask
|= 1u << bufidx
;
1559 /* Clear the descriptor and unset the resource. */
1560 memset(descs
->list
+ bufidx
*4, 0,
1561 sizeof(uint32_t) * 4);
1562 pipe_resource_reference(&buffers
->buffers
[bufidx
],
1564 buffers
->enabled_mask
&= ~(1u << bufidx
);
1566 descs
->dirty_mask
|= 1u << bufidx
;
1568 for (; i
< old_num_targets
; i
++) {
1569 bufidx
= SI_VS_STREAMOUT_BUF0
+ i
;
1570 /* Clear the descriptor and unset the resource. */
1571 memset(descs
->list
+ bufidx
*4, 0, sizeof(uint32_t) * 4);
1572 pipe_resource_reference(&buffers
->buffers
[bufidx
], NULL
);
1573 buffers
->enabled_mask
&= ~(1u << bufidx
);
1574 descs
->dirty_mask
|= 1u << bufidx
;
1577 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1580 static void si_desc_reset_buffer_offset(struct pipe_context
*ctx
,
1581 uint32_t *desc
, uint64_t old_buf_va
,
1582 struct pipe_resource
*new_buf
)
1584 /* Retrieve the buffer offset from the descriptor. */
1585 uint64_t old_desc_va
=
1586 desc
[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
1588 assert(old_buf_va
<= old_desc_va
);
1589 uint64_t offset_within_buffer
= old_desc_va
- old_buf_va
;
1591 /* Update the descriptor. */
1592 si_set_buf_desc_address(r600_resource(new_buf
), offset_within_buffer
,
1596 /* INTERNAL CONST BUFFERS */
1598 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
1599 const struct pipe_poly_stipple
*state
)
1601 struct si_context
*sctx
= (struct si_context
*)ctx
;
1602 struct pipe_constant_buffer cb
= {};
1603 unsigned stipple
[32];
1606 for (i
= 0; i
< 32; i
++)
1607 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1609 cb
.user_buffer
= stipple
;
1610 cb
.buffer_size
= sizeof(stipple
);
1612 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1615 /* TEXTURE METADATA ENABLE/DISABLE */
1617 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1618 * while the texture is bound, possibly by a different context. In that case,
1619 * call this function to update needs_*_decompress_masks.
1621 void si_update_needs_color_decompress_masks(struct si_context
*sctx
)
1623 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1624 si_samplers_update_needs_color_decompress_mask(&sctx
->samplers
[i
]);
1625 si_images_update_needs_color_decompress_mask(&sctx
->images
[i
]);
1626 si_update_shader_needs_decompress_mask(sctx
, i
);
1630 /* BUFFER DISCARD/INVALIDATION */
1632 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1633 static void si_reset_buffer_resources(struct si_context
*sctx
,
1634 struct si_buffer_resources
*buffers
,
1635 unsigned descriptors_idx
,
1637 struct pipe_resource
*buf
,
1639 enum radeon_bo_usage usage
,
1640 enum radeon_bo_priority priority
)
1642 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1643 unsigned mask
= buffers
->enabled_mask
& slot_mask
;
1646 unsigned i
= u_bit_scan(&mask
);
1647 if (buffers
->buffers
[i
] == buf
) {
1648 si_desc_reset_buffer_offset(&sctx
->b
.b
,
1651 descs
->dirty_mask
|= 1u << i
;
1652 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1654 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1655 (struct r600_resource
*)buf
,
1656 usage
, priority
, true);
1661 static void si_rebind_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
,
1664 struct si_context
*sctx
= (struct si_context
*)ctx
;
1665 struct r600_resource
*rbuffer
= r600_resource(buf
);
1667 unsigned num_elems
= sctx
->vertex_elements
?
1668 sctx
->vertex_elements
->count
: 0;
1670 /* We changed the buffer, now we need to bind it where the old one
1671 * was bound. This consists of 2 things:
1672 * 1) Updating the resource descriptor and dirtying it.
1673 * 2) Adding a relocation to the CS, so that it's usable.
1676 /* Vertex buffers. */
1677 if (rbuffer
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
1678 for (i
= 0; i
< num_elems
; i
++) {
1679 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1681 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1683 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1686 if (sctx
->vertex_buffer
[vb
].buffer
.resource
== buf
) {
1687 sctx
->vertex_buffers_dirty
= true;
1693 /* Streamout buffers. (other internal buffers can't be invalidated) */
1694 if (rbuffer
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
1695 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1696 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1697 struct si_descriptors
*descs
=
1698 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1700 if (buffers
->buffers
[i
] != buf
)
1703 si_desc_reset_buffer_offset(ctx
, descs
->list
+ i
*4,
1705 descs
->dirty_mask
|= 1u << i
;
1706 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1708 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1709 rbuffer
, buffers
->shader_usage
,
1710 RADEON_PRIO_SHADER_RW_BUFFER
,
1713 /* Update the streamout state. */
1714 if (sctx
->b
.streamout
.begin_emitted
)
1715 r600_emit_streamout_end(&sctx
->b
);
1716 sctx
->b
.streamout
.append_bitmask
=
1717 sctx
->b
.streamout
.enabled_mask
;
1718 r600_streamout_buffers_dirty(&sctx
->b
);
1722 /* Constant and shader buffers. */
1723 if (rbuffer
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1724 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1725 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1726 si_const_and_shader_buffer_descriptors_idx(shader
),
1727 u_bit_consecutive(SI_NUM_SHADER_BUFFERS
, SI_NUM_CONST_BUFFERS
),
1729 sctx
->const_and_shader_buffers
[shader
].shader_usage_constbuf
,
1730 sctx
->const_and_shader_buffers
[shader
].priority_constbuf
);
1733 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
1734 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1735 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1736 si_const_and_shader_buffer_descriptors_idx(shader
),
1737 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
),
1739 sctx
->const_and_shader_buffers
[shader
].shader_usage
,
1740 sctx
->const_and_shader_buffers
[shader
].priority
);
1743 if (rbuffer
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
1744 /* Texture buffers - update bindings. */
1745 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1746 struct si_sampler_views
*views
= &sctx
->samplers
[shader
].views
;
1747 struct si_descriptors
*descs
=
1748 si_sampler_and_image_descriptors(sctx
, shader
);
1749 unsigned mask
= views
->enabled_mask
;
1752 unsigned i
= u_bit_scan(&mask
);
1753 if (views
->views
[i
]->texture
== buf
) {
1754 unsigned desc_slot
= si_get_sampler_slot(i
);
1756 si_desc_reset_buffer_offset(ctx
,
1760 descs
->dirty_mask
|= 1ull << desc_slot
;
1761 sctx
->descriptors_dirty
|=
1762 1u << si_sampler_and_image_descriptors_idx(shader
);
1764 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1765 rbuffer
, RADEON_USAGE_READ
,
1766 RADEON_PRIO_SAMPLER_BUFFER
,
1774 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
1775 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1776 struct si_images_info
*images
= &sctx
->images
[shader
];
1777 struct si_descriptors
*descs
=
1778 si_sampler_and_image_descriptors(sctx
, shader
);
1779 unsigned mask
= images
->enabled_mask
;
1782 unsigned i
= u_bit_scan(&mask
);
1784 if (images
->views
[i
].resource
== buf
) {
1785 unsigned desc_slot
= si_get_image_slot(i
);
1787 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1788 si_mark_image_range_valid(&images
->views
[i
]);
1790 si_desc_reset_buffer_offset(
1791 ctx
, descs
->list
+ desc_slot
* 8 + 4,
1793 /* two 8-byte images share one 16-byte slot */
1794 descs
->dirty_mask
|= 1u << (desc_slot
/ 2);
1795 sctx
->descriptors_dirty
|=
1796 1u << si_sampler_and_image_descriptors_idx(shader
);
1798 radeon_add_to_buffer_list_check_mem(
1799 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1800 RADEON_USAGE_READWRITE
,
1801 RADEON_PRIO_SAMPLER_BUFFER
, true);
1808 /* Reallocate a buffer a update all resource bindings where the buffer is
1811 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
1812 * idle by discarding its contents. Apps usually tell us when to do this using
1813 * map_buffer flags, for example.
1815 static void si_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
1817 struct si_context
*sctx
= (struct si_context
*)ctx
;
1818 struct r600_resource
*rbuffer
= r600_resource(buf
);
1819 uint64_t old_va
= rbuffer
->gpu_address
;
1821 /* Reallocate the buffer in the same pipe_resource. */
1822 r600_alloc_resource(&sctx
->screen
->b
, rbuffer
);
1824 si_rebind_buffer(ctx
, buf
, old_va
);
1827 /* Update mutable image descriptor fields of all bound textures. */
1828 void si_update_all_texture_descriptors(struct si_context
*sctx
)
1832 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1833 struct si_sampler_views
*samplers
= &sctx
->samplers
[shader
].views
;
1834 struct si_images_info
*images
= &sctx
->images
[shader
];
1838 mask
= images
->enabled_mask
;
1840 unsigned i
= u_bit_scan(&mask
);
1841 struct pipe_image_view
*view
= &images
->views
[i
];
1843 if (!view
->resource
||
1844 view
->resource
->target
== PIPE_BUFFER
)
1847 si_set_shader_image(sctx
, shader
, i
, view
, true);
1850 /* Sampler views. */
1851 mask
= samplers
->enabled_mask
;
1853 unsigned i
= u_bit_scan(&mask
);
1854 struct pipe_sampler_view
*view
= samplers
->views
[i
];
1858 view
->texture
->target
== PIPE_BUFFER
)
1861 si_set_sampler_view(sctx
, shader
, i
,
1862 samplers
->views
[i
], true);
1865 si_update_shader_needs_decompress_mask(sctx
, shader
);
1869 /* SHADER USER DATA */
1871 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
,
1874 sctx
->shader_pointers_dirty
|=
1875 u_bit_consecutive(SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
,
1876 SI_NUM_SHADER_DESCS
);
1878 if (shader
== PIPE_SHADER_VERTEX
)
1879 sctx
->vertex_buffer_pointer_dirty
= sctx
->vertex_buffers
.buffer
!= NULL
;
1881 si_mark_atom_dirty(sctx
, &sctx
->shader_userdata
.atom
);
1884 static void si_shader_userdata_begin_new_cs(struct si_context
*sctx
)
1886 sctx
->shader_pointers_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
1887 sctx
->vertex_buffer_pointer_dirty
= sctx
->vertex_buffers
.buffer
!= NULL
;
1888 si_mark_atom_dirty(sctx
, &sctx
->shader_userdata
.atom
);
1891 /* Set a base register address for user data constants in the given shader.
1892 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1894 static void si_set_user_data_base(struct si_context
*sctx
,
1895 unsigned shader
, uint32_t new_base
)
1897 uint32_t *base
= &sctx
->shader_userdata
.sh_base
[shader
];
1899 if (*base
!= new_base
) {
1903 si_mark_shader_pointers_dirty(sctx
, shader
);
1905 if (shader
== PIPE_SHADER_VERTEX
)
1906 sctx
->last_vs_state
= ~0;
1911 /* This must be called when these shaders are changed from non-NULL to NULL
1914 * - tessellation control shader
1915 * - tessellation evaluation shader
1917 void si_shader_change_notify(struct si_context
*sctx
)
1919 /* VS can be bound as VS, ES, or LS. */
1920 if (sctx
->tes_shader
.cso
) {
1921 if (sctx
->b
.chip_class
>= GFX9
) {
1922 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1923 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
1925 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1926 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
1928 } else if (sctx
->gs_shader
.cso
) {
1929 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1930 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1932 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1933 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1936 /* TES can be bound as ES, VS, or not bound. */
1937 if (sctx
->tes_shader
.cso
) {
1938 if (sctx
->gs_shader
.cso
)
1939 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
1940 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1942 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
1943 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1945 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
1949 static void si_emit_shader_pointer(struct si_context
*sctx
,
1950 struct si_descriptors
*desc
,
1953 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1957 return; /* the pointer is not used by current shaders */
1959 va
= desc
->buffer
->gpu_address
+
1960 desc
->buffer_offset
;
1962 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, 2, 0));
1963 radeon_emit(cs
, (sh_base
+ desc
->shader_userdata_offset
- SI_SH_REG_OFFSET
) >> 2);
1964 radeon_emit(cs
, va
);
1965 radeon_emit(cs
, va
>> 32);
1968 void si_emit_graphics_shader_userdata(struct si_context
*sctx
,
1969 struct r600_atom
*atom
)
1972 uint32_t *sh_base
= sctx
->shader_userdata
.sh_base
;
1973 struct si_descriptors
*descs
;
1975 descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1977 if (sctx
->shader_pointers_dirty
& (1 << SI_DESCS_RW_BUFFERS
)) {
1978 si_emit_shader_pointer(sctx
, descs
,
1979 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
1980 si_emit_shader_pointer(sctx
, descs
,
1981 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1983 if (sctx
->b
.chip_class
>= GFX9
) {
1984 /* GFX9 merged LS-HS and ES-GS.
1985 * Set RW_BUFFERS in the special registers, so that
1986 * it's preloaded into s[0:1] instead of s[8:9].
1988 si_emit_shader_pointer(sctx
, descs
,
1989 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
);
1990 si_emit_shader_pointer(sctx
, descs
,
1991 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
);
1993 si_emit_shader_pointer(sctx
, descs
,
1994 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
1995 si_emit_shader_pointer(sctx
, descs
,
1996 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1997 si_emit_shader_pointer(sctx
, descs
,
1998 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2002 mask
= sctx
->shader_pointers_dirty
&
2003 u_bit_consecutive(SI_DESCS_FIRST_SHADER
,
2004 SI_DESCS_FIRST_COMPUTE
- SI_DESCS_FIRST_SHADER
);
2007 unsigned i
= u_bit_scan(&mask
);
2008 unsigned shader
= (i
- SI_DESCS_FIRST_SHADER
) / SI_NUM_SHADER_DESCS
;
2009 unsigned base
= sh_base
[shader
];
2012 si_emit_shader_pointer(sctx
, descs
+ i
, base
);
2014 sctx
->shader_pointers_dirty
&=
2015 ~u_bit_consecutive(SI_DESCS_RW_BUFFERS
, SI_DESCS_FIRST_COMPUTE
);
2017 if (sctx
->vertex_buffer_pointer_dirty
) {
2018 si_emit_shader_pointer(sctx
, &sctx
->vertex_buffers
,
2019 sh_base
[PIPE_SHADER_VERTEX
]);
2020 sctx
->vertex_buffer_pointer_dirty
= false;
2024 void si_emit_compute_shader_userdata(struct si_context
*sctx
)
2026 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
2027 struct si_descriptors
*descs
= sctx
->descriptors
;
2028 unsigned compute_mask
=
2029 u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
, SI_NUM_SHADER_DESCS
);
2030 unsigned mask
= sctx
->shader_pointers_dirty
& compute_mask
;
2033 unsigned i
= u_bit_scan(&mask
);
2035 si_emit_shader_pointer(sctx
, descs
+ i
, base
);
2037 sctx
->shader_pointers_dirty
&= ~compute_mask
;
2042 struct si_bindless_descriptor_slab
2044 struct pb_slab base
;
2045 struct r600_resource
*buffer
;
2046 struct si_bindless_descriptor
*entries
;
2049 bool si_bindless_descriptor_can_reclaim_slab(void *priv
,
2050 struct pb_slab_entry
*entry
)
2052 /* Do not allow to reclaim any bindless descriptors for now because the
2053 * GPU might be using them. This should be improved later on.
2058 struct pb_slab
*si_bindless_descriptor_slab_alloc(void *priv
, unsigned heap
,
2059 unsigned entry_size
,
2060 unsigned group_index
)
2062 struct si_context
*sctx
= priv
;
2063 struct si_screen
*sscreen
= sctx
->screen
;
2064 struct si_bindless_descriptor_slab
*slab
;
2066 slab
= CALLOC_STRUCT(si_bindless_descriptor_slab
);
2070 /* Create a buffer in VRAM for 1024 bindless descriptors. */
2071 slab
->buffer
= (struct r600_resource
*)
2072 pipe_buffer_create(&sscreen
->b
.b
, 0,
2073 PIPE_USAGE_DEFAULT
, 64 * 1024);
2077 slab
->base
.num_entries
= slab
->buffer
->bo_size
/ entry_size
;
2078 slab
->base
.num_free
= slab
->base
.num_entries
;
2079 slab
->entries
= CALLOC(slab
->base
.num_entries
, sizeof(*slab
->entries
));
2083 LIST_INITHEAD(&slab
->base
.free
);
2085 for (unsigned i
= 0; i
< slab
->base
.num_entries
; ++i
) {
2086 struct si_bindless_descriptor
*desc
= &slab
->entries
[i
];
2088 desc
->entry
.slab
= &slab
->base
;
2089 desc
->entry
.group_index
= group_index
;
2090 desc
->buffer
= slab
->buffer
;
2091 desc
->offset
= i
* entry_size
;
2093 LIST_ADDTAIL(&desc
->entry
.head
, &slab
->base
.free
);
2096 /* Add the descriptor to the per-context list. */
2097 util_dynarray_append(&sctx
->bindless_descriptors
,
2098 struct r600_resource
*, slab
->buffer
);
2103 r600_resource_reference(&slab
->buffer
, NULL
);
2109 void si_bindless_descriptor_slab_free(void *priv
, struct pb_slab
*pslab
)
2111 struct si_context
*sctx
= priv
;
2112 struct si_bindless_descriptor_slab
*slab
=
2113 (struct si_bindless_descriptor_slab
*)pslab
;
2115 /* Remove the descriptor from the per-context list. */
2116 util_dynarray_delete_unordered(&sctx
->bindless_descriptors
,
2117 struct r600_resource
*, slab
->buffer
);
2119 r600_resource_reference(&slab
->buffer
, NULL
);
2120 FREE(slab
->entries
);
2124 static struct si_bindless_descriptor
*
2125 si_create_bindless_descriptor(struct si_context
*sctx
, uint32_t *desc_list
,
2128 struct si_screen
*sscreen
= sctx
->screen
;
2129 struct si_bindless_descriptor
*desc
;
2130 struct pb_slab_entry
*entry
;
2133 /* Sub-allocate the bindless descriptor from a slab to avoid dealing
2134 * with a ton of buffers and for reducing the winsys overhead.
2136 entry
= pb_slab_alloc(&sctx
->bindless_descriptor_slabs
, 64, 0);
2141 desc
= container_of(entry
, desc
, entry
);
2143 /* Upload the descriptor directly in VRAM. Because the slabs are
2144 * currently never reclaimed, we don't need to synchronize the
2147 ptr
= sscreen
->b
.ws
->buffer_map(desc
->buffer
->buf
, NULL
,
2148 PIPE_TRANSFER_WRITE
|
2149 PIPE_TRANSFER_UNSYNCHRONIZED
);
2150 util_memcpy_cpu_to_le32(ptr
+ desc
->offset
, desc_list
, size
);
2155 static uint64_t si_create_texture_handle(struct pipe_context
*ctx
,
2156 struct pipe_sampler_view
*view
,
2157 const struct pipe_sampler_state
*state
)
2159 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
2160 struct si_context
*sctx
= (struct si_context
*)ctx
;
2161 struct si_texture_handle
*tex_handle
;
2162 struct si_sampler_state
*sstate
;
2163 uint32_t desc_list
[16];
2166 tex_handle
= CALLOC_STRUCT(si_texture_handle
);
2170 memset(desc_list
, 0, sizeof(desc_list
));
2171 si_init_descriptor_list(&desc_list
[0], 16, 1, null_texture_descriptor
);
2173 sstate
= ctx
->create_sampler_state(ctx
, state
);
2179 si_set_sampler_view_desc(sctx
, sview
, sstate
, &desc_list
[0]);
2180 ctx
->delete_sampler_state(ctx
, sstate
);
2182 tex_handle
->desc
= si_create_bindless_descriptor(sctx
, desc_list
,
2184 if (!tex_handle
->desc
) {
2189 handle
= tex_handle
->desc
->buffer
->gpu_address
+
2190 tex_handle
->desc
->offset
;
2192 if (!_mesa_hash_table_insert(sctx
->tex_handles
, (void *)handle
,
2194 pb_slab_free(&sctx
->bindless_descriptor_slabs
,
2195 &tex_handle
->desc
->entry
);
2200 pipe_sampler_view_reference(&tex_handle
->view
, view
);
2205 static void si_delete_texture_handle(struct pipe_context
*ctx
, uint64_t handle
)
2207 struct si_context
*sctx
= (struct si_context
*)ctx
;
2208 struct si_texture_handle
*tex_handle
;
2209 struct hash_entry
*entry
;
2211 entry
= _mesa_hash_table_search(sctx
->tex_handles
, (void *)handle
);
2215 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2217 pipe_sampler_view_reference(&tex_handle
->view
, NULL
);
2218 _mesa_hash_table_remove(sctx
->tex_handles
, entry
);
2219 pb_slab_free(&sctx
->bindless_descriptor_slabs
,
2220 &tex_handle
->desc
->entry
);
2224 static void si_make_texture_handle_resident(struct pipe_context
*ctx
,
2225 uint64_t handle
, bool resident
)
2227 struct si_context
*sctx
= (struct si_context
*)ctx
;
2228 struct si_texture_handle
*tex_handle
;
2229 struct si_sampler_view
*sview
;
2230 struct hash_entry
*entry
;
2232 entry
= _mesa_hash_table_search(sctx
->tex_handles
, (void *)handle
);
2236 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2237 sview
= (struct si_sampler_view
*)tex_handle
->view
;
2240 /* Add the texture handle to the per-context list. */
2241 util_dynarray_append(&sctx
->resident_tex_handles
,
2242 struct si_texture_handle
*, tex_handle
);
2244 /* Add the buffers to the current CS in case si_begin_new_cs()
2245 * is not going to be called.
2247 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2248 tex_handle
->desc
->buffer
,
2249 RADEON_USAGE_READWRITE
,
2250 RADEON_PRIO_DESCRIPTORS
);
2252 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2254 sview
->is_stencil_sampler
, false);
2256 /* Remove the texture handle from the per-context list. */
2257 util_dynarray_delete_unordered(&sctx
->resident_tex_handles
,
2258 struct si_texture_handle
*,
2263 static uint64_t si_create_image_handle(struct pipe_context
*ctx
,
2264 const struct pipe_image_view
*view
)
2266 struct si_context
*sctx
= (struct si_context
*)ctx
;
2267 struct si_image_handle
*img_handle
;
2268 uint32_t desc_list
[16];
2271 if (!view
|| !view
->resource
)
2274 img_handle
= CALLOC_STRUCT(si_image_handle
);
2278 memset(desc_list
, 0, sizeof(desc_list
));
2279 si_init_descriptor_list(&desc_list
[0], 8, 1, null_image_descriptor
);
2281 si_set_shader_image_desc(sctx
, view
, false, &desc_list
[0]);
2283 img_handle
->desc
= si_create_bindless_descriptor(sctx
, desc_list
,
2285 if (!img_handle
->desc
) {
2290 handle
= img_handle
->desc
->buffer
->gpu_address
+
2291 img_handle
->desc
->offset
;
2293 if (!_mesa_hash_table_insert(sctx
->img_handles
, (void *)handle
,
2295 pb_slab_free(&sctx
->bindless_descriptor_slabs
,
2296 &img_handle
->desc
->entry
);
2301 util_copy_image_view(&img_handle
->view
, view
);
2306 static void si_delete_image_handle(struct pipe_context
*ctx
, uint64_t handle
)
2308 struct si_context
*sctx
= (struct si_context
*)ctx
;
2309 struct si_image_handle
*img_handle
;
2310 struct hash_entry
*entry
;
2312 entry
= _mesa_hash_table_search(sctx
->img_handles
, (void *)handle
);
2316 img_handle
= (struct si_image_handle
*)entry
->data
;
2318 util_copy_image_view(&img_handle
->view
, NULL
);
2319 _mesa_hash_table_remove(sctx
->img_handles
, entry
);
2320 pb_slab_free(&sctx
->bindless_descriptor_slabs
,
2321 &img_handle
->desc
->entry
);
2325 static void si_make_image_handle_resident(struct pipe_context
*ctx
,
2326 uint64_t handle
, unsigned access
,
2329 struct si_context
*sctx
= (struct si_context
*)ctx
;
2330 struct si_image_handle
*img_handle
;
2331 struct pipe_image_view
*view
;
2332 struct hash_entry
*entry
;
2334 entry
= _mesa_hash_table_search(sctx
->img_handles
, (void *)handle
);
2338 img_handle
= (struct si_image_handle
*)entry
->data
;
2339 view
= &img_handle
->view
;
2342 /* Add the image handle to the per-context list. */
2343 util_dynarray_append(&sctx
->resident_img_handles
,
2344 struct si_image_handle
*, img_handle
);
2346 /* Add the buffers to the current CS in case si_begin_new_cs()
2347 * is not going to be called.
2349 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2350 img_handle
->desc
->buffer
,
2351 RADEON_USAGE_READWRITE
,
2352 RADEON_PRIO_DESCRIPTORS
);
2354 si_sampler_view_add_buffer(sctx
, view
->resource
,
2355 (access
& PIPE_IMAGE_ACCESS_WRITE
) ?
2356 RADEON_USAGE_READWRITE
:
2357 RADEON_USAGE_READ
, false, false);
2359 /* Remove the image handle from the per-context list. */
2360 util_dynarray_delete_unordered(&sctx
->resident_img_handles
,
2361 struct si_image_handle
*,
2367 void si_all_resident_buffers_begin_new_cs(struct si_context
*sctx
)
2369 unsigned num_resident_tex_handles
, num_resident_img_handles
;
2370 unsigned num_bindless_descriptors
;
2373 num_resident_tex_handles
= sctx
->resident_tex_handles
.size
/
2374 sizeof(struct si_texture_handle
*);
2375 num_resident_img_handles
= sctx
->resident_img_handles
.size
/
2376 sizeof(struct si_image_handle
*);
2377 num_bindless_descriptors
= sctx
->bindless_descriptors
.size
/
2378 sizeof(struct r600_resource
*);
2380 /* Add all bindless descriptors. */
2381 for (i
= 0; i
< num_bindless_descriptors
; i
++) {
2382 struct r600_resource
*desc
=
2383 *util_dynarray_element(&sctx
->bindless_descriptors
,
2384 struct r600_resource
*, i
);
2386 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
,
2387 RADEON_USAGE_READWRITE
,
2388 RADEON_PRIO_DESCRIPTORS
);
2391 /* Add all resident texture handles. */
2392 for (i
= 0; i
< num_resident_tex_handles
; i
++) {
2393 struct si_texture_handle
*tex_handle
=
2394 *util_dynarray_element(&sctx
->resident_tex_handles
,
2395 struct si_texture_handle
*, i
);
2396 struct si_sampler_view
*sview
=
2397 (struct si_sampler_view
*)tex_handle
->view
;
2399 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2401 sview
->is_stencil_sampler
, false);
2404 /* Add all resident image handles. */
2405 for (i
= 0; i
< num_resident_img_handles
; i
++) {
2406 struct si_image_handle
*img_handle
=
2407 *util_dynarray_element(&sctx
->resident_img_handles
,
2408 struct si_image_handle
*, i
);
2409 struct pipe_image_view
*view
= &img_handle
->view
;
2411 si_sampler_view_add_buffer(sctx
, view
->resource
,
2412 RADEON_USAGE_READWRITE
,
2417 /* INIT/DEINIT/UPLOAD */
2419 /* GFX9 has only 4KB of CE, while previous chips had 32KB. In order
2420 * to make CE RAM as useful as possible, this defines limits
2421 * for the number slots that can be in CE RAM on GFX9. If a shader
2422 * is using more, descriptors will be uploaded to memory directly and
2425 * These numbers are based on shader-db.
2427 static unsigned gfx9_max_ce_samplers
[SI_NUM_SHADERS
] = {
2428 [PIPE_SHADER_VERTEX
] = 0,
2429 [PIPE_SHADER_TESS_CTRL
] = 0,
2430 [PIPE_SHADER_TESS_EVAL
] = 1,
2431 [PIPE_SHADER_GEOMETRY
] = 0,
2432 [PIPE_SHADER_FRAGMENT
] = 24,
2433 [PIPE_SHADER_COMPUTE
] = 16,
2435 static unsigned gfx9_max_ce_images
[SI_NUM_SHADERS
] = {
2436 /* these must be even due to slot alignment */
2437 [PIPE_SHADER_VERTEX
] = 0,
2438 [PIPE_SHADER_TESS_CTRL
] = 0,
2439 [PIPE_SHADER_TESS_EVAL
] = 0,
2440 [PIPE_SHADER_GEOMETRY
] = 0,
2441 [PIPE_SHADER_FRAGMENT
] = 2,
2442 [PIPE_SHADER_COMPUTE
] = 8,
2444 static unsigned gfx9_max_ce_const_buffers
[SI_NUM_SHADERS
] = {
2445 [PIPE_SHADER_VERTEX
] = 9,
2446 [PIPE_SHADER_TESS_CTRL
] = 3,
2447 [PIPE_SHADER_TESS_EVAL
] = 5,
2448 [PIPE_SHADER_GEOMETRY
] = 0,
2449 [PIPE_SHADER_FRAGMENT
] = 8,
2450 [PIPE_SHADER_COMPUTE
] = 6,
2452 static unsigned gfx9_max_ce_shader_buffers
[SI_NUM_SHADERS
] = {
2453 [PIPE_SHADER_VERTEX
] = 0,
2454 [PIPE_SHADER_TESS_CTRL
] = 0,
2455 [PIPE_SHADER_TESS_EVAL
] = 0,
2456 [PIPE_SHADER_GEOMETRY
] = 0,
2457 [PIPE_SHADER_FRAGMENT
] = 12,
2458 [PIPE_SHADER_COMPUTE
] = 13,
2461 void si_init_all_descriptors(struct si_context
*sctx
)
2464 unsigned ce_offset
= 0;
2466 STATIC_ASSERT(GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS
% 2 == 0);
2467 STATIC_ASSERT(GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS
% 2 == 0);
2469 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2470 bool gfx9_tcs
= false;
2471 bool gfx9_gs
= false;
2472 unsigned num_sampler_slots
= SI_NUM_IMAGES
/ 2 + SI_NUM_SAMPLERS
;
2473 unsigned num_buffer_slots
= SI_NUM_SHADER_BUFFERS
+ SI_NUM_CONST_BUFFERS
;
2475 unsigned first_sampler_ce_slot
= 0;
2476 unsigned num_sampler_ce_slots
= num_sampler_slots
;
2478 unsigned first_buffer_ce_slot
= 0;
2479 unsigned num_buffer_ce_slots
= num_buffer_slots
;
2481 /* Adjust CE slot ranges based on GFX9 CE RAM limits. */
2482 if (sctx
->b
.chip_class
>= GFX9
) {
2483 gfx9_tcs
= i
== PIPE_SHADER_TESS_CTRL
;
2484 gfx9_gs
= i
== PIPE_SHADER_GEOMETRY
;
2486 first_sampler_ce_slot
=
2487 si_get_image_slot(gfx9_max_ce_images
[i
] - 1) / 2;
2488 num_sampler_ce_slots
= gfx9_max_ce_images
[i
] / 2 +
2489 gfx9_max_ce_samplers
[i
];
2491 first_buffer_ce_slot
=
2492 si_get_shaderbuf_slot(gfx9_max_ce_shader_buffers
[i
] - 1);
2493 num_buffer_ce_slots
= gfx9_max_ce_shader_buffers
[i
] +
2494 gfx9_max_ce_const_buffers
[i
];
2497 si_init_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[i
],
2498 si_const_and_shader_buffer_descriptors(sctx
, i
),
2500 first_buffer_ce_slot
, num_buffer_ce_slots
,
2501 gfx9_tcs
? GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS
:
2502 gfx9_gs
? GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS
:
2503 SI_SGPR_CONST_AND_SHADER_BUFFERS
,
2504 RADEON_USAGE_READWRITE
,
2506 RADEON_PRIO_SHADER_RW_BUFFER
,
2507 RADEON_PRIO_CONST_BUFFER
,
2510 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, i
);
2511 si_init_descriptors(sctx
, desc
,
2512 gfx9_tcs
? GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES
:
2513 gfx9_gs
? GFX9_SGPR_GS_SAMPLERS_AND_IMAGES
:
2514 SI_SGPR_SAMPLERS_AND_IMAGES
,
2515 16, num_sampler_slots
,
2516 first_sampler_ce_slot
, num_sampler_ce_slots
,
2520 for (j
= 0; j
< SI_NUM_IMAGES
; j
++)
2521 memcpy(desc
->list
+ j
* 8, null_image_descriptor
, 8 * 4);
2522 for (; j
< SI_NUM_IMAGES
+ SI_NUM_SAMPLERS
* 2; j
++)
2523 memcpy(desc
->list
+ j
* 8, null_texture_descriptor
, 8 * 4);
2526 si_init_buffer_resources(sctx
, &sctx
->rw_buffers
,
2527 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
2528 SI_NUM_RW_BUFFERS
, 0, SI_NUM_RW_BUFFERS
,
2530 /* The second set of usage/priority is used by
2531 * const buffers in RW buffer slots. */
2532 RADEON_USAGE_READWRITE
, RADEON_USAGE_READ
,
2533 RADEON_PRIO_SHADER_RINGS
, RADEON_PRIO_CONST_BUFFER
,
2535 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
= SI_NUM_RW_BUFFERS
;
2537 si_init_descriptors(sctx
, &sctx
->vertex_buffers
, SI_SGPR_VERTEX_BUFFERS
,
2538 4, SI_NUM_VERTEX_BUFFERS
, 0, 0, NULL
);
2540 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2541 sctx
->total_ce_ram_allocated
= ce_offset
;
2543 if (sctx
->b
.chip_class
>= GFX9
)
2544 assert(ce_offset
<= 4096);
2546 assert(ce_offset
<= 32768);
2548 /* Set pipe_context functions. */
2549 sctx
->b
.b
.bind_sampler_states
= si_bind_sampler_states
;
2550 sctx
->b
.b
.set_shader_images
= si_set_shader_images
;
2551 sctx
->b
.b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
2552 sctx
->b
.b
.set_polygon_stipple
= si_set_polygon_stipple
;
2553 sctx
->b
.b
.set_shader_buffers
= si_set_shader_buffers
;
2554 sctx
->b
.b
.set_sampler_views
= si_set_sampler_views
;
2555 sctx
->b
.b
.set_stream_output_targets
= si_set_streamout_targets
;
2556 sctx
->b
.b
.create_texture_handle
= si_create_texture_handle
;
2557 sctx
->b
.b
.delete_texture_handle
= si_delete_texture_handle
;
2558 sctx
->b
.b
.make_texture_handle_resident
= si_make_texture_handle_resident
;
2559 sctx
->b
.b
.create_image_handle
= si_create_image_handle
;
2560 sctx
->b
.b
.delete_image_handle
= si_delete_image_handle
;
2561 sctx
->b
.b
.make_image_handle_resident
= si_make_image_handle_resident
;
2562 sctx
->b
.invalidate_buffer
= si_invalidate_buffer
;
2563 sctx
->b
.rebind_buffer
= si_rebind_buffer
;
2565 /* Shader user data. */
2566 si_init_atom(sctx
, &sctx
->shader_userdata
.atom
, &sctx
->atoms
.s
.shader_userdata
,
2567 si_emit_graphics_shader_userdata
);
2569 /* Set default and immutable mappings. */
2570 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2572 if (sctx
->b
.chip_class
>= GFX9
) {
2573 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2574 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2575 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2576 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2578 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2579 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2580 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2581 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2583 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2586 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
2588 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
2589 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2591 /* Assume nothing will go wrong: */
2592 sctx
->shader_pointers_dirty
|= dirty
;
2595 unsigned i
= u_bit_scan(&dirty
);
2597 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
],
2598 &sctx
->shader_userdata
.atom
))
2602 sctx
->descriptors_dirty
&= ~mask
;
2606 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
2608 /* Does not update rw_buffers as that is not needed for compute shaders
2609 * and the input buffer is using the same SGPR's anyway.
2611 const unsigned mask
= u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
,
2612 SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
2613 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2615 /* Assume nothing will go wrong: */
2616 sctx
->shader_pointers_dirty
|= dirty
;
2619 unsigned i
= u_bit_scan(&dirty
);
2621 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
], NULL
))
2625 sctx
->descriptors_dirty
&= ~mask
;
2630 void si_release_all_descriptors(struct si_context
*sctx
)
2634 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2635 si_release_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2636 si_const_and_shader_buffer_descriptors(sctx
, i
));
2637 si_release_sampler_views(&sctx
->samplers
[i
].views
);
2638 si_release_image_views(&sctx
->images
[i
]);
2640 si_release_buffer_resources(&sctx
->rw_buffers
,
2641 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2643 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2644 si_release_descriptors(&sctx
->descriptors
[i
]);
2645 si_release_descriptors(&sctx
->vertex_buffers
);
2648 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
2652 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2653 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2654 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
].views
);
2655 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
2657 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2658 si_vertex_buffers_begin_new_cs(sctx
);
2660 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2661 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
2663 si_shader_userdata_begin_new_cs(sctx
);
2666 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
2667 uint64_t new_active_mask
)
2669 struct si_descriptors
*desc
= &sctx
->descriptors
[desc_idx
];
2671 /* Ignore no-op updates and updates that disable all slots. */
2672 if (!new_active_mask
||
2673 new_active_mask
== u_bit_consecutive64(desc
->first_active_slot
,
2674 desc
->num_active_slots
))
2678 u_bit_scan_consecutive_range64(&new_active_mask
, &first
, &count
);
2679 assert(new_active_mask
== 0);
2681 /* Upload/dump descriptors if slots are being enabled. */
2682 if (first
< desc
->first_active_slot
||
2683 first
+ count
> desc
->first_active_slot
+ desc
->num_active_slots
)
2684 sctx
->descriptors_dirty
|= 1u << desc_idx
;
2686 /* Enable or disable CE for this descriptor array. */
2687 bool used_ce
= desc
->uses_ce
;
2688 desc
->uses_ce
= desc
->first_ce_slot
<= first
&&
2689 desc
->first_ce_slot
+ desc
->num_ce_slots
>= first
+ count
;
2691 if (desc
->uses_ce
!= used_ce
) {
2692 /* Upload or dump descriptors if we're disabling or enabling CE,
2694 sctx
->descriptors_dirty
|= 1u << desc_idx
;
2696 /* If we're enabling CE, re-upload all descriptors to CE RAM.
2697 * When CE was disabled, uploads to CE RAM stopped.
2699 if (desc
->uses_ce
) {
2701 u_bit_consecutive64(desc
->first_ce_slot
,
2702 desc
->num_ce_slots
);
2706 desc
->first_active_slot
= first
;
2707 desc
->num_active_slots
= count
;
2710 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
2711 struct si_shader_selector
*sel
)
2716 si_set_active_descriptors(sctx
,
2717 si_const_and_shader_buffer_descriptors_idx(sel
->type
),
2718 sel
->active_const_and_shader_buffers
);
2719 si_set_active_descriptors(sctx
,
2720 si_sampler_and_image_descriptors_idx(sel
->type
),
2721 sel
->active_samplers_and_images
);