2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Marek Olšák <marek.olsak@amd.com>
27 /* Resource binding slots and sampler states (each described with 8 or
28 * 4 dwords) are stored in lists in memory which is accessed by shaders
29 * using scalar load instructions.
31 * This file is responsible for managing such lists. It keeps a copy of all
32 * descriptors in CPU memory and re-uploads a whole list if some slots have
35 * This code is also reponsible for updating shader pointers to those lists.
37 * Note that CP DMA can't be used for updating the lists, because a GPU hang
38 * could leave the list in a mid-IB state and the next IB would get wrong
39 * descriptors and the whole context would be unusable at that point.
40 * (Note: The register shadowing can't be used due to the same reason)
42 * Also, uploading descriptors to newly allocated memory doesn't require
46 * Possible scenarios for one 16 dword image+sampler slot:
48 * | Image | w/ FMASK | Buffer | NULL
49 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
50 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
51 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
52 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
54 * FMASK implies MSAA, therefore no sampler state.
55 * Sampler states are never unbound except when FMASK is bound.
58 #include "radeon/r600_cs.h"
63 #include "util/hash_table.h"
64 #include "util/u_idalloc.h"
65 #include "util/u_format.h"
66 #include "util/u_memory.h"
67 #include "util/u_upload_mgr.h"
70 /* NULL image and buffer descriptor for textures (alpha = 1) and images
73 * For images, all fields must be zero except for the swizzle, which
74 * supports arbitrary combinations of 0s and 1s. The texture type must be
75 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
77 * For buffers, all fields must be zero. If they are not, the hw hangs.
79 * This is the only reason why the buffer descriptor must be in words [4:7].
81 static uint32_t null_texture_descriptor
[8] = {
85 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) |
86 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
87 /* the rest must contain zeros, which is also used by the buffer
91 static uint32_t null_image_descriptor
[8] = {
95 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
96 /* the rest must contain zeros, which is also used by the buffer
100 static void si_init_descriptor_list(uint32_t *desc_list
,
101 unsigned element_dw_size
,
102 unsigned num_elements
,
103 const uint32_t *null_descriptor
)
107 /* Initialize the array to NULL descriptors if the element size is 8. */
108 if (null_descriptor
) {
109 assert(element_dw_size
% 8 == 0);
110 for (i
= 0; i
< num_elements
* element_dw_size
/ 8; i
++)
111 memcpy(desc_list
+ i
* 8, null_descriptor
, 8 * 4);
115 static void si_init_descriptors(struct si_descriptors
*desc
,
116 unsigned shader_userdata_index
,
117 unsigned element_dw_size
,
118 unsigned num_elements
)
120 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
121 desc
->element_dw_size
= element_dw_size
;
122 desc
->num_elements
= num_elements
;
123 desc
->shader_userdata_offset
= shader_userdata_index
* 4;
126 static void si_release_descriptors(struct si_descriptors
*desc
)
128 r600_resource_reference(&desc
->buffer
, NULL
);
132 static bool si_upload_descriptors(struct si_context
*sctx
,
133 struct si_descriptors
*desc
,
134 struct r600_atom
* atom
)
136 unsigned slot_size
= desc
->element_dw_size
* 4;
137 unsigned first_slot_offset
= desc
->first_active_slot
* slot_size
;
138 unsigned upload_size
= desc
->num_active_slots
* slot_size
;
140 /* Skip the upload if no shader is using the descriptors. dirty_mask
141 * will stay dirty and the descriptors will be uploaded when there is
142 * a shader using them.
148 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, upload_size
,
149 si_optimal_tcc_alignment(sctx
, upload_size
),
150 (unsigned*)&desc
->buffer_offset
,
151 (struct pipe_resource
**)&desc
->buffer
,
154 return false; /* skip the draw call */
156 util_memcpy_cpu_to_le32(ptr
, (char*)desc
->list
+ first_slot_offset
,
158 desc
->gpu_list
= ptr
- first_slot_offset
/ 4;
160 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
161 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
163 /* The shader pointer should point to slot 0. */
164 desc
->buffer_offset
-= first_slot_offset
;
167 si_mark_atom_dirty(sctx
, atom
);
173 si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
178 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
179 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
185 si_sampler_and_image_descriptors_idx(unsigned shader
)
187 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
188 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
;
191 static struct si_descriptors
*
192 si_sampler_and_image_descriptors(struct si_context
*sctx
, unsigned shader
)
194 return &sctx
->descriptors
[si_sampler_and_image_descriptors_idx(shader
)];
197 static void si_release_sampler_views(struct si_samplers
*samplers
)
201 for (i
= 0; i
< ARRAY_SIZE(samplers
->views
); i
++) {
202 pipe_sampler_view_reference(&samplers
->views
[i
], NULL
);
206 static void si_sampler_view_add_buffer(struct si_context
*sctx
,
207 struct pipe_resource
*resource
,
208 enum radeon_bo_usage usage
,
209 bool is_stencil_sampler
,
212 struct r600_resource
*rres
;
213 struct r600_texture
*rtex
;
214 enum radeon_bo_priority priority
;
219 if (resource
->target
!= PIPE_BUFFER
) {
220 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
222 if (tex
->is_depth
&& !r600_can_sample_zs(tex
, is_stencil_sampler
))
223 resource
= &tex
->flushed_depth_texture
->resource
.b
.b
;
226 rres
= (struct r600_resource
*)resource
;
227 priority
= r600_get_sampler_view_priority(rres
);
229 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
230 rres
, usage
, priority
,
233 if (resource
->target
== PIPE_BUFFER
)
236 /* Now add separate DCC or HTILE. */
237 rtex
= (struct r600_texture
*)resource
;
238 if (rtex
->dcc_separate_buffer
) {
239 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
240 rtex
->dcc_separate_buffer
, usage
,
241 RADEON_PRIO_DCC
, check_mem
);
245 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
,
246 struct si_samplers
*samplers
)
248 unsigned mask
= samplers
->enabled_mask
;
250 /* Add buffers to the CS. */
252 int i
= u_bit_scan(&mask
);
253 struct si_sampler_view
*sview
= (struct si_sampler_view
*)samplers
->views
[i
];
255 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
257 sview
->is_stencil_sampler
, false);
261 /* Set buffer descriptor fields that can be changed by reallocations. */
262 static void si_set_buf_desc_address(struct r600_resource
*buf
,
263 uint64_t offset
, uint32_t *state
)
265 uint64_t va
= buf
->gpu_address
+ offset
;
268 state
[1] &= C_008F04_BASE_ADDRESS_HI
;
269 state
[1] |= S_008F04_BASE_ADDRESS_HI(va
>> 32);
272 /* Set texture descriptor fields that can be changed by reallocations.
275 * \param base_level_info information of the level of BASE_ADDRESS
276 * \param base_level the level of BASE_ADDRESS
277 * \param first_level pipe_sampler_view.u.tex.first_level
278 * \param block_width util_format_get_blockwidth()
279 * \param is_stencil select between separate Z & Stencil
280 * \param state descriptor to update
282 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
283 struct r600_texture
*tex
,
284 const struct legacy_surf_level
*base_level_info
,
285 unsigned base_level
, unsigned first_level
,
286 unsigned block_width
, bool is_stencil
,
289 uint64_t va
, meta_va
= 0;
291 if (tex
->is_depth
&& !r600_can_sample_zs(tex
, is_stencil
)) {
292 tex
= tex
->flushed_depth_texture
;
296 va
= tex
->resource
.gpu_address
;
298 if (sscreen
->b
.chip_class
>= GFX9
) {
299 /* Only stencil_offset needs to be added here. */
301 va
+= tex
->surface
.u
.gfx9
.stencil_offset
;
303 va
+= tex
->surface
.u
.gfx9
.surf_offset
;
305 va
+= base_level_info
->offset
;
309 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
310 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
312 /* Only macrotiled modes can set tile swizzle.
313 * GFX9 doesn't use (legacy) base_level_info.
315 if (sscreen
->b
.chip_class
>= GFX9
||
316 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
317 state
[0] |= tex
->surface
.tile_swizzle
;
319 if (sscreen
->b
.chip_class
>= VI
) {
320 state
[6] &= C_008F28_COMPRESSION_EN
;
323 if (vi_dcc_enabled(tex
, first_level
)) {
324 meta_va
= (!tex
->dcc_separate_buffer
? tex
->resource
.gpu_address
: 0) +
327 if (sscreen
->b
.chip_class
== VI
) {
328 meta_va
+= base_level_info
->dcc_offset
;
329 assert(base_level_info
->mode
== RADEON_SURF_MODE_2D
);
332 meta_va
|= (uint32_t)tex
->surface
.tile_swizzle
<< 8;
333 } else if (vi_tc_compat_htile_enabled(tex
, first_level
)) {
334 meta_va
= tex
->resource
.gpu_address
+ tex
->htile_offset
;
338 state
[6] |= S_008F28_COMPRESSION_EN(1);
339 state
[7] = meta_va
>> 8;
343 if (sscreen
->b
.chip_class
>= GFX9
) {
344 state
[3] &= C_008F1C_SW_MODE
;
345 state
[4] &= C_008F20_PITCH_GFX9
;
348 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
349 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.stencil
.epitch
);
351 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
352 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.surf
.epitch
);
355 state
[5] &= C_008F24_META_DATA_ADDRESS
&
356 C_008F24_META_PIPE_ALIGNED
&
357 C_008F24_META_RB_ALIGNED
;
359 struct gfx9_surf_meta_flags meta
;
362 meta
= tex
->surface
.u
.gfx9
.dcc
;
364 meta
= tex
->surface
.u
.gfx9
.htile
;
366 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
367 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
368 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
372 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
373 unsigned index
= si_tile_mode_index(tex
, base_level
, is_stencil
);
375 state
[3] &= C_008F1C_TILING_INDEX
;
376 state
[3] |= S_008F1C_TILING_INDEX(index
);
377 state
[4] &= C_008F20_PITCH_GFX6
;
378 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
382 static void si_set_sampler_state_desc(struct si_sampler_state
*sstate
,
383 struct si_sampler_view
*sview
,
384 struct r600_texture
*tex
,
387 if (sview
&& sview
->is_integer
)
388 memcpy(desc
, sstate
->integer_val
, 4*4);
389 else if (tex
&& tex
->upgraded_depth
&&
390 (!sview
|| !sview
->is_stencil_sampler
))
391 memcpy(desc
, sstate
->upgraded_depth_val
, 4*4);
393 memcpy(desc
, sstate
->val
, 4*4);
396 static void si_set_sampler_view_desc(struct si_context
*sctx
,
397 struct si_sampler_view
*sview
,
398 struct si_sampler_state
*sstate
,
401 struct pipe_sampler_view
*view
= &sview
->base
;
402 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
403 bool is_buffer
= rtex
->resource
.b
.b
.target
== PIPE_BUFFER
;
405 if (unlikely(!is_buffer
&& sview
->dcc_incompatible
)) {
406 if (vi_dcc_enabled(rtex
, view
->u
.tex
.first_level
))
407 if (!si_texture_disable_dcc(&sctx
->b
, rtex
))
408 sctx
->b
.decompress_dcc(&sctx
->b
.b
, rtex
);
410 sview
->dcc_incompatible
= false;
413 assert(rtex
); /* views with texture == NULL aren't supported */
414 memcpy(desc
, sview
->state
, 8*4);
417 si_set_buf_desc_address(&rtex
->resource
,
418 sview
->base
.u
.buf
.offset
,
421 bool is_separate_stencil
= rtex
->db_compatible
&&
422 sview
->is_stencil_sampler
;
424 si_set_mutable_tex_desc_fields(sctx
->screen
, rtex
,
425 sview
->base_level_info
,
427 sview
->base
.u
.tex
.first_level
,
433 if (!is_buffer
&& rtex
->fmask
.size
) {
434 memcpy(desc
+ 8, sview
->fmask_state
, 8*4);
436 /* Disable FMASK and bind sampler state in [12:15]. */
437 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
440 si_set_sampler_state_desc(sstate
, sview
,
441 is_buffer
? NULL
: rtex
,
446 static bool color_needs_decompression(struct r600_texture
*rtex
)
448 return rtex
->fmask
.size
||
449 (rtex
->dirty_level_mask
&&
450 (rtex
->cmask
.size
|| rtex
->dcc_offset
));
453 static bool depth_needs_decompression(struct r600_texture
*rtex
)
455 /* If the depth/stencil texture is TC-compatible, no decompression
456 * will be done. The decompression function will only flush DB caches
457 * to make it coherent with shaders. That's necessary because the driver
458 * doesn't flush DB caches in any other case.
460 return rtex
->db_compatible
;
463 static void si_set_sampler_view(struct si_context
*sctx
,
465 unsigned slot
, struct pipe_sampler_view
*view
,
466 bool disallow_early_out
)
468 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
469 struct si_sampler_view
*rview
= (struct si_sampler_view
*)view
;
470 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
471 unsigned desc_slot
= si_get_sampler_slot(slot
);
472 uint32_t *desc
= descs
->list
+ desc_slot
* 16;
474 if (samplers
->views
[slot
] == view
&& !disallow_early_out
)
478 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
480 si_set_sampler_view_desc(sctx
, rview
,
481 samplers
->sampler_states
[slot
], desc
);
483 if (rtex
->resource
.b
.b
.target
== PIPE_BUFFER
) {
484 rtex
->resource
.bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
485 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
486 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
488 if (depth_needs_decompression(rtex
)) {
489 samplers
->needs_depth_decompress_mask
|= 1u << slot
;
491 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
493 if (color_needs_decompression(rtex
)) {
494 samplers
->needs_color_decompress_mask
|= 1u << slot
;
496 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
499 if (rtex
->dcc_offset
&&
500 p_atomic_read(&rtex
->framebuffers_bound
))
501 sctx
->need_check_render_feedback
= true;
504 pipe_sampler_view_reference(&samplers
->views
[slot
], view
);
505 samplers
->enabled_mask
|= 1u << slot
;
507 /* Since this can flush, it must be done after enabled_mask is
509 si_sampler_view_add_buffer(sctx
, view
->texture
,
511 rview
->is_stencil_sampler
, true);
513 pipe_sampler_view_reference(&samplers
->views
[slot
], NULL
);
514 memcpy(desc
, null_texture_descriptor
, 8*4);
515 /* Only clear the lower dwords of FMASK. */
516 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
517 /* Re-set the sampler state if we are transitioning from FMASK. */
518 if (samplers
->sampler_states
[slot
])
519 si_set_sampler_state_desc(samplers
->sampler_states
[slot
], NULL
, NULL
,
522 samplers
->enabled_mask
&= ~(1u << slot
);
523 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
524 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
527 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
530 static void si_update_shader_needs_decompress_mask(struct si_context
*sctx
,
533 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
534 unsigned shader_bit
= 1 << shader
;
536 if (samplers
->needs_depth_decompress_mask
||
537 samplers
->needs_color_decompress_mask
||
538 sctx
->images
[shader
].needs_color_decompress_mask
)
539 sctx
->shader_needs_decompress_mask
|= shader_bit
;
541 sctx
->shader_needs_decompress_mask
&= ~shader_bit
;
544 static void si_set_sampler_views(struct pipe_context
*ctx
,
545 enum pipe_shader_type shader
, unsigned start
,
547 struct pipe_sampler_view
**views
)
549 struct si_context
*sctx
= (struct si_context
*)ctx
;
552 if (!count
|| shader
>= SI_NUM_SHADERS
)
556 for (i
= 0; i
< count
; i
++)
557 si_set_sampler_view(sctx
, shader
, start
+ i
, views
[i
], false);
559 for (i
= 0; i
< count
; i
++)
560 si_set_sampler_view(sctx
, shader
, start
+ i
, NULL
, false);
563 si_update_shader_needs_decompress_mask(sctx
, shader
);
567 si_samplers_update_needs_color_decompress_mask(struct si_samplers
*samplers
)
569 unsigned mask
= samplers
->enabled_mask
;
572 int i
= u_bit_scan(&mask
);
573 struct pipe_resource
*res
= samplers
->views
[i
]->texture
;
575 if (res
&& res
->target
!= PIPE_BUFFER
) {
576 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
578 if (color_needs_decompression(rtex
)) {
579 samplers
->needs_color_decompress_mask
|= 1u << i
;
581 samplers
->needs_color_decompress_mask
&= ~(1u << i
);
590 si_release_image_views(struct si_images
*images
)
594 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
595 struct pipe_image_view
*view
= &images
->views
[i
];
597 pipe_resource_reference(&view
->resource
, NULL
);
602 si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images
*images
)
604 uint mask
= images
->enabled_mask
;
606 /* Add buffers to the CS. */
608 int i
= u_bit_scan(&mask
);
609 struct pipe_image_view
*view
= &images
->views
[i
];
611 assert(view
->resource
);
613 si_sampler_view_add_buffer(sctx
, view
->resource
,
614 RADEON_USAGE_READWRITE
, false, false);
619 si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
621 struct si_images
*images
= &ctx
->images
[shader
];
623 if (images
->enabled_mask
& (1u << slot
)) {
624 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
625 unsigned desc_slot
= si_get_image_slot(slot
);
627 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
628 images
->needs_color_decompress_mask
&= ~(1 << slot
);
630 memcpy(descs
->list
+ desc_slot
*8, null_image_descriptor
, 8*4);
631 images
->enabled_mask
&= ~(1u << slot
);
632 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
637 si_mark_image_range_valid(const struct pipe_image_view
*view
)
639 struct r600_resource
*res
= (struct r600_resource
*)view
->resource
;
641 assert(res
&& res
->b
.b
.target
== PIPE_BUFFER
);
643 util_range_add(&res
->valid_buffer_range
,
645 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
648 static void si_set_shader_image_desc(struct si_context
*ctx
,
649 const struct pipe_image_view
*view
,
650 bool skip_decompress
,
653 struct si_screen
*screen
= ctx
->screen
;
654 struct r600_resource
*res
;
656 res
= (struct r600_resource
*)view
->resource
;
658 if (res
->b
.b
.target
== PIPE_BUFFER
) {
659 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
660 si_mark_image_range_valid(view
);
662 si_make_buffer_descriptor(screen
, res
,
665 view
->u
.buf
.size
, desc
);
666 si_set_buf_desc_address(res
, view
->u
.buf
.offset
, desc
+ 4);
668 static const unsigned char swizzle
[4] = { 0, 1, 2, 3 };
669 struct r600_texture
*tex
= (struct r600_texture
*)res
;
670 unsigned level
= view
->u
.tex
.level
;
671 unsigned width
, height
, depth
, hw_level
;
672 bool uses_dcc
= vi_dcc_enabled(tex
, level
);
674 assert(!tex
->is_depth
);
675 assert(tex
->fmask
.size
== 0);
677 if (uses_dcc
&& !skip_decompress
&&
678 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
||
679 !vi_dcc_formats_compatible(res
->b
.b
.format
, view
->format
))) {
680 /* If DCC can't be disabled, at least decompress it.
681 * The decompression is relatively cheap if the surface
682 * has been decompressed already.
684 if (!si_texture_disable_dcc(&ctx
->b
, tex
))
685 ctx
->b
.decompress_dcc(&ctx
->b
.b
, tex
);
688 if (ctx
->b
.chip_class
>= GFX9
) {
689 /* Always set the base address. The swizzle modes don't
690 * allow setting mipmap level offsets as the base.
692 width
= res
->b
.b
.width0
;
693 height
= res
->b
.b
.height0
;
694 depth
= res
->b
.b
.depth0
;
697 /* Always force the base level to the selected level.
699 * This is required for 3D textures, where otherwise
700 * selecting a single slice for non-layered bindings
701 * fails. It doesn't hurt the other targets.
703 width
= u_minify(res
->b
.b
.width0
, level
);
704 height
= u_minify(res
->b
.b
.height0
, level
);
705 depth
= u_minify(res
->b
.b
.depth0
, level
);
709 si_make_texture_descriptor(screen
, tex
,
710 false, res
->b
.b
.target
,
711 view
->format
, swizzle
,
713 view
->u
.tex
.first_layer
,
714 view
->u
.tex
.last_layer
,
715 width
, height
, depth
,
717 si_set_mutable_tex_desc_fields(screen
, tex
,
718 &tex
->surface
.u
.legacy
.level
[level
],
720 util_format_get_blockwidth(view
->format
),
725 static void si_set_shader_image(struct si_context
*ctx
,
727 unsigned slot
, const struct pipe_image_view
*view
,
728 bool skip_decompress
)
730 struct si_images
*images
= &ctx
->images
[shader
];
731 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
732 struct r600_resource
*res
;
733 unsigned desc_slot
= si_get_image_slot(slot
);
734 uint32_t *desc
= descs
->list
+ desc_slot
* 8;
736 if (!view
|| !view
->resource
) {
737 si_disable_shader_image(ctx
, shader
, slot
);
741 res
= (struct r600_resource
*)view
->resource
;
743 if (&images
->views
[slot
] != view
)
744 util_copy_image_view(&images
->views
[slot
], view
);
746 si_set_shader_image_desc(ctx
, view
, skip_decompress
, desc
);
748 if (res
->b
.b
.target
== PIPE_BUFFER
) {
749 images
->needs_color_decompress_mask
&= ~(1 << slot
);
750 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
752 struct r600_texture
*tex
= (struct r600_texture
*)res
;
753 unsigned level
= view
->u
.tex
.level
;
755 if (color_needs_decompression(tex
)) {
756 images
->needs_color_decompress_mask
|= 1 << slot
;
758 images
->needs_color_decompress_mask
&= ~(1 << slot
);
761 if (vi_dcc_enabled(tex
, level
) &&
762 p_atomic_read(&tex
->framebuffers_bound
))
763 ctx
->need_check_render_feedback
= true;
766 images
->enabled_mask
|= 1u << slot
;
767 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
769 /* Since this can flush, it must be done after enabled_mask is updated. */
770 si_sampler_view_add_buffer(ctx
, &res
->b
.b
,
771 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
) ?
772 RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
,
777 si_set_shader_images(struct pipe_context
*pipe
,
778 enum pipe_shader_type shader
,
779 unsigned start_slot
, unsigned count
,
780 const struct pipe_image_view
*views
)
782 struct si_context
*ctx
= (struct si_context
*)pipe
;
785 assert(shader
< SI_NUM_SHADERS
);
790 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
793 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
794 si_set_shader_image(ctx
, shader
, slot
, &views
[i
], false);
796 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
797 si_set_shader_image(ctx
, shader
, slot
, NULL
, false);
800 si_update_shader_needs_decompress_mask(ctx
, shader
);
804 si_images_update_needs_color_decompress_mask(struct si_images
*images
)
806 unsigned mask
= images
->enabled_mask
;
809 int i
= u_bit_scan(&mask
);
810 struct pipe_resource
*res
= images
->views
[i
].resource
;
812 if (res
&& res
->target
!= PIPE_BUFFER
) {
813 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
815 if (color_needs_decompression(rtex
)) {
816 images
->needs_color_decompress_mask
|= 1 << i
;
818 images
->needs_color_decompress_mask
&= ~(1 << i
);
826 static void si_bind_sampler_states(struct pipe_context
*ctx
,
827 enum pipe_shader_type shader
,
828 unsigned start
, unsigned count
, void **states
)
830 struct si_context
*sctx
= (struct si_context
*)ctx
;
831 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
832 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, shader
);
833 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
836 if (!count
|| shader
>= SI_NUM_SHADERS
)
839 for (i
= 0; i
< count
; i
++) {
840 unsigned slot
= start
+ i
;
841 unsigned desc_slot
= si_get_sampler_slot(slot
);
844 sstates
[i
] == samplers
->sampler_states
[slot
])
848 assert(sstates
[i
]->magic
== SI_SAMPLER_STATE_MAGIC
);
850 samplers
->sampler_states
[slot
] = sstates
[i
];
852 /* If FMASK is bound, don't overwrite it.
853 * The sampler state will be set after FMASK is unbound.
855 struct si_sampler_view
*sview
=
856 (struct si_sampler_view
*)samplers
->views
[slot
];
858 struct r600_texture
*tex
= NULL
;
860 if (sview
&& sview
->base
.texture
&&
861 sview
->base
.texture
->target
!= PIPE_BUFFER
)
862 tex
= (struct r600_texture
*)sview
->base
.texture
;
864 if (tex
&& tex
->fmask
.size
)
867 si_set_sampler_state_desc(sstates
[i
], sview
, tex
,
868 desc
->list
+ desc_slot
* 16 + 12);
870 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
874 /* BUFFER RESOURCES */
876 static void si_init_buffer_resources(struct si_buffer_resources
*buffers
,
877 struct si_descriptors
*descs
,
878 unsigned num_buffers
,
879 unsigned shader_userdata_index
,
880 enum radeon_bo_usage shader_usage
,
881 enum radeon_bo_usage shader_usage_constbuf
,
882 enum radeon_bo_priority priority
,
883 enum radeon_bo_priority priority_constbuf
)
885 buffers
->shader_usage
= shader_usage
;
886 buffers
->shader_usage_constbuf
= shader_usage_constbuf
;
887 buffers
->priority
= priority
;
888 buffers
->priority_constbuf
= priority_constbuf
;
889 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
891 si_init_descriptors(descs
, shader_userdata_index
, 4, num_buffers
);
894 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
895 struct si_descriptors
*descs
)
899 for (i
= 0; i
< descs
->num_elements
; i
++) {
900 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
903 FREE(buffers
->buffers
);
906 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
907 struct si_buffer_resources
*buffers
)
909 unsigned mask
= buffers
->enabled_mask
;
911 /* Add buffers to the CS. */
913 int i
= u_bit_scan(&mask
);
915 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
916 r600_resource(buffers
->buffers
[i
]),
917 i
< SI_NUM_SHADER_BUFFERS
? buffers
->shader_usage
:
918 buffers
->shader_usage_constbuf
,
919 i
< SI_NUM_SHADER_BUFFERS
? buffers
->priority
:
920 buffers
->priority_constbuf
);
924 static void si_get_buffer_from_descriptors(struct si_buffer_resources
*buffers
,
925 struct si_descriptors
*descs
,
926 unsigned idx
, struct pipe_resource
**buf
,
927 unsigned *offset
, unsigned *size
)
929 pipe_resource_reference(buf
, buffers
->buffers
[idx
]);
931 struct r600_resource
*res
= r600_resource(*buf
);
932 const uint32_t *desc
= descs
->list
+ idx
* 4;
937 assert(G_008F04_STRIDE(desc
[1]) == 0);
938 va
= ((uint64_t)desc
[1] << 32) | desc
[0];
940 assert(va
>= res
->gpu_address
&& va
+ *size
<= res
->gpu_address
+ res
->bo_size
);
941 *offset
= va
- res
->gpu_address
;
947 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
949 struct si_descriptors
*desc
= &sctx
->vertex_buffers
;
950 int count
= sctx
->vertex_elements
? sctx
->vertex_elements
->count
: 0;
953 for (i
= 0; i
< count
; i
++) {
954 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
956 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
958 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
961 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
962 (struct r600_resource
*)sctx
->vertex_buffer
[vb
].buffer
.resource
,
963 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
968 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
969 desc
->buffer
, RADEON_USAGE_READ
,
970 RADEON_PRIO_DESCRIPTORS
);
973 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
975 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
976 struct si_descriptors
*desc
= &sctx
->vertex_buffers
;
978 unsigned desc_list_byte_size
;
979 unsigned first_vb_use_mask
;
983 if (!sctx
->vertex_buffers_dirty
|| !velems
)
986 count
= velems
->count
;
991 desc_list_byte_size
= velems
->desc_list_byte_size
;
992 first_vb_use_mask
= velems
->first_vb_use_mask
;
994 /* Vertex buffer descriptors are the only ones which are uploaded
995 * directly through a staging buffer and don't go through
996 * the fine-grained upload path.
998 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0,
1000 si_optimal_tcc_alignment(sctx
, desc_list_byte_size
),
1001 (unsigned*)&desc
->buffer_offset
,
1002 (struct pipe_resource
**)&desc
->buffer
, (void**)&ptr
);
1007 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1008 desc
->buffer
, RADEON_USAGE_READ
,
1009 RADEON_PRIO_DESCRIPTORS
);
1011 assert(count
<= SI_MAX_ATTRIBS
);
1013 for (i
= 0; i
< count
; i
++) {
1014 struct pipe_vertex_buffer
*vb
;
1015 struct r600_resource
*rbuffer
;
1017 unsigned vbo_index
= velems
->vertex_buffer_index
[i
];
1018 uint32_t *desc
= &ptr
[i
*4];
1020 vb
= &sctx
->vertex_buffer
[vbo_index
];
1021 rbuffer
= (struct r600_resource
*)vb
->buffer
.resource
;
1023 memset(desc
, 0, 16);
1027 offset
= vb
->buffer_offset
+ velems
->src_offset
[i
];
1028 va
= rbuffer
->gpu_address
+ offset
;
1030 /* Fill in T# buffer resource description */
1032 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1033 S_008F04_STRIDE(vb
->stride
);
1035 if (sctx
->b
.chip_class
!= VI
&& vb
->stride
) {
1036 /* Round up by rounding down and adding 1 */
1037 desc
[2] = (vb
->buffer
.resource
->width0
- offset
-
1038 velems
->format_size
[i
]) /
1041 desc
[2] = vb
->buffer
.resource
->width0
- offset
;
1044 desc
[3] = velems
->rsrc_word3
[i
];
1046 if (first_vb_use_mask
& (1 << i
)) {
1047 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1048 (struct r600_resource
*)vb
->buffer
.resource
,
1049 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1053 /* Don't flush the const cache. It would have a very negative effect
1054 * on performance (confirmed by testing). New descriptors are always
1055 * uploaded to a fresh new buffer, so I don't think flushing the const
1056 * cache is needed. */
1057 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1058 sctx
->vertex_buffers_dirty
= false;
1059 sctx
->vertex_buffer_pointer_dirty
= true;
1060 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VBO_DESCRIPTORS
;
1065 /* CONSTANT BUFFERS */
1068 si_const_and_shader_buffer_descriptors_idx(unsigned shader
)
1070 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
1071 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
;
1074 static struct si_descriptors
*
1075 si_const_and_shader_buffer_descriptors(struct si_context
*sctx
, unsigned shader
)
1077 return &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(shader
)];
1080 void si_upload_const_buffer(struct si_context
*sctx
, struct r600_resource
**rbuffer
,
1081 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
)
1085 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, size
,
1086 si_optimal_tcc_alignment(sctx
, size
),
1088 (struct pipe_resource
**)rbuffer
, &tmp
);
1090 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
1093 static void si_set_constant_buffer(struct si_context
*sctx
,
1094 struct si_buffer_resources
*buffers
,
1095 unsigned descriptors_idx
,
1096 uint slot
, const struct pipe_constant_buffer
*input
)
1098 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1099 assert(slot
< descs
->num_elements
);
1100 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1102 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1103 * with a NULL buffer). We need to use a dummy buffer instead. */
1104 if (sctx
->b
.chip_class
== CIK
&&
1105 (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
1106 input
= &sctx
->null_const_buf
;
1108 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1109 struct pipe_resource
*buffer
= NULL
;
1112 /* Upload the user buffer if needed. */
1113 if (input
->user_buffer
) {
1114 unsigned buffer_offset
;
1116 si_upload_const_buffer(sctx
,
1117 (struct r600_resource
**)&buffer
, input
->user_buffer
,
1118 input
->buffer_size
, &buffer_offset
);
1120 /* Just unbind on failure. */
1121 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1124 va
= r600_resource(buffer
)->gpu_address
+ buffer_offset
;
1126 pipe_resource_reference(&buffer
, input
->buffer
);
1127 va
= r600_resource(buffer
)->gpu_address
+ input
->buffer_offset
;
1128 /* Only track usage for non-user buffers. */
1129 r600_resource(buffer
)->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
1132 /* Set the descriptor. */
1133 uint32_t *desc
= descs
->list
+ slot
*4;
1135 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1137 desc
[2] = input
->buffer_size
;
1138 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1139 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1140 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1141 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1142 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1143 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1145 buffers
->buffers
[slot
] = buffer
;
1146 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1147 (struct r600_resource
*)buffer
,
1148 buffers
->shader_usage_constbuf
,
1149 buffers
->priority_constbuf
, true);
1150 buffers
->enabled_mask
|= 1u << slot
;
1152 /* Clear the descriptor. */
1153 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1154 buffers
->enabled_mask
&= ~(1u << slot
);
1157 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1160 void si_set_rw_buffer(struct si_context
*sctx
,
1161 uint slot
, const struct pipe_constant_buffer
*input
)
1163 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
,
1164 SI_DESCS_RW_BUFFERS
, slot
, input
);
1167 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
,
1168 enum pipe_shader_type shader
, uint slot
,
1169 const struct pipe_constant_buffer
*input
)
1171 struct si_context
*sctx
= (struct si_context
*)ctx
;
1173 if (shader
>= SI_NUM_SHADERS
)
1176 slot
= si_get_constbuf_slot(slot
);
1177 si_set_constant_buffer(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1178 si_const_and_shader_buffer_descriptors_idx(shader
),
1182 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
1183 uint slot
, struct pipe_constant_buffer
*cbuf
)
1185 cbuf
->user_buffer
= NULL
;
1186 si_get_buffer_from_descriptors(
1187 &sctx
->const_and_shader_buffers
[shader
],
1188 si_const_and_shader_buffer_descriptors(sctx
, shader
),
1189 si_get_constbuf_slot(slot
),
1190 &cbuf
->buffer
, &cbuf
->buffer_offset
, &cbuf
->buffer_size
);
1193 /* SHADER BUFFERS */
1195 static void si_set_shader_buffers(struct pipe_context
*ctx
,
1196 enum pipe_shader_type shader
,
1197 unsigned start_slot
, unsigned count
,
1198 const struct pipe_shader_buffer
*sbuffers
)
1200 struct si_context
*sctx
= (struct si_context
*)ctx
;
1201 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1202 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1205 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1207 for (i
= 0; i
< count
; ++i
) {
1208 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1209 struct r600_resource
*buf
;
1210 unsigned slot
= si_get_shaderbuf_slot(start_slot
+ i
);
1211 uint32_t *desc
= descs
->list
+ slot
* 4;
1214 if (!sbuffer
|| !sbuffer
->buffer
) {
1215 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1216 memset(desc
, 0, sizeof(uint32_t) * 4);
1217 buffers
->enabled_mask
&= ~(1u << slot
);
1218 sctx
->descriptors_dirty
|=
1219 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1223 buf
= (struct r600_resource
*)sbuffer
->buffer
;
1224 va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1227 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1229 desc
[2] = sbuffer
->buffer_size
;
1230 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1231 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1232 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1233 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1234 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1235 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1237 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1238 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
, buf
,
1239 buffers
->shader_usage
,
1240 buffers
->priority
, true);
1241 buf
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1243 buffers
->enabled_mask
|= 1u << slot
;
1244 sctx
->descriptors_dirty
|=
1245 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1247 util_range_add(&buf
->valid_buffer_range
, sbuffer
->buffer_offset
,
1248 sbuffer
->buffer_offset
+ sbuffer
->buffer_size
);
1252 void si_get_shader_buffers(struct si_context
*sctx
,
1253 enum pipe_shader_type shader
,
1254 uint start_slot
, uint count
,
1255 struct pipe_shader_buffer
*sbuf
)
1257 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1258 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1260 for (unsigned i
= 0; i
< count
; ++i
) {
1261 si_get_buffer_from_descriptors(
1263 si_get_shaderbuf_slot(start_slot
+ i
),
1264 &sbuf
[i
].buffer
, &sbuf
[i
].buffer_offset
,
1265 &sbuf
[i
].buffer_size
);
1271 void si_set_ring_buffer(struct pipe_context
*ctx
, uint slot
,
1272 struct pipe_resource
*buffer
,
1273 unsigned stride
, unsigned num_records
,
1274 bool add_tid
, bool swizzle
,
1275 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1277 struct si_context
*sctx
= (struct si_context
*)ctx
;
1278 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1279 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1281 /* The stride field in the resource descriptor has 14 bits */
1282 assert(stride
< (1 << 14));
1284 assert(slot
< descs
->num_elements
);
1285 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1290 va
= r600_resource(buffer
)->gpu_address
+ offset
;
1292 switch (element_size
) {
1294 assert(!"Unsupported ring buffer element size");
1310 switch (index_stride
) {
1312 assert(!"Unsupported ring buffer index stride");
1328 if (sctx
->b
.chip_class
>= VI
&& stride
)
1329 num_records
*= stride
;
1331 /* Set the descriptor. */
1332 uint32_t *desc
= descs
->list
+ slot
*4;
1334 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1335 S_008F04_STRIDE(stride
) |
1336 S_008F04_SWIZZLE_ENABLE(swizzle
);
1337 desc
[2] = num_records
;
1338 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1339 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1340 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1341 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1342 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1343 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1344 S_008F0C_INDEX_STRIDE(index_stride
) |
1345 S_008F0C_ADD_TID_ENABLE(add_tid
);
1347 if (sctx
->b
.chip_class
>= GFX9
)
1348 assert(!swizzle
|| element_size
== 1); /* always 4 bytes on GFX9 */
1350 desc
[3] |= S_008F0C_ELEMENT_SIZE(element_size
);
1352 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1353 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1354 (struct r600_resource
*)buffer
,
1355 buffers
->shader_usage
, buffers
->priority
);
1356 buffers
->enabled_mask
|= 1u << slot
;
1358 /* Clear the descriptor. */
1359 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1360 buffers
->enabled_mask
&= ~(1u << slot
);
1363 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1366 static void si_desc_reset_buffer_offset(struct pipe_context
*ctx
,
1367 uint32_t *desc
, uint64_t old_buf_va
,
1368 struct pipe_resource
*new_buf
)
1370 /* Retrieve the buffer offset from the descriptor. */
1371 uint64_t old_desc_va
=
1372 desc
[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
1374 assert(old_buf_va
<= old_desc_va
);
1375 uint64_t offset_within_buffer
= old_desc_va
- old_buf_va
;
1377 /* Update the descriptor. */
1378 si_set_buf_desc_address(r600_resource(new_buf
), offset_within_buffer
,
1382 /* INTERNAL CONST BUFFERS */
1384 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
1385 const struct pipe_poly_stipple
*state
)
1387 struct si_context
*sctx
= (struct si_context
*)ctx
;
1388 struct pipe_constant_buffer cb
= {};
1389 unsigned stipple
[32];
1392 for (i
= 0; i
< 32; i
++)
1393 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1395 cb
.user_buffer
= stipple
;
1396 cb
.buffer_size
= sizeof(stipple
);
1398 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1401 /* TEXTURE METADATA ENABLE/DISABLE */
1404 si_resident_handles_update_needs_color_decompress(struct si_context
*sctx
)
1406 util_dynarray_clear(&sctx
->resident_tex_needs_color_decompress
);
1407 util_dynarray_clear(&sctx
->resident_img_needs_color_decompress
);
1409 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1410 struct si_texture_handle
*, tex_handle
) {
1411 struct pipe_resource
*res
= (*tex_handle
)->view
->texture
;
1412 struct r600_texture
*rtex
;
1414 if (!res
|| res
->target
== PIPE_BUFFER
)
1417 rtex
= (struct r600_texture
*)res
;
1418 if (!color_needs_decompression(rtex
))
1421 util_dynarray_append(&sctx
->resident_tex_needs_color_decompress
,
1422 struct si_texture_handle
*, *tex_handle
);
1425 util_dynarray_foreach(&sctx
->resident_img_handles
,
1426 struct si_image_handle
*, img_handle
) {
1427 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1428 struct pipe_resource
*res
= view
->resource
;
1429 struct r600_texture
*rtex
;
1431 if (!res
|| res
->target
== PIPE_BUFFER
)
1434 rtex
= (struct r600_texture
*)res
;
1435 if (!color_needs_decompression(rtex
))
1438 util_dynarray_append(&sctx
->resident_img_needs_color_decompress
,
1439 struct si_image_handle
*, *img_handle
);
1443 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1444 * while the texture is bound, possibly by a different context. In that case,
1445 * call this function to update needs_*_decompress_masks.
1447 void si_update_needs_color_decompress_masks(struct si_context
*sctx
)
1449 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1450 si_samplers_update_needs_color_decompress_mask(&sctx
->samplers
[i
]);
1451 si_images_update_needs_color_decompress_mask(&sctx
->images
[i
]);
1452 si_update_shader_needs_decompress_mask(sctx
, i
);
1455 si_resident_handles_update_needs_color_decompress(sctx
);
1458 /* BUFFER DISCARD/INVALIDATION */
1460 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1461 static void si_reset_buffer_resources(struct si_context
*sctx
,
1462 struct si_buffer_resources
*buffers
,
1463 unsigned descriptors_idx
,
1465 struct pipe_resource
*buf
,
1467 enum radeon_bo_usage usage
,
1468 enum radeon_bo_priority priority
)
1470 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1471 unsigned mask
= buffers
->enabled_mask
& slot_mask
;
1474 unsigned i
= u_bit_scan(&mask
);
1475 if (buffers
->buffers
[i
] == buf
) {
1476 si_desc_reset_buffer_offset(&sctx
->b
.b
,
1479 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1481 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1482 (struct r600_resource
*)buf
,
1483 usage
, priority
, true);
1488 static void si_rebind_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
,
1491 struct si_context
*sctx
= (struct si_context
*)ctx
;
1492 struct r600_resource
*rbuffer
= r600_resource(buf
);
1494 unsigned num_elems
= sctx
->vertex_elements
?
1495 sctx
->vertex_elements
->count
: 0;
1497 /* We changed the buffer, now we need to bind it where the old one
1498 * was bound. This consists of 2 things:
1499 * 1) Updating the resource descriptor and dirtying it.
1500 * 2) Adding a relocation to the CS, so that it's usable.
1503 /* Vertex buffers. */
1504 if (rbuffer
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
1505 for (i
= 0; i
< num_elems
; i
++) {
1506 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1508 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1510 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1513 if (sctx
->vertex_buffer
[vb
].buffer
.resource
== buf
) {
1514 sctx
->vertex_buffers_dirty
= true;
1520 /* Streamout buffers. (other internal buffers can't be invalidated) */
1521 if (rbuffer
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
1522 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1523 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1524 struct si_descriptors
*descs
=
1525 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1527 if (buffers
->buffers
[i
] != buf
)
1530 si_desc_reset_buffer_offset(ctx
, descs
->list
+ i
*4,
1532 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1534 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1535 rbuffer
, buffers
->shader_usage
,
1536 RADEON_PRIO_SHADER_RW_BUFFER
,
1539 /* Update the streamout state. */
1540 if (sctx
->streamout
.begin_emitted
)
1541 si_emit_streamout_end(sctx
);
1542 sctx
->streamout
.append_bitmask
=
1543 sctx
->streamout
.enabled_mask
;
1544 si_streamout_buffers_dirty(sctx
);
1548 /* Constant and shader buffers. */
1549 if (rbuffer
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1550 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1551 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1552 si_const_and_shader_buffer_descriptors_idx(shader
),
1553 u_bit_consecutive(SI_NUM_SHADER_BUFFERS
, SI_NUM_CONST_BUFFERS
),
1555 sctx
->const_and_shader_buffers
[shader
].shader_usage_constbuf
,
1556 sctx
->const_and_shader_buffers
[shader
].priority_constbuf
);
1559 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
1560 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1561 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1562 si_const_and_shader_buffer_descriptors_idx(shader
),
1563 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
),
1565 sctx
->const_and_shader_buffers
[shader
].shader_usage
,
1566 sctx
->const_and_shader_buffers
[shader
].priority
);
1569 if (rbuffer
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
1570 /* Texture buffers - update bindings. */
1571 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1572 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1573 struct si_descriptors
*descs
=
1574 si_sampler_and_image_descriptors(sctx
, shader
);
1575 unsigned mask
= samplers
->enabled_mask
;
1578 unsigned i
= u_bit_scan(&mask
);
1579 if (samplers
->views
[i
]->texture
== buf
) {
1580 unsigned desc_slot
= si_get_sampler_slot(i
);
1582 si_desc_reset_buffer_offset(ctx
,
1586 sctx
->descriptors_dirty
|=
1587 1u << si_sampler_and_image_descriptors_idx(shader
);
1589 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1590 rbuffer
, RADEON_USAGE_READ
,
1591 RADEON_PRIO_SAMPLER_BUFFER
,
1599 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
1600 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1601 struct si_images
*images
= &sctx
->images
[shader
];
1602 struct si_descriptors
*descs
=
1603 si_sampler_and_image_descriptors(sctx
, shader
);
1604 unsigned mask
= images
->enabled_mask
;
1607 unsigned i
= u_bit_scan(&mask
);
1609 if (images
->views
[i
].resource
== buf
) {
1610 unsigned desc_slot
= si_get_image_slot(i
);
1612 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1613 si_mark_image_range_valid(&images
->views
[i
]);
1615 si_desc_reset_buffer_offset(
1616 ctx
, descs
->list
+ desc_slot
* 8 + 4,
1618 sctx
->descriptors_dirty
|=
1619 1u << si_sampler_and_image_descriptors_idx(shader
);
1621 radeon_add_to_buffer_list_check_mem(
1622 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1623 RADEON_USAGE_READWRITE
,
1624 RADEON_PRIO_SAMPLER_BUFFER
, true);
1630 /* Bindless texture handles */
1631 if (rbuffer
->texture_handle_allocated
) {
1632 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1634 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1635 struct si_texture_handle
*, tex_handle
) {
1636 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
1637 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1639 if (view
->texture
== buf
) {
1640 si_set_buf_desc_address(rbuffer
,
1643 desc_slot
* 16 + 4);
1645 (*tex_handle
)->desc_dirty
= true;
1646 sctx
->bindless_descriptors_dirty
= true;
1648 radeon_add_to_buffer_list_check_mem(
1649 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1651 RADEON_PRIO_SAMPLER_BUFFER
, true);
1656 /* Bindless image handles */
1657 if (rbuffer
->image_handle_allocated
) {
1658 struct si_descriptors
*descs
= &sctx
->bindless_descriptors
;
1660 util_dynarray_foreach(&sctx
->resident_img_handles
,
1661 struct si_image_handle
*, img_handle
) {
1662 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1663 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1665 if (view
->resource
== buf
) {
1666 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
1667 si_mark_image_range_valid(view
);
1669 si_set_buf_desc_address(rbuffer
,
1672 desc_slot
* 16 + 4);
1674 (*img_handle
)->desc_dirty
= true;
1675 sctx
->bindless_descriptors_dirty
= true;
1677 radeon_add_to_buffer_list_check_mem(
1678 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1679 RADEON_USAGE_READWRITE
,
1680 RADEON_PRIO_SAMPLER_BUFFER
, true);
1686 /* Reallocate a buffer a update all resource bindings where the buffer is
1689 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
1690 * idle by discarding its contents. Apps usually tell us when to do this using
1691 * map_buffer flags, for example.
1693 static void si_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
1695 struct si_context
*sctx
= (struct si_context
*)ctx
;
1696 struct r600_resource
*rbuffer
= r600_resource(buf
);
1697 uint64_t old_va
= rbuffer
->gpu_address
;
1699 /* Reallocate the buffer in the same pipe_resource. */
1700 si_alloc_resource(&sctx
->screen
->b
, rbuffer
);
1702 si_rebind_buffer(ctx
, buf
, old_va
);
1705 static void si_upload_bindless_descriptor(struct si_context
*sctx
,
1707 unsigned num_dwords
)
1709 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1710 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1711 unsigned desc_slot_offset
= desc_slot
* 16;
1715 data
= desc
->list
+ desc_slot_offset
;
1717 va
= desc
->buffer
->gpu_address
+ desc
->buffer_offset
+
1718 desc_slot_offset
* 4;
1720 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + num_dwords
, 0));
1721 radeon_emit(cs
, S_370_DST_SEL(V_370_TC_L2
) |
1722 S_370_WR_CONFIRM(1) |
1723 S_370_ENGINE_SEL(V_370_ME
));
1724 radeon_emit(cs
, va
);
1725 radeon_emit(cs
, va
>> 32);
1726 radeon_emit_array(cs
, data
, num_dwords
);
1729 static void si_upload_bindless_descriptors(struct si_context
*sctx
)
1731 if (!sctx
->bindless_descriptors_dirty
)
1734 /* Wait for graphics/compute to be idle before updating the resident
1735 * descriptors directly in memory, in case the GPU is using them.
1737 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
1738 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1739 si_emit_cache_flush(sctx
);
1741 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1742 struct si_texture_handle
*, tex_handle
) {
1743 unsigned desc_slot
= (*tex_handle
)->desc_slot
;
1745 if (!(*tex_handle
)->desc_dirty
)
1748 si_upload_bindless_descriptor(sctx
, desc_slot
, 16);
1749 (*tex_handle
)->desc_dirty
= false;
1752 util_dynarray_foreach(&sctx
->resident_img_handles
,
1753 struct si_image_handle
*, img_handle
) {
1754 unsigned desc_slot
= (*img_handle
)->desc_slot
;
1756 if (!(*img_handle
)->desc_dirty
)
1759 si_upload_bindless_descriptor(sctx
, desc_slot
, 8);
1760 (*img_handle
)->desc_dirty
= false;
1763 /* Invalidate L1 because it doesn't know that L2 changed. */
1764 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
;
1765 si_emit_cache_flush(sctx
);
1767 sctx
->bindless_descriptors_dirty
= false;
1770 /* Update mutable image descriptor fields of all resident textures. */
1771 static void si_update_bindless_texture_descriptor(struct si_context
*sctx
,
1772 struct si_texture_handle
*tex_handle
)
1774 struct si_sampler_view
*sview
= (struct si_sampler_view
*)tex_handle
->view
;
1775 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1776 unsigned desc_slot_offset
= tex_handle
->desc_slot
* 16;
1777 uint32_t desc_list
[16];
1779 if (sview
->base
.texture
->target
== PIPE_BUFFER
)
1782 memcpy(desc_list
, desc
->list
+ desc_slot_offset
, sizeof(desc_list
));
1783 si_set_sampler_view_desc(sctx
, sview
, &tex_handle
->sstate
,
1784 desc
->list
+ desc_slot_offset
);
1786 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1787 sizeof(desc_list
))) {
1788 tex_handle
->desc_dirty
= true;
1789 sctx
->bindless_descriptors_dirty
= true;
1793 static void si_update_bindless_image_descriptor(struct si_context
*sctx
,
1794 struct si_image_handle
*img_handle
)
1796 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
1797 unsigned desc_slot_offset
= img_handle
->desc_slot
* 16;
1798 struct pipe_image_view
*view
= &img_handle
->view
;
1799 uint32_t desc_list
[8];
1801 if (view
->resource
->target
== PIPE_BUFFER
)
1804 memcpy(desc_list
, desc
->list
+ desc_slot_offset
,
1806 si_set_shader_image_desc(sctx
, view
, true,
1807 desc
->list
+ desc_slot_offset
);
1809 if (memcmp(desc_list
, desc
->list
+ desc_slot_offset
,
1810 sizeof(desc_list
))) {
1811 img_handle
->desc_dirty
= true;
1812 sctx
->bindless_descriptors_dirty
= true;
1816 static void si_update_all_resident_texture_descriptors(struct si_context
*sctx
)
1818 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1819 struct si_texture_handle
*, tex_handle
) {
1820 si_update_bindless_texture_descriptor(sctx
, *tex_handle
);
1823 util_dynarray_foreach(&sctx
->resident_img_handles
,
1824 struct si_image_handle
*, img_handle
) {
1825 si_update_bindless_image_descriptor(sctx
, *img_handle
);
1828 si_upload_bindless_descriptors(sctx
);
1831 /* Update mutable image descriptor fields of all bound textures. */
1832 void si_update_all_texture_descriptors(struct si_context
*sctx
)
1836 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1837 struct si_samplers
*samplers
= &sctx
->samplers
[shader
];
1838 struct si_images
*images
= &sctx
->images
[shader
];
1842 mask
= images
->enabled_mask
;
1844 unsigned i
= u_bit_scan(&mask
);
1845 struct pipe_image_view
*view
= &images
->views
[i
];
1847 if (!view
->resource
||
1848 view
->resource
->target
== PIPE_BUFFER
)
1851 si_set_shader_image(sctx
, shader
, i
, view
, true);
1854 /* Sampler views. */
1855 mask
= samplers
->enabled_mask
;
1857 unsigned i
= u_bit_scan(&mask
);
1858 struct pipe_sampler_view
*view
= samplers
->views
[i
];
1862 view
->texture
->target
== PIPE_BUFFER
)
1865 si_set_sampler_view(sctx
, shader
, i
,
1866 samplers
->views
[i
], true);
1869 si_update_shader_needs_decompress_mask(sctx
, shader
);
1872 si_update_all_resident_texture_descriptors(sctx
);
1875 /* SHADER USER DATA */
1877 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
,
1880 sctx
->shader_pointers_dirty
|=
1881 u_bit_consecutive(SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
,
1882 SI_NUM_SHADER_DESCS
);
1884 if (shader
== PIPE_SHADER_VERTEX
)
1885 sctx
->vertex_buffer_pointer_dirty
= sctx
->vertex_buffers
.buffer
!= NULL
;
1887 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1890 static void si_shader_pointers_begin_new_cs(struct si_context
*sctx
)
1892 sctx
->shader_pointers_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
1893 sctx
->vertex_buffer_pointer_dirty
= sctx
->vertex_buffers
.buffer
!= NULL
;
1894 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
1895 sctx
->graphics_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
1896 sctx
->compute_bindless_pointer_dirty
= sctx
->bindless_descriptors
.buffer
!= NULL
;
1899 /* Set a base register address for user data constants in the given shader.
1900 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1902 static void si_set_user_data_base(struct si_context
*sctx
,
1903 unsigned shader
, uint32_t new_base
)
1905 uint32_t *base
= &sctx
->shader_pointers
.sh_base
[shader
];
1907 if (*base
!= new_base
) {
1911 si_mark_shader_pointers_dirty(sctx
, shader
);
1913 if (shader
== PIPE_SHADER_VERTEX
)
1914 sctx
->last_vs_state
= ~0;
1919 /* This must be called when these shaders are changed from non-NULL to NULL
1922 * - tessellation control shader
1923 * - tessellation evaluation shader
1925 void si_shader_change_notify(struct si_context
*sctx
)
1927 /* VS can be bound as VS, ES, or LS. */
1928 if (sctx
->tes_shader
.cso
) {
1929 if (sctx
->b
.chip_class
>= GFX9
) {
1930 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1931 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
1933 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1934 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
1936 } else if (sctx
->gs_shader
.cso
) {
1937 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1938 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1940 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1941 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1944 /* TES can be bound as ES, VS, or not bound. */
1945 if (sctx
->tes_shader
.cso
) {
1946 if (sctx
->gs_shader
.cso
)
1947 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
1948 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1950 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
1951 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1953 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
1957 static void si_emit_shader_pointer_head(struct radeon_winsys_cs
*cs
,
1958 struct si_descriptors
*desc
,
1960 unsigned pointer_count
)
1962 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* 2, 0));
1963 radeon_emit(cs
, (sh_base
+ desc
->shader_userdata_offset
- SI_SH_REG_OFFSET
) >> 2);
1966 static void si_emit_shader_pointer_body(struct radeon_winsys_cs
*cs
,
1967 struct si_descriptors
*desc
)
1972 va
= desc
->buffer
->gpu_address
+ desc
->buffer_offset
;
1974 radeon_emit(cs
, va
);
1975 radeon_emit(cs
, va
>> 32);
1978 static void si_emit_shader_pointer(struct si_context
*sctx
,
1979 struct si_descriptors
*desc
,
1982 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1984 si_emit_shader_pointer_head(cs
, desc
, sh_base
, 1);
1985 si_emit_shader_pointer_body(cs
, desc
);
1988 static void si_emit_global_shader_pointers(struct si_context
*sctx
,
1989 struct si_descriptors
*descs
)
1991 if (sctx
->b
.chip_class
== GFX9
) {
1992 /* Broadcast it to all shader stages. */
1993 si_emit_shader_pointer(sctx
, descs
,
1994 R_00B530_SPI_SHADER_USER_DATA_COMMON_0
);
1998 si_emit_shader_pointer(sctx
, descs
,
1999 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2000 si_emit_shader_pointer(sctx
, descs
,
2001 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2002 si_emit_shader_pointer(sctx
, descs
,
2003 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2004 si_emit_shader_pointer(sctx
, descs
,
2005 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2006 si_emit_shader_pointer(sctx
, descs
,
2007 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2008 si_emit_shader_pointer(sctx
, descs
,
2009 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2012 void si_emit_graphics_shader_pointers(struct si_context
*sctx
,
2013 struct r600_atom
*atom
)
2016 uint32_t *sh_base
= sctx
->shader_pointers
.sh_base
;
2017 struct si_descriptors
*descs
;
2019 descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
2021 if (sctx
->shader_pointers_dirty
& (1 << SI_DESCS_RW_BUFFERS
))
2022 si_emit_global_shader_pointers(sctx
, descs
);
2024 mask
= sctx
->shader_pointers_dirty
&
2025 u_bit_consecutive(SI_DESCS_FIRST_SHADER
,
2026 SI_DESCS_FIRST_COMPUTE
- SI_DESCS_FIRST_SHADER
);
2029 unsigned i
= u_bit_scan(&mask
);
2030 unsigned shader
= (i
- SI_DESCS_FIRST_SHADER
) / SI_NUM_SHADER_DESCS
;
2031 unsigned base
= sh_base
[shader
];
2034 si_emit_shader_pointer(sctx
, descs
+ i
, base
);
2036 sctx
->shader_pointers_dirty
&=
2037 ~u_bit_consecutive(SI_DESCS_RW_BUFFERS
, SI_DESCS_FIRST_COMPUTE
);
2039 if (sctx
->vertex_buffer_pointer_dirty
) {
2040 si_emit_shader_pointer(sctx
, &sctx
->vertex_buffers
,
2041 sh_base
[PIPE_SHADER_VERTEX
]);
2042 sctx
->vertex_buffer_pointer_dirty
= false;
2045 if (sctx
->graphics_bindless_pointer_dirty
) {
2046 si_emit_global_shader_pointers(sctx
,
2047 &sctx
->bindless_descriptors
);
2048 sctx
->graphics_bindless_pointer_dirty
= false;
2052 void si_emit_compute_shader_pointers(struct si_context
*sctx
)
2054 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
2055 struct si_descriptors
*descs
= sctx
->descriptors
;
2056 unsigned compute_mask
=
2057 u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
, SI_NUM_SHADER_DESCS
);
2058 unsigned mask
= sctx
->shader_pointers_dirty
& compute_mask
;
2061 unsigned i
= u_bit_scan(&mask
);
2063 si_emit_shader_pointer(sctx
, descs
+ i
, base
);
2065 sctx
->shader_pointers_dirty
&= ~compute_mask
;
2067 if (sctx
->compute_bindless_pointer_dirty
) {
2068 si_emit_shader_pointer(sctx
, &sctx
->bindless_descriptors
, base
);
2069 sctx
->compute_bindless_pointer_dirty
= false;
2075 static void si_init_bindless_descriptors(struct si_context
*sctx
,
2076 struct si_descriptors
*desc
,
2077 unsigned shader_userdata_index
,
2078 unsigned num_elements
)
2080 MAYBE_UNUSED
unsigned desc_slot
;
2082 si_init_descriptors(desc
, shader_userdata_index
, 16, num_elements
);
2083 sctx
->bindless_descriptors
.num_active_slots
= num_elements
;
2085 /* The first bindless descriptor is stored at slot 1, because 0 is not
2086 * considered to be a valid handle.
2088 sctx
->num_bindless_descriptors
= 1;
2090 /* Track which bindless slots are used (or not). */
2091 util_idalloc_init(&sctx
->bindless_used_slots
);
2092 util_idalloc_resize(&sctx
->bindless_used_slots
, num_elements
);
2094 /* Reserve slot 0 because it's an invalid handle for bindless. */
2095 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2096 assert(desc_slot
== 0);
2099 static void si_release_bindless_descriptors(struct si_context
*sctx
)
2101 si_release_descriptors(&sctx
->bindless_descriptors
);
2102 util_idalloc_fini(&sctx
->bindless_used_slots
);
2105 static unsigned si_get_first_free_bindless_slot(struct si_context
*sctx
)
2107 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2110 desc_slot
= util_idalloc_alloc(&sctx
->bindless_used_slots
);
2111 if (desc_slot
>= desc
->num_elements
) {
2112 /* The array of bindless descriptors is full, resize it. */
2113 unsigned slot_size
= desc
->element_dw_size
* 4;
2114 unsigned new_num_elements
= desc
->num_elements
* 2;
2116 desc
->list
= REALLOC(desc
->list
, desc
->num_elements
* slot_size
,
2117 new_num_elements
* slot_size
);
2118 desc
->num_elements
= new_num_elements
;
2119 desc
->num_active_slots
= new_num_elements
;
2127 si_create_bindless_descriptor(struct si_context
*sctx
, uint32_t *desc_list
,
2130 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2131 unsigned desc_slot
, desc_slot_offset
;
2133 /* Find a free slot. */
2134 desc_slot
= si_get_first_free_bindless_slot(sctx
);
2136 /* For simplicity, sampler and image bindless descriptors use fixed
2137 * 16-dword slots for now. Image descriptors only need 8-dword but this
2138 * doesn't really matter because no real apps use image handles.
2140 desc_slot_offset
= desc_slot
* 16;
2142 /* Copy the descriptor into the array. */
2143 memcpy(desc
->list
+ desc_slot_offset
, desc_list
, size
);
2145 /* Re-upload the whole array of bindless descriptors into a new buffer.
2147 if (!si_upload_descriptors(sctx
, desc
, &sctx
->shader_pointers
.atom
))
2150 /* Make sure to re-emit the shader pointers for all stages. */
2151 sctx
->graphics_bindless_pointer_dirty
= true;
2152 sctx
->compute_bindless_pointer_dirty
= true;
2157 static void si_update_bindless_buffer_descriptor(struct si_context
*sctx
,
2159 struct pipe_resource
*resource
,
2163 struct si_descriptors
*desc
= &sctx
->bindless_descriptors
;
2164 struct r600_resource
*buf
= r600_resource(resource
);
2165 unsigned desc_slot_offset
= desc_slot
* 16;
2166 uint32_t *desc_list
= desc
->list
+ desc_slot_offset
+ 4;
2167 uint64_t old_desc_va
;
2169 assert(resource
->target
== PIPE_BUFFER
);
2171 /* Retrieve the old buffer addr from the descriptor. */
2172 old_desc_va
= desc_list
[0];
2173 old_desc_va
|= ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc_list
[1]) << 32);
2175 if (old_desc_va
!= buf
->gpu_address
+ offset
) {
2176 /* The buffer has been invalidated when the handle wasn't
2177 * resident, update the descriptor and the dirty flag.
2179 si_set_buf_desc_address(buf
, offset
, &desc_list
[0]);
2185 static uint64_t si_create_texture_handle(struct pipe_context
*ctx
,
2186 struct pipe_sampler_view
*view
,
2187 const struct pipe_sampler_state
*state
)
2189 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
2190 struct si_context
*sctx
= (struct si_context
*)ctx
;
2191 struct si_texture_handle
*tex_handle
;
2192 struct si_sampler_state
*sstate
;
2193 uint32_t desc_list
[16];
2196 tex_handle
= CALLOC_STRUCT(si_texture_handle
);
2200 memset(desc_list
, 0, sizeof(desc_list
));
2201 si_init_descriptor_list(&desc_list
[0], 16, 1, null_texture_descriptor
);
2203 sstate
= ctx
->create_sampler_state(ctx
, state
);
2209 si_set_sampler_view_desc(sctx
, sview
, sstate
, &desc_list
[0]);
2210 memcpy(&tex_handle
->sstate
, sstate
, sizeof(*sstate
));
2211 ctx
->delete_sampler_state(ctx
, sstate
);
2213 tex_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2215 if (!tex_handle
->desc_slot
) {
2220 handle
= tex_handle
->desc_slot
;
2222 if (!_mesa_hash_table_insert(sctx
->tex_handles
, (void *)handle
,
2228 pipe_sampler_view_reference(&tex_handle
->view
, view
);
2230 r600_resource(sview
->base
.texture
)->texture_handle_allocated
= true;
2235 static void si_delete_texture_handle(struct pipe_context
*ctx
, uint64_t handle
)
2237 struct si_context
*sctx
= (struct si_context
*)ctx
;
2238 struct si_texture_handle
*tex_handle
;
2239 struct hash_entry
*entry
;
2241 entry
= _mesa_hash_table_search(sctx
->tex_handles
, (void *)handle
);
2245 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2247 /* Allow this descriptor slot to be re-used. */
2248 util_idalloc_free(&sctx
->bindless_used_slots
, tex_handle
->desc_slot
);
2250 pipe_sampler_view_reference(&tex_handle
->view
, NULL
);
2251 _mesa_hash_table_remove(sctx
->tex_handles
, entry
);
2255 static void si_make_texture_handle_resident(struct pipe_context
*ctx
,
2256 uint64_t handle
, bool resident
)
2258 struct si_context
*sctx
= (struct si_context
*)ctx
;
2259 struct si_texture_handle
*tex_handle
;
2260 struct si_sampler_view
*sview
;
2261 struct hash_entry
*entry
;
2263 entry
= _mesa_hash_table_search(sctx
->tex_handles
, (void *)handle
);
2267 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2268 sview
= (struct si_sampler_view
*)tex_handle
->view
;
2271 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2272 struct r600_texture
*rtex
=
2273 (struct r600_texture
*)sview
->base
.texture
;
2275 if (depth_needs_decompression(rtex
)) {
2276 util_dynarray_append(
2277 &sctx
->resident_tex_needs_depth_decompress
,
2278 struct si_texture_handle
*,
2282 if (color_needs_decompression(rtex
)) {
2283 util_dynarray_append(
2284 &sctx
->resident_tex_needs_color_decompress
,
2285 struct si_texture_handle
*,
2289 if (rtex
->dcc_offset
&&
2290 p_atomic_read(&rtex
->framebuffers_bound
))
2291 sctx
->need_check_render_feedback
= true;
2293 si_update_bindless_texture_descriptor(sctx
, tex_handle
);
2295 si_update_bindless_buffer_descriptor(sctx
,
2296 tex_handle
->desc_slot
,
2297 sview
->base
.texture
,
2298 sview
->base
.u
.buf
.offset
,
2299 &tex_handle
->desc_dirty
);
2302 /* Re-upload the descriptor if it has been updated while it
2305 if (tex_handle
->desc_dirty
)
2306 sctx
->bindless_descriptors_dirty
= true;
2308 /* Add the texture handle to the per-context list. */
2309 util_dynarray_append(&sctx
->resident_tex_handles
,
2310 struct si_texture_handle
*, tex_handle
);
2312 /* Add the buffers to the current CS in case si_begin_new_cs()
2313 * is not going to be called.
2315 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2317 sview
->is_stencil_sampler
, false);
2319 /* Remove the texture handle from the per-context list. */
2320 util_dynarray_delete_unordered(&sctx
->resident_tex_handles
,
2321 struct si_texture_handle
*,
2324 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2325 util_dynarray_delete_unordered(
2326 &sctx
->resident_tex_needs_depth_decompress
,
2327 struct si_texture_handle
*, tex_handle
);
2329 util_dynarray_delete_unordered(
2330 &sctx
->resident_tex_needs_color_decompress
,
2331 struct si_texture_handle
*, tex_handle
);
2336 static uint64_t si_create_image_handle(struct pipe_context
*ctx
,
2337 const struct pipe_image_view
*view
)
2339 struct si_context
*sctx
= (struct si_context
*)ctx
;
2340 struct si_image_handle
*img_handle
;
2341 uint32_t desc_list
[8];
2344 if (!view
|| !view
->resource
)
2347 img_handle
= CALLOC_STRUCT(si_image_handle
);
2351 memset(desc_list
, 0, sizeof(desc_list
));
2352 si_init_descriptor_list(&desc_list
[0], 8, 1, null_image_descriptor
);
2354 si_set_shader_image_desc(sctx
, view
, false, &desc_list
[0]);
2356 img_handle
->desc_slot
= si_create_bindless_descriptor(sctx
, desc_list
,
2358 if (!img_handle
->desc_slot
) {
2363 handle
= img_handle
->desc_slot
;
2365 if (!_mesa_hash_table_insert(sctx
->img_handles
, (void *)handle
,
2371 util_copy_image_view(&img_handle
->view
, view
);
2373 r600_resource(view
->resource
)->image_handle_allocated
= true;
2378 static void si_delete_image_handle(struct pipe_context
*ctx
, uint64_t handle
)
2380 struct si_context
*sctx
= (struct si_context
*)ctx
;
2381 struct si_image_handle
*img_handle
;
2382 struct hash_entry
*entry
;
2384 entry
= _mesa_hash_table_search(sctx
->img_handles
, (void *)handle
);
2388 img_handle
= (struct si_image_handle
*)entry
->data
;
2390 util_copy_image_view(&img_handle
->view
, NULL
);
2391 _mesa_hash_table_remove(sctx
->img_handles
, entry
);
2395 static void si_make_image_handle_resident(struct pipe_context
*ctx
,
2396 uint64_t handle
, unsigned access
,
2399 struct si_context
*sctx
= (struct si_context
*)ctx
;
2400 struct si_image_handle
*img_handle
;
2401 struct pipe_image_view
*view
;
2402 struct r600_resource
*res
;
2403 struct hash_entry
*entry
;
2405 entry
= _mesa_hash_table_search(sctx
->img_handles
, (void *)handle
);
2409 img_handle
= (struct si_image_handle
*)entry
->data
;
2410 view
= &img_handle
->view
;
2411 res
= (struct r600_resource
*)view
->resource
;
2414 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2415 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
2416 unsigned level
= view
->u
.tex
.level
;
2418 if (color_needs_decompression(rtex
)) {
2419 util_dynarray_append(
2420 &sctx
->resident_img_needs_color_decompress
,
2421 struct si_image_handle
*,
2425 if (vi_dcc_enabled(rtex
, level
) &&
2426 p_atomic_read(&rtex
->framebuffers_bound
))
2427 sctx
->need_check_render_feedback
= true;
2429 si_update_bindless_image_descriptor(sctx
, img_handle
);
2431 si_update_bindless_buffer_descriptor(sctx
,
2432 img_handle
->desc_slot
,
2435 &img_handle
->desc_dirty
);
2438 /* Re-upload the descriptor if it has been updated while it
2441 if (img_handle
->desc_dirty
)
2442 sctx
->bindless_descriptors_dirty
= true;
2444 /* Add the image handle to the per-context list. */
2445 util_dynarray_append(&sctx
->resident_img_handles
,
2446 struct si_image_handle
*, img_handle
);
2448 /* Add the buffers to the current CS in case si_begin_new_cs()
2449 * is not going to be called.
2451 si_sampler_view_add_buffer(sctx
, view
->resource
,
2452 (access
& PIPE_IMAGE_ACCESS_WRITE
) ?
2453 RADEON_USAGE_READWRITE
:
2454 RADEON_USAGE_READ
, false, false);
2456 /* Remove the image handle from the per-context list. */
2457 util_dynarray_delete_unordered(&sctx
->resident_img_handles
,
2458 struct si_image_handle
*,
2461 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2462 util_dynarray_delete_unordered(
2463 &sctx
->resident_img_needs_color_decompress
,
2464 struct si_image_handle
*,
2471 void si_all_resident_buffers_begin_new_cs(struct si_context
*sctx
)
2473 unsigned num_resident_tex_handles
, num_resident_img_handles
;
2475 num_resident_tex_handles
= sctx
->resident_tex_handles
.size
/
2476 sizeof(struct si_texture_handle
*);
2477 num_resident_img_handles
= sctx
->resident_img_handles
.size
/
2478 sizeof(struct si_image_handle
*);
2480 /* Add all resident texture handles. */
2481 util_dynarray_foreach(&sctx
->resident_tex_handles
,
2482 struct si_texture_handle
*, tex_handle
) {
2483 struct si_sampler_view
*sview
=
2484 (struct si_sampler_view
*)(*tex_handle
)->view
;
2486 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2488 sview
->is_stencil_sampler
, false);
2491 /* Add all resident image handles. */
2492 util_dynarray_foreach(&sctx
->resident_img_handles
,
2493 struct si_image_handle
*, img_handle
) {
2494 struct pipe_image_view
*view
= &(*img_handle
)->view
;
2496 si_sampler_view_add_buffer(sctx
, view
->resource
,
2497 RADEON_USAGE_READWRITE
,
2501 sctx
->b
.num_resident_handles
+= num_resident_tex_handles
+
2502 num_resident_img_handles
;
2505 /* INIT/DEINIT/UPLOAD */
2507 void si_init_all_descriptors(struct si_context
*sctx
)
2511 STATIC_ASSERT(GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS
% 2 == 0);
2512 STATIC_ASSERT(GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS
% 2 == 0);
2514 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2515 bool gfx9_tcs
= false;
2516 bool gfx9_gs
= false;
2517 unsigned num_sampler_slots
= SI_NUM_IMAGES
/ 2 + SI_NUM_SAMPLERS
;
2518 unsigned num_buffer_slots
= SI_NUM_SHADER_BUFFERS
+ SI_NUM_CONST_BUFFERS
;
2520 if (sctx
->b
.chip_class
>= GFX9
) {
2521 gfx9_tcs
= i
== PIPE_SHADER_TESS_CTRL
;
2522 gfx9_gs
= i
== PIPE_SHADER_GEOMETRY
;
2525 si_init_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2526 si_const_and_shader_buffer_descriptors(sctx
, i
),
2528 gfx9_tcs
? GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS
:
2529 gfx9_gs
? GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS
:
2530 SI_SGPR_CONST_AND_SHADER_BUFFERS
,
2531 RADEON_USAGE_READWRITE
,
2533 RADEON_PRIO_SHADER_RW_BUFFER
,
2534 RADEON_PRIO_CONST_BUFFER
);
2536 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, i
);
2537 si_init_descriptors(desc
,
2538 gfx9_tcs
? GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES
:
2539 gfx9_gs
? GFX9_SGPR_GS_SAMPLERS_AND_IMAGES
:
2540 SI_SGPR_SAMPLERS_AND_IMAGES
,
2541 16, num_sampler_slots
);
2544 for (j
= 0; j
< SI_NUM_IMAGES
; j
++)
2545 memcpy(desc
->list
+ j
* 8, null_image_descriptor
, 8 * 4);
2546 for (; j
< SI_NUM_IMAGES
+ SI_NUM_SAMPLERS
* 2; j
++)
2547 memcpy(desc
->list
+ j
* 8, null_texture_descriptor
, 8 * 4);
2550 si_init_buffer_resources(&sctx
->rw_buffers
,
2551 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
2552 SI_NUM_RW_BUFFERS
, SI_SGPR_RW_BUFFERS
,
2553 /* The second set of usage/priority is used by
2554 * const buffers in RW buffer slots. */
2555 RADEON_USAGE_READWRITE
, RADEON_USAGE_READ
,
2556 RADEON_PRIO_SHADER_RINGS
, RADEON_PRIO_CONST_BUFFER
);
2557 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
= SI_NUM_RW_BUFFERS
;
2559 si_init_descriptors(&sctx
->vertex_buffers
, SI_SGPR_VERTEX_BUFFERS
,
2560 4, SI_NUM_VERTEX_BUFFERS
);
2561 FREE(sctx
->vertex_buffers
.list
); /* not used */
2562 sctx
->vertex_buffers
.list
= NULL
;
2564 /* Initialize an array of 1024 bindless descriptors, when the limit is
2565 * reached, just make it larger and re-upload the whole array.
2567 si_init_bindless_descriptors(sctx
, &sctx
->bindless_descriptors
,
2568 SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES
,
2571 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2573 /* Set pipe_context functions. */
2574 sctx
->b
.b
.bind_sampler_states
= si_bind_sampler_states
;
2575 sctx
->b
.b
.set_shader_images
= si_set_shader_images
;
2576 sctx
->b
.b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
2577 sctx
->b
.b
.set_polygon_stipple
= si_set_polygon_stipple
;
2578 sctx
->b
.b
.set_shader_buffers
= si_set_shader_buffers
;
2579 sctx
->b
.b
.set_sampler_views
= si_set_sampler_views
;
2580 sctx
->b
.b
.create_texture_handle
= si_create_texture_handle
;
2581 sctx
->b
.b
.delete_texture_handle
= si_delete_texture_handle
;
2582 sctx
->b
.b
.make_texture_handle_resident
= si_make_texture_handle_resident
;
2583 sctx
->b
.b
.create_image_handle
= si_create_image_handle
;
2584 sctx
->b
.b
.delete_image_handle
= si_delete_image_handle
;
2585 sctx
->b
.b
.make_image_handle_resident
= si_make_image_handle_resident
;
2586 sctx
->b
.invalidate_buffer
= si_invalidate_buffer
;
2587 sctx
->b
.rebind_buffer
= si_rebind_buffer
;
2589 /* Shader user data. */
2590 si_init_atom(sctx
, &sctx
->shader_pointers
.atom
, &sctx
->atoms
.s
.shader_pointers
,
2591 si_emit_graphics_shader_pointers
);
2593 /* Set default and immutable mappings. */
2594 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2596 if (sctx
->b
.chip_class
>= GFX9
) {
2597 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2598 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2599 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2600 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2602 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2603 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2604 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2605 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2607 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2610 static bool si_upload_shader_descriptors(struct si_context
*sctx
, unsigned mask
)
2612 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2614 /* Assume nothing will go wrong: */
2615 sctx
->shader_pointers_dirty
|= dirty
;
2618 unsigned i
= u_bit_scan(&dirty
);
2620 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
],
2621 &sctx
->shader_pointers
.atom
))
2625 sctx
->descriptors_dirty
&= ~mask
;
2627 si_upload_bindless_descriptors(sctx
);
2632 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
2634 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
2635 return si_upload_shader_descriptors(sctx
, mask
);
2638 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
2640 /* Does not update rw_buffers as that is not needed for compute shaders
2641 * and the input buffer is using the same SGPR's anyway.
2643 const unsigned mask
= u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
,
2644 SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
2645 return si_upload_shader_descriptors(sctx
, mask
);
2648 void si_release_all_descriptors(struct si_context
*sctx
)
2652 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2653 si_release_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2654 si_const_and_shader_buffer_descriptors(sctx
, i
));
2655 si_release_sampler_views(&sctx
->samplers
[i
]);
2656 si_release_image_views(&sctx
->images
[i
]);
2658 si_release_buffer_resources(&sctx
->rw_buffers
,
2659 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2660 for (i
= 0; i
< SI_NUM_VERTEX_BUFFERS
; i
++)
2661 pipe_vertex_buffer_unreference(&sctx
->vertex_buffer
[i
]);
2663 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2664 si_release_descriptors(&sctx
->descriptors
[i
]);
2666 sctx
->vertex_buffers
.list
= NULL
; /* points into a mapped buffer */
2667 si_release_descriptors(&sctx
->vertex_buffers
);
2668 si_release_bindless_descriptors(sctx
);
2671 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
2675 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2676 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2677 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
]);
2678 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
2680 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2681 si_vertex_buffers_begin_new_cs(sctx
);
2683 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2684 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
2685 si_descriptors_begin_new_cs(sctx
, &sctx
->bindless_descriptors
);
2687 si_shader_pointers_begin_new_cs(sctx
);
2690 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
2691 uint64_t new_active_mask
)
2693 struct si_descriptors
*desc
= &sctx
->descriptors
[desc_idx
];
2695 /* Ignore no-op updates and updates that disable all slots. */
2696 if (!new_active_mask
||
2697 new_active_mask
== u_bit_consecutive64(desc
->first_active_slot
,
2698 desc
->num_active_slots
))
2702 u_bit_scan_consecutive_range64(&new_active_mask
, &first
, &count
);
2703 assert(new_active_mask
== 0);
2705 /* Upload/dump descriptors if slots are being enabled. */
2706 if (first
< desc
->first_active_slot
||
2707 first
+ count
> desc
->first_active_slot
+ desc
->num_active_slots
)
2708 sctx
->descriptors_dirty
|= 1u << desc_idx
;
2710 desc
->first_active_slot
= first
;
2711 desc
->num_active_slots
= count
;
2714 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
2715 struct si_shader_selector
*sel
)
2720 si_set_active_descriptors(sctx
,
2721 si_const_and_shader_buffer_descriptors_idx(sel
->type
),
2722 sel
->active_const_and_shader_buffers
);
2723 si_set_active_descriptors(sctx
,
2724 si_sampler_and_image_descriptors_idx(sel
->type
),
2725 sel
->active_samplers_and_images
);