2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Marek Olšák <marek.olsak@amd.com>
27 /* Resource binding slots and sampler states (each described with 8 or
28 * 4 dwords) are stored in lists in memory which is accessed by shaders
29 * using scalar load instructions.
31 * This file is responsible for managing such lists. It keeps a copy of all
32 * descriptors in CPU memory and re-uploads a whole list if some slots have
35 * This code is also reponsible for updating shader pointers to those lists.
37 * Note that CP DMA can't be used for updating the lists, because a GPU hang
38 * could leave the list in a mid-IB state and the next IB would get wrong
39 * descriptors and the whole context would be unusable at that point.
40 * (Note: The register shadowing can't be used due to the same reason)
42 * Also, uploading descriptors to newly allocated memory doesn't require
46 * Possible scenarios for one 16 dword image+sampler slot:
48 * | Image | w/ FMASK | Buffer | NULL
49 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
50 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
51 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
52 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
54 * FMASK implies MSAA, therefore no sampler state.
55 * Sampler states are never unbound except when FMASK is bound.
58 #include "radeon/r600_cs.h"
63 #include "util/hash_table.h"
64 #include "util/u_format.h"
65 #include "util/u_memory.h"
66 #include "util/u_upload_mgr.h"
69 /* NULL image and buffer descriptor for textures (alpha = 1) and images
72 * For images, all fields must be zero except for the swizzle, which
73 * supports arbitrary combinations of 0s and 1s. The texture type must be
74 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
76 * For buffers, all fields must be zero. If they are not, the hw hangs.
78 * This is the only reason why the buffer descriptor must be in words [4:7].
80 static uint32_t null_texture_descriptor
[8] = {
84 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) |
85 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
86 /* the rest must contain zeros, which is also used by the buffer
90 static uint32_t null_image_descriptor
[8] = {
94 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
95 /* the rest must contain zeros, which is also used by the buffer
99 static uint16_t si_ce_ram_size(struct si_context
*sctx
)
101 return sctx
->b
.chip_class
>= GFX9
? 4096 : 32768;
104 static void si_init_descriptor_list(uint32_t *desc_list
,
105 unsigned element_dw_size
,
106 unsigned num_elements
,
107 const uint32_t *null_descriptor
)
111 /* Initialize the array to NULL descriptors if the element size is 8. */
112 if (null_descriptor
) {
113 assert(element_dw_size
% 8 == 0);
114 for (i
= 0; i
< num_elements
* element_dw_size
/ 8; i
++)
115 memcpy(desc_list
+ i
* 8, null_descriptor
, 8 * 4);
119 static void si_init_descriptors(struct si_context
*sctx
,
120 struct si_descriptors
*desc
,
121 unsigned shader_userdata_index
,
122 unsigned element_dw_size
,
123 unsigned num_elements
,
124 unsigned first_ce_slot
,
125 unsigned num_ce_slots
,
128 assert(num_elements
<= sizeof(desc
->dirty_mask
)*8);
130 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
131 desc
->element_dw_size
= element_dw_size
;
132 desc
->num_elements
= num_elements
;
133 desc
->first_ce_slot
= sctx
->ce_ib
? first_ce_slot
: 0;
134 desc
->num_ce_slots
= sctx
->ce_ib
? num_ce_slots
: 0;
135 desc
->dirty_mask
= u_bit_consecutive64(0, num_elements
);
136 desc
->shader_userdata_offset
= shader_userdata_index
* 4;
138 if (desc
->num_ce_slots
) {
139 desc
->uses_ce
= true;
140 desc
->ce_offset
= *ce_offset
;
142 *ce_offset
+= element_dw_size
* desc
->num_ce_slots
* 4;
146 static void si_release_descriptors(struct si_descriptors
*desc
)
148 r600_resource_reference(&desc
->buffer
, NULL
);
152 static bool si_ce_upload(struct si_context
*sctx
, unsigned ce_offset
, unsigned size
,
153 unsigned *out_offset
, struct r600_resource
**out_buf
)
156 unsigned cache_line_size
= sctx
->screen
->b
.info
.tcc_cache_line_size
;
158 /* The base and size should be aligned to the L2 cache line size
159 * for optimal performance. (all dumps should rewrite whole lines)
161 size
= align(size
, cache_line_size
);
163 (void)si_ce_ram_size
; /* silence an "unused" warning */
164 assert(offset
+ size
<= si_ce_ram_size(sctx
));
166 u_suballocator_alloc(sctx
->ce_suballocator
, size
, cache_line_size
,
167 out_offset
, (struct pipe_resource
**)out_buf
);
171 va
= (*out_buf
)->gpu_address
+ *out_offset
;
173 radeon_emit(sctx
->ce_ib
, PKT3(PKT3_DUMP_CONST_RAM
, 3, 0));
174 radeon_emit(sctx
->ce_ib
, ce_offset
);
175 radeon_emit(sctx
->ce_ib
, size
/ 4);
176 radeon_emit(sctx
->ce_ib
, va
);
177 radeon_emit(sctx
->ce_ib
, va
>> 32);
179 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, *out_buf
,
180 RADEON_USAGE_READWRITE
, RADEON_PRIO_DESCRIPTORS
);
182 sctx
->ce_need_synchronization
= true;
186 void si_ce_save_all_descriptors_at_ib_end(struct si_context
* sctx
)
188 bool success
= si_ce_upload(sctx
, 0, sctx
->total_ce_ram_allocated
,
189 &sctx
->ce_ram_saved_offset
,
190 &sctx
->ce_ram_saved_buffer
);
195 void si_ce_restore_all_descriptors_at_ib_start(struct si_context
*sctx
)
197 if (!sctx
->ce_ram_saved_buffer
)
200 struct radeon_winsys_cs
*ib
= sctx
->ce_preamble_ib
;
204 uint64_t va
= sctx
->ce_ram_saved_buffer
->gpu_address
+
205 sctx
->ce_ram_saved_offset
;
207 radeon_emit(ib
, PKT3(PKT3_LOAD_CONST_RAM
, 3, 0));
209 radeon_emit(ib
, va
>> 32);
210 radeon_emit(ib
, sctx
->total_ce_ram_allocated
/ 4);
213 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
214 sctx
->ce_ram_saved_buffer
,
215 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
218 void si_ce_enable_loads(struct radeon_winsys_cs
*ib
)
220 radeon_emit(ib
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
221 radeon_emit(ib
, CONTEXT_CONTROL_LOAD_ENABLE(1) |
222 CONTEXT_CONTROL_LOAD_CE_RAM(1));
223 radeon_emit(ib
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
226 static bool si_upload_descriptors(struct si_context
*sctx
,
227 struct si_descriptors
*desc
,
228 struct r600_atom
* atom
)
230 unsigned slot_size
= desc
->element_dw_size
* 4;
231 unsigned first_slot_offset
= desc
->first_active_slot
* slot_size
;
232 unsigned upload_size
= desc
->num_active_slots
* slot_size
;
234 /* Skip the upload if no shader is using the descriptors. dirty_mask
235 * will stay dirty and the descriptors will be uploaded when there is
236 * a shader using them.
242 const uint32_t *list
= desc
->list
+
243 desc
->first_ce_slot
* desc
->element_dw_size
;
244 uint64_t mask
= (desc
->dirty_mask
>> desc
->first_ce_slot
) &
245 u_bit_consecutive64(0, desc
->num_ce_slots
);
250 u_bit_scan_consecutive_range64(&mask
, &begin
, &count
);
252 begin
*= desc
->element_dw_size
;
253 count
*= desc
->element_dw_size
;
255 radeon_emit(sctx
->ce_ib
,
256 PKT3(PKT3_WRITE_CONST_RAM
, count
, 0));
257 radeon_emit(sctx
->ce_ib
, desc
->ce_offset
+ begin
* 4);
258 radeon_emit_array(sctx
->ce_ib
, list
+ begin
, count
);
261 if (!si_ce_upload(sctx
,
263 (first_slot_offset
- desc
->first_ce_slot
* slot_size
),
264 upload_size
, (unsigned*)&desc
->buffer_offset
,
270 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, upload_size
,
271 si_optimal_tcc_alignment(sctx
, upload_size
),
272 (unsigned*)&desc
->buffer_offset
,
273 (struct pipe_resource
**)&desc
->buffer
,
276 return false; /* skip the draw call */
278 util_memcpy_cpu_to_le32(ptr
, (char*)desc
->list
+ first_slot_offset
,
280 desc
->gpu_list
= ptr
- first_slot_offset
/ 4;
282 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
283 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
286 /* The shader pointer should point to slot 0. */
287 desc
->buffer_offset
-= first_slot_offset
;
289 desc
->dirty_mask
= 0;
292 si_mark_atom_dirty(sctx
, atom
);
298 si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
303 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
304 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
310 si_sampler_and_image_descriptors_idx(unsigned shader
)
312 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
313 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
;
316 static struct si_descriptors
*
317 si_sampler_and_image_descriptors(struct si_context
*sctx
, unsigned shader
)
319 return &sctx
->descriptors
[si_sampler_and_image_descriptors_idx(shader
)];
322 static void si_release_sampler_views(struct si_sampler_views
*views
)
326 for (i
= 0; i
< ARRAY_SIZE(views
->views
); i
++) {
327 pipe_sampler_view_reference(&views
->views
[i
], NULL
);
331 static void si_sampler_view_add_buffer(struct si_context
*sctx
,
332 struct pipe_resource
*resource
,
333 enum radeon_bo_usage usage
,
334 bool is_stencil_sampler
,
337 struct r600_resource
*rres
;
338 struct r600_texture
*rtex
;
339 enum radeon_bo_priority priority
;
344 if (resource
->target
!= PIPE_BUFFER
) {
345 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
347 if (tex
->is_depth
&& !r600_can_sample_zs(tex
, is_stencil_sampler
))
348 resource
= &tex
->flushed_depth_texture
->resource
.b
.b
;
351 rres
= (struct r600_resource
*)resource
;
352 priority
= r600_get_sampler_view_priority(rres
);
354 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
355 rres
, usage
, priority
,
358 if (resource
->target
== PIPE_BUFFER
)
361 /* Now add separate DCC or HTILE. */
362 rtex
= (struct r600_texture
*)resource
;
363 if (rtex
->dcc_separate_buffer
) {
364 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
365 rtex
->dcc_separate_buffer
, usage
,
366 RADEON_PRIO_DCC
, check_mem
);
370 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
,
371 struct si_sampler_views
*views
)
373 unsigned mask
= views
->enabled_mask
;
375 /* Add buffers to the CS. */
377 int i
= u_bit_scan(&mask
);
378 struct si_sampler_view
*sview
= (struct si_sampler_view
*)views
->views
[i
];
380 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
382 sview
->is_stencil_sampler
, false);
386 /* Set buffer descriptor fields that can be changed by reallocations. */
387 static void si_set_buf_desc_address(struct r600_resource
*buf
,
388 uint64_t offset
, uint32_t *state
)
390 uint64_t va
= buf
->gpu_address
+ offset
;
393 state
[1] &= C_008F04_BASE_ADDRESS_HI
;
394 state
[1] |= S_008F04_BASE_ADDRESS_HI(va
>> 32);
397 /* Set texture descriptor fields that can be changed by reallocations.
400 * \param base_level_info information of the level of BASE_ADDRESS
401 * \param base_level the level of BASE_ADDRESS
402 * \param first_level pipe_sampler_view.u.tex.first_level
403 * \param block_width util_format_get_blockwidth()
404 * \param is_stencil select between separate Z & Stencil
405 * \param state descriptor to update
407 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
408 struct r600_texture
*tex
,
409 const struct legacy_surf_level
*base_level_info
,
410 unsigned base_level
, unsigned first_level
,
411 unsigned block_width
, bool is_stencil
,
414 uint64_t va
, meta_va
= 0;
416 if (tex
->is_depth
&& !r600_can_sample_zs(tex
, is_stencil
)) {
417 tex
= tex
->flushed_depth_texture
;
421 va
= tex
->resource
.gpu_address
;
423 if (sscreen
->b
.chip_class
>= GFX9
) {
424 /* Only stencil_offset needs to be added here. */
426 va
+= tex
->surface
.u
.gfx9
.stencil_offset
;
428 va
+= tex
->surface
.u
.gfx9
.surf_offset
;
430 va
+= base_level_info
->offset
;
434 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
435 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
437 /* Only macrotiled modes can set tile swizzle.
438 * GFX9 doesn't use (legacy) base_level_info.
440 if (sscreen
->b
.chip_class
>= GFX9
||
441 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
442 state
[0] |= tex
->surface
.tile_swizzle
;
444 if (sscreen
->b
.chip_class
>= VI
) {
445 state
[6] &= C_008F28_COMPRESSION_EN
;
448 if (vi_dcc_enabled(tex
, first_level
)) {
449 meta_va
= (!tex
->dcc_separate_buffer
? tex
->resource
.gpu_address
: 0) +
452 if (sscreen
->b
.chip_class
== VI
) {
453 meta_va
+= base_level_info
->dcc_offset
;
454 assert(base_level_info
->mode
== RADEON_SURF_MODE_2D
);
457 meta_va
|= (uint32_t)tex
->surface
.tile_swizzle
<< 8;
458 } else if (tex
->tc_compatible_htile
&& first_level
== 0) {
459 meta_va
= tex
->resource
.gpu_address
+ tex
->htile_offset
;
463 state
[6] |= S_008F28_COMPRESSION_EN(1);
464 state
[7] = meta_va
>> 8;
468 if (sscreen
->b
.chip_class
>= GFX9
) {
469 state
[3] &= C_008F1C_SW_MODE
;
470 state
[4] &= C_008F20_PITCH_GFX9
;
473 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
474 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.stencil
.epitch
);
476 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
477 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.surf
.epitch
);
480 state
[5] &= C_008F24_META_DATA_ADDRESS
&
481 C_008F24_META_PIPE_ALIGNED
&
482 C_008F24_META_RB_ALIGNED
;
484 struct gfx9_surf_meta_flags meta
;
487 meta
= tex
->surface
.u
.gfx9
.dcc
;
489 meta
= tex
->surface
.u
.gfx9
.htile
;
491 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
492 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
493 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
497 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
498 unsigned index
= si_tile_mode_index(tex
, base_level
, is_stencil
);
500 state
[3] &= C_008F1C_TILING_INDEX
;
501 state
[3] |= S_008F1C_TILING_INDEX(index
);
502 state
[4] &= C_008F20_PITCH_GFX6
;
503 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
507 static void si_set_sampler_view_desc(struct si_context
*sctx
,
508 struct si_sampler_view
*sview
,
509 struct si_sampler_state
*sstate
,
512 struct pipe_sampler_view
*view
= &sview
->base
;
513 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
514 bool is_buffer
= rtex
->resource
.b
.b
.target
== PIPE_BUFFER
;
516 if (unlikely(!is_buffer
&& sview
->dcc_incompatible
)) {
517 if (vi_dcc_enabled(rtex
, view
->u
.tex
.first_level
))
518 if (!r600_texture_disable_dcc(&sctx
->b
, rtex
))
519 sctx
->b
.decompress_dcc(&sctx
->b
.b
, rtex
);
521 sview
->dcc_incompatible
= false;
524 assert(rtex
); /* views with texture == NULL aren't supported */
525 memcpy(desc
, sview
->state
, 8*4);
528 si_set_buf_desc_address(&rtex
->resource
,
529 sview
->base
.u
.buf
.offset
,
532 bool is_separate_stencil
= rtex
->db_compatible
&&
533 sview
->is_stencil_sampler
;
535 si_set_mutable_tex_desc_fields(sctx
->screen
, rtex
,
536 sview
->base_level_info
,
538 sview
->base
.u
.tex
.first_level
,
544 if (!is_buffer
&& rtex
->fmask
.size
) {
545 memcpy(desc
+ 8, sview
->fmask_state
, 8*4);
547 /* Disable FMASK and bind sampler state in [12:15]. */
548 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
551 memcpy(desc
+ 12, sstate
->val
, 4*4);
555 static void si_set_sampler_view(struct si_context
*sctx
,
557 unsigned slot
, struct pipe_sampler_view
*view
,
558 bool disallow_early_out
)
560 struct si_sampler_views
*views
= &sctx
->samplers
[shader
].views
;
561 struct si_sampler_view
*rview
= (struct si_sampler_view
*)view
;
562 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
563 unsigned desc_slot
= si_get_sampler_slot(slot
);
564 uint32_t *desc
= descs
->list
+ desc_slot
* 16;
566 if (views
->views
[slot
] == view
&& !disallow_early_out
)
570 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
572 si_set_sampler_view_desc(sctx
, rview
,
573 views
->sampler_states
[slot
], desc
);
575 if (rtex
->resource
.b
.b
.target
== PIPE_BUFFER
)
576 rtex
->resource
.bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
578 pipe_sampler_view_reference(&views
->views
[slot
], view
);
579 views
->enabled_mask
|= 1u << slot
;
581 /* Since this can flush, it must be done after enabled_mask is
583 si_sampler_view_add_buffer(sctx
, view
->texture
,
585 rview
->is_stencil_sampler
, true);
587 pipe_sampler_view_reference(&views
->views
[slot
], NULL
);
588 memcpy(desc
, null_texture_descriptor
, 8*4);
589 /* Only clear the lower dwords of FMASK. */
590 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
591 /* Re-set the sampler state if we are transitioning from FMASK. */
592 if (views
->sampler_states
[slot
])
594 views
->sampler_states
[slot
]->val
, 4*4);
596 views
->enabled_mask
&= ~(1u << slot
);
599 descs
->dirty_mask
|= 1ull << desc_slot
;
600 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
603 static bool color_needs_decompression(struct r600_texture
*rtex
)
605 return rtex
->fmask
.size
||
606 (rtex
->dirty_level_mask
&&
607 (rtex
->cmask
.size
|| rtex
->dcc_offset
));
610 static bool depth_needs_decompression(struct r600_texture
*rtex
)
612 /* If the depth/stencil texture is TC-compatible, no decompression
613 * will be done. The decompression function will only flush DB caches
614 * to make it coherent with shaders. That's necessary because the driver
615 * doesn't flush DB caches in any other case.
617 return rtex
->db_compatible
;
620 static void si_update_shader_needs_decompress_mask(struct si_context
*sctx
,
623 struct si_textures_info
*samplers
= &sctx
->samplers
[shader
];
624 unsigned shader_bit
= 1 << shader
;
626 if (samplers
->needs_depth_decompress_mask
||
627 samplers
->needs_color_decompress_mask
||
628 sctx
->images
[shader
].needs_color_decompress_mask
)
629 sctx
->shader_needs_decompress_mask
|= shader_bit
;
631 sctx
->shader_needs_decompress_mask
&= ~shader_bit
;
634 static void si_set_sampler_views(struct pipe_context
*ctx
,
635 enum pipe_shader_type shader
, unsigned start
,
637 struct pipe_sampler_view
**views
)
639 struct si_context
*sctx
= (struct si_context
*)ctx
;
640 struct si_textures_info
*samplers
= &sctx
->samplers
[shader
];
643 if (!count
|| shader
>= SI_NUM_SHADERS
)
646 for (i
= 0; i
< count
; i
++) {
647 unsigned slot
= start
+ i
;
649 if (!views
|| !views
[i
]) {
650 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
651 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
652 si_set_sampler_view(sctx
, shader
, slot
, NULL
, false);
656 si_set_sampler_view(sctx
, shader
, slot
, views
[i
], false);
658 if (views
[i
]->texture
&& views
[i
]->texture
->target
!= PIPE_BUFFER
) {
659 struct r600_texture
*rtex
=
660 (struct r600_texture
*)views
[i
]->texture
;
662 if (depth_needs_decompression(rtex
)) {
663 samplers
->needs_depth_decompress_mask
|= 1u << slot
;
665 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
667 if (color_needs_decompression(rtex
)) {
668 samplers
->needs_color_decompress_mask
|= 1u << slot
;
670 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
673 if (rtex
->dcc_offset
&&
674 p_atomic_read(&rtex
->framebuffers_bound
))
675 sctx
->need_check_render_feedback
= true;
677 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
678 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
682 si_update_shader_needs_decompress_mask(sctx
, shader
);
686 si_samplers_update_needs_color_decompress_mask(struct si_textures_info
*samplers
)
688 unsigned mask
= samplers
->views
.enabled_mask
;
691 int i
= u_bit_scan(&mask
);
692 struct pipe_resource
*res
= samplers
->views
.views
[i
]->texture
;
694 if (res
&& res
->target
!= PIPE_BUFFER
) {
695 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
697 if (color_needs_decompression(rtex
)) {
698 samplers
->needs_color_decompress_mask
|= 1u << i
;
700 samplers
->needs_color_decompress_mask
&= ~(1u << i
);
709 si_release_image_views(struct si_images_info
*images
)
713 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
714 struct pipe_image_view
*view
= &images
->views
[i
];
716 pipe_resource_reference(&view
->resource
, NULL
);
721 si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images_info
*images
)
723 uint mask
= images
->enabled_mask
;
725 /* Add buffers to the CS. */
727 int i
= u_bit_scan(&mask
);
728 struct pipe_image_view
*view
= &images
->views
[i
];
730 assert(view
->resource
);
732 si_sampler_view_add_buffer(sctx
, view
->resource
,
733 RADEON_USAGE_READWRITE
, false, false);
738 si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
740 struct si_images_info
*images
= &ctx
->images
[shader
];
742 if (images
->enabled_mask
& (1u << slot
)) {
743 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
744 unsigned desc_slot
= si_get_image_slot(slot
);
746 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
747 images
->needs_color_decompress_mask
&= ~(1 << slot
);
749 memcpy(descs
->list
+ desc_slot
*8, null_image_descriptor
, 8*4);
750 images
->enabled_mask
&= ~(1u << slot
);
751 /* two 8-byte images share one 16-byte slot */
752 descs
->dirty_mask
|= 1u << (desc_slot
/ 2);
753 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
758 si_mark_image_range_valid(const struct pipe_image_view
*view
)
760 struct r600_resource
*res
= (struct r600_resource
*)view
->resource
;
762 assert(res
&& res
->b
.b
.target
== PIPE_BUFFER
);
764 util_range_add(&res
->valid_buffer_range
,
766 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
769 static void si_set_shader_image_desc(struct si_context
*ctx
,
770 const struct pipe_image_view
*view
,
771 bool skip_decompress
,
774 struct si_screen
*screen
= ctx
->screen
;
775 struct r600_resource
*res
;
777 res
= (struct r600_resource
*)view
->resource
;
779 if (res
->b
.b
.target
== PIPE_BUFFER
) {
780 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
781 si_mark_image_range_valid(view
);
783 si_make_buffer_descriptor(screen
, res
,
786 view
->u
.buf
.size
, desc
);
787 si_set_buf_desc_address(res
, view
->u
.buf
.offset
, desc
+ 4);
789 static const unsigned char swizzle
[4] = { 0, 1, 2, 3 };
790 struct r600_texture
*tex
= (struct r600_texture
*)res
;
791 unsigned level
= view
->u
.tex
.level
;
792 unsigned width
, height
, depth
, hw_level
;
793 bool uses_dcc
= vi_dcc_enabled(tex
, level
);
795 assert(!tex
->is_depth
);
796 assert(tex
->fmask
.size
== 0);
798 if (uses_dcc
&& !skip_decompress
&&
799 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
||
800 !vi_dcc_formats_compatible(res
->b
.b
.format
, view
->format
))) {
801 /* If DCC can't be disabled, at least decompress it.
802 * The decompression is relatively cheap if the surface
803 * has been decompressed already.
805 if (!r600_texture_disable_dcc(&ctx
->b
, tex
))
806 ctx
->b
.decompress_dcc(&ctx
->b
.b
, tex
);
809 if (ctx
->b
.chip_class
>= GFX9
) {
810 /* Always set the base address. The swizzle modes don't
811 * allow setting mipmap level offsets as the base.
813 width
= res
->b
.b
.width0
;
814 height
= res
->b
.b
.height0
;
815 depth
= res
->b
.b
.depth0
;
818 /* Always force the base level to the selected level.
820 * This is required for 3D textures, where otherwise
821 * selecting a single slice for non-layered bindings
822 * fails. It doesn't hurt the other targets.
824 width
= u_minify(res
->b
.b
.width0
, level
);
825 height
= u_minify(res
->b
.b
.height0
, level
);
826 depth
= u_minify(res
->b
.b
.depth0
, level
);
830 si_make_texture_descriptor(screen
, tex
,
831 false, res
->b
.b
.target
,
832 view
->format
, swizzle
,
834 view
->u
.tex
.first_layer
,
835 view
->u
.tex
.last_layer
,
836 width
, height
, depth
,
838 si_set_mutable_tex_desc_fields(screen
, tex
,
839 &tex
->surface
.u
.legacy
.level
[level
],
841 util_format_get_blockwidth(view
->format
),
846 static void si_set_shader_image(struct si_context
*ctx
,
848 unsigned slot
, const struct pipe_image_view
*view
,
849 bool skip_decompress
)
851 struct si_images_info
*images
= &ctx
->images
[shader
];
852 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
853 struct r600_resource
*res
;
854 unsigned desc_slot
= si_get_image_slot(slot
);
855 uint32_t *desc
= descs
->list
+ desc_slot
* 8;
857 if (!view
|| !view
->resource
) {
858 si_disable_shader_image(ctx
, shader
, slot
);
862 res
= (struct r600_resource
*)view
->resource
;
864 if (&images
->views
[slot
] != view
)
865 util_copy_image_view(&images
->views
[slot
], view
);
867 si_set_shader_image_desc(ctx
, view
, skip_decompress
, desc
);
869 if (res
->b
.b
.target
== PIPE_BUFFER
) {
870 images
->needs_color_decompress_mask
&= ~(1 << slot
);
871 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
873 struct r600_texture
*tex
= (struct r600_texture
*)res
;
874 unsigned level
= view
->u
.tex
.level
;
876 if (color_needs_decompression(tex
)) {
877 images
->needs_color_decompress_mask
|= 1 << slot
;
879 images
->needs_color_decompress_mask
&= ~(1 << slot
);
882 if (vi_dcc_enabled(tex
, level
) &&
883 p_atomic_read(&tex
->framebuffers_bound
))
884 ctx
->need_check_render_feedback
= true;
887 images
->enabled_mask
|= 1u << slot
;
888 /* two 8-byte images share one 16-byte slot */
889 descs
->dirty_mask
|= 1u << (desc_slot
/ 2);
890 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
892 /* Since this can flush, it must be done after enabled_mask is updated. */
893 si_sampler_view_add_buffer(ctx
, &res
->b
.b
,
894 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
) ?
895 RADEON_USAGE_READWRITE
: RADEON_USAGE_READ
,
900 si_set_shader_images(struct pipe_context
*pipe
,
901 enum pipe_shader_type shader
,
902 unsigned start_slot
, unsigned count
,
903 const struct pipe_image_view
*views
)
905 struct si_context
*ctx
= (struct si_context
*)pipe
;
908 assert(shader
< SI_NUM_SHADERS
);
913 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
916 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
917 si_set_shader_image(ctx
, shader
, slot
, &views
[i
], false);
919 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
920 si_set_shader_image(ctx
, shader
, slot
, NULL
, false);
923 si_update_shader_needs_decompress_mask(ctx
, shader
);
927 si_images_update_needs_color_decompress_mask(struct si_images_info
*images
)
929 unsigned mask
= images
->enabled_mask
;
932 int i
= u_bit_scan(&mask
);
933 struct pipe_resource
*res
= images
->views
[i
].resource
;
935 if (res
&& res
->target
!= PIPE_BUFFER
) {
936 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
938 if (color_needs_decompression(rtex
)) {
939 images
->needs_color_decompress_mask
|= 1 << i
;
941 images
->needs_color_decompress_mask
&= ~(1 << i
);
949 static void si_bind_sampler_states(struct pipe_context
*ctx
,
950 enum pipe_shader_type shader
,
951 unsigned start
, unsigned count
, void **states
)
953 struct si_context
*sctx
= (struct si_context
*)ctx
;
954 struct si_textures_info
*samplers
= &sctx
->samplers
[shader
];
955 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, shader
);
956 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
959 if (!count
|| shader
>= SI_NUM_SHADERS
)
962 for (i
= 0; i
< count
; i
++) {
963 unsigned slot
= start
+ i
;
964 unsigned desc_slot
= si_get_sampler_slot(slot
);
967 sstates
[i
] == samplers
->views
.sampler_states
[slot
])
971 assert(sstates
[i
]->magic
== SI_SAMPLER_STATE_MAGIC
);
973 samplers
->views
.sampler_states
[slot
] = sstates
[i
];
975 /* If FMASK is bound, don't overwrite it.
976 * The sampler state will be set after FMASK is unbound.
978 if (samplers
->views
.views
[slot
] &&
979 samplers
->views
.views
[slot
]->texture
&&
980 samplers
->views
.views
[slot
]->texture
->target
!= PIPE_BUFFER
&&
981 ((struct r600_texture
*)samplers
->views
.views
[slot
]->texture
)->fmask
.size
)
984 memcpy(desc
->list
+ desc_slot
* 16 + 12, sstates
[i
]->val
, 4*4);
985 desc
->dirty_mask
|= 1ull << desc_slot
;
986 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
990 /* BUFFER RESOURCES */
992 static void si_init_buffer_resources(struct si_context
*sctx
,
993 struct si_buffer_resources
*buffers
,
994 struct si_descriptors
*descs
,
995 unsigned num_buffers
,
996 unsigned first_ce_slot
,
997 unsigned num_ce_slots
,
998 unsigned shader_userdata_index
,
999 enum radeon_bo_usage shader_usage
,
1000 enum radeon_bo_usage shader_usage_constbuf
,
1001 enum radeon_bo_priority priority
,
1002 enum radeon_bo_priority priority_constbuf
,
1003 unsigned *ce_offset
)
1005 buffers
->shader_usage
= shader_usage
;
1006 buffers
->shader_usage_constbuf
= shader_usage_constbuf
;
1007 buffers
->priority
= priority
;
1008 buffers
->priority_constbuf
= priority_constbuf
;
1009 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
1011 si_init_descriptors(sctx
, descs
, shader_userdata_index
, 4, num_buffers
,
1012 first_ce_slot
, num_ce_slots
, ce_offset
);
1015 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
1016 struct si_descriptors
*descs
)
1020 for (i
= 0; i
< descs
->num_elements
; i
++) {
1021 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
1024 FREE(buffers
->buffers
);
1027 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
1028 struct si_buffer_resources
*buffers
)
1030 unsigned mask
= buffers
->enabled_mask
;
1032 /* Add buffers to the CS. */
1034 int i
= u_bit_scan(&mask
);
1036 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1037 r600_resource(buffers
->buffers
[i
]),
1038 i
< SI_NUM_SHADER_BUFFERS
? buffers
->shader_usage
:
1039 buffers
->shader_usage_constbuf
,
1040 i
< SI_NUM_SHADER_BUFFERS
? buffers
->priority
:
1041 buffers
->priority_constbuf
);
1045 static void si_get_buffer_from_descriptors(struct si_buffer_resources
*buffers
,
1046 struct si_descriptors
*descs
,
1047 unsigned idx
, struct pipe_resource
**buf
,
1048 unsigned *offset
, unsigned *size
)
1050 pipe_resource_reference(buf
, buffers
->buffers
[idx
]);
1052 struct r600_resource
*res
= r600_resource(*buf
);
1053 const uint32_t *desc
= descs
->list
+ idx
* 4;
1058 assert(G_008F04_STRIDE(desc
[1]) == 0);
1059 va
= ((uint64_t)desc
[1] << 32) | desc
[0];
1061 assert(va
>= res
->gpu_address
&& va
+ *size
<= res
->gpu_address
+ res
->bo_size
);
1062 *offset
= va
- res
->gpu_address
;
1066 /* VERTEX BUFFERS */
1068 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
1070 struct si_descriptors
*desc
= &sctx
->vertex_buffers
;
1071 int count
= sctx
->vertex_elements
? sctx
->vertex_elements
->count
: 0;
1074 for (i
= 0; i
< count
; i
++) {
1075 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1077 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1079 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1082 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1083 (struct r600_resource
*)sctx
->vertex_buffer
[vb
].buffer
.resource
,
1084 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1089 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1090 desc
->buffer
, RADEON_USAGE_READ
,
1091 RADEON_PRIO_DESCRIPTORS
);
1094 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
1096 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
1097 struct si_descriptors
*desc
= &sctx
->vertex_buffers
;
1099 unsigned desc_list_byte_size
;
1100 unsigned first_vb_use_mask
;
1104 if (!sctx
->vertex_buffers_dirty
|| !velems
)
1107 count
= velems
->count
;
1112 desc_list_byte_size
= velems
->desc_list_byte_size
;
1113 first_vb_use_mask
= velems
->first_vb_use_mask
;
1115 /* Vertex buffer descriptors are the only ones which are uploaded
1116 * directly through a staging buffer and don't go through
1117 * the fine-grained upload path.
1119 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0,
1120 desc_list_byte_size
,
1121 si_optimal_tcc_alignment(sctx
, desc_list_byte_size
),
1122 (unsigned*)&desc
->buffer_offset
,
1123 (struct pipe_resource
**)&desc
->buffer
, (void**)&ptr
);
1128 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1129 desc
->buffer
, RADEON_USAGE_READ
,
1130 RADEON_PRIO_DESCRIPTORS
);
1132 assert(count
<= SI_MAX_ATTRIBS
);
1134 for (i
= 0; i
< count
; i
++) {
1135 struct pipe_vertex_buffer
*vb
;
1136 struct r600_resource
*rbuffer
;
1138 unsigned vbo_index
= velems
->vertex_buffer_index
[i
];
1139 uint32_t *desc
= &ptr
[i
*4];
1141 vb
= &sctx
->vertex_buffer
[vbo_index
];
1142 rbuffer
= (struct r600_resource
*)vb
->buffer
.resource
;
1144 memset(desc
, 0, 16);
1148 offset
= vb
->buffer_offset
+ velems
->src_offset
[i
];
1149 va
= rbuffer
->gpu_address
+ offset
;
1151 /* Fill in T# buffer resource description */
1153 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1154 S_008F04_STRIDE(vb
->stride
);
1156 if (sctx
->b
.chip_class
!= VI
&& vb
->stride
) {
1157 /* Round up by rounding down and adding 1 */
1158 desc
[2] = (vb
->buffer
.resource
->width0
- offset
-
1159 velems
->format_size
[i
]) /
1162 desc
[2] = vb
->buffer
.resource
->width0
- offset
;
1165 desc
[3] = velems
->rsrc_word3
[i
];
1167 if (first_vb_use_mask
& (1 << i
)) {
1168 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1169 (struct r600_resource
*)vb
->buffer
.resource
,
1170 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1174 /* Don't flush the const cache. It would have a very negative effect
1175 * on performance (confirmed by testing). New descriptors are always
1176 * uploaded to a fresh new buffer, so I don't think flushing the const
1177 * cache is needed. */
1178 si_mark_atom_dirty(sctx
, &sctx
->shader_userdata
.atom
);
1179 if (sctx
->b
.chip_class
>= CIK
)
1180 si_mark_atom_dirty(sctx
, &sctx
->prefetch_L2
);
1181 sctx
->vertex_buffers_dirty
= false;
1182 sctx
->vertex_buffer_pointer_dirty
= true;
1187 /* CONSTANT BUFFERS */
1190 si_const_and_shader_buffer_descriptors_idx(unsigned shader
)
1192 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
1193 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
;
1196 static struct si_descriptors
*
1197 si_const_and_shader_buffer_descriptors(struct si_context
*sctx
, unsigned shader
)
1199 return &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(shader
)];
1202 void si_upload_const_buffer(struct si_context
*sctx
, struct r600_resource
**rbuffer
,
1203 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
)
1207 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, size
,
1208 si_optimal_tcc_alignment(sctx
, size
),
1210 (struct pipe_resource
**)rbuffer
, &tmp
);
1212 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
1215 static void si_set_constant_buffer(struct si_context
*sctx
,
1216 struct si_buffer_resources
*buffers
,
1217 unsigned descriptors_idx
,
1218 uint slot
, const struct pipe_constant_buffer
*input
)
1220 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1221 assert(slot
< descs
->num_elements
);
1222 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1224 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1225 * with a NULL buffer). We need to use a dummy buffer instead. */
1226 if (sctx
->b
.chip_class
== CIK
&&
1227 (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
1228 input
= &sctx
->null_const_buf
;
1230 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1231 struct pipe_resource
*buffer
= NULL
;
1234 /* Upload the user buffer if needed. */
1235 if (input
->user_buffer
) {
1236 unsigned buffer_offset
;
1238 si_upload_const_buffer(sctx
,
1239 (struct r600_resource
**)&buffer
, input
->user_buffer
,
1240 input
->buffer_size
, &buffer_offset
);
1242 /* Just unbind on failure. */
1243 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1246 va
= r600_resource(buffer
)->gpu_address
+ buffer_offset
;
1248 pipe_resource_reference(&buffer
, input
->buffer
);
1249 va
= r600_resource(buffer
)->gpu_address
+ input
->buffer_offset
;
1250 /* Only track usage for non-user buffers. */
1251 r600_resource(buffer
)->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
1254 /* Set the descriptor. */
1255 uint32_t *desc
= descs
->list
+ slot
*4;
1257 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1259 desc
[2] = input
->buffer_size
;
1260 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1261 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1262 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1263 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1264 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1265 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1267 buffers
->buffers
[slot
] = buffer
;
1268 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1269 (struct r600_resource
*)buffer
,
1270 buffers
->shader_usage_constbuf
,
1271 buffers
->priority_constbuf
, true);
1272 buffers
->enabled_mask
|= 1u << slot
;
1274 /* Clear the descriptor. */
1275 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1276 buffers
->enabled_mask
&= ~(1u << slot
);
1279 descs
->dirty_mask
|= 1u << slot
;
1280 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1283 void si_set_rw_buffer(struct si_context
*sctx
,
1284 uint slot
, const struct pipe_constant_buffer
*input
)
1286 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
,
1287 SI_DESCS_RW_BUFFERS
, slot
, input
);
1290 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
,
1291 enum pipe_shader_type shader
, uint slot
,
1292 const struct pipe_constant_buffer
*input
)
1294 struct si_context
*sctx
= (struct si_context
*)ctx
;
1296 if (shader
>= SI_NUM_SHADERS
)
1299 slot
= si_get_constbuf_slot(slot
);
1300 si_set_constant_buffer(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1301 si_const_and_shader_buffer_descriptors_idx(shader
),
1305 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
1306 uint slot
, struct pipe_constant_buffer
*cbuf
)
1308 cbuf
->user_buffer
= NULL
;
1309 si_get_buffer_from_descriptors(
1310 &sctx
->const_and_shader_buffers
[shader
],
1311 si_const_and_shader_buffer_descriptors(sctx
, shader
),
1312 si_get_constbuf_slot(slot
),
1313 &cbuf
->buffer
, &cbuf
->buffer_offset
, &cbuf
->buffer_size
);
1316 /* SHADER BUFFERS */
1318 static void si_set_shader_buffers(struct pipe_context
*ctx
,
1319 enum pipe_shader_type shader
,
1320 unsigned start_slot
, unsigned count
,
1321 const struct pipe_shader_buffer
*sbuffers
)
1323 struct si_context
*sctx
= (struct si_context
*)ctx
;
1324 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1325 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1328 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1330 for (i
= 0; i
< count
; ++i
) {
1331 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1332 struct r600_resource
*buf
;
1333 unsigned slot
= si_get_shaderbuf_slot(start_slot
+ i
);
1334 uint32_t *desc
= descs
->list
+ slot
* 4;
1337 if (!sbuffer
|| !sbuffer
->buffer
) {
1338 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1339 memset(desc
, 0, sizeof(uint32_t) * 4);
1340 buffers
->enabled_mask
&= ~(1u << slot
);
1341 descs
->dirty_mask
|= 1u << slot
;
1342 sctx
->descriptors_dirty
|=
1343 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1347 buf
= (struct r600_resource
*)sbuffer
->buffer
;
1348 va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1351 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1353 desc
[2] = sbuffer
->buffer_size
;
1354 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1355 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1356 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1357 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1358 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1359 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1361 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1362 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
, buf
,
1363 buffers
->shader_usage
,
1364 buffers
->priority
, true);
1365 buf
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1367 buffers
->enabled_mask
|= 1u << slot
;
1368 descs
->dirty_mask
|= 1u << slot
;
1369 sctx
->descriptors_dirty
|=
1370 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1372 util_range_add(&buf
->valid_buffer_range
, sbuffer
->buffer_offset
,
1373 sbuffer
->buffer_offset
+ sbuffer
->buffer_size
);
1377 void si_get_shader_buffers(struct si_context
*sctx
,
1378 enum pipe_shader_type shader
,
1379 uint start_slot
, uint count
,
1380 struct pipe_shader_buffer
*sbuf
)
1382 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1383 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1385 for (unsigned i
= 0; i
< count
; ++i
) {
1386 si_get_buffer_from_descriptors(
1388 si_get_shaderbuf_slot(start_slot
+ i
),
1389 &sbuf
[i
].buffer
, &sbuf
[i
].buffer_offset
,
1390 &sbuf
[i
].buffer_size
);
1396 void si_set_ring_buffer(struct pipe_context
*ctx
, uint slot
,
1397 struct pipe_resource
*buffer
,
1398 unsigned stride
, unsigned num_records
,
1399 bool add_tid
, bool swizzle
,
1400 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1402 struct si_context
*sctx
= (struct si_context
*)ctx
;
1403 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1404 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1406 /* The stride field in the resource descriptor has 14 bits */
1407 assert(stride
< (1 << 14));
1409 assert(slot
< descs
->num_elements
);
1410 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1415 va
= r600_resource(buffer
)->gpu_address
+ offset
;
1417 switch (element_size
) {
1419 assert(!"Unsupported ring buffer element size");
1435 switch (index_stride
) {
1437 assert(!"Unsupported ring buffer index stride");
1453 if (sctx
->b
.chip_class
>= VI
&& stride
)
1454 num_records
*= stride
;
1456 /* Set the descriptor. */
1457 uint32_t *desc
= descs
->list
+ slot
*4;
1459 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1460 S_008F04_STRIDE(stride
) |
1461 S_008F04_SWIZZLE_ENABLE(swizzle
);
1462 desc
[2] = num_records
;
1463 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1464 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1465 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1466 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1467 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1468 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1469 S_008F0C_INDEX_STRIDE(index_stride
) |
1470 S_008F0C_ADD_TID_ENABLE(add_tid
);
1472 if (sctx
->b
.chip_class
>= GFX9
)
1473 assert(!swizzle
|| element_size
== 1); /* always 4 bytes on GFX9 */
1475 desc
[3] |= S_008F0C_ELEMENT_SIZE(element_size
);
1477 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1478 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1479 (struct r600_resource
*)buffer
,
1480 buffers
->shader_usage
, buffers
->priority
);
1481 buffers
->enabled_mask
|= 1u << slot
;
1483 /* Clear the descriptor. */
1484 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1485 buffers
->enabled_mask
&= ~(1u << slot
);
1488 descs
->dirty_mask
|= 1u << slot
;
1489 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1492 /* STREAMOUT BUFFERS */
1494 static void si_set_streamout_targets(struct pipe_context
*ctx
,
1495 unsigned num_targets
,
1496 struct pipe_stream_output_target
**targets
,
1497 const unsigned *offsets
)
1499 struct si_context
*sctx
= (struct si_context
*)ctx
;
1500 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1501 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1502 unsigned old_num_targets
= sctx
->b
.streamout
.num_targets
;
1505 /* We are going to unbind the buffers. Mark which caches need to be flushed. */
1506 if (sctx
->b
.streamout
.num_targets
&& sctx
->b
.streamout
.begin_emitted
) {
1507 /* Since streamout uses vector writes which go through TC L2
1508 * and most other clients can use TC L2 as well, we don't need
1511 * The only cases which requires flushing it is VGT DMA index
1512 * fetching (on <= CIK) and indirect draw data, which are rare
1513 * cases. Thus, flag the TC L2 dirtiness in the resource and
1514 * handle it at draw call time.
1516 for (i
= 0; i
< sctx
->b
.streamout
.num_targets
; i
++)
1517 if (sctx
->b
.streamout
.targets
[i
])
1518 r600_resource(sctx
->b
.streamout
.targets
[i
]->b
.buffer
)->TC_L2_dirty
= true;
1520 /* Invalidate the scalar cache in case a streamout buffer is
1521 * going to be used as a constant buffer.
1523 * Invalidate TC L1, because streamout bypasses it (done by
1524 * setting GLC=1 in the store instruction), but it can contain
1525 * outdated data of streamout buffers.
1527 * VS_PARTIAL_FLUSH is required if the buffers are going to be
1528 * used as an input immediately.
1530 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
|
1531 SI_CONTEXT_INV_VMEM_L1
|
1532 SI_CONTEXT_VS_PARTIAL_FLUSH
;
1535 /* All readers of the streamout targets need to be finished before we can
1536 * start writing to the targets.
1539 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
1540 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1542 /* Streamout buffers must be bound in 2 places:
1543 * 1) in VGT by setting the VGT_STRMOUT registers
1544 * 2) as shader resources
1547 /* Set the VGT regs. */
1548 r600_set_streamout_targets(ctx
, num_targets
, targets
, offsets
);
1550 /* Set the shader resources.*/
1551 for (i
= 0; i
< num_targets
; i
++) {
1552 bufidx
= SI_VS_STREAMOUT_BUF0
+ i
;
1555 struct pipe_resource
*buffer
= targets
[i
]->buffer
;
1556 uint64_t va
= r600_resource(buffer
)->gpu_address
;
1558 /* Set the descriptor.
1560 * On VI, the format must be non-INVALID, otherwise
1561 * the buffer will be considered not bound and store
1562 * instructions will be no-ops.
1564 uint32_t *desc
= descs
->list
+ bufidx
*4;
1566 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
1567 desc
[2] = 0xffffffff;
1568 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1569 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1570 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1571 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1572 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1574 /* Set the resource. */
1575 pipe_resource_reference(&buffers
->buffers
[bufidx
],
1577 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1578 (struct r600_resource
*)buffer
,
1579 buffers
->shader_usage
,
1580 RADEON_PRIO_SHADER_RW_BUFFER
,
1582 r600_resource(buffer
)->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
1584 buffers
->enabled_mask
|= 1u << bufidx
;
1586 /* Clear the descriptor and unset the resource. */
1587 memset(descs
->list
+ bufidx
*4, 0,
1588 sizeof(uint32_t) * 4);
1589 pipe_resource_reference(&buffers
->buffers
[bufidx
],
1591 buffers
->enabled_mask
&= ~(1u << bufidx
);
1593 descs
->dirty_mask
|= 1u << bufidx
;
1595 for (; i
< old_num_targets
; i
++) {
1596 bufidx
= SI_VS_STREAMOUT_BUF0
+ i
;
1597 /* Clear the descriptor and unset the resource. */
1598 memset(descs
->list
+ bufidx
*4, 0, sizeof(uint32_t) * 4);
1599 pipe_resource_reference(&buffers
->buffers
[bufidx
], NULL
);
1600 buffers
->enabled_mask
&= ~(1u << bufidx
);
1601 descs
->dirty_mask
|= 1u << bufidx
;
1604 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1607 static void si_desc_reset_buffer_offset(struct pipe_context
*ctx
,
1608 uint32_t *desc
, uint64_t old_buf_va
,
1609 struct pipe_resource
*new_buf
)
1611 /* Retrieve the buffer offset from the descriptor. */
1612 uint64_t old_desc_va
=
1613 desc
[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
1615 assert(old_buf_va
<= old_desc_va
);
1616 uint64_t offset_within_buffer
= old_desc_va
- old_buf_va
;
1618 /* Update the descriptor. */
1619 si_set_buf_desc_address(r600_resource(new_buf
), offset_within_buffer
,
1623 /* INTERNAL CONST BUFFERS */
1625 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
1626 const struct pipe_poly_stipple
*state
)
1628 struct si_context
*sctx
= (struct si_context
*)ctx
;
1629 struct pipe_constant_buffer cb
= {};
1630 unsigned stipple
[32];
1633 for (i
= 0; i
< 32; i
++)
1634 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1636 cb
.user_buffer
= stipple
;
1637 cb
.buffer_size
= sizeof(stipple
);
1639 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1642 /* TEXTURE METADATA ENABLE/DISABLE */
1645 si_resident_handles_update_needs_color_decompress(struct si_context
*sctx
)
1647 util_dynarray_clear(&sctx
->resident_tex_needs_color_decompress
);
1648 util_dynarray_clear(&sctx
->resident_img_needs_color_decompress
);
1650 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1651 struct si_texture_handle
*, tex_handle
) {
1652 struct pipe_resource
*res
= (*tex_handle
)->view
->texture
;
1653 struct r600_texture
*rtex
;
1655 if (!res
|| res
->target
== PIPE_BUFFER
)
1658 rtex
= (struct r600_texture
*)res
;
1659 if (!color_needs_decompression(rtex
))
1662 util_dynarray_append(&sctx
->resident_tex_needs_color_decompress
,
1663 struct si_texture_handle
*, *tex_handle
);
1666 util_dynarray_foreach(&sctx
->resident_img_handles
,
1667 struct si_image_handle
*, img_handle
) {
1668 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1669 struct pipe_resource
*res
= view
->resource
;
1670 struct r600_texture
*rtex
;
1672 if (!res
|| res
->target
== PIPE_BUFFER
)
1675 rtex
= (struct r600_texture
*)res
;
1676 if (!color_needs_decompression(rtex
))
1679 util_dynarray_append(&sctx
->resident_img_needs_color_decompress
,
1680 struct si_image_handle
*, *img_handle
);
1684 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1685 * while the texture is bound, possibly by a different context. In that case,
1686 * call this function to update needs_*_decompress_masks.
1688 void si_update_needs_color_decompress_masks(struct si_context
*sctx
)
1690 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1691 si_samplers_update_needs_color_decompress_mask(&sctx
->samplers
[i
]);
1692 si_images_update_needs_color_decompress_mask(&sctx
->images
[i
]);
1693 si_update_shader_needs_decompress_mask(sctx
, i
);
1696 si_resident_handles_update_needs_color_decompress(sctx
);
1699 /* BUFFER DISCARD/INVALIDATION */
1701 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1702 static void si_reset_buffer_resources(struct si_context
*sctx
,
1703 struct si_buffer_resources
*buffers
,
1704 unsigned descriptors_idx
,
1706 struct pipe_resource
*buf
,
1708 enum radeon_bo_usage usage
,
1709 enum radeon_bo_priority priority
)
1711 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1712 unsigned mask
= buffers
->enabled_mask
& slot_mask
;
1715 unsigned i
= u_bit_scan(&mask
);
1716 if (buffers
->buffers
[i
] == buf
) {
1717 si_desc_reset_buffer_offset(&sctx
->b
.b
,
1720 descs
->dirty_mask
|= 1u << i
;
1721 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1723 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1724 (struct r600_resource
*)buf
,
1725 usage
, priority
, true);
1730 static void si_rebind_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
,
1733 struct si_context
*sctx
= (struct si_context
*)ctx
;
1734 struct r600_resource
*rbuffer
= r600_resource(buf
);
1736 unsigned num_elems
= sctx
->vertex_elements
?
1737 sctx
->vertex_elements
->count
: 0;
1739 /* We changed the buffer, now we need to bind it where the old one
1740 * was bound. This consists of 2 things:
1741 * 1) Updating the resource descriptor and dirtying it.
1742 * 2) Adding a relocation to the CS, so that it's usable.
1745 /* Vertex buffers. */
1746 if (rbuffer
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
1747 for (i
= 0; i
< num_elems
; i
++) {
1748 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1750 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1752 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1755 if (sctx
->vertex_buffer
[vb
].buffer
.resource
== buf
) {
1756 sctx
->vertex_buffers_dirty
= true;
1762 /* Streamout buffers. (other internal buffers can't be invalidated) */
1763 if (rbuffer
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
1764 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1765 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1766 struct si_descriptors
*descs
=
1767 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1769 if (buffers
->buffers
[i
] != buf
)
1772 si_desc_reset_buffer_offset(ctx
, descs
->list
+ i
*4,
1774 descs
->dirty_mask
|= 1u << i
;
1775 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1777 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1778 rbuffer
, buffers
->shader_usage
,
1779 RADEON_PRIO_SHADER_RW_BUFFER
,
1782 /* Update the streamout state. */
1783 if (sctx
->b
.streamout
.begin_emitted
)
1784 r600_emit_streamout_end(&sctx
->b
);
1785 sctx
->b
.streamout
.append_bitmask
=
1786 sctx
->b
.streamout
.enabled_mask
;
1787 r600_streamout_buffers_dirty(&sctx
->b
);
1791 /* Constant and shader buffers. */
1792 if (rbuffer
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1793 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1794 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1795 si_const_and_shader_buffer_descriptors_idx(shader
),
1796 u_bit_consecutive(SI_NUM_SHADER_BUFFERS
, SI_NUM_CONST_BUFFERS
),
1798 sctx
->const_and_shader_buffers
[shader
].shader_usage_constbuf
,
1799 sctx
->const_and_shader_buffers
[shader
].priority_constbuf
);
1802 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
1803 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1804 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1805 si_const_and_shader_buffer_descriptors_idx(shader
),
1806 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
),
1808 sctx
->const_and_shader_buffers
[shader
].shader_usage
,
1809 sctx
->const_and_shader_buffers
[shader
].priority
);
1812 if (rbuffer
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
1813 /* Texture buffers - update bindings. */
1814 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1815 struct si_sampler_views
*views
= &sctx
->samplers
[shader
].views
;
1816 struct si_descriptors
*descs
=
1817 si_sampler_and_image_descriptors(sctx
, shader
);
1818 unsigned mask
= views
->enabled_mask
;
1821 unsigned i
= u_bit_scan(&mask
);
1822 if (views
->views
[i
]->texture
== buf
) {
1823 unsigned desc_slot
= si_get_sampler_slot(i
);
1825 si_desc_reset_buffer_offset(ctx
,
1829 descs
->dirty_mask
|= 1ull << desc_slot
;
1830 sctx
->descriptors_dirty
|=
1831 1u << si_sampler_and_image_descriptors_idx(shader
);
1833 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1834 rbuffer
, RADEON_USAGE_READ
,
1835 RADEON_PRIO_SAMPLER_BUFFER
,
1843 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
1844 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1845 struct si_images_info
*images
= &sctx
->images
[shader
];
1846 struct si_descriptors
*descs
=
1847 si_sampler_and_image_descriptors(sctx
, shader
);
1848 unsigned mask
= images
->enabled_mask
;
1851 unsigned i
= u_bit_scan(&mask
);
1853 if (images
->views
[i
].resource
== buf
) {
1854 unsigned desc_slot
= si_get_image_slot(i
);
1856 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1857 si_mark_image_range_valid(&images
->views
[i
]);
1859 si_desc_reset_buffer_offset(
1860 ctx
, descs
->list
+ desc_slot
* 8 + 4,
1862 /* two 8-byte images share one 16-byte slot */
1863 descs
->dirty_mask
|= 1u << (desc_slot
/ 2);
1864 sctx
->descriptors_dirty
|=
1865 1u << si_sampler_and_image_descriptors_idx(shader
);
1867 radeon_add_to_buffer_list_check_mem(
1868 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1869 RADEON_USAGE_READWRITE
,
1870 RADEON_PRIO_SAMPLER_BUFFER
, true);
1876 /* Bindless texture handles */
1877 if (rbuffer
->texture_handle_allocated
) {
1878 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1879 struct si_texture_handle
*, tex_handle
) {
1880 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
1881 struct si_bindless_descriptor
*desc
= (*tex_handle
)->desc
;
1883 if (view
->texture
== buf
) {
1884 si_set_buf_desc_address(rbuffer
,
1886 &desc
->desc_list
[4]);
1888 sctx
->bindless_descriptors_dirty
= true;
1890 radeon_add_to_buffer_list_check_mem(
1891 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1893 RADEON_PRIO_SAMPLER_BUFFER
, true);
1898 /* Bindless image handles */
1899 if (rbuffer
->image_handle_allocated
) {
1900 util_dynarray_foreach(&sctx
->resident_img_handles
,
1901 struct si_image_handle
*, img_handle
) {
1902 struct pipe_image_view
*view
= &(*img_handle
)->view
;
1903 struct si_bindless_descriptor
*desc
= (*img_handle
)->desc
;
1905 if (view
->resource
== buf
) {
1906 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
1907 si_mark_image_range_valid(view
);
1909 si_set_buf_desc_address(rbuffer
,
1911 &desc
->desc_list
[4]);
1913 sctx
->bindless_descriptors_dirty
= true;
1915 radeon_add_to_buffer_list_check_mem(
1916 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1917 RADEON_USAGE_READWRITE
,
1918 RADEON_PRIO_SAMPLER_BUFFER
, true);
1924 /* Reallocate a buffer a update all resource bindings where the buffer is
1927 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
1928 * idle by discarding its contents. Apps usually tell us when to do this using
1929 * map_buffer flags, for example.
1931 static void si_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
1933 struct si_context
*sctx
= (struct si_context
*)ctx
;
1934 struct r600_resource
*rbuffer
= r600_resource(buf
);
1935 uint64_t old_va
= rbuffer
->gpu_address
;
1937 /* Reallocate the buffer in the same pipe_resource. */
1938 r600_alloc_resource(&sctx
->screen
->b
, rbuffer
);
1940 si_rebind_buffer(ctx
, buf
, old_va
);
1943 static void si_upload_bindless_descriptor(struct si_context
*sctx
,
1944 struct si_bindless_descriptor
*desc
)
1946 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1947 uint64_t va
= desc
->buffer
->gpu_address
+ desc
->offset
;
1948 unsigned num_dwords
= sizeof(desc
->desc_list
) / 4;
1950 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + num_dwords
, 0));
1951 radeon_emit(cs
, S_370_DST_SEL(V_370_TC_L2
) |
1952 S_370_WR_CONFIRM(1) |
1953 S_370_ENGINE_SEL(V_370_ME
));
1954 radeon_emit(cs
, va
);
1955 radeon_emit(cs
, va
>> 32);
1956 radeon_emit_array(cs
, desc
->desc_list
, num_dwords
);
1959 static void si_upload_bindless_descriptors(struct si_context
*sctx
)
1961 if (!sctx
->bindless_descriptors_dirty
)
1964 /* Wait for graphics/compute to be idle before updating the resident
1965 * descriptors directly in memory, in case the GPU is using them.
1967 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
1968 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1969 si_emit_cache_flush(sctx
);
1971 util_dynarray_foreach(&sctx
->resident_tex_handles
,
1972 struct si_texture_handle
*, tex_handle
) {
1973 struct si_bindless_descriptor
*desc
= (*tex_handle
)->desc
;
1978 si_upload_bindless_descriptor(sctx
, desc
);
1979 desc
->dirty
= false;
1982 util_dynarray_foreach(&sctx
->resident_img_handles
,
1983 struct si_image_handle
*, img_handle
) {
1984 struct si_bindless_descriptor
*desc
= (*img_handle
)->desc
;
1989 si_upload_bindless_descriptor(sctx
, desc
);
1990 desc
->dirty
= false;
1993 /* Invalidate L1 because it doesn't know that L2 changed. */
1994 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
;
1995 si_emit_cache_flush(sctx
);
1997 sctx
->bindless_descriptors_dirty
= false;
2000 /* Update mutable image descriptor fields of all resident textures. */
2001 static void si_update_all_resident_texture_descriptors(struct si_context
*sctx
)
2003 util_dynarray_foreach(&sctx
->resident_tex_handles
,
2004 struct si_texture_handle
*, tex_handle
) {
2005 struct si_bindless_descriptor
*desc
= (*tex_handle
)->desc
;
2006 struct si_sampler_view
*sview
=
2007 (struct si_sampler_view
*)(*tex_handle
)->view
;
2008 uint32_t desc_list
[16];
2010 if (sview
->base
.texture
->target
== PIPE_BUFFER
)
2013 memcpy(desc_list
, desc
->desc_list
, sizeof(desc_list
));
2014 si_set_sampler_view_desc(sctx
, sview
, &(*tex_handle
)->sstate
,
2015 &desc
->desc_list
[0]);
2017 if (memcmp(desc_list
, desc
->desc_list
, sizeof(desc_list
))) {
2019 sctx
->bindless_descriptors_dirty
= true;
2023 util_dynarray_foreach(&sctx
->resident_img_handles
,
2024 struct si_image_handle
*, img_handle
) {
2025 struct si_bindless_descriptor
*desc
= (*img_handle
)->desc
;
2026 struct pipe_image_view
*view
= &(*img_handle
)->view
;
2027 uint32_t desc_list
[16];
2029 if (view
->resource
->target
== PIPE_BUFFER
)
2032 memcpy(desc_list
, desc
->desc_list
, sizeof(desc_list
));
2033 si_set_shader_image_desc(sctx
, view
, true,
2034 &desc
->desc_list
[0]);
2036 if (memcmp(desc_list
, desc
->desc_list
, sizeof(desc_list
))) {
2038 sctx
->bindless_descriptors_dirty
= true;
2042 si_upload_bindless_descriptors(sctx
);
2045 /* Update mutable image descriptor fields of all bound textures. */
2046 void si_update_all_texture_descriptors(struct si_context
*sctx
)
2050 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
2051 struct si_sampler_views
*samplers
= &sctx
->samplers
[shader
].views
;
2052 struct si_images_info
*images
= &sctx
->images
[shader
];
2056 mask
= images
->enabled_mask
;
2058 unsigned i
= u_bit_scan(&mask
);
2059 struct pipe_image_view
*view
= &images
->views
[i
];
2061 if (!view
->resource
||
2062 view
->resource
->target
== PIPE_BUFFER
)
2065 si_set_shader_image(sctx
, shader
, i
, view
, true);
2068 /* Sampler views. */
2069 mask
= samplers
->enabled_mask
;
2071 unsigned i
= u_bit_scan(&mask
);
2072 struct pipe_sampler_view
*view
= samplers
->views
[i
];
2076 view
->texture
->target
== PIPE_BUFFER
)
2079 si_set_sampler_view(sctx
, shader
, i
,
2080 samplers
->views
[i
], true);
2083 si_update_shader_needs_decompress_mask(sctx
, shader
);
2086 si_update_all_resident_texture_descriptors(sctx
);
2089 /* SHADER USER DATA */
2091 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
,
2094 sctx
->shader_pointers_dirty
|=
2095 u_bit_consecutive(SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
,
2096 SI_NUM_SHADER_DESCS
);
2098 if (shader
== PIPE_SHADER_VERTEX
)
2099 sctx
->vertex_buffer_pointer_dirty
= sctx
->vertex_buffers
.buffer
!= NULL
;
2101 si_mark_atom_dirty(sctx
, &sctx
->shader_userdata
.atom
);
2104 static void si_shader_userdata_begin_new_cs(struct si_context
*sctx
)
2106 sctx
->shader_pointers_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2107 sctx
->vertex_buffer_pointer_dirty
= sctx
->vertex_buffers
.buffer
!= NULL
;
2108 si_mark_atom_dirty(sctx
, &sctx
->shader_userdata
.atom
);
2111 /* Set a base register address for user data constants in the given shader.
2112 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
2114 static void si_set_user_data_base(struct si_context
*sctx
,
2115 unsigned shader
, uint32_t new_base
)
2117 uint32_t *base
= &sctx
->shader_userdata
.sh_base
[shader
];
2119 if (*base
!= new_base
) {
2123 si_mark_shader_pointers_dirty(sctx
, shader
);
2125 if (shader
== PIPE_SHADER_VERTEX
)
2126 sctx
->last_vs_state
= ~0;
2131 /* This must be called when these shaders are changed from non-NULL to NULL
2134 * - tessellation control shader
2135 * - tessellation evaluation shader
2137 void si_shader_change_notify(struct si_context
*sctx
)
2139 /* VS can be bound as VS, ES, or LS. */
2140 if (sctx
->tes_shader
.cso
) {
2141 if (sctx
->b
.chip_class
>= GFX9
) {
2142 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2143 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2145 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2146 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2148 } else if (sctx
->gs_shader
.cso
) {
2149 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2150 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2152 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
2153 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2156 /* TES can be bound as ES, VS, or not bound. */
2157 if (sctx
->tes_shader
.cso
) {
2158 if (sctx
->gs_shader
.cso
)
2159 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2160 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2162 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
2163 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2165 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
2169 static void si_emit_shader_pointer(struct si_context
*sctx
,
2170 struct si_descriptors
*desc
,
2173 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2177 return; /* the pointer is not used by current shaders */
2179 va
= desc
->buffer
->gpu_address
+
2180 desc
->buffer_offset
;
2182 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, 2, 0));
2183 radeon_emit(cs
, (sh_base
+ desc
->shader_userdata_offset
- SI_SH_REG_OFFSET
) >> 2);
2184 radeon_emit(cs
, va
);
2185 radeon_emit(cs
, va
>> 32);
2188 void si_emit_graphics_shader_userdata(struct si_context
*sctx
,
2189 struct r600_atom
*atom
)
2192 uint32_t *sh_base
= sctx
->shader_userdata
.sh_base
;
2193 struct si_descriptors
*descs
;
2195 descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
2197 if (sctx
->shader_pointers_dirty
& (1 << SI_DESCS_RW_BUFFERS
)) {
2198 si_emit_shader_pointer(sctx
, descs
,
2199 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2200 si_emit_shader_pointer(sctx
, descs
,
2201 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2203 if (sctx
->b
.chip_class
>= GFX9
) {
2204 /* GFX9 merged LS-HS and ES-GS.
2205 * Set RW_BUFFERS in the special registers, so that
2206 * it's preloaded into s[0:1] instead of s[8:9].
2208 si_emit_shader_pointer(sctx
, descs
,
2209 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
);
2210 si_emit_shader_pointer(sctx
, descs
,
2211 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
);
2213 si_emit_shader_pointer(sctx
, descs
,
2214 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2215 si_emit_shader_pointer(sctx
, descs
,
2216 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2217 si_emit_shader_pointer(sctx
, descs
,
2218 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2219 si_emit_shader_pointer(sctx
, descs
,
2220 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
2224 mask
= sctx
->shader_pointers_dirty
&
2225 u_bit_consecutive(SI_DESCS_FIRST_SHADER
,
2226 SI_DESCS_FIRST_COMPUTE
- SI_DESCS_FIRST_SHADER
);
2229 unsigned i
= u_bit_scan(&mask
);
2230 unsigned shader
= (i
- SI_DESCS_FIRST_SHADER
) / SI_NUM_SHADER_DESCS
;
2231 unsigned base
= sh_base
[shader
];
2234 si_emit_shader_pointer(sctx
, descs
+ i
, base
);
2236 sctx
->shader_pointers_dirty
&=
2237 ~u_bit_consecutive(SI_DESCS_RW_BUFFERS
, SI_DESCS_FIRST_COMPUTE
);
2239 if (sctx
->vertex_buffer_pointer_dirty
) {
2240 si_emit_shader_pointer(sctx
, &sctx
->vertex_buffers
,
2241 sh_base
[PIPE_SHADER_VERTEX
]);
2242 sctx
->vertex_buffer_pointer_dirty
= false;
2246 void si_emit_compute_shader_userdata(struct si_context
*sctx
)
2248 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
2249 struct si_descriptors
*descs
= sctx
->descriptors
;
2250 unsigned compute_mask
=
2251 u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
, SI_NUM_SHADER_DESCS
);
2252 unsigned mask
= sctx
->shader_pointers_dirty
& compute_mask
;
2255 unsigned i
= u_bit_scan(&mask
);
2257 si_emit_shader_pointer(sctx
, descs
+ i
, base
);
2259 sctx
->shader_pointers_dirty
&= ~compute_mask
;
2264 struct si_bindless_descriptor_slab
2266 struct pb_slab base
;
2267 struct r600_resource
*buffer
;
2268 struct si_bindless_descriptor
*entries
;
2271 bool si_bindless_descriptor_can_reclaim_slab(void *priv
,
2272 struct pb_slab_entry
*entry
)
2274 /* Do not allow to reclaim any bindless descriptors for now because the
2275 * GPU might be using them. This should be improved later on.
2280 struct pb_slab
*si_bindless_descriptor_slab_alloc(void *priv
, unsigned heap
,
2281 unsigned entry_size
,
2282 unsigned group_index
)
2284 struct si_context
*sctx
= priv
;
2285 struct si_screen
*sscreen
= sctx
->screen
;
2286 struct si_bindless_descriptor_slab
*slab
;
2288 slab
= CALLOC_STRUCT(si_bindless_descriptor_slab
);
2292 /* Create a buffer in VRAM for 1024 bindless descriptors. */
2293 slab
->buffer
= (struct r600_resource
*)
2294 pipe_buffer_create(&sscreen
->b
.b
, 0,
2295 PIPE_USAGE_DEFAULT
, 64 * 1024);
2299 slab
->base
.num_entries
= slab
->buffer
->bo_size
/ entry_size
;
2300 slab
->base
.num_free
= slab
->base
.num_entries
;
2301 slab
->entries
= CALLOC(slab
->base
.num_entries
, sizeof(*slab
->entries
));
2305 LIST_INITHEAD(&slab
->base
.free
);
2307 for (unsigned i
= 0; i
< slab
->base
.num_entries
; ++i
) {
2308 struct si_bindless_descriptor
*desc
= &slab
->entries
[i
];
2310 desc
->entry
.slab
= &slab
->base
;
2311 desc
->entry
.group_index
= group_index
;
2312 desc
->buffer
= slab
->buffer
;
2313 desc
->offset
= i
* entry_size
;
2315 LIST_ADDTAIL(&desc
->entry
.head
, &slab
->base
.free
);
2318 /* Add the descriptor to the per-context list. */
2319 util_dynarray_append(&sctx
->bindless_descriptors
,
2320 struct r600_resource
*, slab
->buffer
);
2325 r600_resource_reference(&slab
->buffer
, NULL
);
2331 void si_bindless_descriptor_slab_free(void *priv
, struct pb_slab
*pslab
)
2333 struct si_context
*sctx
= priv
;
2334 struct si_bindless_descriptor_slab
*slab
=
2335 (struct si_bindless_descriptor_slab
*)pslab
;
2337 /* Remove the descriptor from the per-context list. */
2338 util_dynarray_delete_unordered(&sctx
->bindless_descriptors
,
2339 struct r600_resource
*, slab
->buffer
);
2341 r600_resource_reference(&slab
->buffer
, NULL
);
2342 FREE(slab
->entries
);
2346 static struct si_bindless_descriptor
*
2347 si_create_bindless_descriptor(struct si_context
*sctx
, uint32_t *desc_list
,
2350 struct si_screen
*sscreen
= sctx
->screen
;
2351 struct si_bindless_descriptor
*desc
;
2352 struct pb_slab_entry
*entry
;
2355 /* Sub-allocate the bindless descriptor from a slab to avoid dealing
2356 * with a ton of buffers and for reducing the winsys overhead.
2358 entry
= pb_slab_alloc(&sctx
->bindless_descriptor_slabs
, 64, 0);
2363 desc
= container_of(entry
, desc
, entry
);
2365 /* Upload the descriptor directly in VRAM. Because the slabs are
2366 * currently never reclaimed, we don't need to synchronize the
2369 ptr
= sscreen
->b
.ws
->buffer_map(desc
->buffer
->buf
, NULL
,
2370 PIPE_TRANSFER_WRITE
|
2371 PIPE_TRANSFER_UNSYNCHRONIZED
);
2372 util_memcpy_cpu_to_le32(ptr
+ desc
->offset
, desc_list
, size
);
2374 /* Keep track of the initial descriptor especially for buffers
2375 * invalidation because we might need to know the previous address.
2377 memcpy(desc
->desc_list
, desc_list
, sizeof(desc
->desc_list
));
2382 static void si_invalidate_bindless_buf_desc(struct si_context
*sctx
,
2383 struct si_bindless_descriptor
*desc
,
2384 struct pipe_resource
*resource
,
2387 struct r600_resource
*buf
= r600_resource(resource
);
2388 uint32_t *desc_list
= desc
->desc_list
+ 4;
2389 uint64_t old_desc_va
;
2391 assert(resource
->target
== PIPE_BUFFER
);
2393 /* Retrieve the old buffer addr from the descriptor. */
2394 old_desc_va
= desc_list
[0];
2395 old_desc_va
|= ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc_list
[1]) << 32);
2397 if (old_desc_va
!= buf
->gpu_address
+ offset
) {
2398 /* The buffer has been invalidated when the handle wasn't
2399 * resident, update the descriptor and the dirty flag.
2401 si_set_buf_desc_address(buf
, offset
, &desc_list
[0]);
2404 sctx
->bindless_descriptors_dirty
= true;
2408 static uint64_t si_create_texture_handle(struct pipe_context
*ctx
,
2409 struct pipe_sampler_view
*view
,
2410 const struct pipe_sampler_state
*state
)
2412 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
2413 struct si_context
*sctx
= (struct si_context
*)ctx
;
2414 struct si_texture_handle
*tex_handle
;
2415 struct si_sampler_state
*sstate
;
2416 uint32_t desc_list
[16];
2419 tex_handle
= CALLOC_STRUCT(si_texture_handle
);
2423 memset(desc_list
, 0, sizeof(desc_list
));
2424 si_init_descriptor_list(&desc_list
[0], 16, 1, null_texture_descriptor
);
2426 sstate
= ctx
->create_sampler_state(ctx
, state
);
2432 si_set_sampler_view_desc(sctx
, sview
, sstate
, &desc_list
[0]);
2433 memcpy(&tex_handle
->sstate
, sstate
, sizeof(*sstate
));
2434 ctx
->delete_sampler_state(ctx
, sstate
);
2436 tex_handle
->desc
= si_create_bindless_descriptor(sctx
, desc_list
,
2438 if (!tex_handle
->desc
) {
2443 handle
= tex_handle
->desc
->buffer
->gpu_address
+
2444 tex_handle
->desc
->offset
;
2446 if (!_mesa_hash_table_insert(sctx
->tex_handles
, (void *)handle
,
2448 pb_slab_free(&sctx
->bindless_descriptor_slabs
,
2449 &tex_handle
->desc
->entry
);
2454 pipe_sampler_view_reference(&tex_handle
->view
, view
);
2456 r600_resource(sview
->base
.texture
)->texture_handle_allocated
= true;
2461 static void si_delete_texture_handle(struct pipe_context
*ctx
, uint64_t handle
)
2463 struct si_context
*sctx
= (struct si_context
*)ctx
;
2464 struct si_texture_handle
*tex_handle
;
2465 struct hash_entry
*entry
;
2467 entry
= _mesa_hash_table_search(sctx
->tex_handles
, (void *)handle
);
2471 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2473 pipe_sampler_view_reference(&tex_handle
->view
, NULL
);
2474 _mesa_hash_table_remove(sctx
->tex_handles
, entry
);
2475 pb_slab_free(&sctx
->bindless_descriptor_slabs
,
2476 &tex_handle
->desc
->entry
);
2480 static void si_make_texture_handle_resident(struct pipe_context
*ctx
,
2481 uint64_t handle
, bool resident
)
2483 struct si_context
*sctx
= (struct si_context
*)ctx
;
2484 struct si_texture_handle
*tex_handle
;
2485 struct si_sampler_view
*sview
;
2486 struct hash_entry
*entry
;
2488 entry
= _mesa_hash_table_search(sctx
->tex_handles
, (void *)handle
);
2492 tex_handle
= (struct si_texture_handle
*)entry
->data
;
2493 sview
= (struct si_sampler_view
*)tex_handle
->view
;
2496 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2497 struct r600_texture
*rtex
=
2498 (struct r600_texture
*)sview
->base
.texture
;
2500 if (depth_needs_decompression(rtex
)) {
2501 util_dynarray_append(
2502 &sctx
->resident_tex_needs_depth_decompress
,
2503 struct si_texture_handle
*,
2507 if (color_needs_decompression(rtex
)) {
2508 util_dynarray_append(
2509 &sctx
->resident_tex_needs_color_decompress
,
2510 struct si_texture_handle
*,
2514 if (rtex
->dcc_offset
&&
2515 p_atomic_read(&rtex
->framebuffers_bound
))
2516 sctx
->need_check_render_feedback
= true;
2518 si_invalidate_bindless_buf_desc(sctx
, tex_handle
->desc
,
2519 sview
->base
.texture
,
2520 sview
->base
.u
.buf
.offset
);
2523 /* Add the texture handle to the per-context list. */
2524 util_dynarray_append(&sctx
->resident_tex_handles
,
2525 struct si_texture_handle
*, tex_handle
);
2527 /* Add the buffers to the current CS in case si_begin_new_cs()
2528 * is not going to be called.
2530 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2531 tex_handle
->desc
->buffer
,
2532 RADEON_USAGE_READWRITE
,
2533 RADEON_PRIO_DESCRIPTORS
);
2535 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2537 sview
->is_stencil_sampler
, false);
2539 /* Remove the texture handle from the per-context list. */
2540 util_dynarray_delete_unordered(&sctx
->resident_tex_handles
,
2541 struct si_texture_handle
*,
2544 if (sview
->base
.texture
->target
!= PIPE_BUFFER
) {
2545 util_dynarray_delete_unordered(
2546 &sctx
->resident_tex_needs_depth_decompress
,
2547 struct si_texture_handle
*, tex_handle
);
2549 util_dynarray_delete_unordered(
2550 &sctx
->resident_tex_needs_color_decompress
,
2551 struct si_texture_handle
*, tex_handle
);
2556 static uint64_t si_create_image_handle(struct pipe_context
*ctx
,
2557 const struct pipe_image_view
*view
)
2559 struct si_context
*sctx
= (struct si_context
*)ctx
;
2560 struct si_image_handle
*img_handle
;
2561 uint32_t desc_list
[16];
2564 if (!view
|| !view
->resource
)
2567 img_handle
= CALLOC_STRUCT(si_image_handle
);
2571 memset(desc_list
, 0, sizeof(desc_list
));
2572 si_init_descriptor_list(&desc_list
[0], 8, 1, null_image_descriptor
);
2574 si_set_shader_image_desc(sctx
, view
, false, &desc_list
[0]);
2576 img_handle
->desc
= si_create_bindless_descriptor(sctx
, desc_list
,
2578 if (!img_handle
->desc
) {
2583 handle
= img_handle
->desc
->buffer
->gpu_address
+
2584 img_handle
->desc
->offset
;
2586 if (!_mesa_hash_table_insert(sctx
->img_handles
, (void *)handle
,
2588 pb_slab_free(&sctx
->bindless_descriptor_slabs
,
2589 &img_handle
->desc
->entry
);
2594 util_copy_image_view(&img_handle
->view
, view
);
2596 r600_resource(view
->resource
)->image_handle_allocated
= true;
2601 static void si_delete_image_handle(struct pipe_context
*ctx
, uint64_t handle
)
2603 struct si_context
*sctx
= (struct si_context
*)ctx
;
2604 struct si_image_handle
*img_handle
;
2605 struct hash_entry
*entry
;
2607 entry
= _mesa_hash_table_search(sctx
->img_handles
, (void *)handle
);
2611 img_handle
= (struct si_image_handle
*)entry
->data
;
2613 util_copy_image_view(&img_handle
->view
, NULL
);
2614 _mesa_hash_table_remove(sctx
->img_handles
, entry
);
2615 pb_slab_free(&sctx
->bindless_descriptor_slabs
,
2616 &img_handle
->desc
->entry
);
2620 static void si_make_image_handle_resident(struct pipe_context
*ctx
,
2621 uint64_t handle
, unsigned access
,
2624 struct si_context
*sctx
= (struct si_context
*)ctx
;
2625 struct si_image_handle
*img_handle
;
2626 struct pipe_image_view
*view
;
2627 struct r600_resource
*res
;
2628 struct hash_entry
*entry
;
2630 entry
= _mesa_hash_table_search(sctx
->img_handles
, (void *)handle
);
2634 img_handle
= (struct si_image_handle
*)entry
->data
;
2635 view
= &img_handle
->view
;
2636 res
= (struct r600_resource
*)view
->resource
;
2639 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2640 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
2641 unsigned level
= view
->u
.tex
.level
;
2643 if (color_needs_decompression(rtex
)) {
2644 util_dynarray_append(
2645 &sctx
->resident_img_needs_color_decompress
,
2646 struct si_image_handle
*,
2650 if (vi_dcc_enabled(rtex
, level
) &&
2651 p_atomic_read(&rtex
->framebuffers_bound
))
2652 sctx
->need_check_render_feedback
= true;
2654 si_invalidate_bindless_buf_desc(sctx
, img_handle
->desc
,
2656 view
->u
.buf
.offset
);
2659 /* Add the image handle to the per-context list. */
2660 util_dynarray_append(&sctx
->resident_img_handles
,
2661 struct si_image_handle
*, img_handle
);
2663 /* Add the buffers to the current CS in case si_begin_new_cs()
2664 * is not going to be called.
2666 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2667 img_handle
->desc
->buffer
,
2668 RADEON_USAGE_READWRITE
,
2669 RADEON_PRIO_DESCRIPTORS
);
2671 si_sampler_view_add_buffer(sctx
, view
->resource
,
2672 (access
& PIPE_IMAGE_ACCESS_WRITE
) ?
2673 RADEON_USAGE_READWRITE
:
2674 RADEON_USAGE_READ
, false, false);
2676 /* Remove the image handle from the per-context list. */
2677 util_dynarray_delete_unordered(&sctx
->resident_img_handles
,
2678 struct si_image_handle
*,
2681 if (res
->b
.b
.target
!= PIPE_BUFFER
) {
2682 util_dynarray_delete_unordered(
2683 &sctx
->resident_img_needs_color_decompress
,
2684 struct si_image_handle
*,
2691 void si_all_resident_buffers_begin_new_cs(struct si_context
*sctx
)
2693 unsigned num_resident_tex_handles
, num_resident_img_handles
;
2695 num_resident_tex_handles
= sctx
->resident_tex_handles
.size
/
2696 sizeof(struct si_texture_handle
*);
2697 num_resident_img_handles
= sctx
->resident_img_handles
.size
/
2698 sizeof(struct si_image_handle
*);
2700 /* Skip adding the bindless descriptors when no handles are resident.
2702 if (!num_resident_tex_handles
&& !num_resident_img_handles
)
2705 /* Add all bindless descriptors. */
2706 util_dynarray_foreach(&sctx
->bindless_descriptors
,
2707 struct r600_resource
*, desc
) {
2709 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, *desc
,
2710 RADEON_USAGE_READWRITE
,
2711 RADEON_PRIO_DESCRIPTORS
);
2714 /* Add all resident texture handles. */
2715 util_dynarray_foreach(&sctx
->resident_tex_handles
,
2716 struct si_texture_handle
*, tex_handle
) {
2717 struct si_sampler_view
*sview
=
2718 (struct si_sampler_view
*)(*tex_handle
)->view
;
2720 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
2722 sview
->is_stencil_sampler
, false);
2725 /* Add all resident image handles. */
2726 util_dynarray_foreach(&sctx
->resident_img_handles
,
2727 struct si_image_handle
*, img_handle
) {
2728 struct pipe_image_view
*view
= &(*img_handle
)->view
;
2730 si_sampler_view_add_buffer(sctx
, view
->resource
,
2731 RADEON_USAGE_READWRITE
,
2735 sctx
->b
.num_resident_handles
+= num_resident_tex_handles
+
2736 num_resident_img_handles
;
2739 /* INIT/DEINIT/UPLOAD */
2741 /* GFX9 has only 4KB of CE, while previous chips had 32KB. In order
2742 * to make CE RAM as useful as possible, this defines limits
2743 * for the number slots that can be in CE RAM on GFX9. If a shader
2744 * is using more, descriptors will be uploaded to memory directly and
2747 * These numbers are based on shader-db.
2749 static unsigned gfx9_max_ce_samplers
[SI_NUM_SHADERS
] = {
2750 [PIPE_SHADER_VERTEX
] = 0,
2751 [PIPE_SHADER_TESS_CTRL
] = 0,
2752 [PIPE_SHADER_TESS_EVAL
] = 1,
2753 [PIPE_SHADER_GEOMETRY
] = 0,
2754 [PIPE_SHADER_FRAGMENT
] = 24,
2755 [PIPE_SHADER_COMPUTE
] = 16,
2757 static unsigned gfx9_max_ce_images
[SI_NUM_SHADERS
] = {
2758 /* these must be even due to slot alignment */
2759 [PIPE_SHADER_VERTEX
] = 0,
2760 [PIPE_SHADER_TESS_CTRL
] = 0,
2761 [PIPE_SHADER_TESS_EVAL
] = 0,
2762 [PIPE_SHADER_GEOMETRY
] = 0,
2763 [PIPE_SHADER_FRAGMENT
] = 2,
2764 [PIPE_SHADER_COMPUTE
] = 8,
2766 static unsigned gfx9_max_ce_const_buffers
[SI_NUM_SHADERS
] = {
2767 [PIPE_SHADER_VERTEX
] = 9,
2768 [PIPE_SHADER_TESS_CTRL
] = 3,
2769 [PIPE_SHADER_TESS_EVAL
] = 5,
2770 [PIPE_SHADER_GEOMETRY
] = 0,
2771 [PIPE_SHADER_FRAGMENT
] = 8,
2772 [PIPE_SHADER_COMPUTE
] = 6,
2774 static unsigned gfx9_max_ce_shader_buffers
[SI_NUM_SHADERS
] = {
2775 [PIPE_SHADER_VERTEX
] = 0,
2776 [PIPE_SHADER_TESS_CTRL
] = 0,
2777 [PIPE_SHADER_TESS_EVAL
] = 0,
2778 [PIPE_SHADER_GEOMETRY
] = 0,
2779 [PIPE_SHADER_FRAGMENT
] = 12,
2780 [PIPE_SHADER_COMPUTE
] = 13,
2783 void si_init_all_descriptors(struct si_context
*sctx
)
2786 unsigned ce_offset
= 0;
2788 STATIC_ASSERT(GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS
% 2 == 0);
2789 STATIC_ASSERT(GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS
% 2 == 0);
2791 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2792 bool gfx9_tcs
= false;
2793 bool gfx9_gs
= false;
2794 unsigned num_sampler_slots
= SI_NUM_IMAGES
/ 2 + SI_NUM_SAMPLERS
;
2795 unsigned num_buffer_slots
= SI_NUM_SHADER_BUFFERS
+ SI_NUM_CONST_BUFFERS
;
2797 unsigned first_sampler_ce_slot
= 0;
2798 unsigned num_sampler_ce_slots
= num_sampler_slots
;
2800 unsigned first_buffer_ce_slot
= 0;
2801 unsigned num_buffer_ce_slots
= num_buffer_slots
;
2803 /* Adjust CE slot ranges based on GFX9 CE RAM limits. */
2804 if (sctx
->b
.chip_class
>= GFX9
) {
2805 gfx9_tcs
= i
== PIPE_SHADER_TESS_CTRL
;
2806 gfx9_gs
= i
== PIPE_SHADER_GEOMETRY
;
2808 first_sampler_ce_slot
=
2809 si_get_image_slot(gfx9_max_ce_images
[i
] - 1) / 2;
2810 num_sampler_ce_slots
= gfx9_max_ce_images
[i
] / 2 +
2811 gfx9_max_ce_samplers
[i
];
2813 first_buffer_ce_slot
=
2814 si_get_shaderbuf_slot(gfx9_max_ce_shader_buffers
[i
] - 1);
2815 num_buffer_ce_slots
= gfx9_max_ce_shader_buffers
[i
] +
2816 gfx9_max_ce_const_buffers
[i
];
2819 si_init_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[i
],
2820 si_const_and_shader_buffer_descriptors(sctx
, i
),
2822 first_buffer_ce_slot
, num_buffer_ce_slots
,
2823 gfx9_tcs
? GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS
:
2824 gfx9_gs
? GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS
:
2825 SI_SGPR_CONST_AND_SHADER_BUFFERS
,
2826 RADEON_USAGE_READWRITE
,
2828 RADEON_PRIO_SHADER_RW_BUFFER
,
2829 RADEON_PRIO_CONST_BUFFER
,
2832 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, i
);
2833 si_init_descriptors(sctx
, desc
,
2834 gfx9_tcs
? GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES
:
2835 gfx9_gs
? GFX9_SGPR_GS_SAMPLERS_AND_IMAGES
:
2836 SI_SGPR_SAMPLERS_AND_IMAGES
,
2837 16, num_sampler_slots
,
2838 first_sampler_ce_slot
, num_sampler_ce_slots
,
2842 for (j
= 0; j
< SI_NUM_IMAGES
; j
++)
2843 memcpy(desc
->list
+ j
* 8, null_image_descriptor
, 8 * 4);
2844 for (; j
< SI_NUM_IMAGES
+ SI_NUM_SAMPLERS
* 2; j
++)
2845 memcpy(desc
->list
+ j
* 8, null_texture_descriptor
, 8 * 4);
2848 si_init_buffer_resources(sctx
, &sctx
->rw_buffers
,
2849 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
2850 SI_NUM_RW_BUFFERS
, 0, SI_NUM_RW_BUFFERS
,
2852 /* The second set of usage/priority is used by
2853 * const buffers in RW buffer slots. */
2854 RADEON_USAGE_READWRITE
, RADEON_USAGE_READ
,
2855 RADEON_PRIO_SHADER_RINGS
, RADEON_PRIO_CONST_BUFFER
,
2857 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
= SI_NUM_RW_BUFFERS
;
2859 si_init_descriptors(sctx
, &sctx
->vertex_buffers
, SI_SGPR_VERTEX_BUFFERS
,
2860 4, SI_NUM_VERTEX_BUFFERS
, 0, 0, NULL
);
2861 FREE(sctx
->vertex_buffers
.list
); /* not used */
2862 sctx
->vertex_buffers
.list
= NULL
;
2864 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2865 sctx
->total_ce_ram_allocated
= ce_offset
;
2867 assert(ce_offset
<= si_ce_ram_size(sctx
));
2869 /* Set pipe_context functions. */
2870 sctx
->b
.b
.bind_sampler_states
= si_bind_sampler_states
;
2871 sctx
->b
.b
.set_shader_images
= si_set_shader_images
;
2872 sctx
->b
.b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
2873 sctx
->b
.b
.set_polygon_stipple
= si_set_polygon_stipple
;
2874 sctx
->b
.b
.set_shader_buffers
= si_set_shader_buffers
;
2875 sctx
->b
.b
.set_sampler_views
= si_set_sampler_views
;
2876 sctx
->b
.b
.set_stream_output_targets
= si_set_streamout_targets
;
2877 sctx
->b
.b
.create_texture_handle
= si_create_texture_handle
;
2878 sctx
->b
.b
.delete_texture_handle
= si_delete_texture_handle
;
2879 sctx
->b
.b
.make_texture_handle_resident
= si_make_texture_handle_resident
;
2880 sctx
->b
.b
.create_image_handle
= si_create_image_handle
;
2881 sctx
->b
.b
.delete_image_handle
= si_delete_image_handle
;
2882 sctx
->b
.b
.make_image_handle_resident
= si_make_image_handle_resident
;
2883 sctx
->b
.invalidate_buffer
= si_invalidate_buffer
;
2884 sctx
->b
.rebind_buffer
= si_rebind_buffer
;
2886 /* Shader user data. */
2887 si_init_atom(sctx
, &sctx
->shader_userdata
.atom
, &sctx
->atoms
.s
.shader_userdata
,
2888 si_emit_graphics_shader_userdata
);
2890 /* Set default and immutable mappings. */
2891 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2893 if (sctx
->b
.chip_class
>= GFX9
) {
2894 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2895 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2896 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2897 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2899 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2900 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2901 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2902 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2904 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2907 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
2909 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
2910 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2912 /* Assume nothing will go wrong: */
2913 sctx
->shader_pointers_dirty
|= dirty
;
2916 unsigned i
= u_bit_scan(&dirty
);
2918 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
],
2919 &sctx
->shader_userdata
.atom
))
2923 sctx
->descriptors_dirty
&= ~mask
;
2925 si_upload_bindless_descriptors(sctx
);
2930 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
2932 /* Does not update rw_buffers as that is not needed for compute shaders
2933 * and the input buffer is using the same SGPR's anyway.
2935 const unsigned mask
= u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
,
2936 SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
2937 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2939 /* Assume nothing will go wrong: */
2940 sctx
->shader_pointers_dirty
|= dirty
;
2943 unsigned i
= u_bit_scan(&dirty
);
2945 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
], NULL
))
2949 sctx
->descriptors_dirty
&= ~mask
;
2951 si_upload_bindless_descriptors(sctx
);
2956 void si_release_all_descriptors(struct si_context
*sctx
)
2960 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2961 si_release_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2962 si_const_and_shader_buffer_descriptors(sctx
, i
));
2963 si_release_sampler_views(&sctx
->samplers
[i
].views
);
2964 si_release_image_views(&sctx
->images
[i
]);
2966 si_release_buffer_resources(&sctx
->rw_buffers
,
2967 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2968 for (i
= 0; i
< SI_NUM_VERTEX_BUFFERS
; i
++)
2969 pipe_vertex_buffer_unreference(&sctx
->vertex_buffer
[i
]);
2971 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2972 si_release_descriptors(&sctx
->descriptors
[i
]);
2974 sctx
->vertex_buffers
.list
= NULL
; /* points into a mapped buffer */
2975 si_release_descriptors(&sctx
->vertex_buffers
);
2978 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
2982 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2983 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2984 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
].views
);
2985 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
2987 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2988 si_vertex_buffers_begin_new_cs(sctx
);
2990 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2991 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
2993 si_shader_userdata_begin_new_cs(sctx
);
2996 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
2997 uint64_t new_active_mask
)
2999 struct si_descriptors
*desc
= &sctx
->descriptors
[desc_idx
];
3001 /* Ignore no-op updates and updates that disable all slots. */
3002 if (!new_active_mask
||
3003 new_active_mask
== u_bit_consecutive64(desc
->first_active_slot
,
3004 desc
->num_active_slots
))
3008 u_bit_scan_consecutive_range64(&new_active_mask
, &first
, &count
);
3009 assert(new_active_mask
== 0);
3011 /* Upload/dump descriptors if slots are being enabled. */
3012 if (first
< desc
->first_active_slot
||
3013 first
+ count
> desc
->first_active_slot
+ desc
->num_active_slots
)
3014 sctx
->descriptors_dirty
|= 1u << desc_idx
;
3016 /* Enable or disable CE for this descriptor array. */
3017 bool used_ce
= desc
->uses_ce
;
3018 desc
->uses_ce
= desc
->first_ce_slot
<= first
&&
3019 desc
->first_ce_slot
+ desc
->num_ce_slots
>= first
+ count
;
3021 if (desc
->uses_ce
!= used_ce
) {
3022 /* Upload or dump descriptors if we're disabling or enabling CE,
3024 sctx
->descriptors_dirty
|= 1u << desc_idx
;
3026 /* If we're enabling CE, re-upload all descriptors to CE RAM.
3027 * When CE was disabled, uploads to CE RAM stopped.
3029 if (desc
->uses_ce
) {
3031 u_bit_consecutive64(desc
->first_ce_slot
,
3032 desc
->num_ce_slots
);
3036 desc
->first_active_slot
= first
;
3037 desc
->num_active_slots
= count
;
3040 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
3041 struct si_shader_selector
*sel
)
3046 si_set_active_descriptors(sctx
,
3047 si_const_and_shader_buffer_descriptors_idx(sel
->type
),
3048 sel
->active_const_and_shader_buffers
);
3049 si_set_active_descriptors(sctx
,
3050 si_sampler_and_image_descriptors_idx(sel
->type
),
3051 sel
->active_samplers_and_images
);