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radeonsi: add si_get_shader_buffers/get_pipe_constant_buffers (v2)
[mesa.git] / src / gallium / drivers / radeonsi / si_descriptors.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Marek Olšák <marek.olsak@amd.com>
25 */
26
27 /* Resource binding slots and sampler states (each described with 8 or
28 * 4 dwords) are stored in lists in memory which is accessed by shaders
29 * using scalar load instructions.
30 *
31 * This file is responsible for managing such lists. It keeps a copy of all
32 * descriptors in CPU memory and re-uploads a whole list if some slots have
33 * been changed.
34 *
35 * This code is also reponsible for updating shader pointers to those lists.
36 *
37 * Note that CP DMA can't be used for updating the lists, because a GPU hang
38 * could leave the list in a mid-IB state and the next IB would get wrong
39 * descriptors and the whole context would be unusable at that point.
40 * (Note: The register shadowing can't be used due to the same reason)
41 *
42 * Also, uploading descriptors to newly allocated memory doesn't require
43 * a KCACHE flush.
44 *
45 *
46 * Possible scenarios for one 16 dword image+sampler slot:
47 *
48 * | Image | w/ FMASK | Buffer | NULL
49 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
50 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
51 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
52 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
53 *
54 * FMASK implies MSAA, therefore no sampler state.
55 * Sampler states are never unbound except when FMASK is bound.
56 */
57
58 #include "radeon/r600_cs.h"
59 #include "si_pipe.h"
60 #include "si_shader.h"
61 #include "sid.h"
62
63 #include "util/u_format.h"
64 #include "util/u_math.h"
65 #include "util/u_memory.h"
66 #include "util/u_suballoc.h"
67 #include "util/u_upload_mgr.h"
68
69
70 /* NULL image and buffer descriptor for textures (alpha = 1) and images
71 * (alpha = 0).
72 *
73 * For images, all fields must be zero except for the swizzle, which
74 * supports arbitrary combinations of 0s and 1s. The texture type must be
75 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
76 *
77 * For buffers, all fields must be zero. If they are not, the hw hangs.
78 *
79 * This is the only reason why the buffer descriptor must be in words [4:7].
80 */
81 static uint32_t null_texture_descriptor[8] = {
82 0,
83 0,
84 0,
85 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1) |
86 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
87 /* the rest must contain zeros, which is also used by the buffer
88 * descriptor */
89 };
90
91 static uint32_t null_image_descriptor[8] = {
92 0,
93 0,
94 0,
95 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
96 /* the rest must contain zeros, which is also used by the buffer
97 * descriptor */
98 };
99
100 static void si_init_descriptors(struct si_descriptors *desc,
101 unsigned shader_userdata_index,
102 unsigned element_dw_size,
103 unsigned num_elements,
104 const uint32_t *null_descriptor,
105 unsigned *ce_offset)
106 {
107 int i;
108
109 assert(num_elements <= sizeof(desc->dirty_mask)*8);
110
111 desc->list = CALLOC(num_elements, element_dw_size * 4);
112 desc->element_dw_size = element_dw_size;
113 desc->num_elements = num_elements;
114 desc->dirty_mask = num_elements == 32 ? ~0u : (1u << num_elements) - 1;
115 desc->shader_userdata_offset = shader_userdata_index * 4;
116
117 if (ce_offset) {
118 desc->ce_offset = *ce_offset;
119
120 /* make sure that ce_offset stays 32 byte aligned */
121 *ce_offset += align(element_dw_size * num_elements * 4, 32);
122 }
123
124 /* Initialize the array to NULL descriptors if the element size is 8. */
125 if (null_descriptor) {
126 assert(element_dw_size % 8 == 0);
127 for (i = 0; i < num_elements * element_dw_size / 8; i++)
128 memcpy(desc->list + i * 8, null_descriptor,
129 8 * 4);
130 }
131 }
132
133 static void si_release_descriptors(struct si_descriptors *desc)
134 {
135 r600_resource_reference(&desc->buffer, NULL);
136 FREE(desc->list);
137 }
138
139 static bool si_ce_upload(struct si_context *sctx, unsigned ce_offset, unsigned size,
140 unsigned *out_offset, struct r600_resource **out_buf) {
141 uint64_t va;
142
143 u_suballocator_alloc(sctx->ce_suballocator, size, 64, out_offset,
144 (struct pipe_resource**)out_buf);
145 if (!out_buf)
146 return false;
147
148 va = (*out_buf)->gpu_address + *out_offset;
149
150 radeon_emit(sctx->ce_ib, PKT3(PKT3_DUMP_CONST_RAM, 3, 0));
151 radeon_emit(sctx->ce_ib, ce_offset);
152 radeon_emit(sctx->ce_ib, size / 4);
153 radeon_emit(sctx->ce_ib, va);
154 radeon_emit(sctx->ce_ib, va >> 32);
155
156 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, *out_buf,
157 RADEON_USAGE_READWRITE, RADEON_PRIO_DESCRIPTORS);
158
159 sctx->ce_need_synchronization = true;
160 return true;
161 }
162
163 static void si_ce_reinitialize_descriptors(struct si_context *sctx,
164 struct si_descriptors *desc)
165 {
166 if (desc->buffer) {
167 struct r600_resource *buffer = (struct r600_resource*)desc->buffer;
168 unsigned list_size = desc->num_elements * desc->element_dw_size * 4;
169 uint64_t va = buffer->gpu_address + desc->buffer_offset;
170 struct radeon_winsys_cs *ib = sctx->ce_preamble_ib;
171
172 if (!ib)
173 ib = sctx->ce_ib;
174
175 list_size = align(list_size, 32);
176
177 radeon_emit(ib, PKT3(PKT3_LOAD_CONST_RAM, 3, 0));
178 radeon_emit(ib, va);
179 radeon_emit(ib, va >> 32);
180 radeon_emit(ib, list_size / 4);
181 radeon_emit(ib, desc->ce_offset);
182
183 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
184 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
185 }
186 desc->ce_ram_dirty = false;
187 }
188
189 void si_ce_reinitialize_all_descriptors(struct si_context *sctx)
190 {
191 int i;
192
193 for (i = 0; i < SI_NUM_DESCS; ++i)
194 si_ce_reinitialize_descriptors(sctx, &sctx->descriptors[i]);
195 }
196
197 void si_ce_enable_loads(struct radeon_winsys_cs *ib)
198 {
199 radeon_emit(ib, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
200 radeon_emit(ib, CONTEXT_CONTROL_LOAD_ENABLE(1) |
201 CONTEXT_CONTROL_LOAD_CE_RAM(1));
202 radeon_emit(ib, CONTEXT_CONTROL_SHADOW_ENABLE(1));
203 }
204
205 static bool si_upload_descriptors(struct si_context *sctx,
206 struct si_descriptors *desc,
207 struct r600_atom * atom)
208 {
209 unsigned list_size = desc->num_elements * desc->element_dw_size * 4;
210
211 if (!desc->dirty_mask)
212 return true;
213
214 if (sctx->ce_ib) {
215 uint32_t const* list = (uint32_t const*)desc->list;
216
217 if (desc->ce_ram_dirty)
218 si_ce_reinitialize_descriptors(sctx, desc);
219
220 while(desc->dirty_mask) {
221 int begin, count;
222 u_bit_scan_consecutive_range(&desc->dirty_mask, &begin,
223 &count);
224
225 begin *= desc->element_dw_size;
226 count *= desc->element_dw_size;
227
228 radeon_emit(sctx->ce_ib,
229 PKT3(PKT3_WRITE_CONST_RAM, count, 0));
230 radeon_emit(sctx->ce_ib, desc->ce_offset + begin * 4);
231 radeon_emit_array(sctx->ce_ib, list + begin, count);
232 }
233
234 if (!si_ce_upload(sctx, desc->ce_offset, list_size,
235 &desc->buffer_offset, &desc->buffer))
236 return false;
237 } else {
238 void *ptr;
239
240 u_upload_alloc(sctx->b.uploader, 0, list_size, 256,
241 &desc->buffer_offset,
242 (struct pipe_resource**)&desc->buffer, &ptr);
243 if (!desc->buffer)
244 return false; /* skip the draw call */
245
246 util_memcpy_cpu_to_le32(ptr, desc->list, list_size);
247
248 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
249 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
250 }
251 desc->pointer_dirty = true;
252 desc->dirty_mask = 0;
253
254 if (atom)
255 si_mark_atom_dirty(sctx, atom);
256
257 return true;
258 }
259
260 static void
261 si_descriptors_begin_new_cs(struct si_context *sctx, struct si_descriptors *desc)
262 {
263 desc->ce_ram_dirty = true;
264
265 if (!desc->buffer)
266 return;
267
268 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
269 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
270 }
271
272 /* SAMPLER VIEWS */
273
274 static unsigned
275 si_sampler_descriptors_idx(unsigned shader)
276 {
277 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
278 SI_SHADER_DESCS_SAMPLERS;
279 }
280
281 static struct si_descriptors *
282 si_sampler_descriptors(struct si_context *sctx, unsigned shader)
283 {
284 return &sctx->descriptors[si_sampler_descriptors_idx(shader)];
285 }
286
287 static void si_release_sampler_views(struct si_sampler_views *views)
288 {
289 int i;
290
291 for (i = 0; i < ARRAY_SIZE(views->views); i++) {
292 pipe_sampler_view_reference(&views->views[i], NULL);
293 }
294 }
295
296 static void si_sampler_view_add_buffer(struct si_context *sctx,
297 struct pipe_resource *resource,
298 enum radeon_bo_usage usage,
299 bool is_stencil_sampler,
300 bool check_mem)
301 {
302 struct r600_resource *rres;
303 struct r600_texture *rtex;
304 enum radeon_bo_priority priority;
305
306 if (!resource)
307 return;
308
309 if (resource->target != PIPE_BUFFER) {
310 struct r600_texture *tex = (struct r600_texture*)resource;
311
312 if (tex->is_depth && !r600_can_sample_zs(tex, is_stencil_sampler))
313 resource = &tex->flushed_depth_texture->resource.b.b;
314 }
315
316 rres = (struct r600_resource*)resource;
317 priority = r600_get_sampler_view_priority(rres);
318
319 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
320 rres, usage, priority,
321 check_mem);
322
323 if (resource->target == PIPE_BUFFER)
324 return;
325
326 /* Now add separate DCC if it's present. */
327 rtex = (struct r600_texture*)resource;
328 if (!rtex->dcc_separate_buffer)
329 return;
330
331 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
332 rtex->dcc_separate_buffer, usage,
333 RADEON_PRIO_DCC, check_mem);
334 }
335
336 static void si_sampler_views_begin_new_cs(struct si_context *sctx,
337 struct si_sampler_views *views)
338 {
339 unsigned mask = views->enabled_mask;
340
341 /* Add buffers to the CS. */
342 while (mask) {
343 int i = u_bit_scan(&mask);
344 struct si_sampler_view *sview = (struct si_sampler_view *)views->views[i];
345
346 si_sampler_view_add_buffer(sctx, sview->base.texture,
347 RADEON_USAGE_READ,
348 sview->is_stencil_sampler, false);
349 }
350 }
351
352 /* Set texture descriptor fields that can be changed by reallocations.
353 *
354 * \param tex texture
355 * \param base_level_info information of the level of BASE_ADDRESS
356 * \param base_level the level of BASE_ADDRESS
357 * \param first_level pipe_sampler_view.u.tex.first_level
358 * \param block_width util_format_get_blockwidth()
359 * \param is_stencil select between separate Z & Stencil
360 * \param state descriptor to update
361 */
362 void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
363 const struct radeon_surf_level *base_level_info,
364 unsigned base_level, unsigned first_level,
365 unsigned block_width, bool is_stencil,
366 uint32_t *state)
367 {
368 uint64_t va;
369 unsigned pitch = base_level_info->nblk_x * block_width;
370
371 if (tex->is_depth && !r600_can_sample_zs(tex, is_stencil)) {
372 tex = tex->flushed_depth_texture;
373 is_stencil = false;
374 }
375
376 va = tex->resource.gpu_address + base_level_info->offset;
377
378 state[1] &= C_008F14_BASE_ADDRESS_HI;
379 state[3] &= C_008F1C_TILING_INDEX;
380 state[4] &= C_008F20_PITCH;
381 state[6] &= C_008F28_COMPRESSION_EN;
382
383 state[0] = va >> 8;
384 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
385 state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(tex, base_level,
386 is_stencil));
387 state[4] |= S_008F20_PITCH(pitch - 1);
388
389 if (tex->dcc_offset && tex->surface.level[first_level].dcc_enabled) {
390 state[6] |= S_008F28_COMPRESSION_EN(1);
391 state[7] = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
392 tex->dcc_offset +
393 base_level_info->dcc_offset) >> 8;
394 }
395 }
396
397 static void si_set_sampler_view(struct si_context *sctx,
398 unsigned shader,
399 unsigned slot, struct pipe_sampler_view *view,
400 bool disallow_early_out)
401 {
402 struct si_sampler_views *views = &sctx->samplers[shader].views;
403 struct si_sampler_view *rview = (struct si_sampler_view*)view;
404 struct si_descriptors *descs = si_sampler_descriptors(sctx, shader);
405
406 if (views->views[slot] == view && !disallow_early_out)
407 return;
408
409 if (view) {
410 struct r600_texture *rtex = (struct r600_texture *)view->texture;
411 uint32_t *desc = descs->list + slot * 16;
412
413 pipe_sampler_view_reference(&views->views[slot], view);
414 memcpy(desc, rview->state, 8*4);
415
416 if (view->texture && view->texture->target != PIPE_BUFFER) {
417 bool is_separate_stencil =
418 rtex->db_compatible &&
419 rview->is_stencil_sampler;
420
421 si_set_mutable_tex_desc_fields(rtex,
422 rview->base_level_info,
423 rview->base_level,
424 rview->base.u.tex.first_level,
425 rview->block_width,
426 is_separate_stencil,
427 desc);
428 }
429
430 if (view->texture && view->texture->target != PIPE_BUFFER &&
431 rtex->fmask.size) {
432 memcpy(desc + 8,
433 rview->fmask_state, 8*4);
434 } else {
435 /* Disable FMASK and bind sampler state in [12:15]. */
436 memcpy(desc + 8,
437 null_texture_descriptor, 4*4);
438
439 if (views->sampler_states[slot])
440 memcpy(desc + 12,
441 views->sampler_states[slot], 4*4);
442 }
443
444 views->enabled_mask |= 1u << slot;
445
446 /* Since this can flush, it must be done after enabled_mask is
447 * updated. */
448 si_sampler_view_add_buffer(sctx, view->texture,
449 RADEON_USAGE_READ,
450 rview->is_stencil_sampler, true);
451 } else {
452 pipe_sampler_view_reference(&views->views[slot], NULL);
453 memcpy(descs->list + slot*16, null_texture_descriptor, 8*4);
454 /* Only clear the lower dwords of FMASK. */
455 memcpy(descs->list + slot*16 + 8, null_texture_descriptor, 4*4);
456 views->enabled_mask &= ~(1u << slot);
457 }
458
459 descs->dirty_mask |= 1u << slot;
460 sctx->descriptors_dirty |= 1u << si_sampler_descriptors_idx(shader);
461 }
462
463 static bool is_compressed_colortex(struct r600_texture *rtex)
464 {
465 return rtex->cmask.size || rtex->fmask.size ||
466 (rtex->dcc_offset && rtex->dirty_level_mask);
467 }
468
469 static void si_set_sampler_views(struct pipe_context *ctx,
470 enum pipe_shader_type shader, unsigned start,
471 unsigned count,
472 struct pipe_sampler_view **views)
473 {
474 struct si_context *sctx = (struct si_context *)ctx;
475 struct si_textures_info *samplers = &sctx->samplers[shader];
476 int i;
477
478 if (!count || shader >= SI_NUM_SHADERS)
479 return;
480
481 for (i = 0; i < count; i++) {
482 unsigned slot = start + i;
483
484 if (!views || !views[i]) {
485 samplers->depth_texture_mask &= ~(1u << slot);
486 samplers->compressed_colortex_mask &= ~(1u << slot);
487 si_set_sampler_view(sctx, shader, slot, NULL, false);
488 continue;
489 }
490
491 si_set_sampler_view(sctx, shader, slot, views[i], false);
492
493 if (views[i]->texture && views[i]->texture->target != PIPE_BUFFER) {
494 struct r600_texture *rtex =
495 (struct r600_texture*)views[i]->texture;
496
497 if (rtex->db_compatible) {
498 samplers->depth_texture_mask |= 1u << slot;
499 } else {
500 samplers->depth_texture_mask &= ~(1u << slot);
501 }
502 if (is_compressed_colortex(rtex)) {
503 samplers->compressed_colortex_mask |= 1u << slot;
504 } else {
505 samplers->compressed_colortex_mask &= ~(1u << slot);
506 }
507
508 if (rtex->dcc_offset &&
509 p_atomic_read(&rtex->framebuffers_bound))
510 sctx->need_check_render_feedback = true;
511 } else {
512 samplers->depth_texture_mask &= ~(1u << slot);
513 samplers->compressed_colortex_mask &= ~(1u << slot);
514 }
515 }
516 }
517
518 static void
519 si_samplers_update_compressed_colortex_mask(struct si_textures_info *samplers)
520 {
521 unsigned mask = samplers->views.enabled_mask;
522
523 while (mask) {
524 int i = u_bit_scan(&mask);
525 struct pipe_resource *res = samplers->views.views[i]->texture;
526
527 if (res && res->target != PIPE_BUFFER) {
528 struct r600_texture *rtex = (struct r600_texture *)res;
529
530 if (is_compressed_colortex(rtex)) {
531 samplers->compressed_colortex_mask |= 1u << i;
532 } else {
533 samplers->compressed_colortex_mask &= ~(1u << i);
534 }
535 }
536 }
537 }
538
539 /* IMAGE VIEWS */
540
541 static unsigned
542 si_image_descriptors_idx(unsigned shader)
543 {
544 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
545 SI_SHADER_DESCS_IMAGES;
546 }
547
548 static struct si_descriptors*
549 si_image_descriptors(struct si_context *sctx, unsigned shader)
550 {
551 return &sctx->descriptors[si_image_descriptors_idx(shader)];
552 }
553
554 static void
555 si_release_image_views(struct si_images_info *images)
556 {
557 unsigned i;
558
559 for (i = 0; i < SI_NUM_IMAGES; ++i) {
560 struct pipe_image_view *view = &images->views[i];
561
562 pipe_resource_reference(&view->resource, NULL);
563 }
564 }
565
566 static void
567 si_image_views_begin_new_cs(struct si_context *sctx, struct si_images_info *images)
568 {
569 uint mask = images->enabled_mask;
570
571 /* Add buffers to the CS. */
572 while (mask) {
573 int i = u_bit_scan(&mask);
574 struct pipe_image_view *view = &images->views[i];
575
576 assert(view->resource);
577
578 si_sampler_view_add_buffer(sctx, view->resource,
579 RADEON_USAGE_READWRITE, false, false);
580 }
581 }
582
583 static void
584 si_disable_shader_image(struct si_context *ctx, unsigned shader, unsigned slot)
585 {
586 struct si_images_info *images = &ctx->images[shader];
587
588 if (images->enabled_mask & (1u << slot)) {
589 struct si_descriptors *descs = si_image_descriptors(ctx, shader);
590
591 pipe_resource_reference(&images->views[slot].resource, NULL);
592 images->compressed_colortex_mask &= ~(1 << slot);
593
594 memcpy(descs->list + slot*8, null_image_descriptor, 8*4);
595 images->enabled_mask &= ~(1u << slot);
596 descs->dirty_mask |= 1u << slot;
597 ctx->descriptors_dirty |= 1u << si_image_descriptors_idx(shader);
598 }
599 }
600
601 static void
602 si_mark_image_range_valid(const struct pipe_image_view *view)
603 {
604 struct r600_resource *res = (struct r600_resource *)view->resource;
605
606 assert(res && res->b.b.target == PIPE_BUFFER);
607
608 util_range_add(&res->valid_buffer_range,
609 view->u.buf.offset,
610 view->u.buf.offset + view->u.buf.size);
611 }
612
613 static void si_set_shader_image(struct si_context *ctx,
614 unsigned shader,
615 unsigned slot, const struct pipe_image_view *view)
616 {
617 struct si_screen *screen = ctx->screen;
618 struct si_images_info *images = &ctx->images[shader];
619 struct si_descriptors *descs = si_image_descriptors(ctx, shader);
620 struct r600_resource *res;
621
622 if (!view || !view->resource) {
623 si_disable_shader_image(ctx, shader, slot);
624 return;
625 }
626
627 res = (struct r600_resource *)view->resource;
628
629 if (&images->views[slot] != view)
630 util_copy_image_view(&images->views[slot], view);
631
632 if (res->b.b.target == PIPE_BUFFER) {
633 if (view->access & PIPE_IMAGE_ACCESS_WRITE)
634 si_mark_image_range_valid(view);
635
636 si_make_buffer_descriptor(screen, res,
637 view->format,
638 view->u.buf.offset,
639 view->u.buf.size,
640 descs->list + slot * 8);
641 images->compressed_colortex_mask &= ~(1 << slot);
642 } else {
643 static const unsigned char swizzle[4] = { 0, 1, 2, 3 };
644 struct r600_texture *tex = (struct r600_texture *)res;
645 unsigned level = view->u.tex.level;
646 unsigned width, height, depth;
647 uint32_t *desc = descs->list + slot * 8;
648 bool uses_dcc = tex->dcc_offset &&
649 tex->surface.level[level].dcc_enabled;
650
651 assert(!tex->is_depth);
652 assert(tex->fmask.size == 0);
653
654 if (uses_dcc &&
655 (view->access & PIPE_IMAGE_ACCESS_WRITE ||
656 !vi_dcc_formats_compatible(res->b.b.format, view->format))) {
657 /* If DCC can't be disabled, at least decompress it.
658 * The decompression is relatively cheap if the surface
659 * has been decompressed already.
660 */
661 if (r600_texture_disable_dcc(&ctx->b, tex))
662 uses_dcc = false;
663 else
664 ctx->b.decompress_dcc(&ctx->b.b, tex);
665 }
666
667 if (is_compressed_colortex(tex)) {
668 images->compressed_colortex_mask |= 1 << slot;
669 } else {
670 images->compressed_colortex_mask &= ~(1 << slot);
671 }
672
673 if (uses_dcc &&
674 p_atomic_read(&tex->framebuffers_bound))
675 ctx->need_check_render_feedback = true;
676
677 /* Always force the base level to the selected level.
678 *
679 * This is required for 3D textures, where otherwise
680 * selecting a single slice for non-layered bindings
681 * fails. It doesn't hurt the other targets.
682 */
683 width = u_minify(res->b.b.width0, level);
684 height = u_minify(res->b.b.height0, level);
685 depth = u_minify(res->b.b.depth0, level);
686
687 si_make_texture_descriptor(screen, tex,
688 false, res->b.b.target,
689 view->format, swizzle,
690 0, 0,
691 view->u.tex.first_layer,
692 view->u.tex.last_layer,
693 width, height, depth,
694 desc, NULL);
695 si_set_mutable_tex_desc_fields(tex, &tex->surface.level[level],
696 level, level,
697 util_format_get_blockwidth(view->format),
698 false, desc);
699 }
700
701 images->enabled_mask |= 1u << slot;
702 descs->dirty_mask |= 1u << slot;
703 ctx->descriptors_dirty |= 1u << si_image_descriptors_idx(shader);
704
705 /* Since this can flush, it must be done after enabled_mask is updated. */
706 si_sampler_view_add_buffer(ctx, &res->b.b,
707 RADEON_USAGE_READWRITE, false, true);
708 }
709
710 static void
711 si_set_shader_images(struct pipe_context *pipe,
712 enum pipe_shader_type shader,
713 unsigned start_slot, unsigned count,
714 const struct pipe_image_view *views)
715 {
716 struct si_context *ctx = (struct si_context *)pipe;
717 unsigned i, slot;
718
719 assert(shader < SI_NUM_SHADERS);
720
721 if (!count)
722 return;
723
724 assert(start_slot + count <= SI_NUM_IMAGES);
725
726 if (views) {
727 for (i = 0, slot = start_slot; i < count; ++i, ++slot)
728 si_set_shader_image(ctx, shader, slot, &views[i]);
729 } else {
730 for (i = 0, slot = start_slot; i < count; ++i, ++slot)
731 si_set_shader_image(ctx, shader, slot, NULL);
732 }
733 }
734
735 static void
736 si_images_update_compressed_colortex_mask(struct si_images_info *images)
737 {
738 unsigned mask = images->enabled_mask;
739
740 while (mask) {
741 int i = u_bit_scan(&mask);
742 struct pipe_resource *res = images->views[i].resource;
743
744 if (res && res->target != PIPE_BUFFER) {
745 struct r600_texture *rtex = (struct r600_texture *)res;
746
747 if (is_compressed_colortex(rtex)) {
748 images->compressed_colortex_mask |= 1 << i;
749 } else {
750 images->compressed_colortex_mask &= ~(1 << i);
751 }
752 }
753 }
754 }
755
756 /* SAMPLER STATES */
757
758 static void si_bind_sampler_states(struct pipe_context *ctx,
759 enum pipe_shader_type shader,
760 unsigned start, unsigned count, void **states)
761 {
762 struct si_context *sctx = (struct si_context *)ctx;
763 struct si_textures_info *samplers = &sctx->samplers[shader];
764 struct si_descriptors *desc = si_sampler_descriptors(sctx, shader);
765 struct si_sampler_state **sstates = (struct si_sampler_state**)states;
766 int i;
767
768 if (!count || shader >= SI_NUM_SHADERS)
769 return;
770
771 for (i = 0; i < count; i++) {
772 unsigned slot = start + i;
773
774 if (!sstates[i] ||
775 sstates[i] == samplers->views.sampler_states[slot])
776 continue;
777
778 samplers->views.sampler_states[slot] = sstates[i];
779
780 /* If FMASK is bound, don't overwrite it.
781 * The sampler state will be set after FMASK is unbound.
782 */
783 if (samplers->views.views[i] &&
784 samplers->views.views[i]->texture &&
785 samplers->views.views[i]->texture->target != PIPE_BUFFER &&
786 ((struct r600_texture*)samplers->views.views[i]->texture)->fmask.size)
787 continue;
788
789 memcpy(desc->list + slot * 16 + 12, sstates[i]->val, 4*4);
790 desc->dirty_mask |= 1u << slot;
791 sctx->descriptors_dirty |= 1u << si_sampler_descriptors_idx(shader);
792 }
793 }
794
795 /* BUFFER RESOURCES */
796
797 static void si_init_buffer_resources(struct si_buffer_resources *buffers,
798 struct si_descriptors *descs,
799 unsigned num_buffers,
800 unsigned shader_userdata_index,
801 enum radeon_bo_usage shader_usage,
802 enum radeon_bo_priority priority,
803 unsigned *ce_offset)
804 {
805 buffers->shader_usage = shader_usage;
806 buffers->priority = priority;
807 buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource*));
808
809 si_init_descriptors(descs, shader_userdata_index, 4,
810 num_buffers, NULL, ce_offset);
811 }
812
813 static void si_release_buffer_resources(struct si_buffer_resources *buffers,
814 struct si_descriptors *descs)
815 {
816 int i;
817
818 for (i = 0; i < descs->num_elements; i++) {
819 pipe_resource_reference(&buffers->buffers[i], NULL);
820 }
821
822 FREE(buffers->buffers);
823 }
824
825 static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
826 struct si_buffer_resources *buffers)
827 {
828 unsigned mask = buffers->enabled_mask;
829
830 /* Add buffers to the CS. */
831 while (mask) {
832 int i = u_bit_scan(&mask);
833
834 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
835 (struct r600_resource*)buffers->buffers[i],
836 buffers->shader_usage, buffers->priority);
837 }
838 }
839
840 static void si_get_buffer_from_descriptors(struct si_buffer_resources *buffers,
841 struct si_descriptors *descs,
842 unsigned idx, struct pipe_resource **buf,
843 unsigned *offset, unsigned *size)
844 {
845 pipe_resource_reference(buf, buffers->buffers[idx]);
846 if (*buf) {
847 struct r600_resource *res = r600_resource(*buf);
848 const uint32_t *desc = descs->list + idx * 4;
849 uint64_t va;
850
851 *size = desc[2];
852
853 assert(G_008F04_STRIDE(desc[1]) == 0);
854 va = ((uint64_t)desc[1] << 32) | desc[0];
855
856 assert(va >= res->gpu_address && va + *size <= res->gpu_address + res->bo_size);
857 *offset = va - res->gpu_address;
858 }
859 }
860
861 /* VERTEX BUFFERS */
862
863 static void si_vertex_buffers_begin_new_cs(struct si_context *sctx)
864 {
865 struct si_descriptors *desc = &sctx->vertex_buffers;
866 int count = sctx->vertex_elements ? sctx->vertex_elements->count : 0;
867 int i;
868
869 for (i = 0; i < count; i++) {
870 int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
871
872 if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
873 continue;
874 if (!sctx->vertex_buffer[vb].buffer)
875 continue;
876
877 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
878 (struct r600_resource*)sctx->vertex_buffer[vb].buffer,
879 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
880 }
881
882 if (!desc->buffer)
883 return;
884 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
885 desc->buffer, RADEON_USAGE_READ,
886 RADEON_PRIO_DESCRIPTORS);
887 }
888
889 bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
890 {
891 struct si_descriptors *desc = &sctx->vertex_buffers;
892 bool bound[SI_NUM_VERTEX_BUFFERS] = {};
893 unsigned i, count = sctx->vertex_elements->count;
894 uint64_t va;
895 uint32_t *ptr;
896
897 if (!sctx->vertex_buffers_dirty)
898 return true;
899 if (!count || !sctx->vertex_elements)
900 return true;
901
902 /* Vertex buffer descriptors are the only ones which are uploaded
903 * directly through a staging buffer and don't go through
904 * the fine-grained upload path.
905 */
906 u_upload_alloc(sctx->b.uploader, 0, count * 16, 256, &desc->buffer_offset,
907 (struct pipe_resource**)&desc->buffer, (void**)&ptr);
908 if (!desc->buffer)
909 return false;
910
911 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
912 desc->buffer, RADEON_USAGE_READ,
913 RADEON_PRIO_DESCRIPTORS);
914
915 assert(count <= SI_NUM_VERTEX_BUFFERS);
916
917 for (i = 0; i < count; i++) {
918 struct pipe_vertex_element *ve = &sctx->vertex_elements->elements[i];
919 struct pipe_vertex_buffer *vb;
920 struct r600_resource *rbuffer;
921 unsigned offset;
922 uint32_t *desc = &ptr[i*4];
923
924 if (ve->vertex_buffer_index >= ARRAY_SIZE(sctx->vertex_buffer)) {
925 memset(desc, 0, 16);
926 continue;
927 }
928
929 vb = &sctx->vertex_buffer[ve->vertex_buffer_index];
930 rbuffer = (struct r600_resource*)vb->buffer;
931 if (!rbuffer) {
932 memset(desc, 0, 16);
933 continue;
934 }
935
936 offset = vb->buffer_offset + ve->src_offset;
937 va = rbuffer->gpu_address + offset;
938
939 /* Fill in T# buffer resource description */
940 desc[0] = va;
941 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
942 S_008F04_STRIDE(vb->stride);
943
944 if (sctx->b.chip_class <= CIK && vb->stride)
945 /* Round up by rounding down and adding 1 */
946 desc[2] = (vb->buffer->width0 - offset -
947 sctx->vertex_elements->format_size[i]) /
948 vb->stride + 1;
949 else
950 desc[2] = vb->buffer->width0 - offset;
951
952 desc[3] = sctx->vertex_elements->rsrc_word3[i];
953
954 if (!bound[ve->vertex_buffer_index]) {
955 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
956 (struct r600_resource*)vb->buffer,
957 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
958 bound[ve->vertex_buffer_index] = true;
959 }
960 }
961
962 /* Don't flush the const cache. It would have a very negative effect
963 * on performance (confirmed by testing). New descriptors are always
964 * uploaded to a fresh new buffer, so I don't think flushing the const
965 * cache is needed. */
966 desc->pointer_dirty = true;
967 si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
968 sctx->vertex_buffers_dirty = false;
969 return true;
970 }
971
972
973 /* CONSTANT BUFFERS */
974
975 static unsigned
976 si_const_buffer_descriptors_idx(unsigned shader)
977 {
978 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
979 SI_SHADER_DESCS_CONST_BUFFERS;
980 }
981
982 static struct si_descriptors *
983 si_const_buffer_descriptors(struct si_context *sctx, unsigned shader)
984 {
985 return &sctx->descriptors[si_const_buffer_descriptors_idx(shader)];
986 }
987
988 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
989 const uint8_t *ptr, unsigned size, uint32_t *const_offset)
990 {
991 void *tmp;
992
993 u_upload_alloc(sctx->b.uploader, 0, size, 256, const_offset,
994 (struct pipe_resource**)rbuffer, &tmp);
995 if (*rbuffer)
996 util_memcpy_cpu_to_le32(tmp, ptr, size);
997 }
998
999 static void si_set_constant_buffer(struct si_context *sctx,
1000 struct si_buffer_resources *buffers,
1001 unsigned descriptors_idx,
1002 uint slot, const struct pipe_constant_buffer *input)
1003 {
1004 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
1005 assert(slot < descs->num_elements);
1006 pipe_resource_reference(&buffers->buffers[slot], NULL);
1007
1008 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1009 * with a NULL buffer). We need to use a dummy buffer instead. */
1010 if (sctx->b.chip_class == CIK &&
1011 (!input || (!input->buffer && !input->user_buffer)))
1012 input = &sctx->null_const_buf;
1013
1014 if (input && (input->buffer || input->user_buffer)) {
1015 struct pipe_resource *buffer = NULL;
1016 uint64_t va;
1017
1018 /* Upload the user buffer if needed. */
1019 if (input->user_buffer) {
1020 unsigned buffer_offset;
1021
1022 si_upload_const_buffer(sctx,
1023 (struct r600_resource**)&buffer, input->user_buffer,
1024 input->buffer_size, &buffer_offset);
1025 if (!buffer) {
1026 /* Just unbind on failure. */
1027 si_set_constant_buffer(sctx, buffers, descriptors_idx, slot, NULL);
1028 return;
1029 }
1030 va = r600_resource(buffer)->gpu_address + buffer_offset;
1031 } else {
1032 pipe_resource_reference(&buffer, input->buffer);
1033 va = r600_resource(buffer)->gpu_address + input->buffer_offset;
1034 }
1035
1036 /* Set the descriptor. */
1037 uint32_t *desc = descs->list + slot*4;
1038 desc[0] = va;
1039 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1040 S_008F04_STRIDE(0);
1041 desc[2] = input->buffer_size;
1042 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1043 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1044 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1045 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1046 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1047 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1048
1049 buffers->buffers[slot] = buffer;
1050 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1051 (struct r600_resource*)buffer,
1052 buffers->shader_usage,
1053 buffers->priority, true);
1054 buffers->enabled_mask |= 1u << slot;
1055 } else {
1056 /* Clear the descriptor. */
1057 memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4);
1058 buffers->enabled_mask &= ~(1u << slot);
1059 }
1060
1061 descs->dirty_mask |= 1u << slot;
1062 sctx->descriptors_dirty |= 1u << descriptors_idx;
1063 }
1064
1065 void si_set_rw_buffer(struct si_context *sctx,
1066 uint slot, const struct pipe_constant_buffer *input)
1067 {
1068 si_set_constant_buffer(sctx, &sctx->rw_buffers,
1069 SI_DESCS_RW_BUFFERS, slot, input);
1070 }
1071
1072 static void si_pipe_set_constant_buffer(struct pipe_context *ctx,
1073 uint shader, uint slot,
1074 const struct pipe_constant_buffer *input)
1075 {
1076 struct si_context *sctx = (struct si_context *)ctx;
1077
1078 if (shader >= SI_NUM_SHADERS)
1079 return;
1080
1081 si_set_constant_buffer(sctx, &sctx->const_buffers[shader],
1082 si_const_buffer_descriptors_idx(shader),
1083 slot, input);
1084 }
1085
1086 void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader,
1087 uint slot, struct pipe_constant_buffer *cbuf)
1088 {
1089 cbuf->user_buffer = NULL;
1090 si_get_buffer_from_descriptors(
1091 &sctx->const_buffers[shader],
1092 si_const_buffer_descriptors(sctx, shader),
1093 slot, &cbuf->buffer, &cbuf->buffer_offset, &cbuf->buffer_size);
1094 }
1095
1096 /* SHADER BUFFERS */
1097
1098 static unsigned
1099 si_shader_buffer_descriptors_idx(enum pipe_shader_type shader)
1100 {
1101 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
1102 SI_SHADER_DESCS_SHADER_BUFFERS;
1103 }
1104
1105 static struct si_descriptors *
1106 si_shader_buffer_descriptors(struct si_context *sctx,
1107 enum pipe_shader_type shader)
1108 {
1109 return &sctx->descriptors[si_shader_buffer_descriptors_idx(shader)];
1110 }
1111
1112 static void si_set_shader_buffers(struct pipe_context *ctx,
1113 enum pipe_shader_type shader,
1114 unsigned start_slot, unsigned count,
1115 const struct pipe_shader_buffer *sbuffers)
1116 {
1117 struct si_context *sctx = (struct si_context *)ctx;
1118 struct si_buffer_resources *buffers = &sctx->shader_buffers[shader];
1119 struct si_descriptors *descs = si_shader_buffer_descriptors(sctx, shader);
1120 unsigned i;
1121
1122 assert(start_slot + count <= SI_NUM_SHADER_BUFFERS);
1123
1124 for (i = 0; i < count; ++i) {
1125 const struct pipe_shader_buffer *sbuffer = sbuffers ? &sbuffers[i] : NULL;
1126 struct r600_resource *buf;
1127 unsigned slot = start_slot + i;
1128 uint32_t *desc = descs->list + slot * 4;
1129 uint64_t va;
1130
1131 if (!sbuffer || !sbuffer->buffer) {
1132 pipe_resource_reference(&buffers->buffers[slot], NULL);
1133 memset(desc, 0, sizeof(uint32_t) * 4);
1134 buffers->enabled_mask &= ~(1u << slot);
1135 descs->dirty_mask |= 1u << slot;
1136 sctx->descriptors_dirty |=
1137 1u << si_shader_buffer_descriptors_idx(shader);
1138 continue;
1139 }
1140
1141 buf = (struct r600_resource *)sbuffer->buffer;
1142 va = buf->gpu_address + sbuffer->buffer_offset;
1143
1144 desc[0] = va;
1145 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1146 S_008F04_STRIDE(0);
1147 desc[2] = sbuffer->buffer_size;
1148 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1149 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1150 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1151 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1152 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1153 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1154
1155 pipe_resource_reference(&buffers->buffers[slot], &buf->b.b);
1156 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx, buf,
1157 buffers->shader_usage,
1158 buffers->priority, true);
1159 buffers->enabled_mask |= 1u << slot;
1160 descs->dirty_mask |= 1u << slot;
1161 sctx->descriptors_dirty |=
1162 1u << si_shader_buffer_descriptors_idx(shader);
1163 }
1164 }
1165
1166 void si_get_shader_buffers(struct si_context *sctx, uint shader,
1167 uint start_slot, uint count,
1168 struct pipe_shader_buffer *sbuf)
1169 {
1170 struct si_buffer_resources *buffers = &sctx->shader_buffers[shader];
1171 struct si_descriptors *descs = si_shader_buffer_descriptors(sctx, shader);
1172
1173 for (unsigned i = 0; i < count; ++i) {
1174 si_get_buffer_from_descriptors(
1175 buffers, descs, start_slot + i,
1176 &sbuf[i].buffer, &sbuf[i].buffer_offset,
1177 &sbuf[i].buffer_size);
1178 }
1179 }
1180
1181 /* RING BUFFERS */
1182
1183 void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
1184 struct pipe_resource *buffer,
1185 unsigned stride, unsigned num_records,
1186 bool add_tid, bool swizzle,
1187 unsigned element_size, unsigned index_stride, uint64_t offset)
1188 {
1189 struct si_context *sctx = (struct si_context *)ctx;
1190 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1191 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1192
1193 /* The stride field in the resource descriptor has 14 bits */
1194 assert(stride < (1 << 14));
1195
1196 assert(slot < descs->num_elements);
1197 pipe_resource_reference(&buffers->buffers[slot], NULL);
1198
1199 if (buffer) {
1200 uint64_t va;
1201
1202 va = r600_resource(buffer)->gpu_address + offset;
1203
1204 switch (element_size) {
1205 default:
1206 assert(!"Unsupported ring buffer element size");
1207 case 0:
1208 case 2:
1209 element_size = 0;
1210 break;
1211 case 4:
1212 element_size = 1;
1213 break;
1214 case 8:
1215 element_size = 2;
1216 break;
1217 case 16:
1218 element_size = 3;
1219 break;
1220 }
1221
1222 switch (index_stride) {
1223 default:
1224 assert(!"Unsupported ring buffer index stride");
1225 case 0:
1226 case 8:
1227 index_stride = 0;
1228 break;
1229 case 16:
1230 index_stride = 1;
1231 break;
1232 case 32:
1233 index_stride = 2;
1234 break;
1235 case 64:
1236 index_stride = 3;
1237 break;
1238 }
1239
1240 if (sctx->b.chip_class >= VI && stride)
1241 num_records *= stride;
1242
1243 /* Set the descriptor. */
1244 uint32_t *desc = descs->list + slot*4;
1245 desc[0] = va;
1246 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1247 S_008F04_STRIDE(stride) |
1248 S_008F04_SWIZZLE_ENABLE(swizzle);
1249 desc[2] = num_records;
1250 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1251 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1252 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1253 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1254 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1255 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1256 S_008F0C_ELEMENT_SIZE(element_size) |
1257 S_008F0C_INDEX_STRIDE(index_stride) |
1258 S_008F0C_ADD_TID_ENABLE(add_tid);
1259
1260 pipe_resource_reference(&buffers->buffers[slot], buffer);
1261 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1262 (struct r600_resource*)buffer,
1263 buffers->shader_usage, buffers->priority);
1264 buffers->enabled_mask |= 1u << slot;
1265 } else {
1266 /* Clear the descriptor. */
1267 memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4);
1268 buffers->enabled_mask &= ~(1u << slot);
1269 }
1270
1271 descs->dirty_mask |= 1u << slot;
1272 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1273 }
1274
1275 /* STREAMOUT BUFFERS */
1276
1277 static void si_set_streamout_targets(struct pipe_context *ctx,
1278 unsigned num_targets,
1279 struct pipe_stream_output_target **targets,
1280 const unsigned *offsets)
1281 {
1282 struct si_context *sctx = (struct si_context *)ctx;
1283 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1284 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1285 unsigned old_num_targets = sctx->b.streamout.num_targets;
1286 unsigned i, bufidx;
1287
1288 /* We are going to unbind the buffers. Mark which caches need to be flushed. */
1289 if (sctx->b.streamout.num_targets && sctx->b.streamout.begin_emitted) {
1290 /* Since streamout uses vector writes which go through TC L2
1291 * and most other clients can use TC L2 as well, we don't need
1292 * to flush it.
1293 *
1294 * The only cases which requires flushing it is VGT DMA index
1295 * fetching (on <= CIK) and indirect draw data, which are rare
1296 * cases. Thus, flag the TC L2 dirtiness in the resource and
1297 * handle it at draw call time.
1298 */
1299 for (i = 0; i < sctx->b.streamout.num_targets; i++)
1300 if (sctx->b.streamout.targets[i])
1301 r600_resource(sctx->b.streamout.targets[i]->b.buffer)->TC_L2_dirty = true;
1302
1303 /* Invalidate the scalar cache in case a streamout buffer is
1304 * going to be used as a constant buffer.
1305 *
1306 * Invalidate TC L1, because streamout bypasses it (done by
1307 * setting GLC=1 in the store instruction), but it can contain
1308 * outdated data of streamout buffers.
1309 *
1310 * VS_PARTIAL_FLUSH is required if the buffers are going to be
1311 * used as an input immediately.
1312 */
1313 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
1314 SI_CONTEXT_INV_VMEM_L1 |
1315 SI_CONTEXT_VS_PARTIAL_FLUSH;
1316 }
1317
1318 /* All readers of the streamout targets need to be finished before we can
1319 * start writing to the targets.
1320 */
1321 if (num_targets)
1322 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
1323 SI_CONTEXT_CS_PARTIAL_FLUSH;
1324
1325 /* Streamout buffers must be bound in 2 places:
1326 * 1) in VGT by setting the VGT_STRMOUT registers
1327 * 2) as shader resources
1328 */
1329
1330 /* Set the VGT regs. */
1331 r600_set_streamout_targets(ctx, num_targets, targets, offsets);
1332
1333 /* Set the shader resources.*/
1334 for (i = 0; i < num_targets; i++) {
1335 bufidx = SI_VS_STREAMOUT_BUF0 + i;
1336
1337 if (targets[i]) {
1338 struct pipe_resource *buffer = targets[i]->buffer;
1339 uint64_t va = r600_resource(buffer)->gpu_address;
1340
1341 /* Set the descriptor.
1342 *
1343 * On VI, the format must be non-INVALID, otherwise
1344 * the buffer will be considered not bound and store
1345 * instructions will be no-ops.
1346 */
1347 uint32_t *desc = descs->list + bufidx*4;
1348 desc[0] = va;
1349 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1350 desc[2] = 0xffffffff;
1351 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1352 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1353 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1354 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1355 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1356
1357 /* Set the resource. */
1358 pipe_resource_reference(&buffers->buffers[bufidx],
1359 buffer);
1360 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1361 (struct r600_resource*)buffer,
1362 buffers->shader_usage,
1363 RADEON_PRIO_SHADER_RW_BUFFER,
1364 true);
1365 buffers->enabled_mask |= 1u << bufidx;
1366 } else {
1367 /* Clear the descriptor and unset the resource. */
1368 memset(descs->list + bufidx*4, 0,
1369 sizeof(uint32_t) * 4);
1370 pipe_resource_reference(&buffers->buffers[bufidx],
1371 NULL);
1372 buffers->enabled_mask &= ~(1u << bufidx);
1373 }
1374 descs->dirty_mask |= 1u << bufidx;
1375 }
1376 for (; i < old_num_targets; i++) {
1377 bufidx = SI_VS_STREAMOUT_BUF0 + i;
1378 /* Clear the descriptor and unset the resource. */
1379 memset(descs->list + bufidx*4, 0, sizeof(uint32_t) * 4);
1380 pipe_resource_reference(&buffers->buffers[bufidx], NULL);
1381 buffers->enabled_mask &= ~(1u << bufidx);
1382 descs->dirty_mask |= 1u << bufidx;
1383 }
1384
1385 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1386 }
1387
1388 static void si_desc_reset_buffer_offset(struct pipe_context *ctx,
1389 uint32_t *desc, uint64_t old_buf_va,
1390 struct pipe_resource *new_buf)
1391 {
1392 /* Retrieve the buffer offset from the descriptor. */
1393 uint64_t old_desc_va =
1394 desc[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc[1]) << 32);
1395
1396 assert(old_buf_va <= old_desc_va);
1397 uint64_t offset_within_buffer = old_desc_va - old_buf_va;
1398
1399 /* Update the descriptor. */
1400 uint64_t va = r600_resource(new_buf)->gpu_address + offset_within_buffer;
1401
1402 desc[0] = va;
1403 desc[1] = (desc[1] & C_008F04_BASE_ADDRESS_HI) |
1404 S_008F04_BASE_ADDRESS_HI(va >> 32);
1405 }
1406
1407 /* INTERNAL CONST BUFFERS */
1408
1409 static void si_set_polygon_stipple(struct pipe_context *ctx,
1410 const struct pipe_poly_stipple *state)
1411 {
1412 struct si_context *sctx = (struct si_context *)ctx;
1413 struct pipe_constant_buffer cb = {};
1414 unsigned stipple[32];
1415 int i;
1416
1417 for (i = 0; i < 32; i++)
1418 stipple[i] = util_bitreverse(state->stipple[i]);
1419
1420 cb.user_buffer = stipple;
1421 cb.buffer_size = sizeof(stipple);
1422
1423 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE, &cb);
1424 }
1425
1426 /* TEXTURE METADATA ENABLE/DISABLE */
1427
1428 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1429 * while the texture is bound, possibly by a different context. In that case,
1430 * call this function to update compressed_colortex_masks.
1431 */
1432 void si_update_compressed_colortex_masks(struct si_context *sctx)
1433 {
1434 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
1435 si_samplers_update_compressed_colortex_mask(&sctx->samplers[i]);
1436 si_images_update_compressed_colortex_mask(&sctx->images[i]);
1437 }
1438 }
1439
1440 /* BUFFER DISCARD/INVALIDATION */
1441
1442 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1443 static void si_reset_buffer_resources(struct si_context *sctx,
1444 struct si_buffer_resources *buffers,
1445 unsigned descriptors_idx,
1446 struct pipe_resource *buf,
1447 uint64_t old_va)
1448 {
1449 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
1450 unsigned mask = buffers->enabled_mask;
1451
1452 while (mask) {
1453 unsigned i = u_bit_scan(&mask);
1454 if (buffers->buffers[i] == buf) {
1455 si_desc_reset_buffer_offset(&sctx->b.b,
1456 descs->list + i*4,
1457 old_va, buf);
1458 descs->dirty_mask |= 1u << i;
1459 sctx->descriptors_dirty |= 1u << descriptors_idx;
1460
1461 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1462 (struct r600_resource *)buf,
1463 buffers->shader_usage,
1464 buffers->priority, true);
1465 }
1466 }
1467 }
1468
1469 /* Reallocate a buffer a update all resource bindings where the buffer is
1470 * bound.
1471 *
1472 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
1473 * idle by discarding its contents. Apps usually tell us when to do this using
1474 * map_buffer flags, for example.
1475 */
1476 static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
1477 {
1478 struct si_context *sctx = (struct si_context*)ctx;
1479 struct r600_resource *rbuffer = r600_resource(buf);
1480 unsigned i, shader;
1481 uint64_t old_va = rbuffer->gpu_address;
1482 unsigned num_elems = sctx->vertex_elements ?
1483 sctx->vertex_elements->count : 0;
1484 struct si_sampler_view *view;
1485
1486 /* Reallocate the buffer in the same pipe_resource. */
1487 r600_alloc_resource(&sctx->screen->b, rbuffer);
1488
1489 /* We changed the buffer, now we need to bind it where the old one
1490 * was bound. This consists of 2 things:
1491 * 1) Updating the resource descriptor and dirtying it.
1492 * 2) Adding a relocation to the CS, so that it's usable.
1493 */
1494
1495 /* Vertex buffers. */
1496 for (i = 0; i < num_elems; i++) {
1497 int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
1498
1499 if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
1500 continue;
1501 if (!sctx->vertex_buffer[vb].buffer)
1502 continue;
1503
1504 if (sctx->vertex_buffer[vb].buffer == buf) {
1505 sctx->vertex_buffers_dirty = true;
1506 break;
1507 }
1508 }
1509
1510 /* Streamout buffers. (other internal buffers can't be invalidated) */
1511 for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) {
1512 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1513 struct si_descriptors *descs =
1514 &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1515
1516 if (buffers->buffers[i] != buf)
1517 continue;
1518
1519 si_desc_reset_buffer_offset(ctx, descs->list + i*4,
1520 old_va, buf);
1521 descs->dirty_mask |= 1u << i;
1522 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1523
1524 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1525 rbuffer, buffers->shader_usage,
1526 RADEON_PRIO_SHADER_RW_BUFFER,
1527 true);
1528
1529 /* Update the streamout state. */
1530 if (sctx->b.streamout.begin_emitted)
1531 r600_emit_streamout_end(&sctx->b);
1532 sctx->b.streamout.append_bitmask =
1533 sctx->b.streamout.enabled_mask;
1534 r600_streamout_buffers_dirty(&sctx->b);
1535 }
1536
1537 /* Constant and shader buffers. */
1538 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1539 si_reset_buffer_resources(sctx, &sctx->const_buffers[shader],
1540 si_const_buffer_descriptors_idx(shader),
1541 buf, old_va);
1542 si_reset_buffer_resources(sctx, &sctx->shader_buffers[shader],
1543 si_shader_buffer_descriptors_idx(shader),
1544 buf, old_va);
1545 }
1546
1547 /* Texture buffers - update virtual addresses in sampler view descriptors. */
1548 LIST_FOR_EACH_ENTRY(view, &sctx->b.texture_buffers, list) {
1549 if (view->base.texture == buf) {
1550 si_desc_reset_buffer_offset(ctx, &view->state[4], old_va, buf);
1551 }
1552 }
1553 /* Texture buffers - update bindings. */
1554 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1555 struct si_sampler_views *views = &sctx->samplers[shader].views;
1556 struct si_descriptors *descs =
1557 si_sampler_descriptors(sctx, shader);
1558 unsigned mask = views->enabled_mask;
1559
1560 while (mask) {
1561 unsigned i = u_bit_scan(&mask);
1562 if (views->views[i]->texture == buf) {
1563 si_desc_reset_buffer_offset(ctx,
1564 descs->list +
1565 i * 16 + 4,
1566 old_va, buf);
1567 descs->dirty_mask |= 1u << i;
1568 sctx->descriptors_dirty |=
1569 1u << si_sampler_descriptors_idx(shader);
1570
1571 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1572 rbuffer, RADEON_USAGE_READ,
1573 RADEON_PRIO_SAMPLER_BUFFER,
1574 true);
1575 }
1576 }
1577 }
1578
1579 /* Shader images */
1580 for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
1581 struct si_images_info *images = &sctx->images[shader];
1582 struct si_descriptors *descs =
1583 si_image_descriptors(sctx, shader);
1584 unsigned mask = images->enabled_mask;
1585
1586 while (mask) {
1587 unsigned i = u_bit_scan(&mask);
1588
1589 if (images->views[i].resource == buf) {
1590 if (images->views[i].access & PIPE_IMAGE_ACCESS_WRITE)
1591 si_mark_image_range_valid(&images->views[i]);
1592
1593 si_desc_reset_buffer_offset(
1594 ctx, descs->list + i * 8 + 4,
1595 old_va, buf);
1596 descs->dirty_mask |= 1u << i;
1597 sctx->descriptors_dirty |=
1598 1u << si_image_descriptors_idx(shader);
1599
1600 radeon_add_to_buffer_list_check_mem(
1601 &sctx->b, &sctx->b.gfx, rbuffer,
1602 RADEON_USAGE_READWRITE,
1603 RADEON_PRIO_SAMPLER_BUFFER, true);
1604 }
1605 }
1606 }
1607 }
1608
1609 /* Update mutable image descriptor fields of all bound textures. */
1610 void si_update_all_texture_descriptors(struct si_context *sctx)
1611 {
1612 unsigned shader;
1613
1614 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1615 struct si_sampler_views *samplers = &sctx->samplers[shader].views;
1616 struct si_images_info *images = &sctx->images[shader];
1617 unsigned mask;
1618
1619 /* Images. */
1620 mask = images->enabled_mask;
1621 while (mask) {
1622 unsigned i = u_bit_scan(&mask);
1623 struct pipe_image_view *view = &images->views[i];
1624
1625 if (!view->resource ||
1626 view->resource->target == PIPE_BUFFER)
1627 continue;
1628
1629 si_set_shader_image(sctx, shader, i, view);
1630 }
1631
1632 /* Sampler views. */
1633 mask = samplers->enabled_mask;
1634 while (mask) {
1635 unsigned i = u_bit_scan(&mask);
1636 struct pipe_sampler_view *view = samplers->views[i];
1637
1638 if (!view ||
1639 !view->texture ||
1640 view->texture->target == PIPE_BUFFER)
1641 continue;
1642
1643 si_set_sampler_view(sctx, shader, i,
1644 samplers->views[i], true);
1645 }
1646 }
1647 }
1648
1649 /* SHADER USER DATA */
1650
1651 static void si_mark_shader_pointers_dirty(struct si_context *sctx,
1652 unsigned shader)
1653 {
1654 struct si_descriptors *descs =
1655 &sctx->descriptors[SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS];
1656
1657 for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs)
1658 descs->pointer_dirty = true;
1659
1660 if (shader == PIPE_SHADER_VERTEX)
1661 sctx->vertex_buffers.pointer_dirty = true;
1662
1663 si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
1664 }
1665
1666 static void si_shader_userdata_begin_new_cs(struct si_context *sctx)
1667 {
1668 int i;
1669
1670 for (i = 0; i < SI_NUM_SHADERS; i++) {
1671 si_mark_shader_pointers_dirty(sctx, i);
1672 }
1673 sctx->descriptors[SI_DESCS_RW_BUFFERS].pointer_dirty = true;
1674 }
1675
1676 /* Set a base register address for user data constants in the given shader.
1677 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1678 */
1679 static void si_set_user_data_base(struct si_context *sctx,
1680 unsigned shader, uint32_t new_base)
1681 {
1682 uint32_t *base = &sctx->shader_userdata.sh_base[shader];
1683
1684 if (*base != new_base) {
1685 *base = new_base;
1686
1687 if (new_base)
1688 si_mark_shader_pointers_dirty(sctx, shader);
1689 }
1690 }
1691
1692 /* This must be called when these shaders are changed from non-NULL to NULL
1693 * and vice versa:
1694 * - geometry shader
1695 * - tessellation control shader
1696 * - tessellation evaluation shader
1697 */
1698 void si_shader_change_notify(struct si_context *sctx)
1699 {
1700 /* VS can be bound as VS, ES, or LS. */
1701 if (sctx->tes_shader.cso)
1702 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1703 R_00B530_SPI_SHADER_USER_DATA_LS_0);
1704 else if (sctx->gs_shader.cso)
1705 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1706 R_00B330_SPI_SHADER_USER_DATA_ES_0);
1707 else
1708 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1709 R_00B130_SPI_SHADER_USER_DATA_VS_0);
1710
1711 /* TES can be bound as ES, VS, or not bound. */
1712 if (sctx->tes_shader.cso) {
1713 if (sctx->gs_shader.cso)
1714 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
1715 R_00B330_SPI_SHADER_USER_DATA_ES_0);
1716 else
1717 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
1718 R_00B130_SPI_SHADER_USER_DATA_VS_0);
1719 } else {
1720 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, 0);
1721 }
1722 }
1723
1724 static void si_emit_shader_pointer(struct si_context *sctx,
1725 struct si_descriptors *desc,
1726 unsigned sh_base, bool keep_dirty)
1727 {
1728 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1729 uint64_t va;
1730
1731 if (!desc->pointer_dirty || !desc->buffer)
1732 return;
1733
1734 va = desc->buffer->gpu_address +
1735 desc->buffer_offset;
1736
1737 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0));
1738 radeon_emit(cs, (sh_base + desc->shader_userdata_offset - SI_SH_REG_OFFSET) >> 2);
1739 radeon_emit(cs, va);
1740 radeon_emit(cs, va >> 32);
1741
1742 desc->pointer_dirty = keep_dirty;
1743 }
1744
1745 void si_emit_graphics_shader_userdata(struct si_context *sctx,
1746 struct r600_atom *atom)
1747 {
1748 unsigned shader;
1749 uint32_t *sh_base = sctx->shader_userdata.sh_base;
1750 struct si_descriptors *descs;
1751
1752 descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1753
1754 if (descs->pointer_dirty) {
1755 si_emit_shader_pointer(sctx, descs,
1756 R_00B030_SPI_SHADER_USER_DATA_PS_0, true);
1757 si_emit_shader_pointer(sctx, descs,
1758 R_00B130_SPI_SHADER_USER_DATA_VS_0, true);
1759 si_emit_shader_pointer(sctx, descs,
1760 R_00B230_SPI_SHADER_USER_DATA_GS_0, true);
1761 si_emit_shader_pointer(sctx, descs,
1762 R_00B330_SPI_SHADER_USER_DATA_ES_0, true);
1763 si_emit_shader_pointer(sctx, descs,
1764 R_00B430_SPI_SHADER_USER_DATA_HS_0, true);
1765 descs->pointer_dirty = false;
1766 }
1767
1768 descs = &sctx->descriptors[SI_DESCS_FIRST_SHADER];
1769
1770 for (shader = 0; shader < SI_NUM_GRAPHICS_SHADERS; shader++) {
1771 unsigned base = sh_base[shader];
1772 unsigned i;
1773
1774 if (!base)
1775 continue;
1776
1777 for (i = 0; i < SI_NUM_SHADER_DESCS; i++, descs++)
1778 si_emit_shader_pointer(sctx, descs, base, false);
1779 }
1780 si_emit_shader_pointer(sctx, &sctx->vertex_buffers, sh_base[PIPE_SHADER_VERTEX], false);
1781 }
1782
1783 void si_emit_compute_shader_userdata(struct si_context *sctx)
1784 {
1785 unsigned base = R_00B900_COMPUTE_USER_DATA_0;
1786 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_FIRST_COMPUTE];
1787
1788 for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs)
1789 si_emit_shader_pointer(sctx, descs, base, false);
1790 }
1791
1792 /* INIT/DEINIT/UPLOAD */
1793
1794 void si_init_all_descriptors(struct si_context *sctx)
1795 {
1796 int i;
1797 unsigned ce_offset = 0;
1798
1799 for (i = 0; i < SI_NUM_SHADERS; i++) {
1800 si_init_buffer_resources(&sctx->const_buffers[i],
1801 si_const_buffer_descriptors(sctx, i),
1802 SI_NUM_CONST_BUFFERS, SI_SGPR_CONST_BUFFERS,
1803 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER,
1804 &ce_offset);
1805 si_init_buffer_resources(&sctx->shader_buffers[i],
1806 si_shader_buffer_descriptors(sctx, i),
1807 SI_NUM_SHADER_BUFFERS, SI_SGPR_SHADER_BUFFERS,
1808 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RW_BUFFER,
1809 &ce_offset);
1810
1811 si_init_descriptors(si_sampler_descriptors(sctx, i),
1812 SI_SGPR_SAMPLERS, 16, SI_NUM_SAMPLERS,
1813 null_texture_descriptor, &ce_offset);
1814
1815 si_init_descriptors(si_image_descriptors(sctx, i),
1816 SI_SGPR_IMAGES, 8, SI_NUM_IMAGES,
1817 null_image_descriptor, &ce_offset);
1818 }
1819
1820 si_init_buffer_resources(&sctx->rw_buffers,
1821 &sctx->descriptors[SI_DESCS_RW_BUFFERS],
1822 SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS,
1823 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS,
1824 &ce_offset);
1825 si_init_descriptors(&sctx->vertex_buffers, SI_SGPR_VERTEX_BUFFERS,
1826 4, SI_NUM_VERTEX_BUFFERS, NULL, NULL);
1827
1828 sctx->descriptors_dirty = u_bit_consecutive(0, SI_NUM_DESCS);
1829
1830 assert(ce_offset <= 32768);
1831
1832 /* Set pipe_context functions. */
1833 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
1834 sctx->b.b.set_shader_images = si_set_shader_images;
1835 sctx->b.b.set_constant_buffer = si_pipe_set_constant_buffer;
1836 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
1837 sctx->b.b.set_shader_buffers = si_set_shader_buffers;
1838 sctx->b.b.set_sampler_views = si_set_sampler_views;
1839 sctx->b.b.set_stream_output_targets = si_set_streamout_targets;
1840 sctx->b.invalidate_buffer = si_invalidate_buffer;
1841
1842 /* Shader user data. */
1843 si_init_atom(sctx, &sctx->shader_userdata.atom, &sctx->atoms.s.shader_userdata,
1844 si_emit_graphics_shader_userdata);
1845
1846 /* Set default and immutable mappings. */
1847 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
1848 si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, R_00B430_SPI_SHADER_USER_DATA_HS_0);
1849 si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, R_00B230_SPI_SHADER_USER_DATA_GS_0);
1850 si_set_user_data_base(sctx, PIPE_SHADER_FRAGMENT, R_00B030_SPI_SHADER_USER_DATA_PS_0);
1851 }
1852
1853 bool si_upload_graphics_shader_descriptors(struct si_context *sctx)
1854 {
1855 const unsigned mask = u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE);
1856 unsigned dirty = sctx->descriptors_dirty & mask;
1857
1858 while (dirty) {
1859 unsigned i = u_bit_scan(&dirty);
1860
1861 if (!si_upload_descriptors(sctx, &sctx->descriptors[i],
1862 &sctx->shader_userdata.atom))
1863 return false;
1864 }
1865
1866 sctx->descriptors_dirty &= ~mask;
1867 return true;
1868 }
1869
1870 bool si_upload_compute_shader_descriptors(struct si_context *sctx)
1871 {
1872 /* Does not update rw_buffers as that is not needed for compute shaders
1873 * and the input buffer is using the same SGPR's anyway.
1874 */
1875 const unsigned mask = u_bit_consecutive(SI_DESCS_FIRST_COMPUTE,
1876 SI_NUM_DESCS - SI_DESCS_FIRST_COMPUTE);
1877 unsigned dirty = sctx->descriptors_dirty & mask;
1878
1879 while (dirty) {
1880 unsigned i = u_bit_scan(&dirty);
1881
1882 if (!si_upload_descriptors(sctx, &sctx->descriptors[i], NULL))
1883 return false;
1884 }
1885
1886 sctx->descriptors_dirty &= ~mask;
1887
1888 return true;
1889 }
1890
1891 void si_release_all_descriptors(struct si_context *sctx)
1892 {
1893 int i;
1894
1895 for (i = 0; i < SI_NUM_SHADERS; i++) {
1896 si_release_buffer_resources(&sctx->const_buffers[i],
1897 si_const_buffer_descriptors(sctx, i));
1898 si_release_buffer_resources(&sctx->shader_buffers[i],
1899 si_shader_buffer_descriptors(sctx, i));
1900 si_release_sampler_views(&sctx->samplers[i].views);
1901 si_release_image_views(&sctx->images[i]);
1902 }
1903 si_release_buffer_resources(&sctx->rw_buffers,
1904 &sctx->descriptors[SI_DESCS_RW_BUFFERS]);
1905
1906 for (i = 0; i < SI_NUM_DESCS; ++i)
1907 si_release_descriptors(&sctx->descriptors[i]);
1908 si_release_descriptors(&sctx->vertex_buffers);
1909 }
1910
1911 void si_all_descriptors_begin_new_cs(struct si_context *sctx)
1912 {
1913 int i;
1914
1915 for (i = 0; i < SI_NUM_SHADERS; i++) {
1916 si_buffer_resources_begin_new_cs(sctx, &sctx->const_buffers[i]);
1917 si_buffer_resources_begin_new_cs(sctx, &sctx->shader_buffers[i]);
1918 si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i].views);
1919 si_image_views_begin_new_cs(sctx, &sctx->images[i]);
1920 }
1921 si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers);
1922 si_vertex_buffers_begin_new_cs(sctx);
1923
1924 for (i = 0; i < SI_NUM_DESCS; ++i)
1925 si_descriptors_begin_new_cs(sctx, &sctx->descriptors[i]);
1926
1927 si_shader_userdata_begin_new_cs(sctx);
1928 }