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radeonsi: don't set sampler buffer offsets in create_sampler_view
[mesa.git] / src / gallium / drivers / radeonsi / si_descriptors.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Marek Olšák <marek.olsak@amd.com>
25 */
26
27 /* Resource binding slots and sampler states (each described with 8 or
28 * 4 dwords) are stored in lists in memory which is accessed by shaders
29 * using scalar load instructions.
30 *
31 * This file is responsible for managing such lists. It keeps a copy of all
32 * descriptors in CPU memory and re-uploads a whole list if some slots have
33 * been changed.
34 *
35 * This code is also reponsible for updating shader pointers to those lists.
36 *
37 * Note that CP DMA can't be used for updating the lists, because a GPU hang
38 * could leave the list in a mid-IB state and the next IB would get wrong
39 * descriptors and the whole context would be unusable at that point.
40 * (Note: The register shadowing can't be used due to the same reason)
41 *
42 * Also, uploading descriptors to newly allocated memory doesn't require
43 * a KCACHE flush.
44 *
45 *
46 * Possible scenarios for one 16 dword image+sampler slot:
47 *
48 * | Image | w/ FMASK | Buffer | NULL
49 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
50 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
51 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
52 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
53 *
54 * FMASK implies MSAA, therefore no sampler state.
55 * Sampler states are never unbound except when FMASK is bound.
56 */
57
58 #include "radeon/r600_cs.h"
59 #include "si_pipe.h"
60 #include "si_shader.h"
61 #include "sid.h"
62
63 #include "util/u_format.h"
64 #include "util/u_math.h"
65 #include "util/u_memory.h"
66 #include "util/u_suballoc.h"
67 #include "util/u_upload_mgr.h"
68
69
70 /* NULL image and buffer descriptor for textures (alpha = 1) and images
71 * (alpha = 0).
72 *
73 * For images, all fields must be zero except for the swizzle, which
74 * supports arbitrary combinations of 0s and 1s. The texture type must be
75 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
76 *
77 * For buffers, all fields must be zero. If they are not, the hw hangs.
78 *
79 * This is the only reason why the buffer descriptor must be in words [4:7].
80 */
81 static uint32_t null_texture_descriptor[8] = {
82 0,
83 0,
84 0,
85 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1) |
86 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
87 /* the rest must contain zeros, which is also used by the buffer
88 * descriptor */
89 };
90
91 static uint32_t null_image_descriptor[8] = {
92 0,
93 0,
94 0,
95 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D)
96 /* the rest must contain zeros, which is also used by the buffer
97 * descriptor */
98 };
99
100 static void si_init_descriptors(struct si_descriptors *desc,
101 unsigned shader_userdata_index,
102 unsigned element_dw_size,
103 unsigned num_elements,
104 const uint32_t *null_descriptor,
105 unsigned *ce_offset)
106 {
107 int i;
108
109 assert(num_elements <= sizeof(desc->dirty_mask)*8);
110
111 desc->list = CALLOC(num_elements, element_dw_size * 4);
112 desc->element_dw_size = element_dw_size;
113 desc->num_elements = num_elements;
114 desc->dirty_mask = num_elements == 32 ? ~0u : (1u << num_elements) - 1;
115 desc->shader_userdata_offset = shader_userdata_index * 4;
116
117 if (ce_offset) {
118 desc->ce_offset = *ce_offset;
119
120 /* make sure that ce_offset stays 32 byte aligned */
121 *ce_offset += align(element_dw_size * num_elements * 4, 32);
122 }
123
124 /* Initialize the array to NULL descriptors if the element size is 8. */
125 if (null_descriptor) {
126 assert(element_dw_size % 8 == 0);
127 for (i = 0; i < num_elements * element_dw_size / 8; i++)
128 memcpy(desc->list + i * 8, null_descriptor,
129 8 * 4);
130 }
131 }
132
133 static void si_release_descriptors(struct si_descriptors *desc)
134 {
135 r600_resource_reference(&desc->buffer, NULL);
136 FREE(desc->list);
137 }
138
139 static bool si_ce_upload(struct si_context *sctx, unsigned ce_offset, unsigned size,
140 unsigned *out_offset, struct r600_resource **out_buf) {
141 uint64_t va;
142
143 u_suballocator_alloc(sctx->ce_suballocator, size, 64, out_offset,
144 (struct pipe_resource**)out_buf);
145 if (!out_buf)
146 return false;
147
148 va = (*out_buf)->gpu_address + *out_offset;
149
150 radeon_emit(sctx->ce_ib, PKT3(PKT3_DUMP_CONST_RAM, 3, 0));
151 radeon_emit(sctx->ce_ib, ce_offset);
152 radeon_emit(sctx->ce_ib, size / 4);
153 radeon_emit(sctx->ce_ib, va);
154 radeon_emit(sctx->ce_ib, va >> 32);
155
156 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, *out_buf,
157 RADEON_USAGE_READWRITE, RADEON_PRIO_DESCRIPTORS);
158
159 sctx->ce_need_synchronization = true;
160 return true;
161 }
162
163 static void si_ce_reinitialize_descriptors(struct si_context *sctx,
164 struct si_descriptors *desc)
165 {
166 if (desc->buffer) {
167 struct r600_resource *buffer = (struct r600_resource*)desc->buffer;
168 unsigned list_size = desc->num_elements * desc->element_dw_size * 4;
169 uint64_t va = buffer->gpu_address + desc->buffer_offset;
170 struct radeon_winsys_cs *ib = sctx->ce_preamble_ib;
171
172 if (!ib)
173 ib = sctx->ce_ib;
174
175 list_size = align(list_size, 32);
176
177 radeon_emit(ib, PKT3(PKT3_LOAD_CONST_RAM, 3, 0));
178 radeon_emit(ib, va);
179 radeon_emit(ib, va >> 32);
180 radeon_emit(ib, list_size / 4);
181 radeon_emit(ib, desc->ce_offset);
182
183 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
184 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
185 }
186 desc->ce_ram_dirty = false;
187 }
188
189 void si_ce_reinitialize_all_descriptors(struct si_context *sctx)
190 {
191 int i;
192
193 for (i = 0; i < SI_NUM_DESCS; ++i)
194 si_ce_reinitialize_descriptors(sctx, &sctx->descriptors[i]);
195 }
196
197 void si_ce_enable_loads(struct radeon_winsys_cs *ib)
198 {
199 radeon_emit(ib, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
200 radeon_emit(ib, CONTEXT_CONTROL_LOAD_ENABLE(1) |
201 CONTEXT_CONTROL_LOAD_CE_RAM(1));
202 radeon_emit(ib, CONTEXT_CONTROL_SHADOW_ENABLE(1));
203 }
204
205 static bool si_upload_descriptors(struct si_context *sctx,
206 struct si_descriptors *desc,
207 struct r600_atom * atom)
208 {
209 unsigned list_size = desc->num_elements * desc->element_dw_size * 4;
210
211 if (!desc->dirty_mask)
212 return true;
213
214 if (sctx->ce_ib) {
215 uint32_t const* list = (uint32_t const*)desc->list;
216
217 if (desc->ce_ram_dirty)
218 si_ce_reinitialize_descriptors(sctx, desc);
219
220 while(desc->dirty_mask) {
221 int begin, count;
222 u_bit_scan_consecutive_range(&desc->dirty_mask, &begin,
223 &count);
224
225 begin *= desc->element_dw_size;
226 count *= desc->element_dw_size;
227
228 radeon_emit(sctx->ce_ib,
229 PKT3(PKT3_WRITE_CONST_RAM, count, 0));
230 radeon_emit(sctx->ce_ib, desc->ce_offset + begin * 4);
231 radeon_emit_array(sctx->ce_ib, list + begin, count);
232 }
233
234 if (!si_ce_upload(sctx, desc->ce_offset, list_size,
235 &desc->buffer_offset, &desc->buffer))
236 return false;
237 } else {
238 void *ptr;
239
240 u_upload_alloc(sctx->b.uploader, 0, list_size, 256,
241 &desc->buffer_offset,
242 (struct pipe_resource**)&desc->buffer, &ptr);
243 if (!desc->buffer)
244 return false; /* skip the draw call */
245
246 util_memcpy_cpu_to_le32(ptr, desc->list, list_size);
247
248 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
249 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
250 }
251 desc->pointer_dirty = true;
252 desc->dirty_mask = 0;
253
254 if (atom)
255 si_mark_atom_dirty(sctx, atom);
256
257 return true;
258 }
259
260 static void
261 si_descriptors_begin_new_cs(struct si_context *sctx, struct si_descriptors *desc)
262 {
263 desc->ce_ram_dirty = true;
264
265 if (!desc->buffer)
266 return;
267
268 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, desc->buffer,
269 RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS);
270 }
271
272 /* SAMPLER VIEWS */
273
274 static unsigned
275 si_sampler_descriptors_idx(unsigned shader)
276 {
277 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
278 SI_SHADER_DESCS_SAMPLERS;
279 }
280
281 static struct si_descriptors *
282 si_sampler_descriptors(struct si_context *sctx, unsigned shader)
283 {
284 return &sctx->descriptors[si_sampler_descriptors_idx(shader)];
285 }
286
287 static void si_release_sampler_views(struct si_sampler_views *views)
288 {
289 int i;
290
291 for (i = 0; i < ARRAY_SIZE(views->views); i++) {
292 pipe_sampler_view_reference(&views->views[i], NULL);
293 }
294 }
295
296 static void si_sampler_view_add_buffer(struct si_context *sctx,
297 struct pipe_resource *resource,
298 enum radeon_bo_usage usage,
299 bool is_stencil_sampler,
300 bool check_mem)
301 {
302 struct r600_resource *rres;
303 struct r600_texture *rtex;
304 enum radeon_bo_priority priority;
305
306 if (!resource)
307 return;
308
309 if (resource->target != PIPE_BUFFER) {
310 struct r600_texture *tex = (struct r600_texture*)resource;
311
312 if (tex->is_depth && !r600_can_sample_zs(tex, is_stencil_sampler))
313 resource = &tex->flushed_depth_texture->resource.b.b;
314 }
315
316 rres = (struct r600_resource*)resource;
317 priority = r600_get_sampler_view_priority(rres);
318
319 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
320 rres, usage, priority,
321 check_mem);
322
323 if (resource->target == PIPE_BUFFER)
324 return;
325
326 /* Now add separate DCC if it's present. */
327 rtex = (struct r600_texture*)resource;
328 if (!rtex->dcc_separate_buffer)
329 return;
330
331 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
332 rtex->dcc_separate_buffer, usage,
333 RADEON_PRIO_DCC, check_mem);
334 }
335
336 static void si_sampler_views_begin_new_cs(struct si_context *sctx,
337 struct si_sampler_views *views)
338 {
339 unsigned mask = views->enabled_mask;
340
341 /* Add buffers to the CS. */
342 while (mask) {
343 int i = u_bit_scan(&mask);
344 struct si_sampler_view *sview = (struct si_sampler_view *)views->views[i];
345
346 si_sampler_view_add_buffer(sctx, sview->base.texture,
347 RADEON_USAGE_READ,
348 sview->is_stencil_sampler, false);
349 }
350 }
351
352 /* Set buffer descriptor fields that can be changed by reallocations. */
353 static void si_set_buf_desc_address(struct r600_resource *buf,
354 uint64_t offset, uint32_t *state)
355 {
356 uint64_t va = buf->gpu_address + offset;
357
358 state[0] = va;
359 state[1] &= C_008F04_BASE_ADDRESS_HI;
360 state[1] |= S_008F04_BASE_ADDRESS_HI(va >> 32);
361 }
362
363 /* Set texture descriptor fields that can be changed by reallocations.
364 *
365 * \param tex texture
366 * \param base_level_info information of the level of BASE_ADDRESS
367 * \param base_level the level of BASE_ADDRESS
368 * \param first_level pipe_sampler_view.u.tex.first_level
369 * \param block_width util_format_get_blockwidth()
370 * \param is_stencil select between separate Z & Stencil
371 * \param state descriptor to update
372 */
373 void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
374 const struct radeon_surf_level *base_level_info,
375 unsigned base_level, unsigned first_level,
376 unsigned block_width, bool is_stencil,
377 uint32_t *state)
378 {
379 uint64_t va;
380 unsigned pitch = base_level_info->nblk_x * block_width;
381
382 if (tex->is_depth && !r600_can_sample_zs(tex, is_stencil)) {
383 tex = tex->flushed_depth_texture;
384 is_stencil = false;
385 }
386
387 va = tex->resource.gpu_address + base_level_info->offset;
388
389 state[1] &= C_008F14_BASE_ADDRESS_HI;
390 state[3] &= C_008F1C_TILING_INDEX;
391 state[4] &= C_008F20_PITCH;
392 state[6] &= C_008F28_COMPRESSION_EN;
393
394 state[0] = va >> 8;
395 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
396 state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(tex, base_level,
397 is_stencil));
398 state[4] |= S_008F20_PITCH(pitch - 1);
399
400 if (tex->dcc_offset && tex->surface.level[first_level].dcc_enabled) {
401 state[6] |= S_008F28_COMPRESSION_EN(1);
402 state[7] = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
403 tex->dcc_offset +
404 base_level_info->dcc_offset) >> 8;
405 }
406 }
407
408 static void si_set_sampler_view(struct si_context *sctx,
409 unsigned shader,
410 unsigned slot, struct pipe_sampler_view *view,
411 bool disallow_early_out)
412 {
413 struct si_sampler_views *views = &sctx->samplers[shader].views;
414 struct si_sampler_view *rview = (struct si_sampler_view*)view;
415 struct si_descriptors *descs = si_sampler_descriptors(sctx, shader);
416
417 if (views->views[slot] == view && !disallow_early_out)
418 return;
419
420 if (view) {
421 struct r600_texture *rtex = (struct r600_texture *)view->texture;
422 uint32_t *desc = descs->list + slot * 16;
423
424 assert(rtex); /* views with texture == NULL aren't supported */
425 pipe_sampler_view_reference(&views->views[slot], view);
426 memcpy(desc, rview->state, 8*4);
427
428 if (rtex->resource.b.b.target == PIPE_BUFFER) {
429 rtex->resource.bind_history |= PIPE_BIND_SAMPLER_VIEW;
430
431 si_set_buf_desc_address(&rtex->resource,
432 view->u.buf.offset,
433 desc + 4);
434 } else {
435 bool is_separate_stencil =
436 rtex->db_compatible &&
437 rview->is_stencil_sampler;
438
439 si_set_mutable_tex_desc_fields(rtex,
440 rview->base_level_info,
441 rview->base_level,
442 rview->base.u.tex.first_level,
443 rview->block_width,
444 is_separate_stencil,
445 desc);
446 }
447
448 if (rtex->resource.b.b.target != PIPE_BUFFER &&
449 rtex->fmask.size) {
450 memcpy(desc + 8,
451 rview->fmask_state, 8*4);
452 } else {
453 /* Disable FMASK and bind sampler state in [12:15]. */
454 memcpy(desc + 8,
455 null_texture_descriptor, 4*4);
456
457 if (views->sampler_states[slot])
458 memcpy(desc + 12,
459 views->sampler_states[slot], 4*4);
460 }
461
462 views->enabled_mask |= 1u << slot;
463
464 /* Since this can flush, it must be done after enabled_mask is
465 * updated. */
466 si_sampler_view_add_buffer(sctx, view->texture,
467 RADEON_USAGE_READ,
468 rview->is_stencil_sampler, true);
469 } else {
470 pipe_sampler_view_reference(&views->views[slot], NULL);
471 memcpy(descs->list + slot*16, null_texture_descriptor, 8*4);
472 /* Only clear the lower dwords of FMASK. */
473 memcpy(descs->list + slot*16 + 8, null_texture_descriptor, 4*4);
474 views->enabled_mask &= ~(1u << slot);
475 }
476
477 descs->dirty_mask |= 1u << slot;
478 sctx->descriptors_dirty |= 1u << si_sampler_descriptors_idx(shader);
479 }
480
481 static bool is_compressed_colortex(struct r600_texture *rtex)
482 {
483 return rtex->cmask.size || rtex->fmask.size ||
484 (rtex->dcc_offset && rtex->dirty_level_mask);
485 }
486
487 static void si_set_sampler_views(struct pipe_context *ctx,
488 enum pipe_shader_type shader, unsigned start,
489 unsigned count,
490 struct pipe_sampler_view **views)
491 {
492 struct si_context *sctx = (struct si_context *)ctx;
493 struct si_textures_info *samplers = &sctx->samplers[shader];
494 int i;
495
496 if (!count || shader >= SI_NUM_SHADERS)
497 return;
498
499 for (i = 0; i < count; i++) {
500 unsigned slot = start + i;
501
502 if (!views || !views[i]) {
503 samplers->depth_texture_mask &= ~(1u << slot);
504 samplers->compressed_colortex_mask &= ~(1u << slot);
505 si_set_sampler_view(sctx, shader, slot, NULL, false);
506 continue;
507 }
508
509 si_set_sampler_view(sctx, shader, slot, views[i], false);
510
511 if (views[i]->texture && views[i]->texture->target != PIPE_BUFFER) {
512 struct r600_texture *rtex =
513 (struct r600_texture*)views[i]->texture;
514
515 if (rtex->db_compatible) {
516 samplers->depth_texture_mask |= 1u << slot;
517 } else {
518 samplers->depth_texture_mask &= ~(1u << slot);
519 }
520 if (is_compressed_colortex(rtex)) {
521 samplers->compressed_colortex_mask |= 1u << slot;
522 } else {
523 samplers->compressed_colortex_mask &= ~(1u << slot);
524 }
525
526 if (rtex->dcc_offset &&
527 p_atomic_read(&rtex->framebuffers_bound))
528 sctx->need_check_render_feedback = true;
529 } else {
530 samplers->depth_texture_mask &= ~(1u << slot);
531 samplers->compressed_colortex_mask &= ~(1u << slot);
532 }
533 }
534 }
535
536 static void
537 si_samplers_update_compressed_colortex_mask(struct si_textures_info *samplers)
538 {
539 unsigned mask = samplers->views.enabled_mask;
540
541 while (mask) {
542 int i = u_bit_scan(&mask);
543 struct pipe_resource *res = samplers->views.views[i]->texture;
544
545 if (res && res->target != PIPE_BUFFER) {
546 struct r600_texture *rtex = (struct r600_texture *)res;
547
548 if (is_compressed_colortex(rtex)) {
549 samplers->compressed_colortex_mask |= 1u << i;
550 } else {
551 samplers->compressed_colortex_mask &= ~(1u << i);
552 }
553 }
554 }
555 }
556
557 /* IMAGE VIEWS */
558
559 static unsigned
560 si_image_descriptors_idx(unsigned shader)
561 {
562 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
563 SI_SHADER_DESCS_IMAGES;
564 }
565
566 static struct si_descriptors*
567 si_image_descriptors(struct si_context *sctx, unsigned shader)
568 {
569 return &sctx->descriptors[si_image_descriptors_idx(shader)];
570 }
571
572 static void
573 si_release_image_views(struct si_images_info *images)
574 {
575 unsigned i;
576
577 for (i = 0; i < SI_NUM_IMAGES; ++i) {
578 struct pipe_image_view *view = &images->views[i];
579
580 pipe_resource_reference(&view->resource, NULL);
581 }
582 }
583
584 static void
585 si_image_views_begin_new_cs(struct si_context *sctx, struct si_images_info *images)
586 {
587 uint mask = images->enabled_mask;
588
589 /* Add buffers to the CS. */
590 while (mask) {
591 int i = u_bit_scan(&mask);
592 struct pipe_image_view *view = &images->views[i];
593
594 assert(view->resource);
595
596 si_sampler_view_add_buffer(sctx, view->resource,
597 RADEON_USAGE_READWRITE, false, false);
598 }
599 }
600
601 static void
602 si_disable_shader_image(struct si_context *ctx, unsigned shader, unsigned slot)
603 {
604 struct si_images_info *images = &ctx->images[shader];
605
606 if (images->enabled_mask & (1u << slot)) {
607 struct si_descriptors *descs = si_image_descriptors(ctx, shader);
608
609 pipe_resource_reference(&images->views[slot].resource, NULL);
610 images->compressed_colortex_mask &= ~(1 << slot);
611
612 memcpy(descs->list + slot*8, null_image_descriptor, 8*4);
613 images->enabled_mask &= ~(1u << slot);
614 descs->dirty_mask |= 1u << slot;
615 ctx->descriptors_dirty |= 1u << si_image_descriptors_idx(shader);
616 }
617 }
618
619 static void
620 si_mark_image_range_valid(const struct pipe_image_view *view)
621 {
622 struct r600_resource *res = (struct r600_resource *)view->resource;
623
624 assert(res && res->b.b.target == PIPE_BUFFER);
625
626 util_range_add(&res->valid_buffer_range,
627 view->u.buf.offset,
628 view->u.buf.offset + view->u.buf.size);
629 }
630
631 static void si_set_shader_image(struct si_context *ctx,
632 unsigned shader,
633 unsigned slot, const struct pipe_image_view *view)
634 {
635 struct si_screen *screen = ctx->screen;
636 struct si_images_info *images = &ctx->images[shader];
637 struct si_descriptors *descs = si_image_descriptors(ctx, shader);
638 struct r600_resource *res;
639 uint32_t *desc = descs->list + slot * 8;
640
641 if (!view || !view->resource) {
642 si_disable_shader_image(ctx, shader, slot);
643 return;
644 }
645
646 res = (struct r600_resource *)view->resource;
647
648 if (&images->views[slot] != view)
649 util_copy_image_view(&images->views[slot], view);
650
651 if (res->b.b.target == PIPE_BUFFER) {
652 if (view->access & PIPE_IMAGE_ACCESS_WRITE)
653 si_mark_image_range_valid(view);
654
655 si_make_buffer_descriptor(screen, res,
656 view->format,
657 view->u.buf.offset,
658 view->u.buf.size,
659 descs->list + slot * 8);
660 si_set_buf_desc_address(res, view->u.buf.offset, desc + 4);
661
662 images->compressed_colortex_mask &= ~(1 << slot);
663 res->bind_history |= PIPE_BIND_SHADER_IMAGE;
664 } else {
665 static const unsigned char swizzle[4] = { 0, 1, 2, 3 };
666 struct r600_texture *tex = (struct r600_texture *)res;
667 unsigned level = view->u.tex.level;
668 unsigned width, height, depth;
669 bool uses_dcc = tex->dcc_offset &&
670 tex->surface.level[level].dcc_enabled;
671
672 assert(!tex->is_depth);
673 assert(tex->fmask.size == 0);
674
675 if (uses_dcc &&
676 (view->access & PIPE_IMAGE_ACCESS_WRITE ||
677 !vi_dcc_formats_compatible(res->b.b.format, view->format))) {
678 /* If DCC can't be disabled, at least decompress it.
679 * The decompression is relatively cheap if the surface
680 * has been decompressed already.
681 */
682 if (r600_texture_disable_dcc(&ctx->b, tex))
683 uses_dcc = false;
684 else
685 ctx->b.decompress_dcc(&ctx->b.b, tex);
686 }
687
688 if (is_compressed_colortex(tex)) {
689 images->compressed_colortex_mask |= 1 << slot;
690 } else {
691 images->compressed_colortex_mask &= ~(1 << slot);
692 }
693
694 if (uses_dcc &&
695 p_atomic_read(&tex->framebuffers_bound))
696 ctx->need_check_render_feedback = true;
697
698 /* Always force the base level to the selected level.
699 *
700 * This is required for 3D textures, where otherwise
701 * selecting a single slice for non-layered bindings
702 * fails. It doesn't hurt the other targets.
703 */
704 width = u_minify(res->b.b.width0, level);
705 height = u_minify(res->b.b.height0, level);
706 depth = u_minify(res->b.b.depth0, level);
707
708 si_make_texture_descriptor(screen, tex,
709 false, res->b.b.target,
710 view->format, swizzle,
711 0, 0,
712 view->u.tex.first_layer,
713 view->u.tex.last_layer,
714 width, height, depth,
715 desc, NULL);
716 si_set_mutable_tex_desc_fields(tex, &tex->surface.level[level],
717 level, level,
718 util_format_get_blockwidth(view->format),
719 false, desc);
720 }
721
722 images->enabled_mask |= 1u << slot;
723 descs->dirty_mask |= 1u << slot;
724 ctx->descriptors_dirty |= 1u << si_image_descriptors_idx(shader);
725
726 /* Since this can flush, it must be done after enabled_mask is updated. */
727 si_sampler_view_add_buffer(ctx, &res->b.b,
728 RADEON_USAGE_READWRITE, false, true);
729 }
730
731 static void
732 si_set_shader_images(struct pipe_context *pipe,
733 enum pipe_shader_type shader,
734 unsigned start_slot, unsigned count,
735 const struct pipe_image_view *views)
736 {
737 struct si_context *ctx = (struct si_context *)pipe;
738 unsigned i, slot;
739
740 assert(shader < SI_NUM_SHADERS);
741
742 if (!count)
743 return;
744
745 assert(start_slot + count <= SI_NUM_IMAGES);
746
747 if (views) {
748 for (i = 0, slot = start_slot; i < count; ++i, ++slot)
749 si_set_shader_image(ctx, shader, slot, &views[i]);
750 } else {
751 for (i = 0, slot = start_slot; i < count; ++i, ++slot)
752 si_set_shader_image(ctx, shader, slot, NULL);
753 }
754 }
755
756 static void
757 si_images_update_compressed_colortex_mask(struct si_images_info *images)
758 {
759 unsigned mask = images->enabled_mask;
760
761 while (mask) {
762 int i = u_bit_scan(&mask);
763 struct pipe_resource *res = images->views[i].resource;
764
765 if (res && res->target != PIPE_BUFFER) {
766 struct r600_texture *rtex = (struct r600_texture *)res;
767
768 if (is_compressed_colortex(rtex)) {
769 images->compressed_colortex_mask |= 1 << i;
770 } else {
771 images->compressed_colortex_mask &= ~(1 << i);
772 }
773 }
774 }
775 }
776
777 /* SAMPLER STATES */
778
779 static void si_bind_sampler_states(struct pipe_context *ctx,
780 enum pipe_shader_type shader,
781 unsigned start, unsigned count, void **states)
782 {
783 struct si_context *sctx = (struct si_context *)ctx;
784 struct si_textures_info *samplers = &sctx->samplers[shader];
785 struct si_descriptors *desc = si_sampler_descriptors(sctx, shader);
786 struct si_sampler_state **sstates = (struct si_sampler_state**)states;
787 int i;
788
789 if (!count || shader >= SI_NUM_SHADERS)
790 return;
791
792 for (i = 0; i < count; i++) {
793 unsigned slot = start + i;
794
795 if (!sstates[i] ||
796 sstates[i] == samplers->views.sampler_states[slot])
797 continue;
798
799 samplers->views.sampler_states[slot] = sstates[i];
800
801 /* If FMASK is bound, don't overwrite it.
802 * The sampler state will be set after FMASK is unbound.
803 */
804 if (samplers->views.views[i] &&
805 samplers->views.views[i]->texture &&
806 samplers->views.views[i]->texture->target != PIPE_BUFFER &&
807 ((struct r600_texture*)samplers->views.views[i]->texture)->fmask.size)
808 continue;
809
810 memcpy(desc->list + slot * 16 + 12, sstates[i]->val, 4*4);
811 desc->dirty_mask |= 1u << slot;
812 sctx->descriptors_dirty |= 1u << si_sampler_descriptors_idx(shader);
813 }
814 }
815
816 /* BUFFER RESOURCES */
817
818 static void si_init_buffer_resources(struct si_buffer_resources *buffers,
819 struct si_descriptors *descs,
820 unsigned num_buffers,
821 unsigned shader_userdata_index,
822 enum radeon_bo_usage shader_usage,
823 enum radeon_bo_priority priority,
824 unsigned *ce_offset)
825 {
826 buffers->shader_usage = shader_usage;
827 buffers->priority = priority;
828 buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource*));
829
830 si_init_descriptors(descs, shader_userdata_index, 4,
831 num_buffers, NULL, ce_offset);
832 }
833
834 static void si_release_buffer_resources(struct si_buffer_resources *buffers,
835 struct si_descriptors *descs)
836 {
837 int i;
838
839 for (i = 0; i < descs->num_elements; i++) {
840 pipe_resource_reference(&buffers->buffers[i], NULL);
841 }
842
843 FREE(buffers->buffers);
844 }
845
846 static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
847 struct si_buffer_resources *buffers)
848 {
849 unsigned mask = buffers->enabled_mask;
850
851 /* Add buffers to the CS. */
852 while (mask) {
853 int i = u_bit_scan(&mask);
854
855 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
856 (struct r600_resource*)buffers->buffers[i],
857 buffers->shader_usage, buffers->priority);
858 }
859 }
860
861 static void si_get_buffer_from_descriptors(struct si_buffer_resources *buffers,
862 struct si_descriptors *descs,
863 unsigned idx, struct pipe_resource **buf,
864 unsigned *offset, unsigned *size)
865 {
866 pipe_resource_reference(buf, buffers->buffers[idx]);
867 if (*buf) {
868 struct r600_resource *res = r600_resource(*buf);
869 const uint32_t *desc = descs->list + idx * 4;
870 uint64_t va;
871
872 *size = desc[2];
873
874 assert(G_008F04_STRIDE(desc[1]) == 0);
875 va = ((uint64_t)desc[1] << 32) | desc[0];
876
877 assert(va >= res->gpu_address && va + *size <= res->gpu_address + res->bo_size);
878 *offset = va - res->gpu_address;
879 }
880 }
881
882 /* VERTEX BUFFERS */
883
884 static void si_vertex_buffers_begin_new_cs(struct si_context *sctx)
885 {
886 struct si_descriptors *desc = &sctx->vertex_buffers;
887 int count = sctx->vertex_elements ? sctx->vertex_elements->count : 0;
888 int i;
889
890 for (i = 0; i < count; i++) {
891 int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
892
893 if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
894 continue;
895 if (!sctx->vertex_buffer[vb].buffer)
896 continue;
897
898 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
899 (struct r600_resource*)sctx->vertex_buffer[vb].buffer,
900 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
901 }
902
903 if (!desc->buffer)
904 return;
905 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
906 desc->buffer, RADEON_USAGE_READ,
907 RADEON_PRIO_DESCRIPTORS);
908 }
909
910 bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
911 {
912 struct si_descriptors *desc = &sctx->vertex_buffers;
913 bool bound[SI_NUM_VERTEX_BUFFERS] = {};
914 unsigned i, count = sctx->vertex_elements->count;
915 uint64_t va;
916 uint32_t *ptr;
917
918 if (!sctx->vertex_buffers_dirty)
919 return true;
920 if (!count || !sctx->vertex_elements)
921 return true;
922
923 /* Vertex buffer descriptors are the only ones which are uploaded
924 * directly through a staging buffer and don't go through
925 * the fine-grained upload path.
926 */
927 u_upload_alloc(sctx->b.uploader, 0, count * 16, 256, &desc->buffer_offset,
928 (struct pipe_resource**)&desc->buffer, (void**)&ptr);
929 if (!desc->buffer)
930 return false;
931
932 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
933 desc->buffer, RADEON_USAGE_READ,
934 RADEON_PRIO_DESCRIPTORS);
935
936 assert(count <= SI_NUM_VERTEX_BUFFERS);
937
938 for (i = 0; i < count; i++) {
939 struct pipe_vertex_element *ve = &sctx->vertex_elements->elements[i];
940 struct pipe_vertex_buffer *vb;
941 struct r600_resource *rbuffer;
942 unsigned offset;
943 uint32_t *desc = &ptr[i*4];
944
945 if (ve->vertex_buffer_index >= ARRAY_SIZE(sctx->vertex_buffer)) {
946 memset(desc, 0, 16);
947 continue;
948 }
949
950 vb = &sctx->vertex_buffer[ve->vertex_buffer_index];
951 rbuffer = (struct r600_resource*)vb->buffer;
952 if (!rbuffer) {
953 memset(desc, 0, 16);
954 continue;
955 }
956
957 offset = vb->buffer_offset + ve->src_offset;
958 va = rbuffer->gpu_address + offset;
959
960 /* Fill in T# buffer resource description */
961 desc[0] = va;
962 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
963 S_008F04_STRIDE(vb->stride);
964
965 if (sctx->b.chip_class <= CIK && vb->stride)
966 /* Round up by rounding down and adding 1 */
967 desc[2] = (vb->buffer->width0 - offset -
968 sctx->vertex_elements->format_size[i]) /
969 vb->stride + 1;
970 else
971 desc[2] = vb->buffer->width0 - offset;
972
973 desc[3] = sctx->vertex_elements->rsrc_word3[i];
974
975 if (!bound[ve->vertex_buffer_index]) {
976 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
977 (struct r600_resource*)vb->buffer,
978 RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER);
979 bound[ve->vertex_buffer_index] = true;
980 }
981 }
982
983 /* Don't flush the const cache. It would have a very negative effect
984 * on performance (confirmed by testing). New descriptors are always
985 * uploaded to a fresh new buffer, so I don't think flushing the const
986 * cache is needed. */
987 desc->pointer_dirty = true;
988 si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
989 sctx->vertex_buffers_dirty = false;
990 return true;
991 }
992
993
994 /* CONSTANT BUFFERS */
995
996 static unsigned
997 si_const_buffer_descriptors_idx(unsigned shader)
998 {
999 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
1000 SI_SHADER_DESCS_CONST_BUFFERS;
1001 }
1002
1003 static struct si_descriptors *
1004 si_const_buffer_descriptors(struct si_context *sctx, unsigned shader)
1005 {
1006 return &sctx->descriptors[si_const_buffer_descriptors_idx(shader)];
1007 }
1008
1009 void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
1010 const uint8_t *ptr, unsigned size, uint32_t *const_offset)
1011 {
1012 void *tmp;
1013
1014 u_upload_alloc(sctx->b.uploader, 0, size, 256, const_offset,
1015 (struct pipe_resource**)rbuffer, &tmp);
1016 if (*rbuffer)
1017 util_memcpy_cpu_to_le32(tmp, ptr, size);
1018 }
1019
1020 static void si_set_constant_buffer(struct si_context *sctx,
1021 struct si_buffer_resources *buffers,
1022 unsigned descriptors_idx,
1023 uint slot, const struct pipe_constant_buffer *input)
1024 {
1025 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
1026 assert(slot < descs->num_elements);
1027 pipe_resource_reference(&buffers->buffers[slot], NULL);
1028
1029 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1030 * with a NULL buffer). We need to use a dummy buffer instead. */
1031 if (sctx->b.chip_class == CIK &&
1032 (!input || (!input->buffer && !input->user_buffer)))
1033 input = &sctx->null_const_buf;
1034
1035 if (input && (input->buffer || input->user_buffer)) {
1036 struct pipe_resource *buffer = NULL;
1037 uint64_t va;
1038
1039 /* Upload the user buffer if needed. */
1040 if (input->user_buffer) {
1041 unsigned buffer_offset;
1042
1043 si_upload_const_buffer(sctx,
1044 (struct r600_resource**)&buffer, input->user_buffer,
1045 input->buffer_size, &buffer_offset);
1046 if (!buffer) {
1047 /* Just unbind on failure. */
1048 si_set_constant_buffer(sctx, buffers, descriptors_idx, slot, NULL);
1049 return;
1050 }
1051 va = r600_resource(buffer)->gpu_address + buffer_offset;
1052 } else {
1053 pipe_resource_reference(&buffer, input->buffer);
1054 va = r600_resource(buffer)->gpu_address + input->buffer_offset;
1055 /* Only track usage for non-user buffers. */
1056 r600_resource(buffer)->bind_history |= PIPE_BIND_CONSTANT_BUFFER;
1057 }
1058
1059 /* Set the descriptor. */
1060 uint32_t *desc = descs->list + slot*4;
1061 desc[0] = va;
1062 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1063 S_008F04_STRIDE(0);
1064 desc[2] = input->buffer_size;
1065 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1066 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1067 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1068 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1069 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1070 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1071
1072 buffers->buffers[slot] = buffer;
1073 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1074 (struct r600_resource*)buffer,
1075 buffers->shader_usage,
1076 buffers->priority, true);
1077 buffers->enabled_mask |= 1u << slot;
1078 } else {
1079 /* Clear the descriptor. */
1080 memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4);
1081 buffers->enabled_mask &= ~(1u << slot);
1082 }
1083
1084 descs->dirty_mask |= 1u << slot;
1085 sctx->descriptors_dirty |= 1u << descriptors_idx;
1086 }
1087
1088 void si_set_rw_buffer(struct si_context *sctx,
1089 uint slot, const struct pipe_constant_buffer *input)
1090 {
1091 si_set_constant_buffer(sctx, &sctx->rw_buffers,
1092 SI_DESCS_RW_BUFFERS, slot, input);
1093 }
1094
1095 static void si_pipe_set_constant_buffer(struct pipe_context *ctx,
1096 uint shader, uint slot,
1097 const struct pipe_constant_buffer *input)
1098 {
1099 struct si_context *sctx = (struct si_context *)ctx;
1100
1101 if (shader >= SI_NUM_SHADERS)
1102 return;
1103
1104 si_set_constant_buffer(sctx, &sctx->const_buffers[shader],
1105 si_const_buffer_descriptors_idx(shader),
1106 slot, input);
1107 }
1108
1109 void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader,
1110 uint slot, struct pipe_constant_buffer *cbuf)
1111 {
1112 cbuf->user_buffer = NULL;
1113 si_get_buffer_from_descriptors(
1114 &sctx->const_buffers[shader],
1115 si_const_buffer_descriptors(sctx, shader),
1116 slot, &cbuf->buffer, &cbuf->buffer_offset, &cbuf->buffer_size);
1117 }
1118
1119 /* SHADER BUFFERS */
1120
1121 static unsigned
1122 si_shader_buffer_descriptors_idx(enum pipe_shader_type shader)
1123 {
1124 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
1125 SI_SHADER_DESCS_SHADER_BUFFERS;
1126 }
1127
1128 static struct si_descriptors *
1129 si_shader_buffer_descriptors(struct si_context *sctx,
1130 enum pipe_shader_type shader)
1131 {
1132 return &sctx->descriptors[si_shader_buffer_descriptors_idx(shader)];
1133 }
1134
1135 static void si_set_shader_buffers(struct pipe_context *ctx,
1136 enum pipe_shader_type shader,
1137 unsigned start_slot, unsigned count,
1138 const struct pipe_shader_buffer *sbuffers)
1139 {
1140 struct si_context *sctx = (struct si_context *)ctx;
1141 struct si_buffer_resources *buffers = &sctx->shader_buffers[shader];
1142 struct si_descriptors *descs = si_shader_buffer_descriptors(sctx, shader);
1143 unsigned i;
1144
1145 assert(start_slot + count <= SI_NUM_SHADER_BUFFERS);
1146
1147 for (i = 0; i < count; ++i) {
1148 const struct pipe_shader_buffer *sbuffer = sbuffers ? &sbuffers[i] : NULL;
1149 struct r600_resource *buf;
1150 unsigned slot = start_slot + i;
1151 uint32_t *desc = descs->list + slot * 4;
1152 uint64_t va;
1153
1154 if (!sbuffer || !sbuffer->buffer) {
1155 pipe_resource_reference(&buffers->buffers[slot], NULL);
1156 memset(desc, 0, sizeof(uint32_t) * 4);
1157 buffers->enabled_mask &= ~(1u << slot);
1158 descs->dirty_mask |= 1u << slot;
1159 sctx->descriptors_dirty |=
1160 1u << si_shader_buffer_descriptors_idx(shader);
1161 continue;
1162 }
1163
1164 buf = (struct r600_resource *)sbuffer->buffer;
1165 va = buf->gpu_address + sbuffer->buffer_offset;
1166
1167 desc[0] = va;
1168 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1169 S_008F04_STRIDE(0);
1170 desc[2] = sbuffer->buffer_size;
1171 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1172 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1173 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1174 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1175 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1176 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1177
1178 pipe_resource_reference(&buffers->buffers[slot], &buf->b.b);
1179 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx, buf,
1180 buffers->shader_usage,
1181 buffers->priority, true);
1182 buf->bind_history |= PIPE_BIND_SHADER_BUFFER;
1183
1184 buffers->enabled_mask |= 1u << slot;
1185 descs->dirty_mask |= 1u << slot;
1186 sctx->descriptors_dirty |=
1187 1u << si_shader_buffer_descriptors_idx(shader);
1188 }
1189 }
1190
1191 void si_get_shader_buffers(struct si_context *sctx, uint shader,
1192 uint start_slot, uint count,
1193 struct pipe_shader_buffer *sbuf)
1194 {
1195 struct si_buffer_resources *buffers = &sctx->shader_buffers[shader];
1196 struct si_descriptors *descs = si_shader_buffer_descriptors(sctx, shader);
1197
1198 for (unsigned i = 0; i < count; ++i) {
1199 si_get_buffer_from_descriptors(
1200 buffers, descs, start_slot + i,
1201 &sbuf[i].buffer, &sbuf[i].buffer_offset,
1202 &sbuf[i].buffer_size);
1203 }
1204 }
1205
1206 /* RING BUFFERS */
1207
1208 void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
1209 struct pipe_resource *buffer,
1210 unsigned stride, unsigned num_records,
1211 bool add_tid, bool swizzle,
1212 unsigned element_size, unsigned index_stride, uint64_t offset)
1213 {
1214 struct si_context *sctx = (struct si_context *)ctx;
1215 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1216 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1217
1218 /* The stride field in the resource descriptor has 14 bits */
1219 assert(stride < (1 << 14));
1220
1221 assert(slot < descs->num_elements);
1222 pipe_resource_reference(&buffers->buffers[slot], NULL);
1223
1224 if (buffer) {
1225 uint64_t va;
1226
1227 va = r600_resource(buffer)->gpu_address + offset;
1228
1229 switch (element_size) {
1230 default:
1231 assert(!"Unsupported ring buffer element size");
1232 case 0:
1233 case 2:
1234 element_size = 0;
1235 break;
1236 case 4:
1237 element_size = 1;
1238 break;
1239 case 8:
1240 element_size = 2;
1241 break;
1242 case 16:
1243 element_size = 3;
1244 break;
1245 }
1246
1247 switch (index_stride) {
1248 default:
1249 assert(!"Unsupported ring buffer index stride");
1250 case 0:
1251 case 8:
1252 index_stride = 0;
1253 break;
1254 case 16:
1255 index_stride = 1;
1256 break;
1257 case 32:
1258 index_stride = 2;
1259 break;
1260 case 64:
1261 index_stride = 3;
1262 break;
1263 }
1264
1265 if (sctx->b.chip_class >= VI && stride)
1266 num_records *= stride;
1267
1268 /* Set the descriptor. */
1269 uint32_t *desc = descs->list + slot*4;
1270 desc[0] = va;
1271 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
1272 S_008F04_STRIDE(stride) |
1273 S_008F04_SWIZZLE_ENABLE(swizzle);
1274 desc[2] = num_records;
1275 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1276 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1277 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1278 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1279 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1280 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1281 S_008F0C_ELEMENT_SIZE(element_size) |
1282 S_008F0C_INDEX_STRIDE(index_stride) |
1283 S_008F0C_ADD_TID_ENABLE(add_tid);
1284
1285 pipe_resource_reference(&buffers->buffers[slot], buffer);
1286 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
1287 (struct r600_resource*)buffer,
1288 buffers->shader_usage, buffers->priority);
1289 buffers->enabled_mask |= 1u << slot;
1290 } else {
1291 /* Clear the descriptor. */
1292 memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4);
1293 buffers->enabled_mask &= ~(1u << slot);
1294 }
1295
1296 descs->dirty_mask |= 1u << slot;
1297 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1298 }
1299
1300 /* STREAMOUT BUFFERS */
1301
1302 static void si_set_streamout_targets(struct pipe_context *ctx,
1303 unsigned num_targets,
1304 struct pipe_stream_output_target **targets,
1305 const unsigned *offsets)
1306 {
1307 struct si_context *sctx = (struct si_context *)ctx;
1308 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1309 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1310 unsigned old_num_targets = sctx->b.streamout.num_targets;
1311 unsigned i, bufidx;
1312
1313 /* We are going to unbind the buffers. Mark which caches need to be flushed. */
1314 if (sctx->b.streamout.num_targets && sctx->b.streamout.begin_emitted) {
1315 /* Since streamout uses vector writes which go through TC L2
1316 * and most other clients can use TC L2 as well, we don't need
1317 * to flush it.
1318 *
1319 * The only cases which requires flushing it is VGT DMA index
1320 * fetching (on <= CIK) and indirect draw data, which are rare
1321 * cases. Thus, flag the TC L2 dirtiness in the resource and
1322 * handle it at draw call time.
1323 */
1324 for (i = 0; i < sctx->b.streamout.num_targets; i++)
1325 if (sctx->b.streamout.targets[i])
1326 r600_resource(sctx->b.streamout.targets[i]->b.buffer)->TC_L2_dirty = true;
1327
1328 /* Invalidate the scalar cache in case a streamout buffer is
1329 * going to be used as a constant buffer.
1330 *
1331 * Invalidate TC L1, because streamout bypasses it (done by
1332 * setting GLC=1 in the store instruction), but it can contain
1333 * outdated data of streamout buffers.
1334 *
1335 * VS_PARTIAL_FLUSH is required if the buffers are going to be
1336 * used as an input immediately.
1337 */
1338 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
1339 SI_CONTEXT_INV_VMEM_L1 |
1340 SI_CONTEXT_VS_PARTIAL_FLUSH;
1341 }
1342
1343 /* All readers of the streamout targets need to be finished before we can
1344 * start writing to the targets.
1345 */
1346 if (num_targets)
1347 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
1348 SI_CONTEXT_CS_PARTIAL_FLUSH;
1349
1350 /* Streamout buffers must be bound in 2 places:
1351 * 1) in VGT by setting the VGT_STRMOUT registers
1352 * 2) as shader resources
1353 */
1354
1355 /* Set the VGT regs. */
1356 r600_set_streamout_targets(ctx, num_targets, targets, offsets);
1357
1358 /* Set the shader resources.*/
1359 for (i = 0; i < num_targets; i++) {
1360 bufidx = SI_VS_STREAMOUT_BUF0 + i;
1361
1362 if (targets[i]) {
1363 struct pipe_resource *buffer = targets[i]->buffer;
1364 uint64_t va = r600_resource(buffer)->gpu_address;
1365
1366 /* Set the descriptor.
1367 *
1368 * On VI, the format must be non-INVALID, otherwise
1369 * the buffer will be considered not bound and store
1370 * instructions will be no-ops.
1371 */
1372 uint32_t *desc = descs->list + bufidx*4;
1373 desc[0] = va;
1374 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1375 desc[2] = 0xffffffff;
1376 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1377 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1378 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1379 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1380 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1381
1382 /* Set the resource. */
1383 pipe_resource_reference(&buffers->buffers[bufidx],
1384 buffer);
1385 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1386 (struct r600_resource*)buffer,
1387 buffers->shader_usage,
1388 RADEON_PRIO_SHADER_RW_BUFFER,
1389 true);
1390 r600_resource(buffer)->bind_history |= PIPE_BIND_STREAM_OUTPUT;
1391
1392 buffers->enabled_mask |= 1u << bufidx;
1393 } else {
1394 /* Clear the descriptor and unset the resource. */
1395 memset(descs->list + bufidx*4, 0,
1396 sizeof(uint32_t) * 4);
1397 pipe_resource_reference(&buffers->buffers[bufidx],
1398 NULL);
1399 buffers->enabled_mask &= ~(1u << bufidx);
1400 }
1401 descs->dirty_mask |= 1u << bufidx;
1402 }
1403 for (; i < old_num_targets; i++) {
1404 bufidx = SI_VS_STREAMOUT_BUF0 + i;
1405 /* Clear the descriptor and unset the resource. */
1406 memset(descs->list + bufidx*4, 0, sizeof(uint32_t) * 4);
1407 pipe_resource_reference(&buffers->buffers[bufidx], NULL);
1408 buffers->enabled_mask &= ~(1u << bufidx);
1409 descs->dirty_mask |= 1u << bufidx;
1410 }
1411
1412 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1413 }
1414
1415 static void si_desc_reset_buffer_offset(struct pipe_context *ctx,
1416 uint32_t *desc, uint64_t old_buf_va,
1417 struct pipe_resource *new_buf)
1418 {
1419 /* Retrieve the buffer offset from the descriptor. */
1420 uint64_t old_desc_va =
1421 desc[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc[1]) << 32);
1422
1423 assert(old_buf_va <= old_desc_va);
1424 uint64_t offset_within_buffer = old_desc_va - old_buf_va;
1425
1426 /* Update the descriptor. */
1427 si_set_buf_desc_address(r600_resource(new_buf), offset_within_buffer,
1428 desc);
1429 }
1430
1431 /* INTERNAL CONST BUFFERS */
1432
1433 static void si_set_polygon_stipple(struct pipe_context *ctx,
1434 const struct pipe_poly_stipple *state)
1435 {
1436 struct si_context *sctx = (struct si_context *)ctx;
1437 struct pipe_constant_buffer cb = {};
1438 unsigned stipple[32];
1439 int i;
1440
1441 for (i = 0; i < 32; i++)
1442 stipple[i] = util_bitreverse(state->stipple[i]);
1443
1444 cb.user_buffer = stipple;
1445 cb.buffer_size = sizeof(stipple);
1446
1447 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE, &cb);
1448 }
1449
1450 /* TEXTURE METADATA ENABLE/DISABLE */
1451
1452 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1453 * while the texture is bound, possibly by a different context. In that case,
1454 * call this function to update compressed_colortex_masks.
1455 */
1456 void si_update_compressed_colortex_masks(struct si_context *sctx)
1457 {
1458 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
1459 si_samplers_update_compressed_colortex_mask(&sctx->samplers[i]);
1460 si_images_update_compressed_colortex_mask(&sctx->images[i]);
1461 }
1462 }
1463
1464 /* BUFFER DISCARD/INVALIDATION */
1465
1466 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1467 static void si_reset_buffer_resources(struct si_context *sctx,
1468 struct si_buffer_resources *buffers,
1469 unsigned descriptors_idx,
1470 struct pipe_resource *buf,
1471 uint64_t old_va)
1472 {
1473 struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
1474 unsigned mask = buffers->enabled_mask;
1475
1476 while (mask) {
1477 unsigned i = u_bit_scan(&mask);
1478 if (buffers->buffers[i] == buf) {
1479 si_desc_reset_buffer_offset(&sctx->b.b,
1480 descs->list + i*4,
1481 old_va, buf);
1482 descs->dirty_mask |= 1u << i;
1483 sctx->descriptors_dirty |= 1u << descriptors_idx;
1484
1485 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1486 (struct r600_resource *)buf,
1487 buffers->shader_usage,
1488 buffers->priority, true);
1489 }
1490 }
1491 }
1492
1493 /* Reallocate a buffer a update all resource bindings where the buffer is
1494 * bound.
1495 *
1496 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
1497 * idle by discarding its contents. Apps usually tell us when to do this using
1498 * map_buffer flags, for example.
1499 */
1500 static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
1501 {
1502 struct si_context *sctx = (struct si_context*)ctx;
1503 struct r600_resource *rbuffer = r600_resource(buf);
1504 unsigned i, shader;
1505 uint64_t old_va = rbuffer->gpu_address;
1506 unsigned num_elems = sctx->vertex_elements ?
1507 sctx->vertex_elements->count : 0;
1508
1509 /* Reallocate the buffer in the same pipe_resource. */
1510 r600_alloc_resource(&sctx->screen->b, rbuffer);
1511
1512 /* We changed the buffer, now we need to bind it where the old one
1513 * was bound. This consists of 2 things:
1514 * 1) Updating the resource descriptor and dirtying it.
1515 * 2) Adding a relocation to the CS, so that it's usable.
1516 */
1517
1518 /* Vertex buffers. */
1519 if (rbuffer->bind_history & PIPE_BIND_VERTEX_BUFFER) {
1520 for (i = 0; i < num_elems; i++) {
1521 int vb = sctx->vertex_elements->elements[i].vertex_buffer_index;
1522
1523 if (vb >= ARRAY_SIZE(sctx->vertex_buffer))
1524 continue;
1525 if (!sctx->vertex_buffer[vb].buffer)
1526 continue;
1527
1528 if (sctx->vertex_buffer[vb].buffer == buf) {
1529 sctx->vertex_buffers_dirty = true;
1530 break;
1531 }
1532 }
1533 }
1534
1535 /* Streamout buffers. (other internal buffers can't be invalidated) */
1536 if (rbuffer->bind_history & PIPE_BIND_STREAM_OUTPUT) {
1537 for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) {
1538 struct si_buffer_resources *buffers = &sctx->rw_buffers;
1539 struct si_descriptors *descs =
1540 &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1541
1542 if (buffers->buffers[i] != buf)
1543 continue;
1544
1545 si_desc_reset_buffer_offset(ctx, descs->list + i*4,
1546 old_va, buf);
1547 descs->dirty_mask |= 1u << i;
1548 sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
1549
1550 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1551 rbuffer, buffers->shader_usage,
1552 RADEON_PRIO_SHADER_RW_BUFFER,
1553 true);
1554
1555 /* Update the streamout state. */
1556 if (sctx->b.streamout.begin_emitted)
1557 r600_emit_streamout_end(&sctx->b);
1558 sctx->b.streamout.append_bitmask =
1559 sctx->b.streamout.enabled_mask;
1560 r600_streamout_buffers_dirty(&sctx->b);
1561 }
1562 }
1563
1564 /* Constant and shader buffers. */
1565 if (rbuffer->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
1566 for (shader = 0; shader < SI_NUM_SHADERS; shader++)
1567 si_reset_buffer_resources(sctx, &sctx->const_buffers[shader],
1568 si_const_buffer_descriptors_idx(shader),
1569 buf, old_va);
1570 }
1571
1572 if (rbuffer->bind_history & PIPE_BIND_SHADER_BUFFER) {
1573 for (shader = 0; shader < SI_NUM_SHADERS; shader++)
1574 si_reset_buffer_resources(sctx, &sctx->shader_buffers[shader],
1575 si_shader_buffer_descriptors_idx(shader),
1576 buf, old_va);
1577 }
1578
1579 if (rbuffer->bind_history & PIPE_BIND_SAMPLER_VIEW) {
1580 /* Texture buffers - update bindings. */
1581 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1582 struct si_sampler_views *views = &sctx->samplers[shader].views;
1583 struct si_descriptors *descs =
1584 si_sampler_descriptors(sctx, shader);
1585 unsigned mask = views->enabled_mask;
1586
1587 while (mask) {
1588 unsigned i = u_bit_scan(&mask);
1589 if (views->views[i]->texture == buf) {
1590 si_desc_reset_buffer_offset(ctx,
1591 descs->list +
1592 i * 16 + 4,
1593 old_va, buf);
1594 descs->dirty_mask |= 1u << i;
1595 sctx->descriptors_dirty |=
1596 1u << si_sampler_descriptors_idx(shader);
1597
1598 radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
1599 rbuffer, RADEON_USAGE_READ,
1600 RADEON_PRIO_SAMPLER_BUFFER,
1601 true);
1602 }
1603 }
1604 }
1605 }
1606
1607 /* Shader images */
1608 if (rbuffer->bind_history & PIPE_BIND_SHADER_IMAGE) {
1609 for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
1610 struct si_images_info *images = &sctx->images[shader];
1611 struct si_descriptors *descs =
1612 si_image_descriptors(sctx, shader);
1613 unsigned mask = images->enabled_mask;
1614
1615 while (mask) {
1616 unsigned i = u_bit_scan(&mask);
1617
1618 if (images->views[i].resource == buf) {
1619 if (images->views[i].access & PIPE_IMAGE_ACCESS_WRITE)
1620 si_mark_image_range_valid(&images->views[i]);
1621
1622 si_desc_reset_buffer_offset(
1623 ctx, descs->list + i * 8 + 4,
1624 old_va, buf);
1625 descs->dirty_mask |= 1u << i;
1626 sctx->descriptors_dirty |=
1627 1u << si_image_descriptors_idx(shader);
1628
1629 radeon_add_to_buffer_list_check_mem(
1630 &sctx->b, &sctx->b.gfx, rbuffer,
1631 RADEON_USAGE_READWRITE,
1632 RADEON_PRIO_SAMPLER_BUFFER, true);
1633 }
1634 }
1635 }
1636 }
1637 }
1638
1639 /* Update mutable image descriptor fields of all bound textures. */
1640 void si_update_all_texture_descriptors(struct si_context *sctx)
1641 {
1642 unsigned shader;
1643
1644 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
1645 struct si_sampler_views *samplers = &sctx->samplers[shader].views;
1646 struct si_images_info *images = &sctx->images[shader];
1647 unsigned mask;
1648
1649 /* Images. */
1650 mask = images->enabled_mask;
1651 while (mask) {
1652 unsigned i = u_bit_scan(&mask);
1653 struct pipe_image_view *view = &images->views[i];
1654
1655 if (!view->resource ||
1656 view->resource->target == PIPE_BUFFER)
1657 continue;
1658
1659 si_set_shader_image(sctx, shader, i, view);
1660 }
1661
1662 /* Sampler views. */
1663 mask = samplers->enabled_mask;
1664 while (mask) {
1665 unsigned i = u_bit_scan(&mask);
1666 struct pipe_sampler_view *view = samplers->views[i];
1667
1668 if (!view ||
1669 !view->texture ||
1670 view->texture->target == PIPE_BUFFER)
1671 continue;
1672
1673 si_set_sampler_view(sctx, shader, i,
1674 samplers->views[i], true);
1675 }
1676 }
1677 }
1678
1679 /* SHADER USER DATA */
1680
1681 static void si_mark_shader_pointers_dirty(struct si_context *sctx,
1682 unsigned shader)
1683 {
1684 struct si_descriptors *descs =
1685 &sctx->descriptors[SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS];
1686
1687 for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs)
1688 descs->pointer_dirty = true;
1689
1690 if (shader == PIPE_SHADER_VERTEX)
1691 sctx->vertex_buffers.pointer_dirty = true;
1692
1693 si_mark_atom_dirty(sctx, &sctx->shader_userdata.atom);
1694 }
1695
1696 static void si_shader_userdata_begin_new_cs(struct si_context *sctx)
1697 {
1698 int i;
1699
1700 for (i = 0; i < SI_NUM_SHADERS; i++) {
1701 si_mark_shader_pointers_dirty(sctx, i);
1702 }
1703 sctx->descriptors[SI_DESCS_RW_BUFFERS].pointer_dirty = true;
1704 }
1705
1706 /* Set a base register address for user data constants in the given shader.
1707 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1708 */
1709 static void si_set_user_data_base(struct si_context *sctx,
1710 unsigned shader, uint32_t new_base)
1711 {
1712 uint32_t *base = &sctx->shader_userdata.sh_base[shader];
1713
1714 if (*base != new_base) {
1715 *base = new_base;
1716
1717 if (new_base)
1718 si_mark_shader_pointers_dirty(sctx, shader);
1719 }
1720 }
1721
1722 /* This must be called when these shaders are changed from non-NULL to NULL
1723 * and vice versa:
1724 * - geometry shader
1725 * - tessellation control shader
1726 * - tessellation evaluation shader
1727 */
1728 void si_shader_change_notify(struct si_context *sctx)
1729 {
1730 /* VS can be bound as VS, ES, or LS. */
1731 if (sctx->tes_shader.cso)
1732 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1733 R_00B530_SPI_SHADER_USER_DATA_LS_0);
1734 else if (sctx->gs_shader.cso)
1735 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1736 R_00B330_SPI_SHADER_USER_DATA_ES_0);
1737 else
1738 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX,
1739 R_00B130_SPI_SHADER_USER_DATA_VS_0);
1740
1741 /* TES can be bound as ES, VS, or not bound. */
1742 if (sctx->tes_shader.cso) {
1743 if (sctx->gs_shader.cso)
1744 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
1745 R_00B330_SPI_SHADER_USER_DATA_ES_0);
1746 else
1747 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
1748 R_00B130_SPI_SHADER_USER_DATA_VS_0);
1749 } else {
1750 si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, 0);
1751 }
1752 }
1753
1754 static void si_emit_shader_pointer(struct si_context *sctx,
1755 struct si_descriptors *desc,
1756 unsigned sh_base, bool keep_dirty)
1757 {
1758 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1759 uint64_t va;
1760
1761 if (!desc->pointer_dirty || !desc->buffer)
1762 return;
1763
1764 va = desc->buffer->gpu_address +
1765 desc->buffer_offset;
1766
1767 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0));
1768 radeon_emit(cs, (sh_base + desc->shader_userdata_offset - SI_SH_REG_OFFSET) >> 2);
1769 radeon_emit(cs, va);
1770 radeon_emit(cs, va >> 32);
1771
1772 desc->pointer_dirty = keep_dirty;
1773 }
1774
1775 void si_emit_graphics_shader_userdata(struct si_context *sctx,
1776 struct r600_atom *atom)
1777 {
1778 unsigned shader;
1779 uint32_t *sh_base = sctx->shader_userdata.sh_base;
1780 struct si_descriptors *descs;
1781
1782 descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
1783
1784 if (descs->pointer_dirty) {
1785 si_emit_shader_pointer(sctx, descs,
1786 R_00B030_SPI_SHADER_USER_DATA_PS_0, true);
1787 si_emit_shader_pointer(sctx, descs,
1788 R_00B130_SPI_SHADER_USER_DATA_VS_0, true);
1789 si_emit_shader_pointer(sctx, descs,
1790 R_00B230_SPI_SHADER_USER_DATA_GS_0, true);
1791 si_emit_shader_pointer(sctx, descs,
1792 R_00B330_SPI_SHADER_USER_DATA_ES_0, true);
1793 si_emit_shader_pointer(sctx, descs,
1794 R_00B430_SPI_SHADER_USER_DATA_HS_0, true);
1795 descs->pointer_dirty = false;
1796 }
1797
1798 descs = &sctx->descriptors[SI_DESCS_FIRST_SHADER];
1799
1800 for (shader = 0; shader < SI_NUM_GRAPHICS_SHADERS; shader++) {
1801 unsigned base = sh_base[shader];
1802 unsigned i;
1803
1804 if (!base)
1805 continue;
1806
1807 for (i = 0; i < SI_NUM_SHADER_DESCS; i++, descs++)
1808 si_emit_shader_pointer(sctx, descs, base, false);
1809 }
1810 si_emit_shader_pointer(sctx, &sctx->vertex_buffers, sh_base[PIPE_SHADER_VERTEX], false);
1811 }
1812
1813 void si_emit_compute_shader_userdata(struct si_context *sctx)
1814 {
1815 unsigned base = R_00B900_COMPUTE_USER_DATA_0;
1816 struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_FIRST_COMPUTE];
1817
1818 for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs)
1819 si_emit_shader_pointer(sctx, descs, base, false);
1820 }
1821
1822 /* INIT/DEINIT/UPLOAD */
1823
1824 void si_init_all_descriptors(struct si_context *sctx)
1825 {
1826 int i;
1827 unsigned ce_offset = 0;
1828
1829 for (i = 0; i < SI_NUM_SHADERS; i++) {
1830 si_init_buffer_resources(&sctx->const_buffers[i],
1831 si_const_buffer_descriptors(sctx, i),
1832 SI_NUM_CONST_BUFFERS, SI_SGPR_CONST_BUFFERS,
1833 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER,
1834 &ce_offset);
1835 si_init_buffer_resources(&sctx->shader_buffers[i],
1836 si_shader_buffer_descriptors(sctx, i),
1837 SI_NUM_SHADER_BUFFERS, SI_SGPR_SHADER_BUFFERS,
1838 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RW_BUFFER,
1839 &ce_offset);
1840
1841 si_init_descriptors(si_sampler_descriptors(sctx, i),
1842 SI_SGPR_SAMPLERS, 16, SI_NUM_SAMPLERS,
1843 null_texture_descriptor, &ce_offset);
1844
1845 si_init_descriptors(si_image_descriptors(sctx, i),
1846 SI_SGPR_IMAGES, 8, SI_NUM_IMAGES,
1847 null_image_descriptor, &ce_offset);
1848 }
1849
1850 si_init_buffer_resources(&sctx->rw_buffers,
1851 &sctx->descriptors[SI_DESCS_RW_BUFFERS],
1852 SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS,
1853 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS,
1854 &ce_offset);
1855 si_init_descriptors(&sctx->vertex_buffers, SI_SGPR_VERTEX_BUFFERS,
1856 4, SI_NUM_VERTEX_BUFFERS, NULL, NULL);
1857
1858 sctx->descriptors_dirty = u_bit_consecutive(0, SI_NUM_DESCS);
1859
1860 assert(ce_offset <= 32768);
1861
1862 /* Set pipe_context functions. */
1863 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
1864 sctx->b.b.set_shader_images = si_set_shader_images;
1865 sctx->b.b.set_constant_buffer = si_pipe_set_constant_buffer;
1866 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
1867 sctx->b.b.set_shader_buffers = si_set_shader_buffers;
1868 sctx->b.b.set_sampler_views = si_set_sampler_views;
1869 sctx->b.b.set_stream_output_targets = si_set_streamout_targets;
1870 sctx->b.invalidate_buffer = si_invalidate_buffer;
1871
1872 /* Shader user data. */
1873 si_init_atom(sctx, &sctx->shader_userdata.atom, &sctx->atoms.s.shader_userdata,
1874 si_emit_graphics_shader_userdata);
1875
1876 /* Set default and immutable mappings. */
1877 si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0);
1878 si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, R_00B430_SPI_SHADER_USER_DATA_HS_0);
1879 si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, R_00B230_SPI_SHADER_USER_DATA_GS_0);
1880 si_set_user_data_base(sctx, PIPE_SHADER_FRAGMENT, R_00B030_SPI_SHADER_USER_DATA_PS_0);
1881 }
1882
1883 bool si_upload_graphics_shader_descriptors(struct si_context *sctx)
1884 {
1885 const unsigned mask = u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE);
1886 unsigned dirty = sctx->descriptors_dirty & mask;
1887
1888 while (dirty) {
1889 unsigned i = u_bit_scan(&dirty);
1890
1891 if (!si_upload_descriptors(sctx, &sctx->descriptors[i],
1892 &sctx->shader_userdata.atom))
1893 return false;
1894 }
1895
1896 sctx->descriptors_dirty &= ~mask;
1897 return true;
1898 }
1899
1900 bool si_upload_compute_shader_descriptors(struct si_context *sctx)
1901 {
1902 /* Does not update rw_buffers as that is not needed for compute shaders
1903 * and the input buffer is using the same SGPR's anyway.
1904 */
1905 const unsigned mask = u_bit_consecutive(SI_DESCS_FIRST_COMPUTE,
1906 SI_NUM_DESCS - SI_DESCS_FIRST_COMPUTE);
1907 unsigned dirty = sctx->descriptors_dirty & mask;
1908
1909 while (dirty) {
1910 unsigned i = u_bit_scan(&dirty);
1911
1912 if (!si_upload_descriptors(sctx, &sctx->descriptors[i], NULL))
1913 return false;
1914 }
1915
1916 sctx->descriptors_dirty &= ~mask;
1917
1918 return true;
1919 }
1920
1921 void si_release_all_descriptors(struct si_context *sctx)
1922 {
1923 int i;
1924
1925 for (i = 0; i < SI_NUM_SHADERS; i++) {
1926 si_release_buffer_resources(&sctx->const_buffers[i],
1927 si_const_buffer_descriptors(sctx, i));
1928 si_release_buffer_resources(&sctx->shader_buffers[i],
1929 si_shader_buffer_descriptors(sctx, i));
1930 si_release_sampler_views(&sctx->samplers[i].views);
1931 si_release_image_views(&sctx->images[i]);
1932 }
1933 si_release_buffer_resources(&sctx->rw_buffers,
1934 &sctx->descriptors[SI_DESCS_RW_BUFFERS]);
1935
1936 for (i = 0; i < SI_NUM_DESCS; ++i)
1937 si_release_descriptors(&sctx->descriptors[i]);
1938 si_release_descriptors(&sctx->vertex_buffers);
1939 }
1940
1941 void si_all_descriptors_begin_new_cs(struct si_context *sctx)
1942 {
1943 int i;
1944
1945 for (i = 0; i < SI_NUM_SHADERS; i++) {
1946 si_buffer_resources_begin_new_cs(sctx, &sctx->const_buffers[i]);
1947 si_buffer_resources_begin_new_cs(sctx, &sctx->shader_buffers[i]);
1948 si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i].views);
1949 si_image_views_begin_new_cs(sctx, &sctx->images[i]);
1950 }
1951 si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers);
1952 si_vertex_buffers_begin_new_cs(sctx);
1953
1954 for (i = 0; i < SI_NUM_DESCS; ++i)
1955 si_descriptors_begin_new_cs(sctx, &sctx->descriptors[i]);
1956
1957 si_shader_userdata_begin_new_cs(sctx);
1958 }