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radeonsi: implement accelerated buffer copying
[mesa.git] / src / gallium / drivers / radeonsi / si_descriptors.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Marek Olšák <marek.olsak@amd.com>
25 */
26 #include "../radeon/r600_cs.h"
27 #include "radeonsi_pipe.h"
28 #include "radeonsi_resource.h"
29 #include "radeonsi_shader.h"
30
31 #include "util/u_memory.h"
32
33 #define SI_NUM_CONTEXTS 16
34
35 static uint32_t null_desc[8]; /* zeros */
36
37 /* Set this if you want the 3D engine to wait until CP DMA is done.
38 * It should be set on the last CP DMA packet. */
39 #define R600_CP_DMA_SYNC (1 << 0) /* R600+ */
40
41 /* Set this if the source data was used as a destination in a previous CP DMA
42 * packet. It's for preventing a read-after-write (RAW) hazard between two
43 * CP DMA packets. */
44 #define SI_CP_DMA_RAW_WAIT (1 << 1) /* SI+ */
45
46 /* Emit a CP DMA packet to do a copy from one buffer to another.
47 * The size must fit in bits [20:0].
48 */
49 static void si_emit_cp_dma_copy_buffer(struct r600_context *rctx,
50 uint64_t dst_va, uint64_t src_va,
51 unsigned size, unsigned flags)
52 {
53 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
54 uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? PKT3_CP_DMA_CP_SYNC : 0;
55 uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? PKT3_CP_DMA_CMD_RAW_WAIT : 0;
56
57 assert(size);
58 assert((size & ((1<<21)-1)) == size);
59
60 if (rctx->b.chip_class >= CIK) {
61 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
62 radeon_emit(cs, sync_flag); /* CP_SYNC [31] */
63 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
64 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
65 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
66 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
67 radeon_emit(cs, size | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
68 } else {
69 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
70 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
71 radeon_emit(cs, sync_flag | ((src_va >> 32) & 0xffff)); /* CP_SYNC [31] | SRC_ADDR_HI [15:0] */
72 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
73 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
74 radeon_emit(cs, size | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
75 }
76 }
77
78 /* Emit a CP DMA packet to clear a buffer. The size must fit in bits [20:0]. */
79 static void si_emit_cp_dma_clear_buffer(struct r600_context *rctx,
80 uint64_t dst_va, unsigned size,
81 uint32_t clear_value, unsigned flags)
82 {
83 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
84 uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? PKT3_CP_DMA_CP_SYNC : 0;
85 uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? PKT3_CP_DMA_CMD_RAW_WAIT : 0;
86
87 assert(size);
88 assert((size & ((1<<21)-1)) == size);
89
90 if (rctx->b.chip_class >= CIK) {
91 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
92 radeon_emit(cs, sync_flag | PKT3_CP_DMA_SRC_SEL(2)); /* CP_SYNC [31] | SRC_SEL[30:29] */
93 radeon_emit(cs, clear_value); /* DATA [31:0] */
94 radeon_emit(cs, 0);
95 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
96 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [15:0] */
97 radeon_emit(cs, size | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
98 } else {
99 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
100 radeon_emit(cs, clear_value); /* DATA [31:0] */
101 radeon_emit(cs, sync_flag | PKT3_CP_DMA_SRC_SEL(2)); /* CP_SYNC [31] | SRC_SEL[30:29] */
102 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
103 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
104 radeon_emit(cs, size | raw_wait); /* COMMAND [29:22] | BYTE_COUNT [20:0] */
105 }
106 }
107
108 static void si_init_descriptors(struct r600_context *rctx,
109 struct si_descriptors *desc,
110 unsigned shader_userdata_reg,
111 unsigned element_dw_size,
112 unsigned num_elements,
113 void (*emit_func)(struct r600_context *ctx, struct r600_atom *state))
114 {
115 uint64_t va;
116
117 assert(num_elements <= sizeof(desc->enabled_mask)*8);
118 assert(num_elements <= sizeof(desc->dirty_mask)*8);
119
120 desc->atom.emit = (void*)emit_func;
121 desc->shader_userdata_reg = shader_userdata_reg;
122 desc->element_dw_size = element_dw_size;
123 desc->num_elements = num_elements;
124 desc->context_size = num_elements * element_dw_size * 4;
125
126 desc->buffer = (struct r600_resource*)
127 pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
128 PIPE_USAGE_STATIC,
129 SI_NUM_CONTEXTS * desc->context_size);
130
131 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, desc->buffer, RADEON_USAGE_READWRITE);
132 va = r600_resource_va(rctx->b.b.screen, &desc->buffer->b.b);
133
134 /* We don't check for CS space here, because this should be called
135 * only once at context initialization. */
136 si_emit_cp_dma_clear_buffer(rctx, va, desc->buffer->b.b.width0, 0,
137 R600_CP_DMA_SYNC);
138 }
139
140 static void si_release_descriptors(struct si_descriptors *desc)
141 {
142 pipe_resource_reference((struct pipe_resource**)&desc->buffer, NULL);
143 }
144
145 static void si_update_descriptors(struct r600_context *rctx,
146 struct si_descriptors *desc)
147 {
148 if (desc->dirty_mask) {
149 desc->atom.num_dw =
150 7 + /* copy */
151 (4 + desc->element_dw_size) * util_bitcount(desc->dirty_mask) + /* update */
152 4; /* pointer update */
153 desc->atom.dirty = true;
154 /* The descriptors are read with the K cache. */
155 rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
156 } else {
157 desc->atom.dirty = false;
158 }
159 }
160
161 static void si_emit_shader_pointer(struct r600_context *rctx,
162 struct si_descriptors *desc)
163 {
164 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
165 uint64_t va = r600_resource_va(rctx->b.b.screen, &desc->buffer->b.b) +
166 desc->current_context_id * desc->context_size;
167
168 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0));
169 radeon_emit(cs, (desc->shader_userdata_reg - SI_SH_REG_OFFSET) >> 2);
170 radeon_emit(cs, va);
171 radeon_emit(cs, va >> 32);
172 }
173
174 static void si_emit_descriptors(struct r600_context *rctx,
175 struct si_descriptors *desc,
176 uint32_t **descriptors)
177 {
178 struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
179 uint64_t va_base;
180 int packet_start;
181 int packet_size = 0;
182 int last_index = desc->num_elements; /* point to a non-existing element */
183 unsigned dirty_mask = desc->dirty_mask;
184 unsigned new_context_id = (desc->current_context_id + 1) % SI_NUM_CONTEXTS;
185
186 assert(dirty_mask);
187
188 va_base = r600_resource_va(rctx->b.b.screen, &desc->buffer->b.b);
189
190 /* Copy the descriptors to a new context slot. */
191 /* XXX Consider using TC or L2 for this copy on CIK. */
192 si_emit_cp_dma_copy_buffer(rctx,
193 va_base + new_context_id * desc->context_size,
194 va_base + desc->current_context_id * desc->context_size,
195 desc->context_size, R600_CP_DMA_SYNC);
196
197 va_base += new_context_id * desc->context_size;
198
199 /* Update the descriptors.
200 * Updates of consecutive descriptors are merged to one WRITE_DATA packet.
201 *
202 * XXX When unbinding lots of resources, consider clearing the memory
203 * with CP DMA instead of emitting zeros.
204 */
205 while (dirty_mask) {
206 int i = u_bit_scan(&dirty_mask);
207
208 assert(i < desc->num_elements);
209
210 if (last_index+1 == i && packet_size) {
211 /* Append new data at the end of the last packet. */
212 packet_size += desc->element_dw_size;
213 cs->buf[packet_start] = PKT3(PKT3_WRITE_DATA, packet_size, 0);
214 } else {
215 /* Start a new packet. */
216 uint64_t va = va_base + i * desc->element_dw_size * 4;
217
218 packet_start = cs->cdw;
219 packet_size = 2 + desc->element_dw_size;
220
221 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, packet_size, 0));
222 radeon_emit(cs, PKT3_WRITE_DATA_DST_SEL(PKT3_WRITE_DATA_DST_SEL_TC_OR_L2) |
223 PKT3_WRITE_DATA_WR_CONFIRM |
224 PKT3_WRITE_DATA_ENGINE_SEL(PKT3_WRITE_DATA_ENGINE_SEL_ME));
225 radeon_emit(cs, va & 0xFFFFFFFFUL);
226 radeon_emit(cs, (va >> 32UL) & 0xFFFFFFFFUL);
227 }
228
229 radeon_emit_array(cs, descriptors[i], desc->element_dw_size);
230
231 last_index = i;
232 }
233
234 desc->dirty_mask = 0;
235 desc->current_context_id = new_context_id;
236
237 /* Now update the shader userdata pointer. */
238 si_emit_shader_pointer(rctx, desc);
239 }
240
241 static unsigned si_get_shader_user_data_base(unsigned shader)
242 {
243 switch (shader) {
244 case PIPE_SHADER_VERTEX:
245 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
246 case PIPE_SHADER_GEOMETRY:
247 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
248 case PIPE_SHADER_FRAGMENT:
249 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
250 default:
251 assert(0);
252 return 0;
253 }
254 }
255
256 /* SAMPLER VIEWS */
257
258 static void si_emit_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
259 {
260 struct si_sampler_views *views = (struct si_sampler_views*)atom;
261
262 si_emit_descriptors(rctx, &views->desc, views->desc_data);
263 }
264
265 static void si_init_sampler_views(struct r600_context *rctx,
266 struct si_sampler_views *views,
267 unsigned shader)
268 {
269 si_init_descriptors(rctx, &views->desc,
270 si_get_shader_user_data_base(shader) +
271 SI_SGPR_RESOURCE * 4,
272 8, NUM_SAMPLER_VIEWS, si_emit_sampler_views);
273 }
274
275 static void si_release_sampler_views(struct si_sampler_views *views)
276 {
277 int i;
278
279 for (i = 0; i < Elements(views->views); i++) {
280 pipe_sampler_view_reference(&views->views[i], NULL);
281 }
282 si_release_descriptors(&views->desc);
283 }
284
285 static void si_sampler_views_begin_new_cs(struct r600_context *rctx,
286 struct si_sampler_views *views)
287 {
288 unsigned mask = views->desc.enabled_mask;
289
290 /* Add relocations to the CS. */
291 while (mask) {
292 int i = u_bit_scan(&mask);
293 struct si_pipe_sampler_view *rview =
294 (struct si_pipe_sampler_view*)views->views[i];
295
296 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->resource, RADEON_USAGE_READ);
297 }
298
299 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, views->desc.buffer, RADEON_USAGE_READWRITE);
300
301 si_emit_shader_pointer(rctx, &views->desc);
302 }
303
304 void si_set_sampler_view(struct r600_context *rctx, unsigned shader,
305 unsigned slot, struct pipe_sampler_view *view,
306 unsigned *view_desc)
307 {
308 struct si_sampler_views *views = &rctx->samplers[shader].views;
309
310 if (views->views[slot] == view)
311 return;
312
313 if (view) {
314 struct si_pipe_sampler_view *rview =
315 (struct si_pipe_sampler_view*)view;
316
317 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->resource, RADEON_USAGE_READ);
318
319 pipe_sampler_view_reference(&views->views[slot], view);
320 views->desc_data[slot] = view_desc;
321 views->desc.enabled_mask |= 1 << slot;
322 } else {
323 pipe_sampler_view_reference(&views->views[slot], NULL);
324 views->desc_data[slot] = null_desc;
325 views->desc.enabled_mask &= ~(1 << slot);
326 }
327
328 views->desc.dirty_mask |= 1 << slot;
329 si_update_descriptors(rctx, &views->desc);
330 }
331
332 /* BUFFER RESOURCES */
333
334 static void si_emit_buffer_resources(struct r600_context *rctx, struct r600_atom *atom)
335 {
336 struct si_buffer_resources *buffers = (struct si_buffer_resources*)atom;
337
338 si_emit_descriptors(rctx, &buffers->desc, buffers->desc_data);
339 }
340
341 static void si_init_buffer_resources(struct r600_context *rctx,
342 struct si_buffer_resources *buffers,
343 unsigned num_buffers, unsigned shader,
344 unsigned shader_userdata_index,
345 enum radeon_bo_usage shader_usage)
346 {
347 int i;
348
349 buffers->num_buffers = num_buffers;
350 buffers->shader_usage = shader_usage;
351 buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource*));
352 buffers->desc_storage = CALLOC(num_buffers, sizeof(uint32_t) * 4);
353
354 /* si_emit_descriptors only accepts an array of arrays.
355 * This adds such an array. */
356 buffers->desc_data = CALLOC(num_buffers, sizeof(uint32_t*));
357 for (i = 0; i < num_buffers; i++) {
358 buffers->desc_data[i] = &buffers->desc_storage[i*4];
359 }
360
361 si_init_descriptors(rctx, &buffers->desc,
362 si_get_shader_user_data_base(shader) +
363 shader_userdata_index*4, 4, num_buffers,
364 si_emit_buffer_resources);
365 }
366
367 static void si_release_buffer_resources(struct si_buffer_resources *buffers)
368 {
369 int i;
370
371 for (i = 0; i < Elements(buffers->buffers); i++) {
372 pipe_resource_reference(&buffers->buffers[i], NULL);
373 }
374
375 FREE(buffers->buffers);
376 FREE(buffers->desc_storage);
377 FREE(buffers->desc_data);
378 si_release_descriptors(&buffers->desc);
379 }
380
381 static void si_buffer_resources_begin_new_cs(struct r600_context *rctx,
382 struct si_buffer_resources *buffers)
383 {
384 unsigned mask = buffers->desc.enabled_mask;
385
386 /* Add relocations to the CS. */
387 while (mask) {
388 int i = u_bit_scan(&mask);
389
390 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
391 (struct r600_resource*)buffers->buffers[i],
392 buffers->shader_usage);
393 }
394
395 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
396 buffers->desc.buffer, RADEON_USAGE_READWRITE);
397
398 si_emit_shader_pointer(rctx, &buffers->desc);
399 }
400
401 /* CONSTANT BUFFERS */
402
403 static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint slot,
404 struct pipe_constant_buffer *input)
405 {
406 struct r600_context *rctx = (struct r600_context *)ctx;
407 struct si_buffer_resources *buffers = &rctx->const_buffers[shader];
408
409 if (shader >= SI_NUM_SHADERS)
410 return;
411
412 assert(slot < buffers->num_buffers);
413 pipe_resource_reference(&buffers->buffers[slot], NULL);
414
415 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
416 * with a NULL buffer). We need to use a dummy buffer instead. */
417 if (rctx->b.chip_class == CIK &&
418 (!input || (!input->buffer && !input->user_buffer)))
419 input = &rctx->null_const_buf;
420
421 if (input && (input->buffer || input->user_buffer)) {
422 struct pipe_resource *buffer = NULL;
423 uint64_t va;
424
425 /* Upload the user buffer if needed. */
426 if (input->user_buffer) {
427 unsigned buffer_offset;
428
429 r600_upload_const_buffer(rctx,
430 (struct r600_resource**)&buffer, input->user_buffer,
431 input->buffer_size, &buffer_offset);
432 va = r600_resource_va(ctx->screen, buffer) + buffer_offset;
433 } else {
434 pipe_resource_reference(&buffer, input->buffer);
435 va = r600_resource_va(ctx->screen, buffer) + input->buffer_offset;
436 }
437
438 /* Set the descriptor. */
439 uint32_t *desc = buffers->desc_data[slot];
440 desc[0] = va;
441 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
442 S_008F04_STRIDE(0);
443 desc[2] = input->buffer_size;
444 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
445 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
446 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
447 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
448 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
449 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
450
451 buffers->buffers[slot] = buffer;
452 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
453 (struct r600_resource*)buffer, buffers->shader_usage);
454 buffers->desc.enabled_mask |= 1 << slot;
455 } else {
456 /* Clear the descriptor. */
457 memset(buffers->desc_data[slot], 0, sizeof(uint32_t) * 4);
458 buffers->desc.enabled_mask &= ~(1 << slot);
459 }
460
461 buffers->desc.dirty_mask |= 1 << slot;
462 si_update_descriptors(rctx, &buffers->desc);
463 }
464
465 /* STREAMOUT BUFFERS */
466
467 static void si_set_streamout_targets(struct pipe_context *ctx,
468 unsigned num_targets,
469 struct pipe_stream_output_target **targets,
470 unsigned append_bitmask)
471 {
472 struct r600_context *rctx = (struct r600_context *)ctx;
473 struct si_buffer_resources *buffers = &rctx->streamout_buffers;
474 unsigned old_num_targets = rctx->b.streamout.num_targets;
475 unsigned i;
476
477 /* Streamout buffers must be bound in 2 places:
478 * 1) in VGT by setting the VGT_STRMOUT registers
479 * 2) as shader resources
480 */
481
482 /* Set the VGT regs. */
483 r600_set_streamout_targets(ctx, num_targets, targets, append_bitmask);
484
485 /* Set the shader resources.*/
486 for (i = 0; i < num_targets; i++) {
487 if (targets[i]) {
488 struct pipe_resource *buffer = targets[i]->buffer;
489 uint64_t va = r600_resource_va(ctx->screen, buffer);
490
491 /* Set the descriptor. */
492 uint32_t *desc = buffers->desc_data[i];
493 desc[0] = va;
494 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
495 desc[2] = 0xffffffff;
496 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
497 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
498 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
499 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
500
501 /* Set the resource. */
502 pipe_resource_reference(&buffers->buffers[i], buffer);
503 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
504 (struct r600_resource*)buffer,
505 buffers->shader_usage);
506 buffers->desc.enabled_mask |= 1 << i;
507 } else {
508 /* Clear the descriptor and unset the resource. */
509 memset(buffers->desc_data[i], 0, sizeof(uint32_t) * 4);
510 pipe_resource_reference(&buffers->buffers[i], NULL);
511 buffers->desc.enabled_mask &= ~(1 << i);
512 }
513 buffers->desc.dirty_mask |= 1 << i;
514 }
515 for (; i < old_num_targets; i++) {
516 /* Clear the descriptor and unset the resource. */
517 memset(buffers->desc_data[i], 0, sizeof(uint32_t) * 4);
518 pipe_resource_reference(&buffers->buffers[i], NULL);
519 buffers->desc.enabled_mask &= ~(1 << i);
520 buffers->desc.dirty_mask |= 1 << i;
521 }
522
523 si_update_descriptors(rctx, &buffers->desc);
524 }
525
526 /* CP DMA */
527
528 /* The max number of bytes to copy per packet. */
529 #define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - 8)
530
531 static void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
532 unsigned offset, unsigned size, unsigned value)
533 {
534 struct r600_context *rctx = (struct r600_context*)ctx;
535
536 if (!size)
537 return;
538
539 /* Fallback for unaligned clears. */
540 if (offset % 4 != 0 || size % 4 != 0) {
541 uint32_t *map = rctx->b.ws->buffer_map(r600_resource(dst)->cs_buf,
542 rctx->b.rings.gfx.cs,
543 PIPE_TRANSFER_WRITE);
544 size /= 4;
545 for (unsigned i = 0; i < size; i++)
546 *map++ = value;
547
548 util_range_add(&r600_resource(dst)->valid_buffer_range, offset,
549 offset + size);
550 return;
551 }
552
553 uint64_t va = r600_resource_va(&rctx->screen->b.b, dst) + offset;
554
555 /* Flush the caches where the resource is bound. */
556 /* XXX only flush the caches where the buffer is bound. */
557 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
558 R600_CONTEXT_INV_CONST_CACHE |
559 R600_CONTEXT_FLUSH_AND_INV_CB |
560 R600_CONTEXT_FLUSH_AND_INV_DB |
561 R600_CONTEXT_FLUSH_AND_INV_CB_META |
562 R600_CONTEXT_FLUSH_AND_INV_DB_META;
563 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
564
565 while (size) {
566 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
567 unsigned dma_flags = 0;
568
569 si_need_cs_space(rctx, 7 + (rctx->b.flags ? rctx->cache_flush.num_dw : 0),
570 FALSE);
571
572 /* This must be done after need_cs_space. */
573 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
574 (struct r600_resource*)dst, RADEON_USAGE_WRITE);
575
576 /* Flush the caches for the first copy only.
577 * Also wait for the previous CP DMA operations. */
578 if (rctx->b.flags) {
579 si_emit_cache_flush(&rctx->b, NULL);
580 dma_flags |= SI_CP_DMA_RAW_WAIT; /* same as WAIT_UNTIL=CP_DMA_IDLE */
581 }
582
583 /* Do the synchronization after the last copy, so that all data is written to memory. */
584 if (size == byte_count)
585 dma_flags |= R600_CP_DMA_SYNC;
586
587 /* Emit the clear packet. */
588 si_emit_cp_dma_clear_buffer(rctx, va, byte_count, value, dma_flags);
589
590 size -= byte_count;
591 va += byte_count;
592 }
593
594 /* Flush the caches again in case the 3D engine has been prefetching
595 * the resource. */
596 /* XXX only flush the caches where the buffer is bound. */
597 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
598 R600_CONTEXT_INV_CONST_CACHE |
599 R600_CONTEXT_FLUSH_AND_INV_CB |
600 R600_CONTEXT_FLUSH_AND_INV_DB |
601 R600_CONTEXT_FLUSH_AND_INV_CB_META |
602 R600_CONTEXT_FLUSH_AND_INV_DB_META;
603
604 util_range_add(&r600_resource(dst)->valid_buffer_range, offset,
605 offset + size);
606 }
607
608 void si_copy_buffer(struct r600_context *rctx,
609 struct pipe_resource *dst, struct pipe_resource *src,
610 uint64_t dst_offset, uint64_t src_offset, unsigned size)
611 {
612 if (!size)
613 return;
614
615 dst_offset += r600_resource_va(&rctx->screen->b.b, dst);
616 src_offset += r600_resource_va(&rctx->screen->b.b, src);
617
618 /* Flush the caches where the resource is bound. */
619 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
620 R600_CONTEXT_INV_CONST_CACHE |
621 R600_CONTEXT_FLUSH_AND_INV_CB |
622 R600_CONTEXT_FLUSH_AND_INV_DB |
623 R600_CONTEXT_FLUSH_AND_INV_CB_META |
624 R600_CONTEXT_FLUSH_AND_INV_DB_META |
625 R600_CONTEXT_WAIT_3D_IDLE;
626
627 while (size) {
628 unsigned sync_flags = 0;
629 unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
630
631 si_need_cs_space(rctx, 7 + (rctx->b.flags ? rctx->cache_flush.num_dw : 0), FALSE);
632
633 /* Flush the caches for the first copy only. Also wait for old CP DMA packets to complete. */
634 if (rctx->b.flags) {
635 si_emit_cache_flush(&rctx->b, NULL);
636 sync_flags |= SI_CP_DMA_RAW_WAIT;
637 }
638
639 /* Do the synchronization after the last copy, so that all data is written to memory. */
640 if (size == byte_count) {
641 sync_flags |= R600_CP_DMA_SYNC;
642 }
643
644 /* This must be done after r600_need_cs_space. */
645 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)src, RADEON_USAGE_READ);
646 r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)dst, RADEON_USAGE_WRITE);
647
648 si_emit_cp_dma_copy_buffer(rctx, dst_offset, src_offset, byte_count, sync_flags);
649
650 size -= byte_count;
651 src_offset += byte_count;
652 dst_offset += byte_count;
653 }
654
655 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
656 R600_CONTEXT_INV_CONST_CACHE |
657 R600_CONTEXT_FLUSH_AND_INV_CB |
658 R600_CONTEXT_FLUSH_AND_INV_DB |
659 R600_CONTEXT_FLUSH_AND_INV_CB_META |
660 R600_CONTEXT_FLUSH_AND_INV_DB_META;
661
662 util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset,
663 dst_offset + size);
664 }
665
666 /* INIT/DEINIT */
667
668 void si_init_all_descriptors(struct r600_context *rctx)
669 {
670 int i;
671
672 for (i = 0; i < SI_NUM_SHADERS; i++) {
673 si_init_buffer_resources(rctx, &rctx->const_buffers[i],
674 NUM_CONST_BUFFERS, i, SI_SGPR_CONST,
675 RADEON_USAGE_READ);
676
677 si_init_sampler_views(rctx, &rctx->samplers[i].views, i);
678
679 rctx->atoms.const_buffers[i] = &rctx->const_buffers[i].desc.atom;
680 rctx->atoms.sampler_views[i] = &rctx->samplers[i].views.desc.atom;
681 }
682
683 si_init_buffer_resources(rctx, &rctx->streamout_buffers, 4, PIPE_SHADER_VERTEX,
684 SI_SGPR_SO_BUFFER, RADEON_USAGE_WRITE);
685 rctx->atoms.streamout_buffers = &rctx->streamout_buffers.desc.atom;
686
687 /* Set pipe_context functions. */
688 rctx->b.b.set_constant_buffer = si_set_constant_buffer;
689 rctx->b.b.set_stream_output_targets = si_set_streamout_targets;
690 rctx->b.clear_buffer = si_clear_buffer;
691 }
692
693 void si_release_all_descriptors(struct r600_context *rctx)
694 {
695 int i;
696
697 for (i = 0; i < SI_NUM_SHADERS; i++) {
698 si_release_buffer_resources(&rctx->const_buffers[i]);
699 si_release_sampler_views(&rctx->samplers[i].views);
700 }
701 si_release_buffer_resources(&rctx->streamout_buffers);
702 }
703
704 void si_all_descriptors_begin_new_cs(struct r600_context *rctx)
705 {
706 int i;
707
708 for (i = 0; i < SI_NUM_SHADERS; i++) {
709 si_buffer_resources_begin_new_cs(rctx, &rctx->const_buffers[i]);
710 si_sampler_views_begin_new_cs(rctx, &rctx->samplers[i].views);
711 }
712 si_buffer_resources_begin_new_cs(rctx, &rctx->streamout_buffers);
713 }