2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Marek Olšák <marek.olsak@amd.com>
27 /* Resource binding slots and sampler states (each described with 8 or
28 * 4 dwords) are stored in lists in memory which is accessed by shaders
29 * using scalar load instructions.
31 * This file is responsible for managing such lists. It keeps a copy of all
32 * descriptors in CPU memory and re-uploads a whole list if some slots have
35 * This code is also reponsible for updating shader pointers to those lists.
37 * Note that CP DMA can't be used for updating the lists, because a GPU hang
38 * could leave the list in a mid-IB state and the next IB would get wrong
39 * descriptors and the whole context would be unusable at that point.
40 * (Note: The register shadowing can't be used due to the same reason)
42 * Also, uploading descriptors to newly allocated memory doesn't require
46 * Possible scenarios for one 16 dword image+sampler slot:
48 * | Image | w/ FMASK | Buffer | NULL
49 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
50 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
51 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
52 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
54 * FMASK implies MSAA, therefore no sampler state.
55 * Sampler states are never unbound except when FMASK is bound.
58 #include "radeon/r600_cs.h"
63 #include "util/u_format.h"
64 #include "util/u_memory.h"
65 #include "util/u_upload_mgr.h"
68 /* NULL image and buffer descriptor for textures (alpha = 1) and images
71 * For images, all fields must be zero except for the swizzle, which
72 * supports arbitrary combinations of 0s and 1s. The texture type must be
73 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
75 * For buffers, all fields must be zero. If they are not, the hw hangs.
77 * This is the only reason why the buffer descriptor must be in words [4:7].
79 static uint32_t null_texture_descriptor
[8] = {
83 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) |
84 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
85 /* the rest must contain zeros, which is also used by the buffer
89 static uint32_t null_image_descriptor
[8] = {
93 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
94 /* the rest must contain zeros, which is also used by the buffer
98 static void si_init_descriptors(struct si_context
*sctx
,
99 struct si_descriptors
*desc
,
100 unsigned shader_userdata_index
,
101 unsigned element_dw_size
,
102 unsigned num_elements
,
103 unsigned first_ce_slot
,
104 unsigned num_ce_slots
,
107 assert(num_elements
<= sizeof(desc
->dirty_mask
)*8);
109 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
110 desc
->element_dw_size
= element_dw_size
;
111 desc
->num_elements
= num_elements
;
112 desc
->first_ce_slot
= sctx
->ce_ib
? first_ce_slot
: 0;
113 desc
->num_ce_slots
= sctx
->ce_ib
? num_ce_slots
: 0;
114 desc
->dirty_mask
= u_bit_consecutive64(0, num_elements
);
115 desc
->shader_userdata_offset
= shader_userdata_index
* 4;
117 if (desc
->num_ce_slots
) {
118 desc
->uses_ce
= true;
119 desc
->ce_offset
= *ce_offset
;
121 *ce_offset
+= element_dw_size
* desc
->num_ce_slots
* 4;
125 static void si_release_descriptors(struct si_descriptors
*desc
)
127 r600_resource_reference(&desc
->buffer
, NULL
);
131 static bool si_ce_upload(struct si_context
*sctx
, unsigned ce_offset
, unsigned size
,
132 unsigned *out_offset
, struct r600_resource
**out_buf
)
136 u_suballocator_alloc(sctx
->ce_suballocator
, size
,
137 si_optimal_tcc_alignment(sctx
, size
),
139 (struct pipe_resource
**)out_buf
);
143 va
= (*out_buf
)->gpu_address
+ *out_offset
;
145 radeon_emit(sctx
->ce_ib
, PKT3(PKT3_DUMP_CONST_RAM
, 3, 0));
146 radeon_emit(sctx
->ce_ib
, ce_offset
);
147 radeon_emit(sctx
->ce_ib
, size
/ 4);
148 radeon_emit(sctx
->ce_ib
, va
);
149 radeon_emit(sctx
->ce_ib
, va
>> 32);
151 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, *out_buf
,
152 RADEON_USAGE_READWRITE
, RADEON_PRIO_DESCRIPTORS
);
154 sctx
->ce_need_synchronization
= true;
158 void si_ce_save_all_descriptors_at_ib_end(struct si_context
* sctx
)
160 bool success
= si_ce_upload(sctx
, 0, sctx
->total_ce_ram_allocated
,
161 &sctx
->ce_ram_saved_offset
,
162 &sctx
->ce_ram_saved_buffer
);
167 void si_ce_restore_all_descriptors_at_ib_start(struct si_context
*sctx
)
169 if (!sctx
->ce_ram_saved_buffer
)
172 struct radeon_winsys_cs
*ib
= sctx
->ce_preamble_ib
;
176 uint64_t va
= sctx
->ce_ram_saved_buffer
->gpu_address
+
177 sctx
->ce_ram_saved_offset
;
179 radeon_emit(ib
, PKT3(PKT3_LOAD_CONST_RAM
, 3, 0));
181 radeon_emit(ib
, va
>> 32);
182 radeon_emit(ib
, sctx
->total_ce_ram_allocated
/ 4);
185 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
186 sctx
->ce_ram_saved_buffer
,
187 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
190 void si_ce_enable_loads(struct radeon_winsys_cs
*ib
)
192 radeon_emit(ib
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
193 radeon_emit(ib
, CONTEXT_CONTROL_LOAD_ENABLE(1) |
194 CONTEXT_CONTROL_LOAD_CE_RAM(1));
195 radeon_emit(ib
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
198 static bool si_upload_descriptors(struct si_context
*sctx
,
199 struct si_descriptors
*desc
,
200 struct r600_atom
* atom
)
202 unsigned slot_size
= desc
->element_dw_size
* 4;
203 unsigned first_slot_offset
= desc
->first_active_slot
* slot_size
;
204 unsigned upload_size
= desc
->num_active_slots
* slot_size
;
206 /* Skip the upload if no shader is using the descriptors. dirty_mask
207 * will stay dirty and the descriptors will be uploaded when there is
208 * a shader using them.
214 const uint32_t *list
= desc
->list
+
215 desc
->first_ce_slot
* desc
->element_dw_size
;
216 uint64_t mask
= (desc
->dirty_mask
>> desc
->first_ce_slot
) &
217 u_bit_consecutive64(0, desc
->num_ce_slots
);
222 u_bit_scan_consecutive_range64(&mask
, &begin
, &count
);
224 begin
*= desc
->element_dw_size
;
225 count
*= desc
->element_dw_size
;
227 radeon_emit(sctx
->ce_ib
,
228 PKT3(PKT3_WRITE_CONST_RAM
, count
, 0));
229 radeon_emit(sctx
->ce_ib
, desc
->ce_offset
+ begin
* 4);
230 radeon_emit_array(sctx
->ce_ib
, list
+ begin
, count
);
233 if (!si_ce_upload(sctx
,
235 (first_slot_offset
- desc
->first_ce_slot
* slot_size
),
236 upload_size
, (unsigned*)&desc
->buffer_offset
,
242 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, upload_size
,
243 si_optimal_tcc_alignment(sctx
, upload_size
),
244 (unsigned*)&desc
->buffer_offset
,
245 (struct pipe_resource
**)&desc
->buffer
,
248 return false; /* skip the draw call */
250 util_memcpy_cpu_to_le32(ptr
, (char*)desc
->list
+ first_slot_offset
,
252 desc
->gpu_list
= ptr
- first_slot_offset
/ 4;
254 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
255 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
258 /* The shader pointer should point to slot 0. */
259 desc
->buffer_offset
-= first_slot_offset
;
261 desc
->dirty_mask
= 0;
264 si_mark_atom_dirty(sctx
, atom
);
270 si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
275 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
276 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
282 si_sampler_and_image_descriptors_idx(unsigned shader
)
284 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
285 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
;
288 static struct si_descriptors
*
289 si_sampler_and_image_descriptors(struct si_context
*sctx
, unsigned shader
)
291 return &sctx
->descriptors
[si_sampler_and_image_descriptors_idx(shader
)];
294 static void si_release_sampler_views(struct si_sampler_views
*views
)
298 for (i
= 0; i
< ARRAY_SIZE(views
->views
); i
++) {
299 pipe_sampler_view_reference(&views
->views
[i
], NULL
);
303 static void si_sampler_view_add_buffer(struct si_context
*sctx
,
304 struct pipe_resource
*resource
,
305 enum radeon_bo_usage usage
,
306 bool is_stencil_sampler
,
309 struct r600_resource
*rres
;
310 struct r600_texture
*rtex
;
311 enum radeon_bo_priority priority
;
316 if (resource
->target
!= PIPE_BUFFER
) {
317 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
319 if (tex
->is_depth
&& !r600_can_sample_zs(tex
, is_stencil_sampler
))
320 resource
= &tex
->flushed_depth_texture
->resource
.b
.b
;
323 rres
= (struct r600_resource
*)resource
;
324 priority
= r600_get_sampler_view_priority(rres
);
326 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
327 rres
, usage
, priority
,
330 if (resource
->target
== PIPE_BUFFER
)
333 /* Now add separate DCC or HTILE. */
334 rtex
= (struct r600_texture
*)resource
;
335 if (rtex
->dcc_separate_buffer
) {
336 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
337 rtex
->dcc_separate_buffer
, usage
,
338 RADEON_PRIO_DCC
, check_mem
);
342 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
,
343 struct si_sampler_views
*views
)
345 unsigned mask
= views
->enabled_mask
;
347 /* Add buffers to the CS. */
349 int i
= u_bit_scan(&mask
);
350 struct si_sampler_view
*sview
= (struct si_sampler_view
*)views
->views
[i
];
352 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
354 sview
->is_stencil_sampler
, false);
358 /* Set buffer descriptor fields that can be changed by reallocations. */
359 static void si_set_buf_desc_address(struct r600_resource
*buf
,
360 uint64_t offset
, uint32_t *state
)
362 uint64_t va
= buf
->gpu_address
+ offset
;
365 state
[1] &= C_008F04_BASE_ADDRESS_HI
;
366 state
[1] |= S_008F04_BASE_ADDRESS_HI(va
>> 32);
369 /* Set texture descriptor fields that can be changed by reallocations.
372 * \param base_level_info information of the level of BASE_ADDRESS
373 * \param base_level the level of BASE_ADDRESS
374 * \param first_level pipe_sampler_view.u.tex.first_level
375 * \param block_width util_format_get_blockwidth()
376 * \param is_stencil select between separate Z & Stencil
377 * \param state descriptor to update
379 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
380 struct r600_texture
*tex
,
381 const struct legacy_surf_level
*base_level_info
,
382 unsigned base_level
, unsigned first_level
,
383 unsigned block_width
, bool is_stencil
,
386 uint64_t va
, meta_va
= 0;
388 if (tex
->is_depth
&& !r600_can_sample_zs(tex
, is_stencil
)) {
389 tex
= tex
->flushed_depth_texture
;
393 va
= tex
->resource
.gpu_address
;
395 if (sscreen
->b
.chip_class
>= GFX9
) {
396 /* Only stencil_offset needs to be added here. */
398 va
+= tex
->surface
.u
.gfx9
.stencil_offset
;
400 va
+= tex
->surface
.u
.gfx9
.surf_offset
;
402 va
+= base_level_info
->offset
;
406 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
407 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
409 if (sscreen
->b
.chip_class
>= VI
) {
410 state
[6] &= C_008F28_COMPRESSION_EN
;
413 if (vi_dcc_enabled(tex
, first_level
)) {
414 meta_va
= (!tex
->dcc_separate_buffer
? tex
->resource
.gpu_address
: 0) +
417 if (sscreen
->b
.chip_class
<= VI
)
418 meta_va
+= base_level_info
->dcc_offset
;
419 } else if (tex
->tc_compatible_htile
) {
420 meta_va
= tex
->resource
.gpu_address
+ tex
->htile_offset
;
424 state
[6] |= S_008F28_COMPRESSION_EN(1);
425 state
[7] = meta_va
>> 8;
429 if (sscreen
->b
.chip_class
>= GFX9
) {
430 state
[3] &= C_008F1C_SW_MODE
;
431 state
[4] &= C_008F20_PITCH_GFX9
;
434 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
435 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.stencil
.epitch
);
437 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
438 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.surf
.epitch
);
441 state
[5] &= C_008F24_META_DATA_ADDRESS
&
442 C_008F24_META_PIPE_ALIGNED
&
443 C_008F24_META_RB_ALIGNED
;
445 struct gfx9_surf_meta_flags meta
;
448 meta
= tex
->surface
.u
.gfx9
.dcc
;
450 meta
= tex
->surface
.u
.gfx9
.htile
;
452 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
453 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
454 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
458 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
459 unsigned index
= si_tile_mode_index(tex
, base_level
, is_stencil
);
461 state
[3] &= C_008F1C_TILING_INDEX
;
462 state
[3] |= S_008F1C_TILING_INDEX(index
);
463 state
[4] &= C_008F20_PITCH_GFX6
;
464 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
468 static void si_set_sampler_view(struct si_context
*sctx
,
470 unsigned slot
, struct pipe_sampler_view
*view
,
471 bool disallow_early_out
)
473 struct si_sampler_views
*views
= &sctx
->samplers
[shader
].views
;
474 struct si_sampler_view
*rview
= (struct si_sampler_view
*)view
;
475 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
476 unsigned desc_slot
= si_get_sampler_slot(slot
);
477 uint32_t *desc
= descs
->list
+ desc_slot
* 16;
479 if (views
->views
[slot
] == view
&& !disallow_early_out
)
483 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
484 bool is_buffer
= rtex
->resource
.b
.b
.target
== PIPE_BUFFER
;
486 if (unlikely(!is_buffer
&& rview
->dcc_incompatible
)) {
487 if (vi_dcc_enabled(rtex
, view
->u
.tex
.first_level
))
488 if (!r600_texture_disable_dcc(&sctx
->b
, rtex
))
489 sctx
->b
.decompress_dcc(&sctx
->b
.b
, rtex
);
491 rview
->dcc_incompatible
= false;
494 assert(rtex
); /* views with texture == NULL aren't supported */
495 pipe_sampler_view_reference(&views
->views
[slot
], view
);
496 memcpy(desc
, rview
->state
, 8*4);
499 rtex
->resource
.bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
501 si_set_buf_desc_address(&rtex
->resource
,
505 bool is_separate_stencil
=
506 rtex
->db_compatible
&&
507 rview
->is_stencil_sampler
;
509 si_set_mutable_tex_desc_fields(sctx
->screen
, rtex
,
510 rview
->base_level_info
,
512 rview
->base
.u
.tex
.first_level
,
518 if (!is_buffer
&& rtex
->fmask
.size
) {
520 rview
->fmask_state
, 8*4);
522 /* Disable FMASK and bind sampler state in [12:15]. */
524 null_texture_descriptor
, 4*4);
526 if (views
->sampler_states
[slot
])
528 views
->sampler_states
[slot
]->val
, 4*4);
531 views
->enabled_mask
|= 1u << slot
;
533 /* Since this can flush, it must be done after enabled_mask is
535 si_sampler_view_add_buffer(sctx
, view
->texture
,
537 rview
->is_stencil_sampler
, true);
539 pipe_sampler_view_reference(&views
->views
[slot
], NULL
);
540 memcpy(desc
, null_texture_descriptor
, 8*4);
541 /* Only clear the lower dwords of FMASK. */
542 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
543 /* Re-set the sampler state if we are transitioning from FMASK. */
544 if (views
->sampler_states
[slot
])
546 views
->sampler_states
[slot
]->val
, 4*4);
548 views
->enabled_mask
&= ~(1u << slot
);
551 descs
->dirty_mask
|= 1ull << desc_slot
;
552 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
555 static bool color_needs_decompression(struct r600_texture
*rtex
)
557 return rtex
->fmask
.size
||
558 (rtex
->dirty_level_mask
&&
559 (rtex
->cmask
.size
|| rtex
->dcc_offset
));
562 static bool depth_needs_decompression(struct r600_texture
*rtex
,
563 struct si_sampler_view
*sview
)
565 return rtex
->db_compatible
&&
566 (!rtex
->tc_compatible_htile
||
567 !r600_can_sample_zs(rtex
, sview
->is_stencil_sampler
));
570 static void si_update_shader_needs_decompress_mask(struct si_context
*sctx
,
573 struct si_textures_info
*samplers
= &sctx
->samplers
[shader
];
574 unsigned shader_bit
= 1 << shader
;
576 if (samplers
->needs_depth_decompress_mask
||
577 samplers
->needs_color_decompress_mask
||
578 sctx
->images
[shader
].needs_color_decompress_mask
)
579 sctx
->shader_needs_decompress_mask
|= shader_bit
;
581 sctx
->shader_needs_decompress_mask
&= ~shader_bit
;
584 static void si_set_sampler_views(struct pipe_context
*ctx
,
585 enum pipe_shader_type shader
, unsigned start
,
587 struct pipe_sampler_view
**views
)
589 struct si_context
*sctx
= (struct si_context
*)ctx
;
590 struct si_textures_info
*samplers
= &sctx
->samplers
[shader
];
593 if (!count
|| shader
>= SI_NUM_SHADERS
)
596 for (i
= 0; i
< count
; i
++) {
597 unsigned slot
= start
+ i
;
599 if (!views
|| !views
[i
]) {
600 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
601 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
602 si_set_sampler_view(sctx
, shader
, slot
, NULL
, false);
606 si_set_sampler_view(sctx
, shader
, slot
, views
[i
], false);
608 if (views
[i
]->texture
&& views
[i
]->texture
->target
!= PIPE_BUFFER
) {
609 struct r600_texture
*rtex
=
610 (struct r600_texture
*)views
[i
]->texture
;
611 struct si_sampler_view
*rview
= (struct si_sampler_view
*)views
[i
];
613 if (depth_needs_decompression(rtex
, rview
)) {
614 samplers
->needs_depth_decompress_mask
|= 1u << slot
;
616 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
618 if (color_needs_decompression(rtex
)) {
619 samplers
->needs_color_decompress_mask
|= 1u << slot
;
621 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
624 if (rtex
->dcc_offset
&&
625 p_atomic_read(&rtex
->framebuffers_bound
))
626 sctx
->need_check_render_feedback
= true;
628 samplers
->needs_depth_decompress_mask
&= ~(1u << slot
);
629 samplers
->needs_color_decompress_mask
&= ~(1u << slot
);
633 si_update_shader_needs_decompress_mask(sctx
, shader
);
637 si_samplers_update_needs_color_decompress_mask(struct si_textures_info
*samplers
)
639 unsigned mask
= samplers
->views
.enabled_mask
;
642 int i
= u_bit_scan(&mask
);
643 struct pipe_resource
*res
= samplers
->views
.views
[i
]->texture
;
645 if (res
&& res
->target
!= PIPE_BUFFER
) {
646 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
648 if (color_needs_decompression(rtex
)) {
649 samplers
->needs_color_decompress_mask
|= 1u << i
;
651 samplers
->needs_color_decompress_mask
&= ~(1u << i
);
660 si_release_image_views(struct si_images_info
*images
)
664 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
665 struct pipe_image_view
*view
= &images
->views
[i
];
667 pipe_resource_reference(&view
->resource
, NULL
);
672 si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images_info
*images
)
674 uint mask
= images
->enabled_mask
;
676 /* Add buffers to the CS. */
678 int i
= u_bit_scan(&mask
);
679 struct pipe_image_view
*view
= &images
->views
[i
];
681 assert(view
->resource
);
683 si_sampler_view_add_buffer(sctx
, view
->resource
,
684 RADEON_USAGE_READWRITE
, false, false);
689 si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
691 struct si_images_info
*images
= &ctx
->images
[shader
];
693 if (images
->enabled_mask
& (1u << slot
)) {
694 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
695 unsigned desc_slot
= si_get_image_slot(slot
);
697 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
698 images
->needs_color_decompress_mask
&= ~(1 << slot
);
700 memcpy(descs
->list
+ desc_slot
*8, null_image_descriptor
, 8*4);
701 images
->enabled_mask
&= ~(1u << slot
);
702 /* two 8-byte images share one 16-byte slot */
703 descs
->dirty_mask
|= 1u << (desc_slot
/ 2);
704 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
709 si_mark_image_range_valid(const struct pipe_image_view
*view
)
711 struct r600_resource
*res
= (struct r600_resource
*)view
->resource
;
713 assert(res
&& res
->b
.b
.target
== PIPE_BUFFER
);
715 util_range_add(&res
->valid_buffer_range
,
717 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
720 static void si_set_shader_image(struct si_context
*ctx
,
722 unsigned slot
, const struct pipe_image_view
*view
,
723 bool skip_decompress
)
725 struct si_screen
*screen
= ctx
->screen
;
726 struct si_images_info
*images
= &ctx
->images
[shader
];
727 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
728 struct r600_resource
*res
;
729 unsigned desc_slot
= si_get_image_slot(slot
);
730 uint32_t *desc
= descs
->list
+ desc_slot
* 8;
732 if (!view
|| !view
->resource
) {
733 si_disable_shader_image(ctx
, shader
, slot
);
737 res
= (struct r600_resource
*)view
->resource
;
739 if (&images
->views
[slot
] != view
)
740 util_copy_image_view(&images
->views
[slot
], view
);
742 if (res
->b
.b
.target
== PIPE_BUFFER
) {
743 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
744 si_mark_image_range_valid(view
);
746 si_make_buffer_descriptor(screen
, res
,
749 view
->u
.buf
.size
, desc
);
750 si_set_buf_desc_address(res
, view
->u
.buf
.offset
, desc
+ 4);
752 images
->needs_color_decompress_mask
&= ~(1 << slot
);
753 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
755 static const unsigned char swizzle
[4] = { 0, 1, 2, 3 };
756 struct r600_texture
*tex
= (struct r600_texture
*)res
;
757 unsigned level
= view
->u
.tex
.level
;
758 unsigned width
, height
, depth
, hw_level
;
759 bool uses_dcc
= vi_dcc_enabled(tex
, level
);
761 assert(!tex
->is_depth
);
762 assert(tex
->fmask
.size
== 0);
764 if (uses_dcc
&& !skip_decompress
&&
765 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
||
766 !vi_dcc_formats_compatible(res
->b
.b
.format
, view
->format
))) {
767 /* If DCC can't be disabled, at least decompress it.
768 * The decompression is relatively cheap if the surface
769 * has been decompressed already.
771 if (r600_texture_disable_dcc(&ctx
->b
, tex
))
774 ctx
->b
.decompress_dcc(&ctx
->b
.b
, tex
);
777 if (color_needs_decompression(tex
)) {
778 images
->needs_color_decompress_mask
|= 1 << slot
;
780 images
->needs_color_decompress_mask
&= ~(1 << slot
);
784 p_atomic_read(&tex
->framebuffers_bound
))
785 ctx
->need_check_render_feedback
= true;
787 if (ctx
->b
.chip_class
>= GFX9
) {
788 /* Always set the base address. The swizzle modes don't
789 * allow setting mipmap level offsets as the base.
791 width
= res
->b
.b
.width0
;
792 height
= res
->b
.b
.height0
;
793 depth
= res
->b
.b
.depth0
;
796 /* Always force the base level to the selected level.
798 * This is required for 3D textures, where otherwise
799 * selecting a single slice for non-layered bindings
800 * fails. It doesn't hurt the other targets.
802 width
= u_minify(res
->b
.b
.width0
, level
);
803 height
= u_minify(res
->b
.b
.height0
, level
);
804 depth
= u_minify(res
->b
.b
.depth0
, level
);
808 si_make_texture_descriptor(screen
, tex
,
809 false, res
->b
.b
.target
,
810 view
->format
, swizzle
,
812 view
->u
.tex
.first_layer
,
813 view
->u
.tex
.last_layer
,
814 width
, height
, depth
,
816 si_set_mutable_tex_desc_fields(screen
, tex
,
817 &tex
->surface
.u
.legacy
.level
[level
],
819 util_format_get_blockwidth(view
->format
),
823 images
->enabled_mask
|= 1u << slot
;
824 /* two 8-byte images share one 16-byte slot */
825 descs
->dirty_mask
|= 1u << (desc_slot
/ 2);
826 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
828 /* Since this can flush, it must be done after enabled_mask is updated. */
829 si_sampler_view_add_buffer(ctx
, &res
->b
.b
,
830 RADEON_USAGE_READWRITE
, false, true);
834 si_set_shader_images(struct pipe_context
*pipe
,
835 enum pipe_shader_type shader
,
836 unsigned start_slot
, unsigned count
,
837 const struct pipe_image_view
*views
)
839 struct si_context
*ctx
= (struct si_context
*)pipe
;
842 assert(shader
< SI_NUM_SHADERS
);
847 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
850 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
851 si_set_shader_image(ctx
, shader
, slot
, &views
[i
], false);
853 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
854 si_set_shader_image(ctx
, shader
, slot
, NULL
, false);
857 si_update_shader_needs_decompress_mask(ctx
, shader
);
861 si_images_update_needs_color_decompress_mask(struct si_images_info
*images
)
863 unsigned mask
= images
->enabled_mask
;
866 int i
= u_bit_scan(&mask
);
867 struct pipe_resource
*res
= images
->views
[i
].resource
;
869 if (res
&& res
->target
!= PIPE_BUFFER
) {
870 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
872 if (color_needs_decompression(rtex
)) {
873 images
->needs_color_decompress_mask
|= 1 << i
;
875 images
->needs_color_decompress_mask
&= ~(1 << i
);
883 static void si_bind_sampler_states(struct pipe_context
*ctx
,
884 enum pipe_shader_type shader
,
885 unsigned start
, unsigned count
, void **states
)
887 struct si_context
*sctx
= (struct si_context
*)ctx
;
888 struct si_textures_info
*samplers
= &sctx
->samplers
[shader
];
889 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, shader
);
890 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
893 if (!count
|| shader
>= SI_NUM_SHADERS
)
896 for (i
= 0; i
< count
; i
++) {
897 unsigned slot
= start
+ i
;
898 unsigned desc_slot
= si_get_sampler_slot(slot
);
901 sstates
[i
] == samplers
->views
.sampler_states
[slot
])
905 assert(sstates
[i
]->magic
== SI_SAMPLER_STATE_MAGIC
);
907 samplers
->views
.sampler_states
[slot
] = sstates
[i
];
909 /* If FMASK is bound, don't overwrite it.
910 * The sampler state will be set after FMASK is unbound.
912 if (samplers
->views
.views
[slot
] &&
913 samplers
->views
.views
[slot
]->texture
&&
914 samplers
->views
.views
[slot
]->texture
->target
!= PIPE_BUFFER
&&
915 ((struct r600_texture
*)samplers
->views
.views
[slot
]->texture
)->fmask
.size
)
918 memcpy(desc
->list
+ desc_slot
* 16 + 12, sstates
[i
]->val
, 4*4);
919 desc
->dirty_mask
|= 1ull << desc_slot
;
920 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
924 /* BUFFER RESOURCES */
926 static void si_init_buffer_resources(struct si_context
*sctx
,
927 struct si_buffer_resources
*buffers
,
928 struct si_descriptors
*descs
,
929 unsigned num_buffers
,
930 unsigned first_ce_slot
,
931 unsigned num_ce_slots
,
932 unsigned shader_userdata_index
,
933 enum radeon_bo_usage shader_usage
,
934 enum radeon_bo_usage shader_usage_constbuf
,
935 enum radeon_bo_priority priority
,
936 enum radeon_bo_priority priority_constbuf
,
939 buffers
->shader_usage
= shader_usage
;
940 buffers
->shader_usage_constbuf
= shader_usage_constbuf
;
941 buffers
->priority
= priority
;
942 buffers
->priority_constbuf
= priority_constbuf
;
943 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
945 si_init_descriptors(sctx
, descs
, shader_userdata_index
, 4, num_buffers
,
946 first_ce_slot
, num_ce_slots
, ce_offset
);
949 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
950 struct si_descriptors
*descs
)
954 for (i
= 0; i
< descs
->num_elements
; i
++) {
955 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
958 FREE(buffers
->buffers
);
961 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
962 struct si_buffer_resources
*buffers
)
964 unsigned mask
= buffers
->enabled_mask
;
966 /* Add buffers to the CS. */
968 int i
= u_bit_scan(&mask
);
970 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
971 r600_resource(buffers
->buffers
[i
]),
972 i
< SI_NUM_SHADER_BUFFERS
? buffers
->shader_usage
:
973 buffers
->shader_usage_constbuf
,
974 i
< SI_NUM_SHADER_BUFFERS
? buffers
->priority
:
975 buffers
->priority_constbuf
);
979 static void si_get_buffer_from_descriptors(struct si_buffer_resources
*buffers
,
980 struct si_descriptors
*descs
,
981 unsigned idx
, struct pipe_resource
**buf
,
982 unsigned *offset
, unsigned *size
)
984 pipe_resource_reference(buf
, buffers
->buffers
[idx
]);
986 struct r600_resource
*res
= r600_resource(*buf
);
987 const uint32_t *desc
= descs
->list
+ idx
* 4;
992 assert(G_008F04_STRIDE(desc
[1]) == 0);
993 va
= ((uint64_t)desc
[1] << 32) | desc
[0];
995 assert(va
>= res
->gpu_address
&& va
+ *size
<= res
->gpu_address
+ res
->bo_size
);
996 *offset
= va
- res
->gpu_address
;
1000 /* VERTEX BUFFERS */
1002 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
1004 struct si_descriptors
*desc
= &sctx
->vertex_buffers
;
1005 int count
= sctx
->vertex_elements
? sctx
->vertex_elements
->count
: 0;
1008 for (i
= 0; i
< count
; i
++) {
1009 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1011 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1013 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1016 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1017 (struct r600_resource
*)sctx
->vertex_buffer
[vb
].buffer
.resource
,
1018 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1023 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1024 desc
->buffer
, RADEON_USAGE_READ
,
1025 RADEON_PRIO_DESCRIPTORS
);
1028 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
1030 struct si_vertex_elements
*velems
= sctx
->vertex_elements
;
1031 struct si_descriptors
*desc
= &sctx
->vertex_buffers
;
1033 unsigned desc_list_byte_size
;
1034 unsigned first_vb_use_mask
;
1038 if (!sctx
->vertex_buffers_dirty
|| !velems
)
1041 count
= velems
->count
;
1046 desc_list_byte_size
= velems
->desc_list_byte_size
;
1047 first_vb_use_mask
= velems
->first_vb_use_mask
;
1049 /* Vertex buffer descriptors are the only ones which are uploaded
1050 * directly through a staging buffer and don't go through
1051 * the fine-grained upload path.
1053 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0,
1054 desc_list_byte_size
,
1055 si_optimal_tcc_alignment(sctx
, desc_list_byte_size
),
1056 (unsigned*)&desc
->buffer_offset
,
1057 (struct pipe_resource
**)&desc
->buffer
, (void**)&ptr
);
1061 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1062 desc
->buffer
, RADEON_USAGE_READ
,
1063 RADEON_PRIO_DESCRIPTORS
);
1065 assert(count
<= SI_MAX_ATTRIBS
);
1067 for (i
= 0; i
< count
; i
++) {
1068 struct pipe_vertex_buffer
*vb
;
1069 struct r600_resource
*rbuffer
;
1071 unsigned vbo_index
= velems
->vertex_buffer_index
[i
];
1072 uint32_t *desc
= &ptr
[i
*4];
1074 vb
= &sctx
->vertex_buffer
[vbo_index
];
1075 rbuffer
= (struct r600_resource
*)vb
->buffer
.resource
;
1077 memset(desc
, 0, 16);
1081 offset
= vb
->buffer_offset
+ velems
->src_offset
[i
];
1082 va
= rbuffer
->gpu_address
+ offset
;
1084 /* Fill in T# buffer resource description */
1086 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1087 S_008F04_STRIDE(vb
->stride
);
1089 if (sctx
->b
.chip_class
!= VI
&& vb
->stride
) {
1090 /* Round up by rounding down and adding 1 */
1091 desc
[2] = (vb
->buffer
.resource
->width0
- offset
-
1092 velems
->format_size
[i
]) /
1095 desc
[2] = vb
->buffer
.resource
->width0
- offset
;
1098 desc
[3] = velems
->rsrc_word3
[i
];
1100 if (first_vb_use_mask
& (1 << i
)) {
1101 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1102 (struct r600_resource
*)vb
->buffer
.resource
,
1103 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1107 /* Don't flush the const cache. It would have a very negative effect
1108 * on performance (confirmed by testing). New descriptors are always
1109 * uploaded to a fresh new buffer, so I don't think flushing the const
1110 * cache is needed. */
1111 si_mark_atom_dirty(sctx
, &sctx
->shader_userdata
.atom
);
1112 if (sctx
->b
.chip_class
>= CIK
)
1113 si_mark_atom_dirty(sctx
, &sctx
->prefetch_L2
);
1114 sctx
->vertex_buffers_dirty
= false;
1115 sctx
->vertex_buffer_pointer_dirty
= true;
1120 /* CONSTANT BUFFERS */
1123 si_const_and_shader_buffer_descriptors_idx(unsigned shader
)
1125 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
1126 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
;
1129 static struct si_descriptors
*
1130 si_const_and_shader_buffer_descriptors(struct si_context
*sctx
, unsigned shader
)
1132 return &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(shader
)];
1135 void si_upload_const_buffer(struct si_context
*sctx
, struct r600_resource
**rbuffer
,
1136 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
)
1140 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, size
,
1141 si_optimal_tcc_alignment(sctx
, size
),
1143 (struct pipe_resource
**)rbuffer
, &tmp
);
1145 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
1148 static void si_set_constant_buffer(struct si_context
*sctx
,
1149 struct si_buffer_resources
*buffers
,
1150 unsigned descriptors_idx
,
1151 uint slot
, const struct pipe_constant_buffer
*input
)
1153 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1154 assert(slot
< descs
->num_elements
);
1155 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1157 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1158 * with a NULL buffer). We need to use a dummy buffer instead. */
1159 if (sctx
->b
.chip_class
== CIK
&&
1160 (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
1161 input
= &sctx
->null_const_buf
;
1163 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1164 struct pipe_resource
*buffer
= NULL
;
1167 /* Upload the user buffer if needed. */
1168 if (input
->user_buffer
) {
1169 unsigned buffer_offset
;
1171 si_upload_const_buffer(sctx
,
1172 (struct r600_resource
**)&buffer
, input
->user_buffer
,
1173 input
->buffer_size
, &buffer_offset
);
1175 /* Just unbind on failure. */
1176 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1179 va
= r600_resource(buffer
)->gpu_address
+ buffer_offset
;
1181 pipe_resource_reference(&buffer
, input
->buffer
);
1182 va
= r600_resource(buffer
)->gpu_address
+ input
->buffer_offset
;
1183 /* Only track usage for non-user buffers. */
1184 r600_resource(buffer
)->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
1187 /* Set the descriptor. */
1188 uint32_t *desc
= descs
->list
+ slot
*4;
1190 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1192 desc
[2] = input
->buffer_size
;
1193 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1194 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1195 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1196 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1197 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1198 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1200 buffers
->buffers
[slot
] = buffer
;
1201 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1202 (struct r600_resource
*)buffer
,
1203 buffers
->shader_usage_constbuf
,
1204 buffers
->priority_constbuf
, true);
1205 buffers
->enabled_mask
|= 1u << slot
;
1207 /* Clear the descriptor. */
1208 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1209 buffers
->enabled_mask
&= ~(1u << slot
);
1212 descs
->dirty_mask
|= 1u << slot
;
1213 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1216 void si_set_rw_buffer(struct si_context
*sctx
,
1217 uint slot
, const struct pipe_constant_buffer
*input
)
1219 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
,
1220 SI_DESCS_RW_BUFFERS
, slot
, input
);
1223 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
,
1224 enum pipe_shader_type shader
, uint slot
,
1225 const struct pipe_constant_buffer
*input
)
1227 struct si_context
*sctx
= (struct si_context
*)ctx
;
1229 if (shader
>= SI_NUM_SHADERS
)
1232 slot
= si_get_constbuf_slot(slot
);
1233 si_set_constant_buffer(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1234 si_const_and_shader_buffer_descriptors_idx(shader
),
1238 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
1239 uint slot
, struct pipe_constant_buffer
*cbuf
)
1241 cbuf
->user_buffer
= NULL
;
1242 si_get_buffer_from_descriptors(
1243 &sctx
->const_and_shader_buffers
[shader
],
1244 si_const_and_shader_buffer_descriptors(sctx
, shader
),
1245 si_get_constbuf_slot(slot
),
1246 &cbuf
->buffer
, &cbuf
->buffer_offset
, &cbuf
->buffer_size
);
1249 /* SHADER BUFFERS */
1251 static void si_set_shader_buffers(struct pipe_context
*ctx
,
1252 enum pipe_shader_type shader
,
1253 unsigned start_slot
, unsigned count
,
1254 const struct pipe_shader_buffer
*sbuffers
)
1256 struct si_context
*sctx
= (struct si_context
*)ctx
;
1257 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1258 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1261 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1263 for (i
= 0; i
< count
; ++i
) {
1264 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1265 struct r600_resource
*buf
;
1266 unsigned slot
= si_get_shaderbuf_slot(start_slot
+ i
);
1267 uint32_t *desc
= descs
->list
+ slot
* 4;
1270 if (!sbuffer
|| !sbuffer
->buffer
) {
1271 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1272 memset(desc
, 0, sizeof(uint32_t) * 4);
1273 buffers
->enabled_mask
&= ~(1u << slot
);
1274 descs
->dirty_mask
|= 1u << slot
;
1275 sctx
->descriptors_dirty
|=
1276 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1280 buf
= (struct r600_resource
*)sbuffer
->buffer
;
1281 va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1284 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1286 desc
[2] = sbuffer
->buffer_size
;
1287 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1288 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1289 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1290 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1291 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1292 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1294 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1295 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
, buf
,
1296 buffers
->shader_usage
,
1297 buffers
->priority
, true);
1298 buf
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1300 buffers
->enabled_mask
|= 1u << slot
;
1301 descs
->dirty_mask
|= 1u << slot
;
1302 sctx
->descriptors_dirty
|=
1303 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1305 util_range_add(&buf
->valid_buffer_range
, sbuffer
->buffer_offset
,
1306 sbuffer
->buffer_offset
+ sbuffer
->buffer_size
);
1310 void si_get_shader_buffers(struct si_context
*sctx
,
1311 enum pipe_shader_type shader
,
1312 uint start_slot
, uint count
,
1313 struct pipe_shader_buffer
*sbuf
)
1315 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1316 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1318 for (unsigned i
= 0; i
< count
; ++i
) {
1319 si_get_buffer_from_descriptors(
1321 si_get_shaderbuf_slot(start_slot
+ i
),
1322 &sbuf
[i
].buffer
, &sbuf
[i
].buffer_offset
,
1323 &sbuf
[i
].buffer_size
);
1329 void si_set_ring_buffer(struct pipe_context
*ctx
, uint slot
,
1330 struct pipe_resource
*buffer
,
1331 unsigned stride
, unsigned num_records
,
1332 bool add_tid
, bool swizzle
,
1333 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1335 struct si_context
*sctx
= (struct si_context
*)ctx
;
1336 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1337 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1339 /* The stride field in the resource descriptor has 14 bits */
1340 assert(stride
< (1 << 14));
1342 assert(slot
< descs
->num_elements
);
1343 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1348 va
= r600_resource(buffer
)->gpu_address
+ offset
;
1350 switch (element_size
) {
1352 assert(!"Unsupported ring buffer element size");
1368 switch (index_stride
) {
1370 assert(!"Unsupported ring buffer index stride");
1386 if (sctx
->b
.chip_class
>= VI
&& stride
)
1387 num_records
*= stride
;
1389 /* Set the descriptor. */
1390 uint32_t *desc
= descs
->list
+ slot
*4;
1392 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1393 S_008F04_STRIDE(stride
) |
1394 S_008F04_SWIZZLE_ENABLE(swizzle
);
1395 desc
[2] = num_records
;
1396 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1397 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1398 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1399 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1400 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1401 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1402 S_008F0C_INDEX_STRIDE(index_stride
) |
1403 S_008F0C_ADD_TID_ENABLE(add_tid
);
1405 if (sctx
->b
.chip_class
>= GFX9
)
1406 assert(!swizzle
|| element_size
== 1); /* always 4 bytes on GFX9 */
1408 desc
[3] |= S_008F0C_ELEMENT_SIZE(element_size
);
1410 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1411 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1412 (struct r600_resource
*)buffer
,
1413 buffers
->shader_usage
, buffers
->priority
);
1414 buffers
->enabled_mask
|= 1u << slot
;
1416 /* Clear the descriptor. */
1417 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1418 buffers
->enabled_mask
&= ~(1u << slot
);
1421 descs
->dirty_mask
|= 1u << slot
;
1422 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1425 /* STREAMOUT BUFFERS */
1427 static void si_set_streamout_targets(struct pipe_context
*ctx
,
1428 unsigned num_targets
,
1429 struct pipe_stream_output_target
**targets
,
1430 const unsigned *offsets
)
1432 struct si_context
*sctx
= (struct si_context
*)ctx
;
1433 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1434 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1435 unsigned old_num_targets
= sctx
->b
.streamout
.num_targets
;
1438 /* We are going to unbind the buffers. Mark which caches need to be flushed. */
1439 if (sctx
->b
.streamout
.num_targets
&& sctx
->b
.streamout
.begin_emitted
) {
1440 /* Since streamout uses vector writes which go through TC L2
1441 * and most other clients can use TC L2 as well, we don't need
1444 * The only cases which requires flushing it is VGT DMA index
1445 * fetching (on <= CIK) and indirect draw data, which are rare
1446 * cases. Thus, flag the TC L2 dirtiness in the resource and
1447 * handle it at draw call time.
1449 for (i
= 0; i
< sctx
->b
.streamout
.num_targets
; i
++)
1450 if (sctx
->b
.streamout
.targets
[i
])
1451 r600_resource(sctx
->b
.streamout
.targets
[i
]->b
.buffer
)->TC_L2_dirty
= true;
1453 /* Invalidate the scalar cache in case a streamout buffer is
1454 * going to be used as a constant buffer.
1456 * Invalidate TC L1, because streamout bypasses it (done by
1457 * setting GLC=1 in the store instruction), but it can contain
1458 * outdated data of streamout buffers.
1460 * VS_PARTIAL_FLUSH is required if the buffers are going to be
1461 * used as an input immediately.
1463 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
|
1464 SI_CONTEXT_INV_VMEM_L1
|
1465 SI_CONTEXT_VS_PARTIAL_FLUSH
;
1468 /* All readers of the streamout targets need to be finished before we can
1469 * start writing to the targets.
1472 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
1473 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1475 /* Streamout buffers must be bound in 2 places:
1476 * 1) in VGT by setting the VGT_STRMOUT registers
1477 * 2) as shader resources
1480 /* Set the VGT regs. */
1481 r600_set_streamout_targets(ctx
, num_targets
, targets
, offsets
);
1483 /* Set the shader resources.*/
1484 for (i
= 0; i
< num_targets
; i
++) {
1485 bufidx
= SI_VS_STREAMOUT_BUF0
+ i
;
1488 struct pipe_resource
*buffer
= targets
[i
]->buffer
;
1489 uint64_t va
= r600_resource(buffer
)->gpu_address
;
1491 /* Set the descriptor.
1493 * On VI, the format must be non-INVALID, otherwise
1494 * the buffer will be considered not bound and store
1495 * instructions will be no-ops.
1497 uint32_t *desc
= descs
->list
+ bufidx
*4;
1499 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
1500 desc
[2] = 0xffffffff;
1501 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1502 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1503 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1504 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1505 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1507 /* Set the resource. */
1508 pipe_resource_reference(&buffers
->buffers
[bufidx
],
1510 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1511 (struct r600_resource
*)buffer
,
1512 buffers
->shader_usage
,
1513 RADEON_PRIO_SHADER_RW_BUFFER
,
1515 r600_resource(buffer
)->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
1517 buffers
->enabled_mask
|= 1u << bufidx
;
1519 /* Clear the descriptor and unset the resource. */
1520 memset(descs
->list
+ bufidx
*4, 0,
1521 sizeof(uint32_t) * 4);
1522 pipe_resource_reference(&buffers
->buffers
[bufidx
],
1524 buffers
->enabled_mask
&= ~(1u << bufidx
);
1526 descs
->dirty_mask
|= 1u << bufidx
;
1528 for (; i
< old_num_targets
; i
++) {
1529 bufidx
= SI_VS_STREAMOUT_BUF0
+ i
;
1530 /* Clear the descriptor and unset the resource. */
1531 memset(descs
->list
+ bufidx
*4, 0, sizeof(uint32_t) * 4);
1532 pipe_resource_reference(&buffers
->buffers
[bufidx
], NULL
);
1533 buffers
->enabled_mask
&= ~(1u << bufidx
);
1534 descs
->dirty_mask
|= 1u << bufidx
;
1537 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1540 static void si_desc_reset_buffer_offset(struct pipe_context
*ctx
,
1541 uint32_t *desc
, uint64_t old_buf_va
,
1542 struct pipe_resource
*new_buf
)
1544 /* Retrieve the buffer offset from the descriptor. */
1545 uint64_t old_desc_va
=
1546 desc
[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
1548 assert(old_buf_va
<= old_desc_va
);
1549 uint64_t offset_within_buffer
= old_desc_va
- old_buf_va
;
1551 /* Update the descriptor. */
1552 si_set_buf_desc_address(r600_resource(new_buf
), offset_within_buffer
,
1556 /* INTERNAL CONST BUFFERS */
1558 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
1559 const struct pipe_poly_stipple
*state
)
1561 struct si_context
*sctx
= (struct si_context
*)ctx
;
1562 struct pipe_constant_buffer cb
= {};
1563 unsigned stipple
[32];
1566 for (i
= 0; i
< 32; i
++)
1567 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1569 cb
.user_buffer
= stipple
;
1570 cb
.buffer_size
= sizeof(stipple
);
1572 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1575 /* TEXTURE METADATA ENABLE/DISABLE */
1577 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1578 * while the texture is bound, possibly by a different context. In that case,
1579 * call this function to update needs_*_decompress_masks.
1581 void si_update_needs_color_decompress_masks(struct si_context
*sctx
)
1583 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1584 si_samplers_update_needs_color_decompress_mask(&sctx
->samplers
[i
]);
1585 si_images_update_needs_color_decompress_mask(&sctx
->images
[i
]);
1586 si_update_shader_needs_decompress_mask(sctx
, i
);
1590 /* BUFFER DISCARD/INVALIDATION */
1592 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1593 static void si_reset_buffer_resources(struct si_context
*sctx
,
1594 struct si_buffer_resources
*buffers
,
1595 unsigned descriptors_idx
,
1597 struct pipe_resource
*buf
,
1599 enum radeon_bo_usage usage
,
1600 enum radeon_bo_priority priority
)
1602 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1603 unsigned mask
= buffers
->enabled_mask
& slot_mask
;
1606 unsigned i
= u_bit_scan(&mask
);
1607 if (buffers
->buffers
[i
] == buf
) {
1608 si_desc_reset_buffer_offset(&sctx
->b
.b
,
1611 descs
->dirty_mask
|= 1u << i
;
1612 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1614 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1615 (struct r600_resource
*)buf
,
1616 usage
, priority
, true);
1621 static void si_rebind_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
,
1624 struct si_context
*sctx
= (struct si_context
*)ctx
;
1625 struct r600_resource
*rbuffer
= r600_resource(buf
);
1627 unsigned num_elems
= sctx
->vertex_elements
?
1628 sctx
->vertex_elements
->count
: 0;
1630 /* We changed the buffer, now we need to bind it where the old one
1631 * was bound. This consists of 2 things:
1632 * 1) Updating the resource descriptor and dirtying it.
1633 * 2) Adding a relocation to the CS, so that it's usable.
1636 /* Vertex buffers. */
1637 if (rbuffer
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
1638 for (i
= 0; i
< num_elems
; i
++) {
1639 int vb
= sctx
->vertex_elements
->vertex_buffer_index
[i
];
1641 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1643 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1646 if (sctx
->vertex_buffer
[vb
].buffer
.resource
== buf
) {
1647 sctx
->vertex_buffers_dirty
= true;
1653 /* Streamout buffers. (other internal buffers can't be invalidated) */
1654 if (rbuffer
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
1655 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1656 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1657 struct si_descriptors
*descs
=
1658 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1660 if (buffers
->buffers
[i
] != buf
)
1663 si_desc_reset_buffer_offset(ctx
, descs
->list
+ i
*4,
1665 descs
->dirty_mask
|= 1u << i
;
1666 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1668 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1669 rbuffer
, buffers
->shader_usage
,
1670 RADEON_PRIO_SHADER_RW_BUFFER
,
1673 /* Update the streamout state. */
1674 if (sctx
->b
.streamout
.begin_emitted
)
1675 r600_emit_streamout_end(&sctx
->b
);
1676 sctx
->b
.streamout
.append_bitmask
=
1677 sctx
->b
.streamout
.enabled_mask
;
1678 r600_streamout_buffers_dirty(&sctx
->b
);
1682 /* Constant and shader buffers. */
1683 if (rbuffer
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1684 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1685 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1686 si_const_and_shader_buffer_descriptors_idx(shader
),
1687 u_bit_consecutive(SI_NUM_SHADER_BUFFERS
, SI_NUM_CONST_BUFFERS
),
1689 sctx
->const_and_shader_buffers
[shader
].shader_usage_constbuf
,
1690 sctx
->const_and_shader_buffers
[shader
].priority_constbuf
);
1693 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
1694 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1695 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1696 si_const_and_shader_buffer_descriptors_idx(shader
),
1697 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
),
1699 sctx
->const_and_shader_buffers
[shader
].shader_usage
,
1700 sctx
->const_and_shader_buffers
[shader
].priority
);
1703 if (rbuffer
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
1704 /* Texture buffers - update bindings. */
1705 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1706 struct si_sampler_views
*views
= &sctx
->samplers
[shader
].views
;
1707 struct si_descriptors
*descs
=
1708 si_sampler_and_image_descriptors(sctx
, shader
);
1709 unsigned mask
= views
->enabled_mask
;
1712 unsigned i
= u_bit_scan(&mask
);
1713 if (views
->views
[i
]->texture
== buf
) {
1714 unsigned desc_slot
= si_get_sampler_slot(i
);
1716 si_desc_reset_buffer_offset(ctx
,
1720 descs
->dirty_mask
|= 1ull << desc_slot
;
1721 sctx
->descriptors_dirty
|=
1722 1u << si_sampler_and_image_descriptors_idx(shader
);
1724 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1725 rbuffer
, RADEON_USAGE_READ
,
1726 RADEON_PRIO_SAMPLER_BUFFER
,
1734 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
1735 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1736 struct si_images_info
*images
= &sctx
->images
[shader
];
1737 struct si_descriptors
*descs
=
1738 si_sampler_and_image_descriptors(sctx
, shader
);
1739 unsigned mask
= images
->enabled_mask
;
1742 unsigned i
= u_bit_scan(&mask
);
1744 if (images
->views
[i
].resource
== buf
) {
1745 unsigned desc_slot
= si_get_image_slot(i
);
1747 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1748 si_mark_image_range_valid(&images
->views
[i
]);
1750 si_desc_reset_buffer_offset(
1751 ctx
, descs
->list
+ desc_slot
* 8 + 4,
1753 /* two 8-byte images share one 16-byte slot */
1754 descs
->dirty_mask
|= 1u << (desc_slot
/ 2);
1755 sctx
->descriptors_dirty
|=
1756 1u << si_sampler_and_image_descriptors_idx(shader
);
1758 radeon_add_to_buffer_list_check_mem(
1759 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1760 RADEON_USAGE_READWRITE
,
1761 RADEON_PRIO_SAMPLER_BUFFER
, true);
1768 /* Reallocate a buffer a update all resource bindings where the buffer is
1771 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
1772 * idle by discarding its contents. Apps usually tell us when to do this using
1773 * map_buffer flags, for example.
1775 static void si_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
1777 struct si_context
*sctx
= (struct si_context
*)ctx
;
1778 struct r600_resource
*rbuffer
= r600_resource(buf
);
1779 uint64_t old_va
= rbuffer
->gpu_address
;
1781 /* Reallocate the buffer in the same pipe_resource. */
1782 r600_alloc_resource(&sctx
->screen
->b
, rbuffer
);
1784 si_rebind_buffer(ctx
, buf
, old_va
);
1787 /* Update mutable image descriptor fields of all bound textures. */
1788 void si_update_all_texture_descriptors(struct si_context
*sctx
)
1792 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1793 struct si_sampler_views
*samplers
= &sctx
->samplers
[shader
].views
;
1794 struct si_images_info
*images
= &sctx
->images
[shader
];
1798 mask
= images
->enabled_mask
;
1800 unsigned i
= u_bit_scan(&mask
);
1801 struct pipe_image_view
*view
= &images
->views
[i
];
1803 if (!view
->resource
||
1804 view
->resource
->target
== PIPE_BUFFER
)
1807 si_set_shader_image(sctx
, shader
, i
, view
, true);
1810 /* Sampler views. */
1811 mask
= samplers
->enabled_mask
;
1813 unsigned i
= u_bit_scan(&mask
);
1814 struct pipe_sampler_view
*view
= samplers
->views
[i
];
1818 view
->texture
->target
== PIPE_BUFFER
)
1821 si_set_sampler_view(sctx
, shader
, i
,
1822 samplers
->views
[i
], true);
1825 si_update_shader_needs_decompress_mask(sctx
, shader
);
1829 /* SHADER USER DATA */
1831 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
,
1834 sctx
->shader_pointers_dirty
|=
1835 u_bit_consecutive(SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
,
1836 SI_NUM_SHADER_DESCS
);
1838 if (shader
== PIPE_SHADER_VERTEX
)
1839 sctx
->vertex_buffer_pointer_dirty
= sctx
->vertex_buffers
.buffer
!= NULL
;
1841 si_mark_atom_dirty(sctx
, &sctx
->shader_userdata
.atom
);
1844 static void si_shader_userdata_begin_new_cs(struct si_context
*sctx
)
1846 sctx
->shader_pointers_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
1847 sctx
->vertex_buffer_pointer_dirty
= sctx
->vertex_buffers
.buffer
!= NULL
;
1848 si_mark_atom_dirty(sctx
, &sctx
->shader_userdata
.atom
);
1851 /* Set a base register address for user data constants in the given shader.
1852 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1854 static void si_set_user_data_base(struct si_context
*sctx
,
1855 unsigned shader
, uint32_t new_base
)
1857 uint32_t *base
= &sctx
->shader_userdata
.sh_base
[shader
];
1859 if (*base
!= new_base
) {
1863 si_mark_shader_pointers_dirty(sctx
, shader
);
1865 if (shader
== PIPE_SHADER_VERTEX
)
1866 sctx
->last_vs_state
= ~0;
1871 /* This must be called when these shaders are changed from non-NULL to NULL
1874 * - tessellation control shader
1875 * - tessellation evaluation shader
1877 void si_shader_change_notify(struct si_context
*sctx
)
1879 /* VS can be bound as VS, ES, or LS. */
1880 if (sctx
->tes_shader
.cso
) {
1881 if (sctx
->b
.chip_class
>= GFX9
) {
1882 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1883 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
1885 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1886 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
1888 } else if (sctx
->gs_shader
.cso
) {
1889 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1890 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1892 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1893 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1896 /* TES can be bound as ES, VS, or not bound. */
1897 if (sctx
->tes_shader
.cso
) {
1898 if (sctx
->gs_shader
.cso
)
1899 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
1900 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1902 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
1903 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1905 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
1909 static void si_emit_shader_pointer(struct si_context
*sctx
,
1910 struct si_descriptors
*desc
,
1913 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1917 return; /* the pointer is not used by current shaders */
1919 va
= desc
->buffer
->gpu_address
+
1920 desc
->buffer_offset
;
1922 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, 2, 0));
1923 radeon_emit(cs
, (sh_base
+ desc
->shader_userdata_offset
- SI_SH_REG_OFFSET
) >> 2);
1924 radeon_emit(cs
, va
);
1925 radeon_emit(cs
, va
>> 32);
1928 void si_emit_graphics_shader_userdata(struct si_context
*sctx
,
1929 struct r600_atom
*atom
)
1932 uint32_t *sh_base
= sctx
->shader_userdata
.sh_base
;
1933 struct si_descriptors
*descs
;
1935 descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1937 if (sctx
->shader_pointers_dirty
& (1 << SI_DESCS_RW_BUFFERS
)) {
1938 si_emit_shader_pointer(sctx
, descs
,
1939 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
1940 si_emit_shader_pointer(sctx
, descs
,
1941 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1943 if (sctx
->b
.chip_class
>= GFX9
) {
1944 /* GFX9 merged LS-HS and ES-GS.
1945 * Set RW_BUFFERS in the special registers, so that
1946 * it's preloaded into s[0:1] instead of s[8:9].
1948 si_emit_shader_pointer(sctx
, descs
,
1949 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
);
1950 si_emit_shader_pointer(sctx
, descs
,
1951 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
);
1953 si_emit_shader_pointer(sctx
, descs
,
1954 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
1955 si_emit_shader_pointer(sctx
, descs
,
1956 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1957 si_emit_shader_pointer(sctx
, descs
,
1958 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
1962 mask
= sctx
->shader_pointers_dirty
&
1963 u_bit_consecutive(SI_DESCS_FIRST_SHADER
,
1964 SI_DESCS_FIRST_COMPUTE
- SI_DESCS_FIRST_SHADER
);
1967 unsigned i
= u_bit_scan(&mask
);
1968 unsigned shader
= (i
- SI_DESCS_FIRST_SHADER
) / SI_NUM_SHADER_DESCS
;
1969 unsigned base
= sh_base
[shader
];
1972 si_emit_shader_pointer(sctx
, descs
+ i
, base
);
1974 sctx
->shader_pointers_dirty
&=
1975 ~u_bit_consecutive(SI_DESCS_RW_BUFFERS
, SI_DESCS_FIRST_COMPUTE
);
1977 if (sctx
->vertex_buffer_pointer_dirty
) {
1978 si_emit_shader_pointer(sctx
, &sctx
->vertex_buffers
,
1979 sh_base
[PIPE_SHADER_VERTEX
]);
1980 sctx
->vertex_buffer_pointer_dirty
= false;
1984 void si_emit_compute_shader_userdata(struct si_context
*sctx
)
1986 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
1987 struct si_descriptors
*descs
= sctx
->descriptors
;
1988 unsigned compute_mask
=
1989 u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
, SI_NUM_SHADER_DESCS
);
1990 unsigned mask
= sctx
->shader_pointers_dirty
& compute_mask
;
1993 unsigned i
= u_bit_scan(&mask
);
1995 si_emit_shader_pointer(sctx
, descs
+ i
, base
);
1997 sctx
->shader_pointers_dirty
&= ~compute_mask
;
2000 /* INIT/DEINIT/UPLOAD */
2002 /* GFX9 has only 4KB of CE, while previous chips had 32KB. In order
2003 * to make CE RAM as useful as possible, this defines limits
2004 * for the number slots that can be in CE RAM on GFX9. If a shader
2005 * is using more, descriptors will be uploaded to memory directly and
2008 * These numbers are based on shader-db.
2010 static unsigned gfx9_max_ce_samplers
[SI_NUM_SHADERS
] = {
2011 [PIPE_SHADER_VERTEX
] = 0,
2012 [PIPE_SHADER_TESS_CTRL
] = 0,
2013 [PIPE_SHADER_TESS_EVAL
] = 1,
2014 [PIPE_SHADER_GEOMETRY
] = 0,
2015 [PIPE_SHADER_FRAGMENT
] = 24,
2016 [PIPE_SHADER_COMPUTE
] = 16,
2018 static unsigned gfx9_max_ce_images
[SI_NUM_SHADERS
] = {
2019 /* these must be even due to slot alignment */
2020 [PIPE_SHADER_VERTEX
] = 0,
2021 [PIPE_SHADER_TESS_CTRL
] = 0,
2022 [PIPE_SHADER_TESS_EVAL
] = 0,
2023 [PIPE_SHADER_GEOMETRY
] = 0,
2024 [PIPE_SHADER_FRAGMENT
] = 2,
2025 [PIPE_SHADER_COMPUTE
] = 8,
2027 static unsigned gfx9_max_ce_const_buffers
[SI_NUM_SHADERS
] = {
2028 [PIPE_SHADER_VERTEX
] = 9,
2029 [PIPE_SHADER_TESS_CTRL
] = 3,
2030 [PIPE_SHADER_TESS_EVAL
] = 5,
2031 [PIPE_SHADER_GEOMETRY
] = 0,
2032 [PIPE_SHADER_FRAGMENT
] = 8,
2033 [PIPE_SHADER_COMPUTE
] = 6,
2035 static unsigned gfx9_max_ce_shader_buffers
[SI_NUM_SHADERS
] = {
2036 [PIPE_SHADER_VERTEX
] = 0,
2037 [PIPE_SHADER_TESS_CTRL
] = 0,
2038 [PIPE_SHADER_TESS_EVAL
] = 0,
2039 [PIPE_SHADER_GEOMETRY
] = 0,
2040 [PIPE_SHADER_FRAGMENT
] = 12,
2041 [PIPE_SHADER_COMPUTE
] = 13,
2044 void si_init_all_descriptors(struct si_context
*sctx
)
2047 unsigned ce_offset
= 0;
2049 STATIC_ASSERT(GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS
% 2 == 0);
2050 STATIC_ASSERT(GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS
% 2 == 0);
2052 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2053 bool gfx9_tcs
= false;
2054 bool gfx9_gs
= false;
2055 unsigned num_sampler_slots
= SI_NUM_IMAGES
/ 2 + SI_NUM_SAMPLERS
;
2056 unsigned num_buffer_slots
= SI_NUM_SHADER_BUFFERS
+ SI_NUM_CONST_BUFFERS
;
2058 unsigned first_sampler_ce_slot
= 0;
2059 unsigned num_sampler_ce_slots
= num_sampler_slots
;
2061 unsigned first_buffer_ce_slot
= 0;
2062 unsigned num_buffer_ce_slots
= num_buffer_slots
;
2064 /* Adjust CE slot ranges based on GFX9 CE RAM limits. */
2065 if (sctx
->b
.chip_class
>= GFX9
) {
2066 gfx9_tcs
= i
== PIPE_SHADER_TESS_CTRL
;
2067 gfx9_gs
= i
== PIPE_SHADER_GEOMETRY
;
2069 first_sampler_ce_slot
=
2070 si_get_image_slot(gfx9_max_ce_images
[i
] - 1) / 2;
2071 num_sampler_ce_slots
= gfx9_max_ce_images
[i
] / 2 +
2072 gfx9_max_ce_samplers
[i
];
2074 first_buffer_ce_slot
=
2075 si_get_shaderbuf_slot(gfx9_max_ce_shader_buffers
[i
] - 1);
2076 num_buffer_ce_slots
= gfx9_max_ce_shader_buffers
[i
] +
2077 gfx9_max_ce_const_buffers
[i
];
2080 si_init_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[i
],
2081 si_const_and_shader_buffer_descriptors(sctx
, i
),
2083 first_buffer_ce_slot
, num_buffer_ce_slots
,
2084 gfx9_tcs
? GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS
:
2085 gfx9_gs
? GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS
:
2086 SI_SGPR_CONST_AND_SHADER_BUFFERS
,
2087 RADEON_USAGE_READWRITE
,
2089 RADEON_PRIO_SHADER_RW_BUFFER
,
2090 RADEON_PRIO_CONST_BUFFER
,
2093 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, i
);
2094 si_init_descriptors(sctx
, desc
,
2095 gfx9_tcs
? GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES
:
2096 gfx9_gs
? GFX9_SGPR_GS_SAMPLERS_AND_IMAGES
:
2097 SI_SGPR_SAMPLERS_AND_IMAGES
,
2098 16, num_sampler_slots
,
2099 first_sampler_ce_slot
, num_sampler_ce_slots
,
2103 for (j
= 0; j
< SI_NUM_IMAGES
; j
++)
2104 memcpy(desc
->list
+ j
* 8, null_image_descriptor
, 8 * 4);
2105 for (; j
< SI_NUM_IMAGES
+ SI_NUM_SAMPLERS
* 2; j
++)
2106 memcpy(desc
->list
+ j
* 8, null_texture_descriptor
, 8 * 4);
2109 si_init_buffer_resources(sctx
, &sctx
->rw_buffers
,
2110 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
2111 SI_NUM_RW_BUFFERS
, 0, SI_NUM_RW_BUFFERS
,
2113 /* The second set of usage/priority is used by
2114 * const buffers in RW buffer slots. */
2115 RADEON_USAGE_READWRITE
, RADEON_USAGE_READ
,
2116 RADEON_PRIO_SHADER_RINGS
, RADEON_PRIO_CONST_BUFFER
,
2118 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
= SI_NUM_RW_BUFFERS
;
2120 si_init_descriptors(sctx
, &sctx
->vertex_buffers
, SI_SGPR_VERTEX_BUFFERS
,
2121 4, SI_NUM_VERTEX_BUFFERS
, 0, 0, NULL
);
2123 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2124 sctx
->total_ce_ram_allocated
= ce_offset
;
2126 if (sctx
->b
.chip_class
>= GFX9
)
2127 assert(ce_offset
<= 4096);
2129 assert(ce_offset
<= 32768);
2131 /* Set pipe_context functions. */
2132 sctx
->b
.b
.bind_sampler_states
= si_bind_sampler_states
;
2133 sctx
->b
.b
.set_shader_images
= si_set_shader_images
;
2134 sctx
->b
.b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
2135 sctx
->b
.b
.set_polygon_stipple
= si_set_polygon_stipple
;
2136 sctx
->b
.b
.set_shader_buffers
= si_set_shader_buffers
;
2137 sctx
->b
.b
.set_sampler_views
= si_set_sampler_views
;
2138 sctx
->b
.b
.set_stream_output_targets
= si_set_streamout_targets
;
2139 sctx
->b
.invalidate_buffer
= si_invalidate_buffer
;
2140 sctx
->b
.rebind_buffer
= si_rebind_buffer
;
2142 /* Shader user data. */
2143 si_init_atom(sctx
, &sctx
->shader_userdata
.atom
, &sctx
->atoms
.s
.shader_userdata
,
2144 si_emit_graphics_shader_userdata
);
2146 /* Set default and immutable mappings. */
2147 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2149 if (sctx
->b
.chip_class
>= GFX9
) {
2150 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2151 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2152 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2153 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2155 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2156 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2157 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2158 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2160 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2163 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
2165 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
2166 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2168 /* Assume nothing will go wrong: */
2169 sctx
->shader_pointers_dirty
|= dirty
;
2172 unsigned i
= u_bit_scan(&dirty
);
2174 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
],
2175 &sctx
->shader_userdata
.atom
))
2179 sctx
->descriptors_dirty
&= ~mask
;
2183 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
2185 /* Does not update rw_buffers as that is not needed for compute shaders
2186 * and the input buffer is using the same SGPR's anyway.
2188 const unsigned mask
= u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
,
2189 SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
2190 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2192 /* Assume nothing will go wrong: */
2193 sctx
->shader_pointers_dirty
|= dirty
;
2196 unsigned i
= u_bit_scan(&dirty
);
2198 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
], NULL
))
2202 sctx
->descriptors_dirty
&= ~mask
;
2207 void si_release_all_descriptors(struct si_context
*sctx
)
2211 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2212 si_release_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2213 si_const_and_shader_buffer_descriptors(sctx
, i
));
2214 si_release_sampler_views(&sctx
->samplers
[i
].views
);
2215 si_release_image_views(&sctx
->images
[i
]);
2217 si_release_buffer_resources(&sctx
->rw_buffers
,
2218 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2220 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2221 si_release_descriptors(&sctx
->descriptors
[i
]);
2222 si_release_descriptors(&sctx
->vertex_buffers
);
2225 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
2229 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2230 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2231 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
].views
);
2232 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
2234 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2235 si_vertex_buffers_begin_new_cs(sctx
);
2237 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2238 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
2240 si_shader_userdata_begin_new_cs(sctx
);
2243 void si_set_active_descriptors(struct si_context
*sctx
, unsigned desc_idx
,
2244 uint64_t new_active_mask
)
2246 struct si_descriptors
*desc
= &sctx
->descriptors
[desc_idx
];
2248 /* Ignore no-op updates and updates that disable all slots. */
2249 if (!new_active_mask
||
2250 new_active_mask
== u_bit_consecutive64(desc
->first_active_slot
,
2251 desc
->num_active_slots
))
2255 u_bit_scan_consecutive_range64(&new_active_mask
, &first
, &count
);
2256 assert(new_active_mask
== 0);
2258 /* Upload/dump descriptors if slots are being enabled. */
2259 if (first
< desc
->first_active_slot
||
2260 first
+ count
> desc
->first_active_slot
+ desc
->num_active_slots
)
2261 sctx
->descriptors_dirty
|= 1u << desc_idx
;
2263 /* Enable or disable CE for this descriptor array. */
2264 bool used_ce
= desc
->uses_ce
;
2265 desc
->uses_ce
= desc
->first_ce_slot
<= first
&&
2266 desc
->first_ce_slot
+ desc
->num_ce_slots
>= first
+ count
;
2268 if (desc
->uses_ce
!= used_ce
) {
2269 /* Upload or dump descriptors if we're disabling or enabling CE,
2271 sctx
->descriptors_dirty
|= 1u << desc_idx
;
2273 /* If we're enabling CE, re-upload all descriptors to CE RAM.
2274 * When CE was disabled, uploads to CE RAM stopped.
2276 if (desc
->uses_ce
) {
2278 u_bit_consecutive64(desc
->first_ce_slot
,
2279 desc
->num_ce_slots
);
2283 desc
->first_active_slot
= first
;
2284 desc
->num_active_slots
= count
;
2287 void si_set_active_descriptors_for_shader(struct si_context
*sctx
,
2288 struct si_shader_selector
*sel
)
2293 si_set_active_descriptors(sctx
,
2294 si_const_and_shader_buffer_descriptors_idx(sel
->type
),
2295 sel
->active_const_and_shader_buffers
);
2296 si_set_active_descriptors(sctx
,
2297 si_sampler_and_image_descriptors_idx(sel
->type
),
2298 sel
->active_samplers_and_images
);