2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Marek Olšák <marek.olsak@amd.com>
27 /* Resource binding slots and sampler states (each described with 8 or
28 * 4 dwords) are stored in lists in memory which is accessed by shaders
29 * using scalar load instructions.
31 * This file is responsible for managing such lists. It keeps a copy of all
32 * descriptors in CPU memory and re-uploads a whole list if some slots have
35 * This code is also reponsible for updating shader pointers to those lists.
37 * Note that CP DMA can't be used for updating the lists, because a GPU hang
38 * could leave the list in a mid-IB state and the next IB would get wrong
39 * descriptors and the whole context would be unusable at that point.
40 * (Note: The register shadowing can't be used due to the same reason)
42 * Also, uploading descriptors to newly allocated memory doesn't require
46 * Possible scenarios for one 16 dword image+sampler slot:
48 * | Image | w/ FMASK | Buffer | NULL
49 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
50 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
51 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
52 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
54 * FMASK implies MSAA, therefore no sampler state.
55 * Sampler states are never unbound except when FMASK is bound.
58 #include "radeon/r600_cs.h"
63 #include "util/u_format.h"
64 #include "util/u_memory.h"
65 #include "util/u_upload_mgr.h"
68 /* NULL image and buffer descriptor for textures (alpha = 1) and images
71 * For images, all fields must be zero except for the swizzle, which
72 * supports arbitrary combinations of 0s and 1s. The texture type must be
73 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
75 * For buffers, all fields must be zero. If they are not, the hw hangs.
77 * This is the only reason why the buffer descriptor must be in words [4:7].
79 static uint32_t null_texture_descriptor
[8] = {
83 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) |
84 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
85 /* the rest must contain zeros, which is also used by the buffer
89 static uint32_t null_image_descriptor
[8] = {
93 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
94 /* the rest must contain zeros, which is also used by the buffer
98 static void si_init_descriptors(struct si_descriptors
*desc
,
99 unsigned shader_userdata_index
,
100 unsigned element_dw_size
,
101 unsigned num_elements
,
104 assert(num_elements
<= sizeof(desc
->dirty_mask
)*8);
106 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
107 desc
->element_dw_size
= element_dw_size
;
108 desc
->num_elements
= num_elements
;
109 desc
->dirty_mask
= u_bit_consecutive64(0, num_elements
);
110 desc
->shader_userdata_offset
= shader_userdata_index
* 4;
113 desc
->uses_ce
= true;
114 desc
->ce_offset
= *ce_offset
;
116 /* make sure that ce_offset stays 32 byte aligned */
117 *ce_offset
+= align(element_dw_size
* num_elements
* 4, 32);
121 static void si_release_descriptors(struct si_descriptors
*desc
)
123 r600_resource_reference(&desc
->buffer
, NULL
);
127 static bool si_ce_upload(struct si_context
*sctx
, unsigned ce_offset
, unsigned size
,
128 unsigned *out_offset
, struct r600_resource
**out_buf
) {
131 u_suballocator_alloc(sctx
->ce_suballocator
, size
,
132 sctx
->screen
->b
.info
.tcc_cache_line_size
,
133 out_offset
, (struct pipe_resource
**)out_buf
);
137 va
= (*out_buf
)->gpu_address
+ *out_offset
;
139 radeon_emit(sctx
->ce_ib
, PKT3(PKT3_DUMP_CONST_RAM
, 3, 0));
140 radeon_emit(sctx
->ce_ib
, ce_offset
);
141 radeon_emit(sctx
->ce_ib
, size
/ 4);
142 radeon_emit(sctx
->ce_ib
, va
);
143 radeon_emit(sctx
->ce_ib
, va
>> 32);
145 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, *out_buf
,
146 RADEON_USAGE_READWRITE
, RADEON_PRIO_DESCRIPTORS
);
148 sctx
->ce_need_synchronization
= true;
152 static void si_ce_reinitialize_descriptors(struct si_context
*sctx
,
153 struct si_descriptors
*desc
)
156 struct r600_resource
*buffer
= (struct r600_resource
*)desc
->buffer
;
157 unsigned list_size
= desc
->num_elements
* desc
->element_dw_size
* 4;
158 uint64_t va
= buffer
->gpu_address
+ desc
->buffer_offset
;
159 struct radeon_winsys_cs
*ib
= sctx
->ce_preamble_ib
;
164 list_size
= align(list_size
, 32);
166 radeon_emit(ib
, PKT3(PKT3_LOAD_CONST_RAM
, 3, 0));
168 radeon_emit(ib
, va
>> 32);
169 radeon_emit(ib
, list_size
/ 4);
170 radeon_emit(ib
, desc
->ce_offset
);
172 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
173 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
175 desc
->ce_ram_dirty
= false;
178 void si_ce_reinitialize_all_descriptors(struct si_context
*sctx
)
182 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
183 si_ce_reinitialize_descriptors(sctx
, &sctx
->descriptors
[i
]);
186 void si_ce_enable_loads(struct radeon_winsys_cs
*ib
)
188 radeon_emit(ib
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
189 radeon_emit(ib
, CONTEXT_CONTROL_LOAD_ENABLE(1) |
190 CONTEXT_CONTROL_LOAD_CE_RAM(1));
191 radeon_emit(ib
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
194 static bool si_upload_descriptors(struct si_context
*sctx
,
195 struct si_descriptors
*desc
,
196 struct r600_atom
* atom
)
198 unsigned list_size
= desc
->num_elements
* desc
->element_dw_size
* 4;
200 if (!desc
->dirty_mask
)
203 if (sctx
->ce_ib
&& desc
->uses_ce
) {
204 uint32_t const* list
= (uint32_t const*)desc
->list
;
206 if (desc
->ce_ram_dirty
)
207 si_ce_reinitialize_descriptors(sctx
, desc
);
209 while(desc
->dirty_mask
) {
211 u_bit_scan_consecutive_range64(&desc
->dirty_mask
, &begin
,
214 begin
*= desc
->element_dw_size
;
215 count
*= desc
->element_dw_size
;
217 radeon_emit(sctx
->ce_ib
,
218 PKT3(PKT3_WRITE_CONST_RAM
, count
, 0));
219 radeon_emit(sctx
->ce_ib
, desc
->ce_offset
+ begin
* 4);
220 radeon_emit_array(sctx
->ce_ib
, list
+ begin
, count
);
223 if (!si_ce_upload(sctx
, desc
->ce_offset
, list_size
,
224 &desc
->buffer_offset
, &desc
->buffer
))
229 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, list_size
,
230 sctx
->screen
->b
.info
.tcc_cache_line_size
,
231 &desc
->buffer_offset
,
232 (struct pipe_resource
**)&desc
->buffer
, &ptr
);
234 return false; /* skip the draw call */
236 util_memcpy_cpu_to_le32(ptr
, desc
->list
, list_size
);
237 desc
->gpu_list
= ptr
;
239 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
240 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
242 desc
->dirty_mask
= 0;
245 si_mark_atom_dirty(sctx
, atom
);
251 si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
253 desc
->ce_ram_dirty
= true;
258 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
259 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
265 si_sampler_and_image_descriptors_idx(unsigned shader
)
267 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
268 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
;
271 static struct si_descriptors
*
272 si_sampler_and_image_descriptors(struct si_context
*sctx
, unsigned shader
)
274 return &sctx
->descriptors
[si_sampler_and_image_descriptors_idx(shader
)];
277 static void si_release_sampler_views(struct si_sampler_views
*views
)
281 for (i
= 0; i
< ARRAY_SIZE(views
->views
); i
++) {
282 pipe_sampler_view_reference(&views
->views
[i
], NULL
);
286 static void si_sampler_view_add_buffer(struct si_context
*sctx
,
287 struct pipe_resource
*resource
,
288 enum radeon_bo_usage usage
,
289 bool is_stencil_sampler
,
292 struct r600_resource
*rres
;
293 struct r600_texture
*rtex
;
294 enum radeon_bo_priority priority
;
299 if (resource
->target
!= PIPE_BUFFER
) {
300 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
302 if (tex
->is_depth
&& !r600_can_sample_zs(tex
, is_stencil_sampler
))
303 resource
= &tex
->flushed_depth_texture
->resource
.b
.b
;
306 rres
= (struct r600_resource
*)resource
;
307 priority
= r600_get_sampler_view_priority(rres
);
309 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
310 rres
, usage
, priority
,
313 if (resource
->target
== PIPE_BUFFER
)
316 /* Now add separate DCC or HTILE. */
317 rtex
= (struct r600_texture
*)resource
;
318 if (rtex
->dcc_separate_buffer
) {
319 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
320 rtex
->dcc_separate_buffer
, usage
,
321 RADEON_PRIO_DCC
, check_mem
);
324 if (rtex
->htile_buffer
&&
325 rtex
->tc_compatible_htile
&&
326 !is_stencil_sampler
) {
327 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
328 rtex
->htile_buffer
, usage
,
329 RADEON_PRIO_HTILE
, check_mem
);
333 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
,
334 struct si_sampler_views
*views
)
336 unsigned mask
= views
->enabled_mask
;
338 /* Add buffers to the CS. */
340 int i
= u_bit_scan(&mask
);
341 struct si_sampler_view
*sview
= (struct si_sampler_view
*)views
->views
[i
];
343 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
345 sview
->is_stencil_sampler
, false);
349 /* Set buffer descriptor fields that can be changed by reallocations. */
350 static void si_set_buf_desc_address(struct r600_resource
*buf
,
351 uint64_t offset
, uint32_t *state
)
353 uint64_t va
= buf
->gpu_address
+ offset
;
356 state
[1] &= C_008F04_BASE_ADDRESS_HI
;
357 state
[1] |= S_008F04_BASE_ADDRESS_HI(va
>> 32);
360 /* Set texture descriptor fields that can be changed by reallocations.
363 * \param base_level_info information of the level of BASE_ADDRESS
364 * \param base_level the level of BASE_ADDRESS
365 * \param first_level pipe_sampler_view.u.tex.first_level
366 * \param block_width util_format_get_blockwidth()
367 * \param is_stencil select between separate Z & Stencil
368 * \param state descriptor to update
370 void si_set_mutable_tex_desc_fields(struct si_screen
*sscreen
,
371 struct r600_texture
*tex
,
372 const struct legacy_surf_level
*base_level_info
,
373 unsigned base_level
, unsigned first_level
,
374 unsigned block_width
, bool is_stencil
,
377 uint64_t va
, meta_va
= 0;
379 if (tex
->is_depth
&& !r600_can_sample_zs(tex
, is_stencil
)) {
380 tex
= tex
->flushed_depth_texture
;
384 va
= tex
->resource
.gpu_address
;
386 if (sscreen
->b
.chip_class
>= GFX9
) {
387 /* Only stencil_offset needs to be added here. */
389 va
+= tex
->surface
.u
.gfx9
.stencil_offset
;
391 va
+= tex
->surface
.u
.gfx9
.surf_offset
;
393 va
+= base_level_info
->offset
;
397 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
398 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
400 if (sscreen
->b
.chip_class
>= VI
) {
401 state
[6] &= C_008F28_COMPRESSION_EN
;
404 if (vi_dcc_enabled(tex
, first_level
)) {
405 meta_va
= (!tex
->dcc_separate_buffer
? tex
->resource
.gpu_address
: 0) +
408 if (sscreen
->b
.chip_class
<= VI
)
409 meta_va
+= base_level_info
->dcc_offset
;
410 } else if (tex
->tc_compatible_htile
&& !is_stencil
) {
411 meta_va
= tex
->htile_buffer
->gpu_address
;
415 state
[6] |= S_008F28_COMPRESSION_EN(1);
416 state
[7] = meta_va
>> 8;
420 if (sscreen
->b
.chip_class
>= GFX9
) {
421 state
[3] &= C_008F1C_SW_MODE
;
422 state
[4] &= C_008F20_PITCH_GFX9
;
425 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
426 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.stencil
.epitch
);
428 state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
);
429 state
[4] |= S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.surf
.epitch
);
432 state
[5] &= C_008F24_META_DATA_ADDRESS
&
433 C_008F24_META_PIPE_ALIGNED
&
434 C_008F24_META_RB_ALIGNED
;
436 struct gfx9_surf_meta_flags meta
;
439 meta
= tex
->surface
.u
.gfx9
.dcc
;
441 meta
= tex
->surface
.u
.gfx9
.htile
;
443 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
444 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
445 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
449 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
450 unsigned index
= si_tile_mode_index(tex
, base_level
, is_stencil
);
452 state
[3] &= C_008F1C_TILING_INDEX
;
453 state
[3] |= S_008F1C_TILING_INDEX(index
);
454 state
[4] &= C_008F20_PITCH_GFX6
;
455 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
459 static void si_set_sampler_view(struct si_context
*sctx
,
461 unsigned slot
, struct pipe_sampler_view
*view
,
462 bool disallow_early_out
)
464 struct si_sampler_views
*views
= &sctx
->samplers
[shader
].views
;
465 struct si_sampler_view
*rview
= (struct si_sampler_view
*)view
;
466 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(sctx
, shader
);
467 unsigned desc_slot
= si_get_sampler_slot(slot
);
468 uint32_t *desc
= descs
->list
+ desc_slot
* 16;
470 if (views
->views
[slot
] == view
&& !disallow_early_out
)
474 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
475 bool is_buffer
= rtex
->resource
.b
.b
.target
== PIPE_BUFFER
;
477 if (unlikely(!is_buffer
&& rview
->dcc_incompatible
)) {
478 if (vi_dcc_enabled(rtex
, view
->u
.tex
.first_level
))
479 if (!r600_texture_disable_dcc(&sctx
->b
, rtex
))
480 sctx
->b
.decompress_dcc(&sctx
->b
.b
, rtex
);
482 rview
->dcc_incompatible
= false;
485 assert(rtex
); /* views with texture == NULL aren't supported */
486 pipe_sampler_view_reference(&views
->views
[slot
], view
);
487 memcpy(desc
, rview
->state
, 8*4);
490 rtex
->resource
.bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
492 si_set_buf_desc_address(&rtex
->resource
,
496 bool is_separate_stencil
=
497 rtex
->db_compatible
&&
498 rview
->is_stencil_sampler
;
500 si_set_mutable_tex_desc_fields(sctx
->screen
, rtex
,
501 rview
->base_level_info
,
503 rview
->base
.u
.tex
.first_level
,
509 if (!is_buffer
&& rtex
->fmask
.size
) {
511 rview
->fmask_state
, 8*4);
513 /* Disable FMASK and bind sampler state in [12:15]. */
515 null_texture_descriptor
, 4*4);
517 if (views
->sampler_states
[slot
])
519 views
->sampler_states
[slot
]->val
, 4*4);
522 views
->enabled_mask
|= 1u << slot
;
524 /* Since this can flush, it must be done after enabled_mask is
526 si_sampler_view_add_buffer(sctx
, view
->texture
,
528 rview
->is_stencil_sampler
, true);
530 pipe_sampler_view_reference(&views
->views
[slot
], NULL
);
531 memcpy(desc
, null_texture_descriptor
, 8*4);
532 /* Only clear the lower dwords of FMASK. */
533 memcpy(desc
+ 8, null_texture_descriptor
, 4*4);
534 /* Re-set the sampler state if we are transitioning from FMASK. */
535 if (views
->sampler_states
[slot
])
537 views
->sampler_states
[slot
]->val
, 4*4);
539 views
->enabled_mask
&= ~(1u << slot
);
542 descs
->dirty_mask
|= 1ull << desc_slot
;
543 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
546 static bool is_compressed_colortex(struct r600_texture
*rtex
)
548 return rtex
->fmask
.size
||
549 (rtex
->dirty_level_mask
&&
550 (rtex
->cmask
.size
|| rtex
->dcc_offset
));
553 static bool depth_needs_decompression(struct r600_texture
*rtex
,
554 struct si_sampler_view
*sview
)
556 return rtex
->db_compatible
&&
557 (!rtex
->tc_compatible_htile
|| sview
->is_stencil_sampler
);
560 static void si_update_compressed_tex_shader_mask(struct si_context
*sctx
,
563 struct si_textures_info
*samplers
= &sctx
->samplers
[shader
];
564 unsigned shader_bit
= 1 << shader
;
566 if (samplers
->depth_texture_mask
||
567 samplers
->compressed_colortex_mask
||
568 sctx
->images
[shader
].compressed_colortex_mask
)
569 sctx
->compressed_tex_shader_mask
|= shader_bit
;
571 sctx
->compressed_tex_shader_mask
&= ~shader_bit
;
574 static void si_set_sampler_views(struct pipe_context
*ctx
,
575 enum pipe_shader_type shader
, unsigned start
,
577 struct pipe_sampler_view
**views
)
579 struct si_context
*sctx
= (struct si_context
*)ctx
;
580 struct si_textures_info
*samplers
= &sctx
->samplers
[shader
];
583 if (!count
|| shader
>= SI_NUM_SHADERS
)
586 for (i
= 0; i
< count
; i
++) {
587 unsigned slot
= start
+ i
;
589 if (!views
|| !views
[i
]) {
590 samplers
->depth_texture_mask
&= ~(1u << slot
);
591 samplers
->compressed_colortex_mask
&= ~(1u << slot
);
592 si_set_sampler_view(sctx
, shader
, slot
, NULL
, false);
596 si_set_sampler_view(sctx
, shader
, slot
, views
[i
], false);
598 if (views
[i
]->texture
&& views
[i
]->texture
->target
!= PIPE_BUFFER
) {
599 struct r600_texture
*rtex
=
600 (struct r600_texture
*)views
[i
]->texture
;
601 struct si_sampler_view
*rview
= (struct si_sampler_view
*)views
[i
];
603 if (depth_needs_decompression(rtex
, rview
)) {
604 samplers
->depth_texture_mask
|= 1u << slot
;
606 samplers
->depth_texture_mask
&= ~(1u << slot
);
608 if (is_compressed_colortex(rtex
)) {
609 samplers
->compressed_colortex_mask
|= 1u << slot
;
611 samplers
->compressed_colortex_mask
&= ~(1u << slot
);
614 if (rtex
->dcc_offset
&&
615 p_atomic_read(&rtex
->framebuffers_bound
))
616 sctx
->need_check_render_feedback
= true;
618 samplers
->depth_texture_mask
&= ~(1u << slot
);
619 samplers
->compressed_colortex_mask
&= ~(1u << slot
);
623 si_update_compressed_tex_shader_mask(sctx
, shader
);
627 si_samplers_update_compressed_colortex_mask(struct si_textures_info
*samplers
)
629 unsigned mask
= samplers
->views
.enabled_mask
;
632 int i
= u_bit_scan(&mask
);
633 struct pipe_resource
*res
= samplers
->views
.views
[i
]->texture
;
635 if (res
&& res
->target
!= PIPE_BUFFER
) {
636 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
638 if (is_compressed_colortex(rtex
)) {
639 samplers
->compressed_colortex_mask
|= 1u << i
;
641 samplers
->compressed_colortex_mask
&= ~(1u << i
);
650 si_release_image_views(struct si_images_info
*images
)
654 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
655 struct pipe_image_view
*view
= &images
->views
[i
];
657 pipe_resource_reference(&view
->resource
, NULL
);
662 si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images_info
*images
)
664 uint mask
= images
->enabled_mask
;
666 /* Add buffers to the CS. */
668 int i
= u_bit_scan(&mask
);
669 struct pipe_image_view
*view
= &images
->views
[i
];
671 assert(view
->resource
);
673 si_sampler_view_add_buffer(sctx
, view
->resource
,
674 RADEON_USAGE_READWRITE
, false, false);
679 si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
681 struct si_images_info
*images
= &ctx
->images
[shader
];
683 if (images
->enabled_mask
& (1u << slot
)) {
684 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
685 unsigned desc_slot
= si_get_image_slot(slot
);
687 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
688 images
->compressed_colortex_mask
&= ~(1 << slot
);
690 memcpy(descs
->list
+ desc_slot
*8, null_image_descriptor
, 8*4);
691 images
->enabled_mask
&= ~(1u << slot
);
692 /* two 8-byte images share one 16-byte slot */
693 descs
->dirty_mask
|= 1u << (desc_slot
/ 2);
694 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
699 si_mark_image_range_valid(const struct pipe_image_view
*view
)
701 struct r600_resource
*res
= (struct r600_resource
*)view
->resource
;
703 assert(res
&& res
->b
.b
.target
== PIPE_BUFFER
);
705 util_range_add(&res
->valid_buffer_range
,
707 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
710 static void si_set_shader_image(struct si_context
*ctx
,
712 unsigned slot
, const struct pipe_image_view
*view
,
713 bool skip_decompress
)
715 struct si_screen
*screen
= ctx
->screen
;
716 struct si_images_info
*images
= &ctx
->images
[shader
];
717 struct si_descriptors
*descs
= si_sampler_and_image_descriptors(ctx
, shader
);
718 struct r600_resource
*res
;
719 unsigned desc_slot
= si_get_image_slot(slot
);
720 uint32_t *desc
= descs
->list
+ desc_slot
* 8;
722 if (!view
|| !view
->resource
) {
723 si_disable_shader_image(ctx
, shader
, slot
);
727 res
= (struct r600_resource
*)view
->resource
;
729 if (&images
->views
[slot
] != view
)
730 util_copy_image_view(&images
->views
[slot
], view
);
732 if (res
->b
.b
.target
== PIPE_BUFFER
) {
733 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
734 si_mark_image_range_valid(view
);
736 si_make_buffer_descriptor(screen
, res
,
739 view
->u
.buf
.size
, desc
);
740 si_set_buf_desc_address(res
, view
->u
.buf
.offset
, desc
+ 4);
742 images
->compressed_colortex_mask
&= ~(1 << slot
);
743 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
745 static const unsigned char swizzle
[4] = { 0, 1, 2, 3 };
746 struct r600_texture
*tex
= (struct r600_texture
*)res
;
747 unsigned level
= view
->u
.tex
.level
;
748 unsigned width
, height
, depth
, hw_level
;
749 bool uses_dcc
= vi_dcc_enabled(tex
, level
);
751 assert(!tex
->is_depth
);
752 assert(tex
->fmask
.size
== 0);
754 if (uses_dcc
&& !skip_decompress
&&
755 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
||
756 !vi_dcc_formats_compatible(res
->b
.b
.format
, view
->format
))) {
757 /* If DCC can't be disabled, at least decompress it.
758 * The decompression is relatively cheap if the surface
759 * has been decompressed already.
761 if (r600_texture_disable_dcc(&ctx
->b
, tex
))
764 ctx
->b
.decompress_dcc(&ctx
->b
.b
, tex
);
767 if (is_compressed_colortex(tex
)) {
768 images
->compressed_colortex_mask
|= 1 << slot
;
770 images
->compressed_colortex_mask
&= ~(1 << slot
);
774 p_atomic_read(&tex
->framebuffers_bound
))
775 ctx
->need_check_render_feedback
= true;
777 if (ctx
->b
.chip_class
>= GFX9
) {
778 /* Always set the base address. The swizzle modes don't
779 * allow setting mipmap level offsets as the base.
781 width
= res
->b
.b
.width0
;
782 height
= res
->b
.b
.height0
;
783 depth
= res
->b
.b
.depth0
;
786 /* Always force the base level to the selected level.
788 * This is required for 3D textures, where otherwise
789 * selecting a single slice for non-layered bindings
790 * fails. It doesn't hurt the other targets.
792 width
= u_minify(res
->b
.b
.width0
, level
);
793 height
= u_minify(res
->b
.b
.height0
, level
);
794 depth
= u_minify(res
->b
.b
.depth0
, level
);
798 si_make_texture_descriptor(screen
, tex
,
799 false, res
->b
.b
.target
,
800 view
->format
, swizzle
,
802 view
->u
.tex
.first_layer
,
803 view
->u
.tex
.last_layer
,
804 width
, height
, depth
,
806 si_set_mutable_tex_desc_fields(screen
, tex
,
807 &tex
->surface
.u
.legacy
.level
[level
],
809 util_format_get_blockwidth(view
->format
),
813 images
->enabled_mask
|= 1u << slot
;
814 /* two 8-byte images share one 16-byte slot */
815 descs
->dirty_mask
|= 1u << (desc_slot
/ 2);
816 ctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
818 /* Since this can flush, it must be done after enabled_mask is updated. */
819 si_sampler_view_add_buffer(ctx
, &res
->b
.b
,
820 RADEON_USAGE_READWRITE
, false, true);
824 si_set_shader_images(struct pipe_context
*pipe
,
825 enum pipe_shader_type shader
,
826 unsigned start_slot
, unsigned count
,
827 const struct pipe_image_view
*views
)
829 struct si_context
*ctx
= (struct si_context
*)pipe
;
832 assert(shader
< SI_NUM_SHADERS
);
837 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
840 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
841 si_set_shader_image(ctx
, shader
, slot
, &views
[i
], false);
843 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
844 si_set_shader_image(ctx
, shader
, slot
, NULL
, false);
847 si_update_compressed_tex_shader_mask(ctx
, shader
);
851 si_images_update_compressed_colortex_mask(struct si_images_info
*images
)
853 unsigned mask
= images
->enabled_mask
;
856 int i
= u_bit_scan(&mask
);
857 struct pipe_resource
*res
= images
->views
[i
].resource
;
859 if (res
&& res
->target
!= PIPE_BUFFER
) {
860 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
862 if (is_compressed_colortex(rtex
)) {
863 images
->compressed_colortex_mask
|= 1 << i
;
865 images
->compressed_colortex_mask
&= ~(1 << i
);
873 static void si_bind_sampler_states(struct pipe_context
*ctx
,
874 enum pipe_shader_type shader
,
875 unsigned start
, unsigned count
, void **states
)
877 struct si_context
*sctx
= (struct si_context
*)ctx
;
878 struct si_textures_info
*samplers
= &sctx
->samplers
[shader
];
879 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, shader
);
880 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
883 if (!count
|| shader
>= SI_NUM_SHADERS
)
886 for (i
= 0; i
< count
; i
++) {
887 unsigned slot
= start
+ i
;
888 unsigned desc_slot
= si_get_sampler_slot(slot
);
891 sstates
[i
] == samplers
->views
.sampler_states
[slot
])
895 assert(sstates
[i
]->magic
== SI_SAMPLER_STATE_MAGIC
);
897 samplers
->views
.sampler_states
[slot
] = sstates
[i
];
899 /* If FMASK is bound, don't overwrite it.
900 * The sampler state will be set after FMASK is unbound.
902 if (samplers
->views
.views
[slot
] &&
903 samplers
->views
.views
[slot
]->texture
&&
904 samplers
->views
.views
[slot
]->texture
->target
!= PIPE_BUFFER
&&
905 ((struct r600_texture
*)samplers
->views
.views
[slot
]->texture
)->fmask
.size
)
908 memcpy(desc
->list
+ desc_slot
* 16 + 12, sstates
[i
]->val
, 4*4);
909 desc
->dirty_mask
|= 1ull << desc_slot
;
910 sctx
->descriptors_dirty
|= 1u << si_sampler_and_image_descriptors_idx(shader
);
914 /* BUFFER RESOURCES */
916 static void si_init_buffer_resources(struct si_buffer_resources
*buffers
,
917 struct si_descriptors
*descs
,
918 unsigned num_buffers
,
919 unsigned shader_userdata_index
,
920 enum radeon_bo_usage shader_usage
,
921 enum radeon_bo_usage shader_usage_constbuf
,
922 enum radeon_bo_priority priority
,
923 enum radeon_bo_priority priority_constbuf
,
926 buffers
->shader_usage
= shader_usage
;
927 buffers
->shader_usage_constbuf
= shader_usage_constbuf
;
928 buffers
->priority
= priority
;
929 buffers
->priority_constbuf
= priority_constbuf
;
930 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
932 si_init_descriptors(descs
, shader_userdata_index
, 4,
933 num_buffers
, ce_offset
);
936 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
937 struct si_descriptors
*descs
)
941 for (i
= 0; i
< descs
->num_elements
; i
++) {
942 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
945 FREE(buffers
->buffers
);
948 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
949 struct si_buffer_resources
*buffers
)
951 unsigned mask
= buffers
->enabled_mask
;
953 /* Add buffers to the CS. */
955 int i
= u_bit_scan(&mask
);
957 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
958 r600_resource(buffers
->buffers
[i
]),
959 i
< SI_NUM_SHADER_BUFFERS
? buffers
->shader_usage
:
960 buffers
->shader_usage_constbuf
,
961 i
< SI_NUM_SHADER_BUFFERS
? buffers
->priority
:
962 buffers
->priority_constbuf
);
966 static void si_get_buffer_from_descriptors(struct si_buffer_resources
*buffers
,
967 struct si_descriptors
*descs
,
968 unsigned idx
, struct pipe_resource
**buf
,
969 unsigned *offset
, unsigned *size
)
971 pipe_resource_reference(buf
, buffers
->buffers
[idx
]);
973 struct r600_resource
*res
= r600_resource(*buf
);
974 const uint32_t *desc
= descs
->list
+ idx
* 4;
979 assert(G_008F04_STRIDE(desc
[1]) == 0);
980 va
= ((uint64_t)desc
[1] << 32) | desc
[0];
982 assert(va
>= res
->gpu_address
&& va
+ *size
<= res
->gpu_address
+ res
->bo_size
);
983 *offset
= va
- res
->gpu_address
;
989 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
991 struct si_descriptors
*desc
= &sctx
->vertex_buffers
;
992 int count
= sctx
->vertex_elements
? sctx
->vertex_elements
->count
: 0;
995 for (i
= 0; i
< count
; i
++) {
996 int vb
= sctx
->vertex_elements
->elements
[i
].vertex_buffer_index
;
998 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1000 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1003 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1004 (struct r600_resource
*)sctx
->vertex_buffer
[vb
].buffer
.resource
,
1005 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1010 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1011 desc
->buffer
, RADEON_USAGE_READ
,
1012 RADEON_PRIO_DESCRIPTORS
);
1015 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
1017 struct si_vertex_element
*velems
= sctx
->vertex_elements
;
1018 struct si_descriptors
*desc
= &sctx
->vertex_buffers
;
1020 unsigned desc_list_byte_size
;
1021 unsigned first_vb_use_mask
;
1025 if (!sctx
->vertex_buffers_dirty
|| !velems
)
1028 count
= velems
->count
;
1033 desc_list_byte_size
= velems
->desc_list_byte_size
;
1034 first_vb_use_mask
= velems
->first_vb_use_mask
;
1036 /* Vertex buffer descriptors are the only ones which are uploaded
1037 * directly through a staging buffer and don't go through
1038 * the fine-grained upload path.
1040 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0,
1041 desc_list_byte_size
,
1042 si_optimal_tcc_alignment(sctx
, desc_list_byte_size
),
1043 &desc
->buffer_offset
,
1044 (struct pipe_resource
**)&desc
->buffer
, (void**)&ptr
);
1048 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1049 desc
->buffer
, RADEON_USAGE_READ
,
1050 RADEON_PRIO_DESCRIPTORS
);
1052 assert(count
<= SI_MAX_ATTRIBS
);
1054 for (i
= 0; i
< count
; i
++) {
1055 struct pipe_vertex_element
*ve
= &velems
->elements
[i
];
1056 struct pipe_vertex_buffer
*vb
;
1057 struct r600_resource
*rbuffer
;
1059 unsigned vbo_index
= ve
->vertex_buffer_index
;
1060 uint32_t *desc
= &ptr
[i
*4];
1062 vb
= &sctx
->vertex_buffer
[vbo_index
];
1063 rbuffer
= (struct r600_resource
*)vb
->buffer
.resource
;
1065 memset(desc
, 0, 16);
1069 offset
= vb
->buffer_offset
+ ve
->src_offset
;
1070 va
= rbuffer
->gpu_address
+ offset
;
1072 /* Fill in T# buffer resource description */
1074 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1075 S_008F04_STRIDE(vb
->stride
);
1077 if (sctx
->b
.chip_class
!= VI
&& vb
->stride
) {
1078 /* Round up by rounding down and adding 1 */
1079 desc
[2] = (vb
->buffer
.resource
->width0
- offset
-
1080 velems
->format_size
[i
]) /
1083 desc
[2] = vb
->buffer
.resource
->width0
- offset
;
1086 desc
[3] = velems
->rsrc_word3
[i
];
1088 if (first_vb_use_mask
& (1 << i
)) {
1089 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1090 (struct r600_resource
*)vb
->buffer
.resource
,
1091 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
1095 /* Don't flush the const cache. It would have a very negative effect
1096 * on performance (confirmed by testing). New descriptors are always
1097 * uploaded to a fresh new buffer, so I don't think flushing the const
1098 * cache is needed. */
1099 si_mark_atom_dirty(sctx
, &sctx
->shader_userdata
.atom
);
1100 if (sctx
->b
.chip_class
>= CIK
)
1101 si_mark_atom_dirty(sctx
, &sctx
->prefetch_L2
);
1102 sctx
->vertex_buffers_dirty
= false;
1103 sctx
->vertex_buffer_pointer_dirty
= true;
1108 /* CONSTANT BUFFERS */
1111 si_const_and_shader_buffer_descriptors_idx(unsigned shader
)
1113 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
1114 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
;
1117 static struct si_descriptors
*
1118 si_const_and_shader_buffer_descriptors(struct si_context
*sctx
, unsigned shader
)
1120 return &sctx
->descriptors
[si_const_and_shader_buffer_descriptors_idx(shader
)];
1123 void si_upload_const_buffer(struct si_context
*sctx
, struct r600_resource
**rbuffer
,
1124 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
)
1128 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, size
,
1129 si_optimal_tcc_alignment(sctx
, size
),
1131 (struct pipe_resource
**)rbuffer
, &tmp
);
1133 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
1136 static void si_set_constant_buffer(struct si_context
*sctx
,
1137 struct si_buffer_resources
*buffers
,
1138 unsigned descriptors_idx
,
1139 uint slot
, const struct pipe_constant_buffer
*input
)
1141 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1142 assert(slot
< descs
->num_elements
);
1143 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1145 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
1146 * with a NULL buffer). We need to use a dummy buffer instead. */
1147 if (sctx
->b
.chip_class
== CIK
&&
1148 (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
1149 input
= &sctx
->null_const_buf
;
1151 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
1152 struct pipe_resource
*buffer
= NULL
;
1155 /* Upload the user buffer if needed. */
1156 if (input
->user_buffer
) {
1157 unsigned buffer_offset
;
1159 si_upload_const_buffer(sctx
,
1160 (struct r600_resource
**)&buffer
, input
->user_buffer
,
1161 input
->buffer_size
, &buffer_offset
);
1163 /* Just unbind on failure. */
1164 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1167 va
= r600_resource(buffer
)->gpu_address
+ buffer_offset
;
1169 pipe_resource_reference(&buffer
, input
->buffer
);
1170 va
= r600_resource(buffer
)->gpu_address
+ input
->buffer_offset
;
1171 /* Only track usage for non-user buffers. */
1172 r600_resource(buffer
)->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
1175 /* Set the descriptor. */
1176 uint32_t *desc
= descs
->list
+ slot
*4;
1178 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1180 desc
[2] = input
->buffer_size
;
1181 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1182 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1183 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1184 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1185 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1186 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1188 buffers
->buffers
[slot
] = buffer
;
1189 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1190 (struct r600_resource
*)buffer
,
1191 buffers
->shader_usage_constbuf
,
1192 buffers
->priority_constbuf
, true);
1193 buffers
->enabled_mask
|= 1u << slot
;
1195 /* Clear the descriptor. */
1196 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1197 buffers
->enabled_mask
&= ~(1u << slot
);
1200 descs
->dirty_mask
|= 1u << slot
;
1201 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1204 void si_set_rw_buffer(struct si_context
*sctx
,
1205 uint slot
, const struct pipe_constant_buffer
*input
)
1207 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
,
1208 SI_DESCS_RW_BUFFERS
, slot
, input
);
1211 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
,
1212 enum pipe_shader_type shader
, uint slot
,
1213 const struct pipe_constant_buffer
*input
)
1215 struct si_context
*sctx
= (struct si_context
*)ctx
;
1217 if (shader
>= SI_NUM_SHADERS
)
1220 slot
= si_get_constbuf_slot(slot
);
1221 si_set_constant_buffer(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1222 si_const_and_shader_buffer_descriptors_idx(shader
),
1226 void si_get_pipe_constant_buffer(struct si_context
*sctx
, uint shader
,
1227 uint slot
, struct pipe_constant_buffer
*cbuf
)
1229 cbuf
->user_buffer
= NULL
;
1230 si_get_buffer_from_descriptors(
1231 &sctx
->const_and_shader_buffers
[shader
],
1232 si_const_and_shader_buffer_descriptors(sctx
, shader
),
1233 si_get_constbuf_slot(slot
),
1234 &cbuf
->buffer
, &cbuf
->buffer_offset
, &cbuf
->buffer_size
);
1237 /* SHADER BUFFERS */
1239 static void si_set_shader_buffers(struct pipe_context
*ctx
,
1240 enum pipe_shader_type shader
,
1241 unsigned start_slot
, unsigned count
,
1242 const struct pipe_shader_buffer
*sbuffers
)
1244 struct si_context
*sctx
= (struct si_context
*)ctx
;
1245 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1246 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1249 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1251 for (i
= 0; i
< count
; ++i
) {
1252 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1253 struct r600_resource
*buf
;
1254 unsigned slot
= si_get_shaderbuf_slot(start_slot
+ i
);
1255 uint32_t *desc
= descs
->list
+ slot
* 4;
1258 if (!sbuffer
|| !sbuffer
->buffer
) {
1259 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1260 memset(desc
, 0, sizeof(uint32_t) * 4);
1261 buffers
->enabled_mask
&= ~(1u << slot
);
1262 descs
->dirty_mask
|= 1u << slot
;
1263 sctx
->descriptors_dirty
|=
1264 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1268 buf
= (struct r600_resource
*)sbuffer
->buffer
;
1269 va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1272 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1274 desc
[2] = sbuffer
->buffer_size
;
1275 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1276 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1277 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1278 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1279 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1280 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1282 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1283 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
, buf
,
1284 buffers
->shader_usage
,
1285 buffers
->priority
, true);
1286 buf
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1288 buffers
->enabled_mask
|= 1u << slot
;
1289 descs
->dirty_mask
|= 1u << slot
;
1290 sctx
->descriptors_dirty
|=
1291 1u << si_const_and_shader_buffer_descriptors_idx(shader
);
1293 util_range_add(&buf
->valid_buffer_range
, sbuffer
->buffer_offset
,
1294 sbuffer
->buffer_offset
+ sbuffer
->buffer_size
);
1298 void si_get_shader_buffers(struct si_context
*sctx
,
1299 enum pipe_shader_type shader
,
1300 uint start_slot
, uint count
,
1301 struct pipe_shader_buffer
*sbuf
)
1303 struct si_buffer_resources
*buffers
= &sctx
->const_and_shader_buffers
[shader
];
1304 struct si_descriptors
*descs
= si_const_and_shader_buffer_descriptors(sctx
, shader
);
1306 for (unsigned i
= 0; i
< count
; ++i
) {
1307 si_get_buffer_from_descriptors(
1309 si_get_shaderbuf_slot(start_slot
+ i
),
1310 &sbuf
[i
].buffer
, &sbuf
[i
].buffer_offset
,
1311 &sbuf
[i
].buffer_size
);
1317 void si_set_ring_buffer(struct pipe_context
*ctx
, uint slot
,
1318 struct pipe_resource
*buffer
,
1319 unsigned stride
, unsigned num_records
,
1320 bool add_tid
, bool swizzle
,
1321 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1323 struct si_context
*sctx
= (struct si_context
*)ctx
;
1324 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1325 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1327 /* The stride field in the resource descriptor has 14 bits */
1328 assert(stride
< (1 << 14));
1330 assert(slot
< descs
->num_elements
);
1331 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1336 va
= r600_resource(buffer
)->gpu_address
+ offset
;
1338 switch (element_size
) {
1340 assert(!"Unsupported ring buffer element size");
1356 switch (index_stride
) {
1358 assert(!"Unsupported ring buffer index stride");
1374 if (sctx
->b
.chip_class
>= VI
&& stride
)
1375 num_records
*= stride
;
1377 /* Set the descriptor. */
1378 uint32_t *desc
= descs
->list
+ slot
*4;
1380 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1381 S_008F04_STRIDE(stride
) |
1382 S_008F04_SWIZZLE_ENABLE(swizzle
);
1383 desc
[2] = num_records
;
1384 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1385 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1386 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1387 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1388 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1389 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1390 S_008F0C_INDEX_STRIDE(index_stride
) |
1391 S_008F0C_ADD_TID_ENABLE(add_tid
);
1393 if (sctx
->b
.chip_class
>= GFX9
)
1394 assert(!swizzle
|| element_size
== 1); /* always 4 bytes on GFX9 */
1396 desc
[3] |= S_008F0C_ELEMENT_SIZE(element_size
);
1398 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1399 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1400 (struct r600_resource
*)buffer
,
1401 buffers
->shader_usage
, buffers
->priority
);
1402 buffers
->enabled_mask
|= 1u << slot
;
1404 /* Clear the descriptor. */
1405 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1406 buffers
->enabled_mask
&= ~(1u << slot
);
1409 descs
->dirty_mask
|= 1u << slot
;
1410 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1413 /* STREAMOUT BUFFERS */
1415 static void si_set_streamout_targets(struct pipe_context
*ctx
,
1416 unsigned num_targets
,
1417 struct pipe_stream_output_target
**targets
,
1418 const unsigned *offsets
)
1420 struct si_context
*sctx
= (struct si_context
*)ctx
;
1421 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1422 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1423 unsigned old_num_targets
= sctx
->b
.streamout
.num_targets
;
1426 /* We are going to unbind the buffers. Mark which caches need to be flushed. */
1427 if (sctx
->b
.streamout
.num_targets
&& sctx
->b
.streamout
.begin_emitted
) {
1428 /* Since streamout uses vector writes which go through TC L2
1429 * and most other clients can use TC L2 as well, we don't need
1432 * The only cases which requires flushing it is VGT DMA index
1433 * fetching (on <= CIK) and indirect draw data, which are rare
1434 * cases. Thus, flag the TC L2 dirtiness in the resource and
1435 * handle it at draw call time.
1437 for (i
= 0; i
< sctx
->b
.streamout
.num_targets
; i
++)
1438 if (sctx
->b
.streamout
.targets
[i
])
1439 r600_resource(sctx
->b
.streamout
.targets
[i
]->b
.buffer
)->TC_L2_dirty
= true;
1441 /* Invalidate the scalar cache in case a streamout buffer is
1442 * going to be used as a constant buffer.
1444 * Invalidate TC L1, because streamout bypasses it (done by
1445 * setting GLC=1 in the store instruction), but it can contain
1446 * outdated data of streamout buffers.
1448 * VS_PARTIAL_FLUSH is required if the buffers are going to be
1449 * used as an input immediately.
1451 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
|
1452 SI_CONTEXT_INV_VMEM_L1
|
1453 SI_CONTEXT_VS_PARTIAL_FLUSH
;
1456 /* All readers of the streamout targets need to be finished before we can
1457 * start writing to the targets.
1460 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
1461 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1463 /* Streamout buffers must be bound in 2 places:
1464 * 1) in VGT by setting the VGT_STRMOUT registers
1465 * 2) as shader resources
1468 /* Set the VGT regs. */
1469 r600_set_streamout_targets(ctx
, num_targets
, targets
, offsets
);
1471 /* Set the shader resources.*/
1472 for (i
= 0; i
< num_targets
; i
++) {
1473 bufidx
= SI_VS_STREAMOUT_BUF0
+ i
;
1476 struct pipe_resource
*buffer
= targets
[i
]->buffer
;
1477 uint64_t va
= r600_resource(buffer
)->gpu_address
;
1479 /* Set the descriptor.
1481 * On VI, the format must be non-INVALID, otherwise
1482 * the buffer will be considered not bound and store
1483 * instructions will be no-ops.
1485 uint32_t *desc
= descs
->list
+ bufidx
*4;
1487 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
1488 desc
[2] = 0xffffffff;
1489 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1490 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1491 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1492 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1493 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1495 /* Set the resource. */
1496 pipe_resource_reference(&buffers
->buffers
[bufidx
],
1498 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1499 (struct r600_resource
*)buffer
,
1500 buffers
->shader_usage
,
1501 RADEON_PRIO_SHADER_RW_BUFFER
,
1503 r600_resource(buffer
)->bind_history
|= PIPE_BIND_STREAM_OUTPUT
;
1505 buffers
->enabled_mask
|= 1u << bufidx
;
1507 /* Clear the descriptor and unset the resource. */
1508 memset(descs
->list
+ bufidx
*4, 0,
1509 sizeof(uint32_t) * 4);
1510 pipe_resource_reference(&buffers
->buffers
[bufidx
],
1512 buffers
->enabled_mask
&= ~(1u << bufidx
);
1514 descs
->dirty_mask
|= 1u << bufidx
;
1516 for (; i
< old_num_targets
; i
++) {
1517 bufidx
= SI_VS_STREAMOUT_BUF0
+ i
;
1518 /* Clear the descriptor and unset the resource. */
1519 memset(descs
->list
+ bufidx
*4, 0, sizeof(uint32_t) * 4);
1520 pipe_resource_reference(&buffers
->buffers
[bufidx
], NULL
);
1521 buffers
->enabled_mask
&= ~(1u << bufidx
);
1522 descs
->dirty_mask
|= 1u << bufidx
;
1525 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1528 static void si_desc_reset_buffer_offset(struct pipe_context
*ctx
,
1529 uint32_t *desc
, uint64_t old_buf_va
,
1530 struct pipe_resource
*new_buf
)
1532 /* Retrieve the buffer offset from the descriptor. */
1533 uint64_t old_desc_va
=
1534 desc
[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
1536 assert(old_buf_va
<= old_desc_va
);
1537 uint64_t offset_within_buffer
= old_desc_va
- old_buf_va
;
1539 /* Update the descriptor. */
1540 si_set_buf_desc_address(r600_resource(new_buf
), offset_within_buffer
,
1544 /* INTERNAL CONST BUFFERS */
1546 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
1547 const struct pipe_poly_stipple
*state
)
1549 struct si_context
*sctx
= (struct si_context
*)ctx
;
1550 struct pipe_constant_buffer cb
= {};
1551 unsigned stipple
[32];
1554 for (i
= 0; i
< 32; i
++)
1555 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1557 cb
.user_buffer
= stipple
;
1558 cb
.buffer_size
= sizeof(stipple
);
1560 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1563 /* TEXTURE METADATA ENABLE/DISABLE */
1565 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1566 * while the texture is bound, possibly by a different context. In that case,
1567 * call this function to update compressed_colortex_masks.
1569 void si_update_compressed_colortex_masks(struct si_context
*sctx
)
1571 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1572 si_samplers_update_compressed_colortex_mask(&sctx
->samplers
[i
]);
1573 si_images_update_compressed_colortex_mask(&sctx
->images
[i
]);
1574 si_update_compressed_tex_shader_mask(sctx
, i
);
1578 /* BUFFER DISCARD/INVALIDATION */
1580 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1581 static void si_reset_buffer_resources(struct si_context
*sctx
,
1582 struct si_buffer_resources
*buffers
,
1583 unsigned descriptors_idx
,
1585 struct pipe_resource
*buf
,
1587 enum radeon_bo_usage usage
,
1588 enum radeon_bo_priority priority
)
1590 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1591 unsigned mask
= buffers
->enabled_mask
& slot_mask
;
1594 unsigned i
= u_bit_scan(&mask
);
1595 if (buffers
->buffers
[i
] == buf
) {
1596 si_desc_reset_buffer_offset(&sctx
->b
.b
,
1599 descs
->dirty_mask
|= 1u << i
;
1600 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1602 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1603 (struct r600_resource
*)buf
,
1604 usage
, priority
, true);
1609 static void si_rebind_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
,
1612 struct si_context
*sctx
= (struct si_context
*)ctx
;
1613 struct r600_resource
*rbuffer
= r600_resource(buf
);
1615 unsigned num_elems
= sctx
->vertex_elements
?
1616 sctx
->vertex_elements
->count
: 0;
1618 /* We changed the buffer, now we need to bind it where the old one
1619 * was bound. This consists of 2 things:
1620 * 1) Updating the resource descriptor and dirtying it.
1621 * 2) Adding a relocation to the CS, so that it's usable.
1624 /* Vertex buffers. */
1625 if (rbuffer
->bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
1626 for (i
= 0; i
< num_elems
; i
++) {
1627 int vb
= sctx
->vertex_elements
->elements
[i
].vertex_buffer_index
;
1629 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1631 if (!sctx
->vertex_buffer
[vb
].buffer
.resource
)
1634 if (sctx
->vertex_buffer
[vb
].buffer
.resource
== buf
) {
1635 sctx
->vertex_buffers_dirty
= true;
1641 /* Streamout buffers. (other internal buffers can't be invalidated) */
1642 if (rbuffer
->bind_history
& PIPE_BIND_STREAM_OUTPUT
) {
1643 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1644 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1645 struct si_descriptors
*descs
=
1646 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1648 if (buffers
->buffers
[i
] != buf
)
1651 si_desc_reset_buffer_offset(ctx
, descs
->list
+ i
*4,
1653 descs
->dirty_mask
|= 1u << i
;
1654 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1656 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1657 rbuffer
, buffers
->shader_usage
,
1658 RADEON_PRIO_SHADER_RW_BUFFER
,
1661 /* Update the streamout state. */
1662 if (sctx
->b
.streamout
.begin_emitted
)
1663 r600_emit_streamout_end(&sctx
->b
);
1664 sctx
->b
.streamout
.append_bitmask
=
1665 sctx
->b
.streamout
.enabled_mask
;
1666 r600_streamout_buffers_dirty(&sctx
->b
);
1670 /* Constant and shader buffers. */
1671 if (rbuffer
->bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
1672 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1673 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1674 si_const_and_shader_buffer_descriptors_idx(shader
),
1675 u_bit_consecutive(SI_NUM_SHADER_BUFFERS
, SI_NUM_CONST_BUFFERS
),
1677 sctx
->const_and_shader_buffers
[shader
].shader_usage_constbuf
,
1678 sctx
->const_and_shader_buffers
[shader
].priority_constbuf
);
1681 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_BUFFER
) {
1682 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++)
1683 si_reset_buffer_resources(sctx
, &sctx
->const_and_shader_buffers
[shader
],
1684 si_const_and_shader_buffer_descriptors_idx(shader
),
1685 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
),
1687 sctx
->const_and_shader_buffers
[shader
].shader_usage
,
1688 sctx
->const_and_shader_buffers
[shader
].priority
);
1691 if (rbuffer
->bind_history
& PIPE_BIND_SAMPLER_VIEW
) {
1692 /* Texture buffers - update bindings. */
1693 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1694 struct si_sampler_views
*views
= &sctx
->samplers
[shader
].views
;
1695 struct si_descriptors
*descs
=
1696 si_sampler_and_image_descriptors(sctx
, shader
);
1697 unsigned mask
= views
->enabled_mask
;
1700 unsigned i
= u_bit_scan(&mask
);
1701 if (views
->views
[i
]->texture
== buf
) {
1702 unsigned desc_slot
= si_get_sampler_slot(i
);
1704 si_desc_reset_buffer_offset(ctx
,
1708 descs
->dirty_mask
|= 1ull << desc_slot
;
1709 sctx
->descriptors_dirty
|=
1710 1u << si_sampler_and_image_descriptors_idx(shader
);
1712 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1713 rbuffer
, RADEON_USAGE_READ
,
1714 RADEON_PRIO_SAMPLER_BUFFER
,
1722 if (rbuffer
->bind_history
& PIPE_BIND_SHADER_IMAGE
) {
1723 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1724 struct si_images_info
*images
= &sctx
->images
[shader
];
1725 struct si_descriptors
*descs
=
1726 si_sampler_and_image_descriptors(sctx
, shader
);
1727 unsigned mask
= images
->enabled_mask
;
1730 unsigned i
= u_bit_scan(&mask
);
1732 if (images
->views
[i
].resource
== buf
) {
1733 unsigned desc_slot
= si_get_image_slot(i
);
1735 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1736 si_mark_image_range_valid(&images
->views
[i
]);
1738 si_desc_reset_buffer_offset(
1739 ctx
, descs
->list
+ desc_slot
* 8 + 4,
1741 /* two 8-byte images share one 16-byte slot */
1742 descs
->dirty_mask
|= 1u << (desc_slot
/ 2);
1743 sctx
->descriptors_dirty
|=
1744 1u << si_sampler_and_image_descriptors_idx(shader
);
1746 radeon_add_to_buffer_list_check_mem(
1747 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1748 RADEON_USAGE_READWRITE
,
1749 RADEON_PRIO_SAMPLER_BUFFER
, true);
1756 /* Reallocate a buffer a update all resource bindings where the buffer is
1759 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
1760 * idle by discarding its contents. Apps usually tell us when to do this using
1761 * map_buffer flags, for example.
1763 static void si_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
1765 struct si_context
*sctx
= (struct si_context
*)ctx
;
1766 struct r600_resource
*rbuffer
= r600_resource(buf
);
1767 uint64_t old_va
= rbuffer
->gpu_address
;
1769 /* Reallocate the buffer in the same pipe_resource. */
1770 r600_alloc_resource(&sctx
->screen
->b
, rbuffer
);
1772 si_rebind_buffer(ctx
, buf
, old_va
);
1775 /* Update mutable image descriptor fields of all bound textures. */
1776 void si_update_all_texture_descriptors(struct si_context
*sctx
)
1780 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1781 struct si_sampler_views
*samplers
= &sctx
->samplers
[shader
].views
;
1782 struct si_images_info
*images
= &sctx
->images
[shader
];
1786 mask
= images
->enabled_mask
;
1788 unsigned i
= u_bit_scan(&mask
);
1789 struct pipe_image_view
*view
= &images
->views
[i
];
1791 if (!view
->resource
||
1792 view
->resource
->target
== PIPE_BUFFER
)
1795 si_set_shader_image(sctx
, shader
, i
, view
, true);
1798 /* Sampler views. */
1799 mask
= samplers
->enabled_mask
;
1801 unsigned i
= u_bit_scan(&mask
);
1802 struct pipe_sampler_view
*view
= samplers
->views
[i
];
1806 view
->texture
->target
== PIPE_BUFFER
)
1809 si_set_sampler_view(sctx
, shader
, i
,
1810 samplers
->views
[i
], true);
1813 si_update_compressed_tex_shader_mask(sctx
, shader
);
1817 /* SHADER USER DATA */
1819 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
,
1822 sctx
->shader_pointers_dirty
|=
1823 u_bit_consecutive(SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
,
1824 SI_NUM_SHADER_DESCS
);
1826 if (shader
== PIPE_SHADER_VERTEX
)
1827 sctx
->vertex_buffer_pointer_dirty
= sctx
->vertex_buffers
.buffer
!= NULL
;
1829 si_mark_atom_dirty(sctx
, &sctx
->shader_userdata
.atom
);
1832 static void si_shader_userdata_begin_new_cs(struct si_context
*sctx
)
1834 sctx
->shader_pointers_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
1835 sctx
->vertex_buffer_pointer_dirty
= sctx
->vertex_buffers
.buffer
!= NULL
;
1836 si_mark_atom_dirty(sctx
, &sctx
->shader_userdata
.atom
);
1839 /* Set a base register address for user data constants in the given shader.
1840 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1842 static void si_set_user_data_base(struct si_context
*sctx
,
1843 unsigned shader
, uint32_t new_base
)
1845 uint32_t *base
= &sctx
->shader_userdata
.sh_base
[shader
];
1847 if (*base
!= new_base
) {
1851 si_mark_shader_pointers_dirty(sctx
, shader
);
1853 if (shader
== PIPE_SHADER_VERTEX
)
1854 sctx
->last_vs_state
= ~0;
1859 /* This must be called when these shaders are changed from non-NULL to NULL
1862 * - tessellation control shader
1863 * - tessellation evaluation shader
1865 void si_shader_change_notify(struct si_context
*sctx
)
1867 /* VS can be bound as VS, ES, or LS. */
1868 if (sctx
->tes_shader
.cso
) {
1869 if (sctx
->b
.chip_class
>= GFX9
) {
1870 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1871 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
1873 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1874 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
1876 } else if (sctx
->gs_shader
.cso
) {
1877 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1878 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1880 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1881 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1884 /* TES can be bound as ES, VS, or not bound. */
1885 if (sctx
->tes_shader
.cso
) {
1886 if (sctx
->gs_shader
.cso
)
1887 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
1888 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1890 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
1891 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1893 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
1897 static void si_emit_shader_pointer(struct si_context
*sctx
,
1898 struct si_descriptors
*desc
,
1901 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1904 assert(desc
->buffer
);
1906 va
= desc
->buffer
->gpu_address
+
1907 desc
->buffer_offset
;
1909 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, 2, 0));
1910 radeon_emit(cs
, (sh_base
+ desc
->shader_userdata_offset
- SI_SH_REG_OFFSET
) >> 2);
1911 radeon_emit(cs
, va
);
1912 radeon_emit(cs
, va
>> 32);
1915 void si_emit_graphics_shader_userdata(struct si_context
*sctx
,
1916 struct r600_atom
*atom
)
1919 uint32_t *sh_base
= sctx
->shader_userdata
.sh_base
;
1920 struct si_descriptors
*descs
;
1922 descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1924 if (sctx
->shader_pointers_dirty
& (1 << SI_DESCS_RW_BUFFERS
)) {
1925 si_emit_shader_pointer(sctx
, descs
,
1926 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
1927 si_emit_shader_pointer(sctx
, descs
,
1928 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1930 if (sctx
->b
.chip_class
>= GFX9
) {
1931 /* GFX9 merged LS-HS and ES-GS.
1932 * Set RW_BUFFERS in the special registers, so that
1933 * it's preloaded into s[0:1] instead of s[8:9].
1935 si_emit_shader_pointer(sctx
, descs
,
1936 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
);
1937 si_emit_shader_pointer(sctx
, descs
,
1938 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
);
1940 si_emit_shader_pointer(sctx
, descs
,
1941 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
1942 si_emit_shader_pointer(sctx
, descs
,
1943 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1944 si_emit_shader_pointer(sctx
, descs
,
1945 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
1949 mask
= sctx
->shader_pointers_dirty
&
1950 u_bit_consecutive(SI_DESCS_FIRST_SHADER
,
1951 SI_DESCS_FIRST_COMPUTE
- SI_DESCS_FIRST_SHADER
);
1954 unsigned i
= u_bit_scan(&mask
);
1955 unsigned shader
= (i
- SI_DESCS_FIRST_SHADER
) / SI_NUM_SHADER_DESCS
;
1956 unsigned base
= sh_base
[shader
];
1959 si_emit_shader_pointer(sctx
, descs
+ i
, base
);
1961 sctx
->shader_pointers_dirty
&=
1962 ~u_bit_consecutive(SI_DESCS_RW_BUFFERS
, SI_DESCS_FIRST_COMPUTE
);
1964 if (sctx
->vertex_buffer_pointer_dirty
) {
1965 si_emit_shader_pointer(sctx
, &sctx
->vertex_buffers
,
1966 sh_base
[PIPE_SHADER_VERTEX
]);
1967 sctx
->vertex_buffer_pointer_dirty
= false;
1971 void si_emit_compute_shader_userdata(struct si_context
*sctx
)
1973 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
1974 struct si_descriptors
*descs
= sctx
->descriptors
;
1975 unsigned compute_mask
=
1976 u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
, SI_NUM_SHADER_DESCS
);
1977 unsigned mask
= sctx
->shader_pointers_dirty
& compute_mask
;
1980 unsigned i
= u_bit_scan(&mask
);
1982 si_emit_shader_pointer(sctx
, descs
+ i
, base
);
1984 sctx
->shader_pointers_dirty
&= ~compute_mask
;
1987 /* INIT/DEINIT/UPLOAD */
1989 void si_init_all_descriptors(struct si_context
*sctx
)
1992 unsigned ce_offset
= 0;
1994 STATIC_ASSERT(GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS
% 2 == 0);
1995 STATIC_ASSERT(GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS
% 2 == 0);
1997 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
1998 bool gfx9_tcs
= sctx
->b
.chip_class
== GFX9
&&
1999 i
== PIPE_SHADER_TESS_CTRL
;
2000 bool gfx9_gs
= sctx
->b
.chip_class
== GFX9
&&
2001 i
== PIPE_SHADER_GEOMETRY
;
2002 /* GFX9 has only 4KB of CE, while previous chips had 32KB.
2003 * Rarely used descriptors don't use CE RAM.
2005 bool big_ce
= sctx
->b
.chip_class
<= VI
;
2006 bool const_and_shaderbufs_use_ce
= big_ce
||
2007 i
== PIPE_SHADER_VERTEX
||
2008 i
== PIPE_SHADER_FRAGMENT
;
2009 bool samplers_and_images_use_ce
= big_ce
||
2010 i
== PIPE_SHADER_FRAGMENT
;
2012 si_init_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2013 si_const_and_shader_buffer_descriptors(sctx
, i
),
2014 SI_NUM_SHADER_BUFFERS
+ SI_NUM_CONST_BUFFERS
,
2015 gfx9_tcs
? GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS
:
2016 gfx9_gs
? GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS
:
2017 SI_SGPR_CONST_AND_SHADER_BUFFERS
,
2018 RADEON_USAGE_READWRITE
,
2020 RADEON_PRIO_SHADER_RW_BUFFER
,
2021 RADEON_PRIO_CONST_BUFFER
,
2022 const_and_shaderbufs_use_ce
? &ce_offset
: NULL
);
2024 struct si_descriptors
*desc
= si_sampler_and_image_descriptors(sctx
, i
);
2025 si_init_descriptors(desc
,
2026 gfx9_tcs
? GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES
:
2027 gfx9_gs
? GFX9_SGPR_GS_SAMPLERS_AND_IMAGES
:
2028 SI_SGPR_SAMPLERS_AND_IMAGES
,
2029 16, SI_NUM_IMAGES
/ 2 + SI_NUM_SAMPLERS
,
2030 samplers_and_images_use_ce
? &ce_offset
: NULL
);
2033 for (j
= 0; j
< SI_NUM_IMAGES
; j
++)
2034 memcpy(desc
->list
+ j
* 8, null_image_descriptor
, 8 * 4);
2035 for (; j
< SI_NUM_IMAGES
+ SI_NUM_SAMPLERS
* 2; j
++)
2036 memcpy(desc
->list
+ j
* 8, null_texture_descriptor
, 8 * 4);
2039 si_init_buffer_resources(&sctx
->rw_buffers
,
2040 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
2041 SI_NUM_RW_BUFFERS
, SI_SGPR_RW_BUFFERS
,
2042 /* The second set of usage/priority is used by
2043 * const buffers in RW buffer slots. */
2044 RADEON_USAGE_READWRITE
, RADEON_USAGE_READ
,
2045 RADEON_PRIO_SHADER_RINGS
, RADEON_PRIO_CONST_BUFFER
,
2047 si_init_descriptors(&sctx
->vertex_buffers
, SI_SGPR_VERTEX_BUFFERS
,
2048 4, SI_NUM_VERTEX_BUFFERS
, NULL
);
2050 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
2052 if (sctx
->b
.chip_class
>= GFX9
)
2053 assert(ce_offset
<= 4096);
2055 assert(ce_offset
<= 32768);
2057 /* Set pipe_context functions. */
2058 sctx
->b
.b
.bind_sampler_states
= si_bind_sampler_states
;
2059 sctx
->b
.b
.set_shader_images
= si_set_shader_images
;
2060 sctx
->b
.b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
2061 sctx
->b
.b
.set_polygon_stipple
= si_set_polygon_stipple
;
2062 sctx
->b
.b
.set_shader_buffers
= si_set_shader_buffers
;
2063 sctx
->b
.b
.set_sampler_views
= si_set_sampler_views
;
2064 sctx
->b
.b
.set_stream_output_targets
= si_set_streamout_targets
;
2065 sctx
->b
.invalidate_buffer
= si_invalidate_buffer
;
2066 sctx
->b
.rebind_buffer
= si_rebind_buffer
;
2068 /* Shader user data. */
2069 si_init_atom(sctx
, &sctx
->shader_userdata
.atom
, &sctx
->atoms
.s
.shader_userdata
,
2070 si_emit_graphics_shader_userdata
);
2072 /* Set default and immutable mappings. */
2073 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2075 if (sctx
->b
.chip_class
>= GFX9
) {
2076 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2077 R_00B430_SPI_SHADER_USER_DATA_LS_0
);
2078 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2079 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2081 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
,
2082 R_00B430_SPI_SHADER_USER_DATA_HS_0
);
2083 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
,
2084 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2086 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2089 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
2091 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
2092 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2094 /* Assume nothing will go wrong: */
2095 sctx
->shader_pointers_dirty
|= dirty
;
2098 unsigned i
= u_bit_scan(&dirty
);
2100 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
],
2101 &sctx
->shader_userdata
.atom
))
2105 sctx
->descriptors_dirty
&= ~mask
;
2109 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
2111 /* Does not update rw_buffers as that is not needed for compute shaders
2112 * and the input buffer is using the same SGPR's anyway.
2114 const unsigned mask
= u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
,
2115 SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
2116 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
2118 /* Assume nothing will go wrong: */
2119 sctx
->shader_pointers_dirty
|= dirty
;
2122 unsigned i
= u_bit_scan(&dirty
);
2124 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
], NULL
))
2128 sctx
->descriptors_dirty
&= ~mask
;
2133 void si_release_all_descriptors(struct si_context
*sctx
)
2137 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2138 si_release_buffer_resources(&sctx
->const_and_shader_buffers
[i
],
2139 si_const_and_shader_buffer_descriptors(sctx
, i
));
2140 si_release_sampler_views(&sctx
->samplers
[i
].views
);
2141 si_release_image_views(&sctx
->images
[i
]);
2143 si_release_buffer_resources(&sctx
->rw_buffers
,
2144 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
2146 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2147 si_release_descriptors(&sctx
->descriptors
[i
]);
2148 si_release_descriptors(&sctx
->vertex_buffers
);
2151 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
2155 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
2156 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_and_shader_buffers
[i
]);
2157 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
].views
);
2158 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
2160 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
2161 si_vertex_buffers_begin_new_cs(sctx
);
2163 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
2164 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
2166 si_shader_userdata_begin_new_cs(sctx
);