2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Marek Olšák <marek.olsak@amd.com>
27 /* Resource binding slots and sampler states (each described with 8 or
28 * 4 dwords) are stored in lists in memory which is accessed by shaders
29 * using scalar load instructions.
31 * This file is responsible for managing such lists. It keeps a copy of all
32 * descriptors in CPU memory and re-uploads a whole list if some slots have
35 * This code is also reponsible for updating shader pointers to those lists.
37 * Note that CP DMA can't be used for updating the lists, because a GPU hang
38 * could leave the list in a mid-IB state and the next IB would get wrong
39 * descriptors and the whole context would be unusable at that point.
40 * (Note: The register shadowing can't be used due to the same reason)
42 * Also, uploading descriptors to newly allocated memory doesn't require
46 * Possible scenarios for one 16 dword image+sampler slot:
48 * | Image | w/ FMASK | Buffer | NULL
49 * [ 0: 3] Image[0:3] | Image[0:3] | Null[0:3] | Null[0:3]
50 * [ 4: 7] Image[4:7] | Image[4:7] | Buffer[0:3] | 0
51 * [ 8:11] Null[0:3] | Fmask[0:3] | Null[0:3] | Null[0:3]
52 * [12:15] Sampler[0:3] | Fmask[4:7] | Sampler[0:3] | Sampler[0:3]
54 * FMASK implies MSAA, therefore no sampler state.
55 * Sampler states are never unbound except when FMASK is bound.
58 #include "radeon/r600_cs.h"
60 #include "si_shader.h"
63 #include "util/u_format.h"
64 #include "util/u_math.h"
65 #include "util/u_memory.h"
66 #include "util/u_suballoc.h"
67 #include "util/u_upload_mgr.h"
70 /* NULL image and buffer descriptor for textures (alpha = 1) and images
73 * For images, all fields must be zero except for the swizzle, which
74 * supports arbitrary combinations of 0s and 1s. The texture type must be
75 * any valid type (e.g. 1D). If the texture type isn't set, the hw hangs.
77 * For buffers, all fields must be zero. If they are not, the hw hangs.
79 * This is the only reason why the buffer descriptor must be in words [4:7].
81 static uint32_t null_texture_descriptor
[8] = {
85 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1
) |
86 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
87 /* the rest must contain zeros, which is also used by the buffer
91 static uint32_t null_image_descriptor
[8] = {
95 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
)
96 /* the rest must contain zeros, which is also used by the buffer
100 static void si_init_descriptors(struct si_descriptors
*desc
,
101 unsigned shader_userdata_index
,
102 unsigned element_dw_size
,
103 unsigned num_elements
,
104 const uint32_t *null_descriptor
,
109 assert(num_elements
<= sizeof(desc
->dirty_mask
)*8);
111 desc
->list
= CALLOC(num_elements
, element_dw_size
* 4);
112 desc
->element_dw_size
= element_dw_size
;
113 desc
->num_elements
= num_elements
;
114 desc
->dirty_mask
= num_elements
== 32 ? ~0u : (1u << num_elements
) - 1;
115 desc
->shader_userdata_offset
= shader_userdata_index
* 4;
118 desc
->ce_offset
= *ce_offset
;
120 /* make sure that ce_offset stays 32 byte aligned */
121 *ce_offset
+= align(element_dw_size
* num_elements
* 4, 32);
124 /* Initialize the array to NULL descriptors if the element size is 8. */
125 if (null_descriptor
) {
126 assert(element_dw_size
% 8 == 0);
127 for (i
= 0; i
< num_elements
* element_dw_size
/ 8; i
++)
128 memcpy(desc
->list
+ i
* 8, null_descriptor
,
133 static void si_release_descriptors(struct si_descriptors
*desc
)
135 r600_resource_reference(&desc
->buffer
, NULL
);
139 static bool si_ce_upload(struct si_context
*sctx
, unsigned ce_offset
, unsigned size
,
140 unsigned *out_offset
, struct r600_resource
**out_buf
) {
143 u_suballocator_alloc(sctx
->ce_suballocator
, size
, 64, out_offset
,
144 (struct pipe_resource
**)out_buf
);
148 va
= (*out_buf
)->gpu_address
+ *out_offset
;
150 radeon_emit(sctx
->ce_ib
, PKT3(PKT3_DUMP_CONST_RAM
, 3, 0));
151 radeon_emit(sctx
->ce_ib
, ce_offset
);
152 radeon_emit(sctx
->ce_ib
, size
/ 4);
153 radeon_emit(sctx
->ce_ib
, va
);
154 radeon_emit(sctx
->ce_ib
, va
>> 32);
156 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, *out_buf
,
157 RADEON_USAGE_READWRITE
, RADEON_PRIO_DESCRIPTORS
);
159 sctx
->ce_need_synchronization
= true;
163 static void si_ce_reinitialize_descriptors(struct si_context
*sctx
,
164 struct si_descriptors
*desc
)
167 struct r600_resource
*buffer
= (struct r600_resource
*)desc
->buffer
;
168 unsigned list_size
= desc
->num_elements
* desc
->element_dw_size
* 4;
169 uint64_t va
= buffer
->gpu_address
+ desc
->buffer_offset
;
170 struct radeon_winsys_cs
*ib
= sctx
->ce_preamble_ib
;
175 list_size
= align(list_size
, 32);
177 radeon_emit(ib
, PKT3(PKT3_LOAD_CONST_RAM
, 3, 0));
179 radeon_emit(ib
, va
>> 32);
180 radeon_emit(ib
, list_size
/ 4);
181 radeon_emit(ib
, desc
->ce_offset
);
183 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
184 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
186 desc
->ce_ram_dirty
= false;
189 void si_ce_reinitialize_all_descriptors(struct si_context
*sctx
)
193 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
194 si_ce_reinitialize_descriptors(sctx
, &sctx
->descriptors
[i
]);
197 void si_ce_enable_loads(struct radeon_winsys_cs
*ib
)
199 radeon_emit(ib
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
200 radeon_emit(ib
, CONTEXT_CONTROL_LOAD_ENABLE(1) |
201 CONTEXT_CONTROL_LOAD_CE_RAM(1));
202 radeon_emit(ib
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
205 static bool si_upload_descriptors(struct si_context
*sctx
,
206 struct si_descriptors
*desc
,
207 struct r600_atom
* atom
)
209 unsigned list_size
= desc
->num_elements
* desc
->element_dw_size
* 4;
211 if (!desc
->dirty_mask
)
215 uint32_t const* list
= (uint32_t const*)desc
->list
;
217 if (desc
->ce_ram_dirty
)
218 si_ce_reinitialize_descriptors(sctx
, desc
);
220 while(desc
->dirty_mask
) {
222 u_bit_scan_consecutive_range(&desc
->dirty_mask
, &begin
,
225 begin
*= desc
->element_dw_size
;
226 count
*= desc
->element_dw_size
;
228 radeon_emit(sctx
->ce_ib
,
229 PKT3(PKT3_WRITE_CONST_RAM
, count
, 0));
230 radeon_emit(sctx
->ce_ib
, desc
->ce_offset
+ begin
* 4);
231 radeon_emit_array(sctx
->ce_ib
, list
+ begin
, count
);
234 if (!si_ce_upload(sctx
, desc
->ce_offset
, list_size
,
235 &desc
->buffer_offset
, &desc
->buffer
))
240 u_upload_alloc(sctx
->b
.uploader
, 0, list_size
, 256,
241 &desc
->buffer_offset
,
242 (struct pipe_resource
**)&desc
->buffer
, &ptr
);
244 return false; /* skip the draw call */
246 util_memcpy_cpu_to_le32(ptr
, desc
->list
, list_size
);
248 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
249 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
251 desc
->pointer_dirty
= true;
252 desc
->dirty_mask
= 0;
255 si_mark_atom_dirty(sctx
, atom
);
261 si_descriptors_begin_new_cs(struct si_context
*sctx
, struct si_descriptors
*desc
)
263 desc
->ce_ram_dirty
= true;
268 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, desc
->buffer
,
269 RADEON_USAGE_READ
, RADEON_PRIO_DESCRIPTORS
);
275 si_sampler_descriptors_idx(unsigned shader
)
277 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
278 SI_SHADER_DESCS_SAMPLERS
;
281 static struct si_descriptors
*
282 si_sampler_descriptors(struct si_context
*sctx
, unsigned shader
)
284 return &sctx
->descriptors
[si_sampler_descriptors_idx(shader
)];
287 static void si_release_sampler_views(struct si_sampler_views
*views
)
291 for (i
= 0; i
< ARRAY_SIZE(views
->views
); i
++) {
292 pipe_sampler_view_reference(&views
->views
[i
], NULL
);
296 static void si_sampler_view_add_buffer(struct si_context
*sctx
,
297 struct pipe_resource
*resource
,
298 enum radeon_bo_usage usage
,
299 bool is_stencil_sampler
,
302 struct r600_resource
*rres
;
303 struct r600_texture
*rtex
;
304 enum radeon_bo_priority priority
;
309 if (resource
->target
!= PIPE_BUFFER
) {
310 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
312 if (tex
->is_depth
&& !r600_can_sample_zs(tex
, is_stencil_sampler
))
313 resource
= &tex
->flushed_depth_texture
->resource
.b
.b
;
316 rres
= (struct r600_resource
*)resource
;
317 priority
= r600_get_sampler_view_priority(rres
);
319 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
320 rres
, usage
, priority
,
323 if (resource
->target
== PIPE_BUFFER
)
326 /* Now add separate DCC if it's present. */
327 rtex
= (struct r600_texture
*)resource
;
328 if (!rtex
->dcc_separate_buffer
)
331 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
332 rtex
->dcc_separate_buffer
, usage
,
333 RADEON_PRIO_DCC
, check_mem
);
336 static void si_sampler_views_begin_new_cs(struct si_context
*sctx
,
337 struct si_sampler_views
*views
)
339 unsigned mask
= views
->enabled_mask
;
341 /* Add buffers to the CS. */
343 int i
= u_bit_scan(&mask
);
344 struct si_sampler_view
*sview
= (struct si_sampler_view
*)views
->views
[i
];
346 si_sampler_view_add_buffer(sctx
, sview
->base
.texture
,
348 sview
->is_stencil_sampler
, false);
352 /* Set texture descriptor fields that can be changed by reallocations.
355 * \param base_level_info information of the level of BASE_ADDRESS
356 * \param base_level the level of BASE_ADDRESS
357 * \param first_level pipe_sampler_view.u.tex.first_level
358 * \param block_width util_format_get_blockwidth()
359 * \param is_stencil select between separate Z & Stencil
360 * \param state descriptor to update
362 void si_set_mutable_tex_desc_fields(struct r600_texture
*tex
,
363 const struct radeon_surf_level
*base_level_info
,
364 unsigned base_level
, unsigned first_level
,
365 unsigned block_width
, bool is_stencil
,
369 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
371 if (tex
->is_depth
&& !r600_can_sample_zs(tex
, is_stencil
)) {
372 tex
= tex
->flushed_depth_texture
;
376 va
= tex
->resource
.gpu_address
+ base_level_info
->offset
;
378 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
379 state
[3] &= C_008F1C_TILING_INDEX
;
380 state
[4] &= C_008F20_PITCH
;
381 state
[6] &= C_008F28_COMPRESSION_EN
;
384 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
385 state
[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(tex
, base_level
,
387 state
[4] |= S_008F20_PITCH(pitch
- 1);
389 if (tex
->dcc_offset
&& tex
->surface
.level
[first_level
].dcc_enabled
) {
390 state
[6] |= S_008F28_COMPRESSION_EN(1);
391 state
[7] = ((!tex
->dcc_separate_buffer
? tex
->resource
.gpu_address
: 0) +
393 base_level_info
->dcc_offset
) >> 8;
397 static void si_set_sampler_view(struct si_context
*sctx
,
399 unsigned slot
, struct pipe_sampler_view
*view
,
400 bool disallow_early_out
)
402 struct si_sampler_views
*views
= &sctx
->samplers
[shader
].views
;
403 struct si_sampler_view
*rview
= (struct si_sampler_view
*)view
;
404 struct si_descriptors
*descs
= si_sampler_descriptors(sctx
, shader
);
406 if (views
->views
[slot
] == view
&& !disallow_early_out
)
410 struct r600_texture
*rtex
= (struct r600_texture
*)view
->texture
;
411 uint32_t *desc
= descs
->list
+ slot
* 16;
413 pipe_sampler_view_reference(&views
->views
[slot
], view
);
414 memcpy(desc
, rview
->state
, 8*4);
416 if (view
->texture
&& view
->texture
->target
!= PIPE_BUFFER
) {
417 bool is_separate_stencil
=
418 rtex
->db_compatible
&&
419 rview
->is_stencil_sampler
;
421 si_set_mutable_tex_desc_fields(rtex
,
422 rview
->base_level_info
,
424 rview
->base
.u
.tex
.first_level
,
430 if (view
->texture
&& view
->texture
->target
!= PIPE_BUFFER
&&
433 rview
->fmask_state
, 8*4);
435 /* Disable FMASK and bind sampler state in [12:15]. */
437 null_texture_descriptor
, 4*4);
439 if (views
->sampler_states
[slot
])
441 views
->sampler_states
[slot
], 4*4);
444 views
->enabled_mask
|= 1u << slot
;
446 /* Since this can flush, it must be done after enabled_mask is
448 si_sampler_view_add_buffer(sctx
, view
->texture
,
450 rview
->is_stencil_sampler
, true);
452 pipe_sampler_view_reference(&views
->views
[slot
], NULL
);
453 memcpy(descs
->list
+ slot
*16, null_texture_descriptor
, 8*4);
454 /* Only clear the lower dwords of FMASK. */
455 memcpy(descs
->list
+ slot
*16 + 8, null_texture_descriptor
, 4*4);
456 views
->enabled_mask
&= ~(1u << slot
);
459 descs
->dirty_mask
|= 1u << slot
;
460 sctx
->descriptors_dirty
|= 1u << si_sampler_descriptors_idx(shader
);
463 static bool is_compressed_colortex(struct r600_texture
*rtex
)
465 return rtex
->cmask
.size
|| rtex
->fmask
.size
||
466 (rtex
->dcc_offset
&& rtex
->dirty_level_mask
);
469 static void si_set_sampler_views(struct pipe_context
*ctx
,
470 enum pipe_shader_type shader
, unsigned start
,
472 struct pipe_sampler_view
**views
)
474 struct si_context
*sctx
= (struct si_context
*)ctx
;
475 struct si_textures_info
*samplers
= &sctx
->samplers
[shader
];
478 if (!count
|| shader
>= SI_NUM_SHADERS
)
481 for (i
= 0; i
< count
; i
++) {
482 unsigned slot
= start
+ i
;
484 if (!views
|| !views
[i
]) {
485 samplers
->depth_texture_mask
&= ~(1u << slot
);
486 samplers
->compressed_colortex_mask
&= ~(1u << slot
);
487 si_set_sampler_view(sctx
, shader
, slot
, NULL
, false);
491 si_set_sampler_view(sctx
, shader
, slot
, views
[i
], false);
493 if (views
[i
]->texture
&& views
[i
]->texture
->target
!= PIPE_BUFFER
) {
494 struct r600_texture
*rtex
=
495 (struct r600_texture
*)views
[i
]->texture
;
497 if (rtex
->db_compatible
) {
498 samplers
->depth_texture_mask
|= 1u << slot
;
500 samplers
->depth_texture_mask
&= ~(1u << slot
);
502 if (is_compressed_colortex(rtex
)) {
503 samplers
->compressed_colortex_mask
|= 1u << slot
;
505 samplers
->compressed_colortex_mask
&= ~(1u << slot
);
508 if (rtex
->dcc_offset
&&
509 p_atomic_read(&rtex
->framebuffers_bound
))
510 sctx
->need_check_render_feedback
= true;
512 samplers
->depth_texture_mask
&= ~(1u << slot
);
513 samplers
->compressed_colortex_mask
&= ~(1u << slot
);
519 si_samplers_update_compressed_colortex_mask(struct si_textures_info
*samplers
)
521 unsigned mask
= samplers
->views
.enabled_mask
;
524 int i
= u_bit_scan(&mask
);
525 struct pipe_resource
*res
= samplers
->views
.views
[i
]->texture
;
527 if (res
&& res
->target
!= PIPE_BUFFER
) {
528 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
530 if (is_compressed_colortex(rtex
)) {
531 samplers
->compressed_colortex_mask
|= 1u << i
;
533 samplers
->compressed_colortex_mask
&= ~(1u << i
);
542 si_image_descriptors_idx(unsigned shader
)
544 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
545 SI_SHADER_DESCS_IMAGES
;
548 static struct si_descriptors
*
549 si_image_descriptors(struct si_context
*sctx
, unsigned shader
)
551 return &sctx
->descriptors
[si_image_descriptors_idx(shader
)];
555 si_release_image_views(struct si_images_info
*images
)
559 for (i
= 0; i
< SI_NUM_IMAGES
; ++i
) {
560 struct pipe_image_view
*view
= &images
->views
[i
];
562 pipe_resource_reference(&view
->resource
, NULL
);
567 si_image_views_begin_new_cs(struct si_context
*sctx
, struct si_images_info
*images
)
569 uint mask
= images
->enabled_mask
;
571 /* Add buffers to the CS. */
573 int i
= u_bit_scan(&mask
);
574 struct pipe_image_view
*view
= &images
->views
[i
];
576 assert(view
->resource
);
578 si_sampler_view_add_buffer(sctx
, view
->resource
,
579 RADEON_USAGE_READWRITE
, false, false);
584 si_disable_shader_image(struct si_context
*ctx
, unsigned shader
, unsigned slot
)
586 struct si_images_info
*images
= &ctx
->images
[shader
];
588 if (images
->enabled_mask
& (1u << slot
)) {
589 struct si_descriptors
*descs
= si_image_descriptors(ctx
, shader
);
591 pipe_resource_reference(&images
->views
[slot
].resource
, NULL
);
592 images
->compressed_colortex_mask
&= ~(1 << slot
);
594 memcpy(descs
->list
+ slot
*8, null_image_descriptor
, 8*4);
595 images
->enabled_mask
&= ~(1u << slot
);
596 descs
->dirty_mask
|= 1u << slot
;
597 ctx
->descriptors_dirty
|= 1u << si_image_descriptors_idx(shader
);
602 si_mark_image_range_valid(const struct pipe_image_view
*view
)
604 struct r600_resource
*res
= (struct r600_resource
*)view
->resource
;
606 assert(res
&& res
->b
.b
.target
== PIPE_BUFFER
);
608 util_range_add(&res
->valid_buffer_range
,
610 view
->u
.buf
.offset
+ view
->u
.buf
.size
);
613 static void si_set_shader_image(struct si_context
*ctx
,
615 unsigned slot
, const struct pipe_image_view
*view
)
617 struct si_screen
*screen
= ctx
->screen
;
618 struct si_images_info
*images
= &ctx
->images
[shader
];
619 struct si_descriptors
*descs
= si_image_descriptors(ctx
, shader
);
620 struct r600_resource
*res
;
622 if (!view
|| !view
->resource
) {
623 si_disable_shader_image(ctx
, shader
, slot
);
627 res
= (struct r600_resource
*)view
->resource
;
629 if (&images
->views
[slot
] != view
)
630 util_copy_image_view(&images
->views
[slot
], view
);
632 if (res
->b
.b
.target
== PIPE_BUFFER
) {
633 if (view
->access
& PIPE_IMAGE_ACCESS_WRITE
)
634 si_mark_image_range_valid(view
);
636 si_make_buffer_descriptor(screen
, res
,
640 descs
->list
+ slot
* 8);
641 images
->compressed_colortex_mask
&= ~(1 << slot
);
643 static const unsigned char swizzle
[4] = { 0, 1, 2, 3 };
644 struct r600_texture
*tex
= (struct r600_texture
*)res
;
645 unsigned level
= view
->u
.tex
.level
;
646 unsigned width
, height
, depth
;
647 uint32_t *desc
= descs
->list
+ slot
* 8;
648 bool uses_dcc
= tex
->dcc_offset
&&
649 tex
->surface
.level
[level
].dcc_enabled
;
651 assert(!tex
->is_depth
);
652 assert(tex
->fmask
.size
== 0);
655 (view
->access
& PIPE_IMAGE_ACCESS_WRITE
||
656 !vi_dcc_formats_compatible(res
->b
.b
.format
, view
->format
))) {
657 /* If DCC can't be disabled, at least decompress it.
658 * The decompression is relatively cheap if the surface
659 * has been decompressed already.
661 if (r600_texture_disable_dcc(&ctx
->b
, tex
))
664 ctx
->b
.decompress_dcc(&ctx
->b
.b
, tex
);
667 if (is_compressed_colortex(tex
)) {
668 images
->compressed_colortex_mask
|= 1 << slot
;
670 images
->compressed_colortex_mask
&= ~(1 << slot
);
674 p_atomic_read(&tex
->framebuffers_bound
))
675 ctx
->need_check_render_feedback
= true;
677 /* Always force the base level to the selected level.
679 * This is required for 3D textures, where otherwise
680 * selecting a single slice for non-layered bindings
681 * fails. It doesn't hurt the other targets.
683 width
= u_minify(res
->b
.b
.width0
, level
);
684 height
= u_minify(res
->b
.b
.height0
, level
);
685 depth
= u_minify(res
->b
.b
.depth0
, level
);
687 si_make_texture_descriptor(screen
, tex
,
688 false, res
->b
.b
.target
,
689 view
->format
, swizzle
,
691 view
->u
.tex
.first_layer
,
692 view
->u
.tex
.last_layer
,
693 width
, height
, depth
,
695 si_set_mutable_tex_desc_fields(tex
, &tex
->surface
.level
[level
],
697 util_format_get_blockwidth(view
->format
),
701 images
->enabled_mask
|= 1u << slot
;
702 descs
->dirty_mask
|= 1u << slot
;
703 ctx
->descriptors_dirty
|= 1u << si_image_descriptors_idx(shader
);
705 /* Since this can flush, it must be done after enabled_mask is updated. */
706 si_sampler_view_add_buffer(ctx
, &res
->b
.b
,
707 RADEON_USAGE_READWRITE
, false, true);
711 si_set_shader_images(struct pipe_context
*pipe
,
712 enum pipe_shader_type shader
,
713 unsigned start_slot
, unsigned count
,
714 const struct pipe_image_view
*views
)
716 struct si_context
*ctx
= (struct si_context
*)pipe
;
719 assert(shader
< SI_NUM_SHADERS
);
724 assert(start_slot
+ count
<= SI_NUM_IMAGES
);
727 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
728 si_set_shader_image(ctx
, shader
, slot
, &views
[i
]);
730 for (i
= 0, slot
= start_slot
; i
< count
; ++i
, ++slot
)
731 si_set_shader_image(ctx
, shader
, slot
, NULL
);
736 si_images_update_compressed_colortex_mask(struct si_images_info
*images
)
738 unsigned mask
= images
->enabled_mask
;
741 int i
= u_bit_scan(&mask
);
742 struct pipe_resource
*res
= images
->views
[i
].resource
;
744 if (res
&& res
->target
!= PIPE_BUFFER
) {
745 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
747 if (is_compressed_colortex(rtex
)) {
748 images
->compressed_colortex_mask
|= 1 << i
;
750 images
->compressed_colortex_mask
&= ~(1 << i
);
758 static void si_bind_sampler_states(struct pipe_context
*ctx
,
759 enum pipe_shader_type shader
,
760 unsigned start
, unsigned count
, void **states
)
762 struct si_context
*sctx
= (struct si_context
*)ctx
;
763 struct si_textures_info
*samplers
= &sctx
->samplers
[shader
];
764 struct si_descriptors
*desc
= si_sampler_descriptors(sctx
, shader
);
765 struct si_sampler_state
**sstates
= (struct si_sampler_state
**)states
;
768 if (!count
|| shader
>= SI_NUM_SHADERS
)
771 for (i
= 0; i
< count
; i
++) {
772 unsigned slot
= start
+ i
;
775 sstates
[i
] == samplers
->views
.sampler_states
[slot
])
778 samplers
->views
.sampler_states
[slot
] = sstates
[i
];
780 /* If FMASK is bound, don't overwrite it.
781 * The sampler state will be set after FMASK is unbound.
783 if (samplers
->views
.views
[i
] &&
784 samplers
->views
.views
[i
]->texture
&&
785 samplers
->views
.views
[i
]->texture
->target
!= PIPE_BUFFER
&&
786 ((struct r600_texture
*)samplers
->views
.views
[i
]->texture
)->fmask
.size
)
789 memcpy(desc
->list
+ slot
* 16 + 12, sstates
[i
]->val
, 4*4);
790 desc
->dirty_mask
|= 1u << slot
;
791 sctx
->descriptors_dirty
|= 1u << si_sampler_descriptors_idx(shader
);
795 /* BUFFER RESOURCES */
797 static void si_init_buffer_resources(struct si_buffer_resources
*buffers
,
798 struct si_descriptors
*descs
,
799 unsigned num_buffers
,
800 unsigned shader_userdata_index
,
801 enum radeon_bo_usage shader_usage
,
802 enum radeon_bo_priority priority
,
805 buffers
->shader_usage
= shader_usage
;
806 buffers
->priority
= priority
;
807 buffers
->buffers
= CALLOC(num_buffers
, sizeof(struct pipe_resource
*));
809 si_init_descriptors(descs
, shader_userdata_index
, 4,
810 num_buffers
, NULL
, ce_offset
);
813 static void si_release_buffer_resources(struct si_buffer_resources
*buffers
,
814 struct si_descriptors
*descs
)
818 for (i
= 0; i
< descs
->num_elements
; i
++) {
819 pipe_resource_reference(&buffers
->buffers
[i
], NULL
);
822 FREE(buffers
->buffers
);
825 static void si_buffer_resources_begin_new_cs(struct si_context
*sctx
,
826 struct si_buffer_resources
*buffers
)
828 unsigned mask
= buffers
->enabled_mask
;
830 /* Add buffers to the CS. */
832 int i
= u_bit_scan(&mask
);
834 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
835 (struct r600_resource
*)buffers
->buffers
[i
],
836 buffers
->shader_usage
, buffers
->priority
);
842 static void si_vertex_buffers_begin_new_cs(struct si_context
*sctx
)
844 struct si_descriptors
*desc
= &sctx
->vertex_buffers
;
845 int count
= sctx
->vertex_elements
? sctx
->vertex_elements
->count
: 0;
848 for (i
= 0; i
< count
; i
++) {
849 int vb
= sctx
->vertex_elements
->elements
[i
].vertex_buffer_index
;
851 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
853 if (!sctx
->vertex_buffer
[vb
].buffer
)
856 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
857 (struct r600_resource
*)sctx
->vertex_buffer
[vb
].buffer
,
858 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
863 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
864 desc
->buffer
, RADEON_USAGE_READ
,
865 RADEON_PRIO_DESCRIPTORS
);
868 bool si_upload_vertex_buffer_descriptors(struct si_context
*sctx
)
870 struct si_descriptors
*desc
= &sctx
->vertex_buffers
;
871 bool bound
[SI_NUM_VERTEX_BUFFERS
] = {};
872 unsigned i
, count
= sctx
->vertex_elements
->count
;
876 if (!sctx
->vertex_buffers_dirty
)
878 if (!count
|| !sctx
->vertex_elements
)
881 /* Vertex buffer descriptors are the only ones which are uploaded
882 * directly through a staging buffer and don't go through
883 * the fine-grained upload path.
885 u_upload_alloc(sctx
->b
.uploader
, 0, count
* 16, 256, &desc
->buffer_offset
,
886 (struct pipe_resource
**)&desc
->buffer
, (void**)&ptr
);
890 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
891 desc
->buffer
, RADEON_USAGE_READ
,
892 RADEON_PRIO_DESCRIPTORS
);
894 assert(count
<= SI_NUM_VERTEX_BUFFERS
);
896 for (i
= 0; i
< count
; i
++) {
897 struct pipe_vertex_element
*ve
= &sctx
->vertex_elements
->elements
[i
];
898 struct pipe_vertex_buffer
*vb
;
899 struct r600_resource
*rbuffer
;
901 uint32_t *desc
= &ptr
[i
*4];
903 if (ve
->vertex_buffer_index
>= ARRAY_SIZE(sctx
->vertex_buffer
)) {
908 vb
= &sctx
->vertex_buffer
[ve
->vertex_buffer_index
];
909 rbuffer
= (struct r600_resource
*)vb
->buffer
;
915 offset
= vb
->buffer_offset
+ ve
->src_offset
;
916 va
= rbuffer
->gpu_address
+ offset
;
918 /* Fill in T# buffer resource description */
920 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
921 S_008F04_STRIDE(vb
->stride
);
923 if (sctx
->b
.chip_class
<= CIK
&& vb
->stride
)
924 /* Round up by rounding down and adding 1 */
925 desc
[2] = (vb
->buffer
->width0
- offset
-
926 sctx
->vertex_elements
->format_size
[i
]) /
929 desc
[2] = vb
->buffer
->width0
- offset
;
931 desc
[3] = sctx
->vertex_elements
->rsrc_word3
[i
];
933 if (!bound
[ve
->vertex_buffer_index
]) {
934 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
935 (struct r600_resource
*)vb
->buffer
,
936 RADEON_USAGE_READ
, RADEON_PRIO_VERTEX_BUFFER
);
937 bound
[ve
->vertex_buffer_index
] = true;
941 /* Don't flush the const cache. It would have a very negative effect
942 * on performance (confirmed by testing). New descriptors are always
943 * uploaded to a fresh new buffer, so I don't think flushing the const
944 * cache is needed. */
945 desc
->pointer_dirty
= true;
946 si_mark_atom_dirty(sctx
, &sctx
->shader_userdata
.atom
);
947 sctx
->vertex_buffers_dirty
= false;
952 /* CONSTANT BUFFERS */
955 si_const_buffer_descriptors_idx(unsigned shader
)
957 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
958 SI_SHADER_DESCS_CONST_BUFFERS
;
961 static struct si_descriptors
*
962 si_const_buffer_descriptors(struct si_context
*sctx
, unsigned shader
)
964 return &sctx
->descriptors
[si_const_buffer_descriptors_idx(shader
)];
967 void si_upload_const_buffer(struct si_context
*sctx
, struct r600_resource
**rbuffer
,
968 const uint8_t *ptr
, unsigned size
, uint32_t *const_offset
)
972 u_upload_alloc(sctx
->b
.uploader
, 0, size
, 256, const_offset
,
973 (struct pipe_resource
**)rbuffer
, &tmp
);
975 util_memcpy_cpu_to_le32(tmp
, ptr
, size
);
978 static void si_set_constant_buffer(struct si_context
*sctx
,
979 struct si_buffer_resources
*buffers
,
980 unsigned descriptors_idx
,
981 uint slot
, const struct pipe_constant_buffer
*input
)
983 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
984 assert(slot
< descs
->num_elements
);
985 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
987 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
988 * with a NULL buffer). We need to use a dummy buffer instead. */
989 if (sctx
->b
.chip_class
== CIK
&&
990 (!input
|| (!input
->buffer
&& !input
->user_buffer
)))
991 input
= &sctx
->null_const_buf
;
993 if (input
&& (input
->buffer
|| input
->user_buffer
)) {
994 struct pipe_resource
*buffer
= NULL
;
997 /* Upload the user buffer if needed. */
998 if (input
->user_buffer
) {
999 unsigned buffer_offset
;
1001 si_upload_const_buffer(sctx
,
1002 (struct r600_resource
**)&buffer
, input
->user_buffer
,
1003 input
->buffer_size
, &buffer_offset
);
1005 /* Just unbind on failure. */
1006 si_set_constant_buffer(sctx
, buffers
, descriptors_idx
, slot
, NULL
);
1009 va
= r600_resource(buffer
)->gpu_address
+ buffer_offset
;
1011 pipe_resource_reference(&buffer
, input
->buffer
);
1012 va
= r600_resource(buffer
)->gpu_address
+ input
->buffer_offset
;
1015 /* Set the descriptor. */
1016 uint32_t *desc
= descs
->list
+ slot
*4;
1018 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1020 desc
[2] = input
->buffer_size
;
1021 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1022 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1023 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1024 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1025 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1026 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1028 buffers
->buffers
[slot
] = buffer
;
1029 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1030 (struct r600_resource
*)buffer
,
1031 buffers
->shader_usage
,
1032 buffers
->priority
, true);
1033 buffers
->enabled_mask
|= 1u << slot
;
1035 /* Clear the descriptor. */
1036 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1037 buffers
->enabled_mask
&= ~(1u << slot
);
1040 descs
->dirty_mask
|= 1u << slot
;
1041 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1044 void si_set_rw_buffer(struct si_context
*sctx
,
1045 uint slot
, const struct pipe_constant_buffer
*input
)
1047 si_set_constant_buffer(sctx
, &sctx
->rw_buffers
,
1048 SI_DESCS_RW_BUFFERS
, slot
, input
);
1051 static void si_pipe_set_constant_buffer(struct pipe_context
*ctx
,
1052 uint shader
, uint slot
,
1053 const struct pipe_constant_buffer
*input
)
1055 struct si_context
*sctx
= (struct si_context
*)ctx
;
1057 if (shader
>= SI_NUM_SHADERS
)
1060 si_set_constant_buffer(sctx
, &sctx
->const_buffers
[shader
],
1061 si_const_buffer_descriptors_idx(shader
),
1065 /* SHADER BUFFERS */
1068 si_shader_buffer_descriptors_idx(enum pipe_shader_type shader
)
1070 return SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
+
1071 SI_SHADER_DESCS_SHADER_BUFFERS
;
1074 static struct si_descriptors
*
1075 si_shader_buffer_descriptors(struct si_context
*sctx
,
1076 enum pipe_shader_type shader
)
1078 return &sctx
->descriptors
[si_shader_buffer_descriptors_idx(shader
)];
1081 static void si_set_shader_buffers(struct pipe_context
*ctx
,
1082 enum pipe_shader_type shader
,
1083 unsigned start_slot
, unsigned count
,
1084 const struct pipe_shader_buffer
*sbuffers
)
1086 struct si_context
*sctx
= (struct si_context
*)ctx
;
1087 struct si_buffer_resources
*buffers
= &sctx
->shader_buffers
[shader
];
1088 struct si_descriptors
*descs
= si_shader_buffer_descriptors(sctx
, shader
);
1091 assert(start_slot
+ count
<= SI_NUM_SHADER_BUFFERS
);
1093 for (i
= 0; i
< count
; ++i
) {
1094 const struct pipe_shader_buffer
*sbuffer
= sbuffers
? &sbuffers
[i
] : NULL
;
1095 struct r600_resource
*buf
;
1096 unsigned slot
= start_slot
+ i
;
1097 uint32_t *desc
= descs
->list
+ slot
* 4;
1100 if (!sbuffer
|| !sbuffer
->buffer
) {
1101 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1102 memset(desc
, 0, sizeof(uint32_t) * 4);
1103 buffers
->enabled_mask
&= ~(1u << slot
);
1104 descs
->dirty_mask
|= 1u << slot
;
1105 sctx
->descriptors_dirty
|=
1106 1u << si_shader_buffer_descriptors_idx(shader
);
1110 buf
= (struct r600_resource
*)sbuffer
->buffer
;
1111 va
= buf
->gpu_address
+ sbuffer
->buffer_offset
;
1114 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1116 desc
[2] = sbuffer
->buffer_size
;
1117 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1118 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1119 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1120 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1121 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1122 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1124 pipe_resource_reference(&buffers
->buffers
[slot
], &buf
->b
.b
);
1125 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
, buf
,
1126 buffers
->shader_usage
,
1127 buffers
->priority
, true);
1128 buffers
->enabled_mask
|= 1u << slot
;
1129 descs
->dirty_mask
|= 1u << slot
;
1130 sctx
->descriptors_dirty
|=
1131 1u << si_shader_buffer_descriptors_idx(shader
);
1137 void si_set_ring_buffer(struct pipe_context
*ctx
, uint slot
,
1138 struct pipe_resource
*buffer
,
1139 unsigned stride
, unsigned num_records
,
1140 bool add_tid
, bool swizzle
,
1141 unsigned element_size
, unsigned index_stride
, uint64_t offset
)
1143 struct si_context
*sctx
= (struct si_context
*)ctx
;
1144 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1145 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1147 /* The stride field in the resource descriptor has 14 bits */
1148 assert(stride
< (1 << 14));
1150 assert(slot
< descs
->num_elements
);
1151 pipe_resource_reference(&buffers
->buffers
[slot
], NULL
);
1156 va
= r600_resource(buffer
)->gpu_address
+ offset
;
1158 switch (element_size
) {
1160 assert(!"Unsupported ring buffer element size");
1176 switch (index_stride
) {
1178 assert(!"Unsupported ring buffer index stride");
1194 if (sctx
->b
.chip_class
>= VI
&& stride
)
1195 num_records
*= stride
;
1197 /* Set the descriptor. */
1198 uint32_t *desc
= descs
->list
+ slot
*4;
1200 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
1201 S_008F04_STRIDE(stride
) |
1202 S_008F04_SWIZZLE_ENABLE(swizzle
);
1203 desc
[2] = num_records
;
1204 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1205 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1206 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1207 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1208 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1209 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1210 S_008F0C_ELEMENT_SIZE(element_size
) |
1211 S_008F0C_INDEX_STRIDE(index_stride
) |
1212 S_008F0C_ADD_TID_ENABLE(add_tid
);
1214 pipe_resource_reference(&buffers
->buffers
[slot
], buffer
);
1215 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
1216 (struct r600_resource
*)buffer
,
1217 buffers
->shader_usage
, buffers
->priority
);
1218 buffers
->enabled_mask
|= 1u << slot
;
1220 /* Clear the descriptor. */
1221 memset(descs
->list
+ slot
*4, 0, sizeof(uint32_t) * 4);
1222 buffers
->enabled_mask
&= ~(1u << slot
);
1225 descs
->dirty_mask
|= 1u << slot
;
1226 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1229 /* STREAMOUT BUFFERS */
1231 static void si_set_streamout_targets(struct pipe_context
*ctx
,
1232 unsigned num_targets
,
1233 struct pipe_stream_output_target
**targets
,
1234 const unsigned *offsets
)
1236 struct si_context
*sctx
= (struct si_context
*)ctx
;
1237 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1238 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1239 unsigned old_num_targets
= sctx
->b
.streamout
.num_targets
;
1242 /* We are going to unbind the buffers. Mark which caches need to be flushed. */
1243 if (sctx
->b
.streamout
.num_targets
&& sctx
->b
.streamout
.begin_emitted
) {
1244 /* Since streamout uses vector writes which go through TC L2
1245 * and most other clients can use TC L2 as well, we don't need
1248 * The only cases which requires flushing it is VGT DMA index
1249 * fetching (on <= CIK) and indirect draw data, which are rare
1250 * cases. Thus, flag the TC L2 dirtiness in the resource and
1251 * handle it at draw call time.
1253 for (i
= 0; i
< sctx
->b
.streamout
.num_targets
; i
++)
1254 if (sctx
->b
.streamout
.targets
[i
])
1255 r600_resource(sctx
->b
.streamout
.targets
[i
]->b
.buffer
)->TC_L2_dirty
= true;
1257 /* Invalidate the scalar cache in case a streamout buffer is
1258 * going to be used as a constant buffer.
1260 * Invalidate TC L1, because streamout bypasses it (done by
1261 * setting GLC=1 in the store instruction), but it can contain
1262 * outdated data of streamout buffers.
1264 * VS_PARTIAL_FLUSH is required if the buffers are going to be
1265 * used as an input immediately.
1267 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
|
1268 SI_CONTEXT_INV_VMEM_L1
|
1269 SI_CONTEXT_VS_PARTIAL_FLUSH
;
1272 /* All readers of the streamout targets need to be finished before we can
1273 * start writing to the targets.
1276 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
1277 SI_CONTEXT_CS_PARTIAL_FLUSH
;
1279 /* Streamout buffers must be bound in 2 places:
1280 * 1) in VGT by setting the VGT_STRMOUT registers
1281 * 2) as shader resources
1284 /* Set the VGT regs. */
1285 r600_set_streamout_targets(ctx
, num_targets
, targets
, offsets
);
1287 /* Set the shader resources.*/
1288 for (i
= 0; i
< num_targets
; i
++) {
1289 bufidx
= SI_VS_STREAMOUT_BUF0
+ i
;
1292 struct pipe_resource
*buffer
= targets
[i
]->buffer
;
1293 uint64_t va
= r600_resource(buffer
)->gpu_address
;
1295 /* Set the descriptor.
1297 * On VI, the format must be non-INVALID, otherwise
1298 * the buffer will be considered not bound and store
1299 * instructions will be no-ops.
1301 uint32_t *desc
= descs
->list
+ bufidx
*4;
1303 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
1304 desc
[2] = 0xffffffff;
1305 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1306 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1307 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1308 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1309 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1311 /* Set the resource. */
1312 pipe_resource_reference(&buffers
->buffers
[bufidx
],
1314 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1315 (struct r600_resource
*)buffer
,
1316 buffers
->shader_usage
,
1317 RADEON_PRIO_SHADER_RW_BUFFER
,
1319 buffers
->enabled_mask
|= 1u << bufidx
;
1321 /* Clear the descriptor and unset the resource. */
1322 memset(descs
->list
+ bufidx
*4, 0,
1323 sizeof(uint32_t) * 4);
1324 pipe_resource_reference(&buffers
->buffers
[bufidx
],
1326 buffers
->enabled_mask
&= ~(1u << bufidx
);
1328 descs
->dirty_mask
|= 1u << bufidx
;
1330 for (; i
< old_num_targets
; i
++) {
1331 bufidx
= SI_VS_STREAMOUT_BUF0
+ i
;
1332 /* Clear the descriptor and unset the resource. */
1333 memset(descs
->list
+ bufidx
*4, 0, sizeof(uint32_t) * 4);
1334 pipe_resource_reference(&buffers
->buffers
[bufidx
], NULL
);
1335 buffers
->enabled_mask
&= ~(1u << bufidx
);
1336 descs
->dirty_mask
|= 1u << bufidx
;
1339 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1342 static void si_desc_reset_buffer_offset(struct pipe_context
*ctx
,
1343 uint32_t *desc
, uint64_t old_buf_va
,
1344 struct pipe_resource
*new_buf
)
1346 /* Retrieve the buffer offset from the descriptor. */
1347 uint64_t old_desc_va
=
1348 desc
[0] | ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc
[1]) << 32);
1350 assert(old_buf_va
<= old_desc_va
);
1351 uint64_t offset_within_buffer
= old_desc_va
- old_buf_va
;
1353 /* Update the descriptor. */
1354 uint64_t va
= r600_resource(new_buf
)->gpu_address
+ offset_within_buffer
;
1357 desc
[1] = (desc
[1] & C_008F04_BASE_ADDRESS_HI
) |
1358 S_008F04_BASE_ADDRESS_HI(va
>> 32);
1361 /* INTERNAL CONST BUFFERS */
1363 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
1364 const struct pipe_poly_stipple
*state
)
1366 struct si_context
*sctx
= (struct si_context
*)ctx
;
1367 struct pipe_constant_buffer cb
= {};
1368 unsigned stipple
[32];
1371 for (i
= 0; i
< 32; i
++)
1372 stipple
[i
] = util_bitreverse(state
->stipple
[i
]);
1374 cb
.user_buffer
= stipple
;
1375 cb
.buffer_size
= sizeof(stipple
);
1377 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
, &cb
);
1380 /* TEXTURE METADATA ENABLE/DISABLE */
1382 /* CMASK can be enabled (for fast clear) and disabled (for texture export)
1383 * while the texture is bound, possibly by a different context. In that case,
1384 * call this function to update compressed_colortex_masks.
1386 void si_update_compressed_colortex_masks(struct si_context
*sctx
)
1388 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
1389 si_samplers_update_compressed_colortex_mask(&sctx
->samplers
[i
]);
1390 si_images_update_compressed_colortex_mask(&sctx
->images
[i
]);
1394 /* BUFFER DISCARD/INVALIDATION */
1396 /** Reset descriptors of buffer resources after \p buf has been invalidated. */
1397 static void si_reset_buffer_resources(struct si_context
*sctx
,
1398 struct si_buffer_resources
*buffers
,
1399 unsigned descriptors_idx
,
1400 struct pipe_resource
*buf
,
1403 struct si_descriptors
*descs
= &sctx
->descriptors
[descriptors_idx
];
1404 unsigned mask
= buffers
->enabled_mask
;
1407 unsigned i
= u_bit_scan(&mask
);
1408 if (buffers
->buffers
[i
] == buf
) {
1409 si_desc_reset_buffer_offset(&sctx
->b
.b
,
1412 descs
->dirty_mask
|= 1u << i
;
1413 sctx
->descriptors_dirty
|= 1u << descriptors_idx
;
1415 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1416 (struct r600_resource
*)buf
,
1417 buffers
->shader_usage
,
1418 buffers
->priority
, true);
1423 /* Reallocate a buffer a update all resource bindings where the buffer is
1426 * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
1427 * idle by discarding its contents. Apps usually tell us when to do this using
1428 * map_buffer flags, for example.
1430 static void si_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
1432 struct si_context
*sctx
= (struct si_context
*)ctx
;
1433 struct r600_resource
*rbuffer
= r600_resource(buf
);
1435 uint64_t old_va
= rbuffer
->gpu_address
;
1436 unsigned num_elems
= sctx
->vertex_elements
?
1437 sctx
->vertex_elements
->count
: 0;
1438 struct si_sampler_view
*view
;
1440 /* Reallocate the buffer in the same pipe_resource. */
1441 r600_alloc_resource(&sctx
->screen
->b
, rbuffer
);
1443 /* We changed the buffer, now we need to bind it where the old one
1444 * was bound. This consists of 2 things:
1445 * 1) Updating the resource descriptor and dirtying it.
1446 * 2) Adding a relocation to the CS, so that it's usable.
1449 /* Vertex buffers. */
1450 for (i
= 0; i
< num_elems
; i
++) {
1451 int vb
= sctx
->vertex_elements
->elements
[i
].vertex_buffer_index
;
1453 if (vb
>= ARRAY_SIZE(sctx
->vertex_buffer
))
1455 if (!sctx
->vertex_buffer
[vb
].buffer
)
1458 if (sctx
->vertex_buffer
[vb
].buffer
== buf
) {
1459 sctx
->vertex_buffers_dirty
= true;
1464 /* Streamout buffers. (other internal buffers can't be invalidated) */
1465 for (i
= SI_VS_STREAMOUT_BUF0
; i
<= SI_VS_STREAMOUT_BUF3
; i
++) {
1466 struct si_buffer_resources
*buffers
= &sctx
->rw_buffers
;
1467 struct si_descriptors
*descs
=
1468 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1470 if (buffers
->buffers
[i
] != buf
)
1473 si_desc_reset_buffer_offset(ctx
, descs
->list
+ i
*4,
1475 descs
->dirty_mask
|= 1u << i
;
1476 sctx
->descriptors_dirty
|= 1u << SI_DESCS_RW_BUFFERS
;
1478 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1479 rbuffer
, buffers
->shader_usage
,
1480 RADEON_PRIO_SHADER_RW_BUFFER
,
1483 /* Update the streamout state. */
1484 if (sctx
->b
.streamout
.begin_emitted
)
1485 r600_emit_streamout_end(&sctx
->b
);
1486 sctx
->b
.streamout
.append_bitmask
=
1487 sctx
->b
.streamout
.enabled_mask
;
1488 r600_streamout_buffers_dirty(&sctx
->b
);
1491 /* Constant and shader buffers. */
1492 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1493 si_reset_buffer_resources(sctx
, &sctx
->const_buffers
[shader
],
1494 si_const_buffer_descriptors_idx(shader
),
1496 si_reset_buffer_resources(sctx
, &sctx
->shader_buffers
[shader
],
1497 si_shader_buffer_descriptors_idx(shader
),
1501 /* Texture buffers - update virtual addresses in sampler view descriptors. */
1502 LIST_FOR_EACH_ENTRY(view
, &sctx
->b
.texture_buffers
, list
) {
1503 if (view
->base
.texture
== buf
) {
1504 si_desc_reset_buffer_offset(ctx
, &view
->state
[4], old_va
, buf
);
1507 /* Texture buffers - update bindings. */
1508 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1509 struct si_sampler_views
*views
= &sctx
->samplers
[shader
].views
;
1510 struct si_descriptors
*descs
=
1511 si_sampler_descriptors(sctx
, shader
);
1512 unsigned mask
= views
->enabled_mask
;
1515 unsigned i
= u_bit_scan(&mask
);
1516 if (views
->views
[i
]->texture
== buf
) {
1517 si_desc_reset_buffer_offset(ctx
,
1521 descs
->dirty_mask
|= 1u << i
;
1522 sctx
->descriptors_dirty
|=
1523 1u << si_sampler_descriptors_idx(shader
);
1525 radeon_add_to_buffer_list_check_mem(&sctx
->b
, &sctx
->b
.gfx
,
1526 rbuffer
, RADEON_USAGE_READ
,
1527 RADEON_PRIO_SAMPLER_BUFFER
,
1534 for (shader
= 0; shader
< SI_NUM_SHADERS
; ++shader
) {
1535 struct si_images_info
*images
= &sctx
->images
[shader
];
1536 struct si_descriptors
*descs
=
1537 si_image_descriptors(sctx
, shader
);
1538 unsigned mask
= images
->enabled_mask
;
1541 unsigned i
= u_bit_scan(&mask
);
1543 if (images
->views
[i
].resource
== buf
) {
1544 if (images
->views
[i
].access
& PIPE_IMAGE_ACCESS_WRITE
)
1545 si_mark_image_range_valid(&images
->views
[i
]);
1547 si_desc_reset_buffer_offset(
1548 ctx
, descs
->list
+ i
* 8 + 4,
1550 descs
->dirty_mask
|= 1u << i
;
1551 sctx
->descriptors_dirty
|=
1552 1u << si_image_descriptors_idx(shader
);
1554 radeon_add_to_buffer_list_check_mem(
1555 &sctx
->b
, &sctx
->b
.gfx
, rbuffer
,
1556 RADEON_USAGE_READWRITE
,
1557 RADEON_PRIO_SAMPLER_BUFFER
, true);
1563 /* Update mutable image descriptor fields of all bound textures. */
1564 void si_update_all_texture_descriptors(struct si_context
*sctx
)
1568 for (shader
= 0; shader
< SI_NUM_SHADERS
; shader
++) {
1569 struct si_sampler_views
*samplers
= &sctx
->samplers
[shader
].views
;
1570 struct si_images_info
*images
= &sctx
->images
[shader
];
1574 mask
= images
->enabled_mask
;
1576 unsigned i
= u_bit_scan(&mask
);
1577 struct pipe_image_view
*view
= &images
->views
[i
];
1579 if (!view
->resource
||
1580 view
->resource
->target
== PIPE_BUFFER
)
1583 si_set_shader_image(sctx
, shader
, i
, view
);
1586 /* Sampler views. */
1587 mask
= samplers
->enabled_mask
;
1589 unsigned i
= u_bit_scan(&mask
);
1590 struct pipe_sampler_view
*view
= samplers
->views
[i
];
1594 view
->texture
->target
== PIPE_BUFFER
)
1597 si_set_sampler_view(sctx
, shader
, i
,
1598 samplers
->views
[i
], true);
1603 /* SHADER USER DATA */
1605 static void si_mark_shader_pointers_dirty(struct si_context
*sctx
,
1608 struct si_descriptors
*descs
=
1609 &sctx
->descriptors
[SI_DESCS_FIRST_SHADER
+ shader
* SI_NUM_SHADER_DESCS
];
1611 for (unsigned i
= 0; i
< SI_NUM_SHADER_DESCS
; ++i
, ++descs
)
1612 descs
->pointer_dirty
= true;
1614 if (shader
== PIPE_SHADER_VERTEX
)
1615 sctx
->vertex_buffers
.pointer_dirty
= true;
1617 si_mark_atom_dirty(sctx
, &sctx
->shader_userdata
.atom
);
1620 static void si_shader_userdata_begin_new_cs(struct si_context
*sctx
)
1624 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
1625 si_mark_shader_pointers_dirty(sctx
, i
);
1627 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].pointer_dirty
= true;
1630 /* Set a base register address for user data constants in the given shader.
1631 * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*.
1633 static void si_set_user_data_base(struct si_context
*sctx
,
1634 unsigned shader
, uint32_t new_base
)
1636 uint32_t *base
= &sctx
->shader_userdata
.sh_base
[shader
];
1638 if (*base
!= new_base
) {
1642 si_mark_shader_pointers_dirty(sctx
, shader
);
1646 /* This must be called when these shaders are changed from non-NULL to NULL
1649 * - tessellation control shader
1650 * - tessellation evaluation shader
1652 void si_shader_change_notify(struct si_context
*sctx
)
1654 /* VS can be bound as VS, ES, or LS. */
1655 if (sctx
->tes_shader
.cso
)
1656 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1657 R_00B530_SPI_SHADER_USER_DATA_LS_0
);
1658 else if (sctx
->gs_shader
.cso
)
1659 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1660 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1662 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
,
1663 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1665 /* TES can be bound as ES, VS, or not bound. */
1666 if (sctx
->tes_shader
.cso
) {
1667 if (sctx
->gs_shader
.cso
)
1668 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
1669 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
1671 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
,
1672 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1674 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_EVAL
, 0);
1678 static void si_emit_shader_pointer(struct si_context
*sctx
,
1679 struct si_descriptors
*desc
,
1680 unsigned sh_base
, bool keep_dirty
)
1682 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1685 if (!desc
->pointer_dirty
|| !desc
->buffer
)
1688 va
= desc
->buffer
->gpu_address
+
1689 desc
->buffer_offset
;
1691 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, 2, 0));
1692 radeon_emit(cs
, (sh_base
+ desc
->shader_userdata_offset
- SI_SH_REG_OFFSET
) >> 2);
1693 radeon_emit(cs
, va
);
1694 radeon_emit(cs
, va
>> 32);
1696 desc
->pointer_dirty
= keep_dirty
;
1699 void si_emit_graphics_shader_userdata(struct si_context
*sctx
,
1700 struct r600_atom
*atom
)
1703 uint32_t *sh_base
= sctx
->shader_userdata
.sh_base
;
1704 struct si_descriptors
*descs
;
1706 descs
= &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
];
1708 if (descs
->pointer_dirty
) {
1709 si_emit_shader_pointer(sctx
, descs
,
1710 R_00B030_SPI_SHADER_USER_DATA_PS_0
, true);
1711 si_emit_shader_pointer(sctx
, descs
,
1712 R_00B130_SPI_SHADER_USER_DATA_VS_0
, true);
1713 si_emit_shader_pointer(sctx
, descs
,
1714 R_00B230_SPI_SHADER_USER_DATA_GS_0
, true);
1715 si_emit_shader_pointer(sctx
, descs
,
1716 R_00B330_SPI_SHADER_USER_DATA_ES_0
, true);
1717 si_emit_shader_pointer(sctx
, descs
,
1718 R_00B430_SPI_SHADER_USER_DATA_HS_0
, true);
1719 descs
->pointer_dirty
= false;
1722 descs
= &sctx
->descriptors
[SI_DESCS_FIRST_SHADER
];
1724 for (shader
= 0; shader
< SI_NUM_GRAPHICS_SHADERS
; shader
++) {
1725 unsigned base
= sh_base
[shader
];
1731 for (i
= 0; i
< SI_NUM_SHADER_DESCS
; i
++, descs
++)
1732 si_emit_shader_pointer(sctx
, descs
, base
, false);
1734 si_emit_shader_pointer(sctx
, &sctx
->vertex_buffers
, sh_base
[PIPE_SHADER_VERTEX
], false);
1737 void si_emit_compute_shader_userdata(struct si_context
*sctx
)
1739 unsigned base
= R_00B900_COMPUTE_USER_DATA_0
;
1740 struct si_descriptors
*descs
= &sctx
->descriptors
[SI_DESCS_FIRST_COMPUTE
];
1742 for (unsigned i
= 0; i
< SI_NUM_SHADER_DESCS
; ++i
, ++descs
)
1743 si_emit_shader_pointer(sctx
, descs
, base
, false);
1746 /* INIT/DEINIT/UPLOAD */
1748 void si_init_all_descriptors(struct si_context
*sctx
)
1751 unsigned ce_offset
= 0;
1753 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
1754 si_init_buffer_resources(&sctx
->const_buffers
[i
],
1755 si_const_buffer_descriptors(sctx
, i
),
1756 SI_NUM_CONST_BUFFERS
, SI_SGPR_CONST_BUFFERS
,
1757 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
,
1759 si_init_buffer_resources(&sctx
->shader_buffers
[i
],
1760 si_shader_buffer_descriptors(sctx
, i
),
1761 SI_NUM_SHADER_BUFFERS
, SI_SGPR_SHADER_BUFFERS
,
1762 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RW_BUFFER
,
1765 si_init_descriptors(si_sampler_descriptors(sctx
, i
),
1766 SI_SGPR_SAMPLERS
, 16, SI_NUM_SAMPLERS
,
1767 null_texture_descriptor
, &ce_offset
);
1769 si_init_descriptors(si_image_descriptors(sctx
, i
),
1770 SI_SGPR_IMAGES
, 8, SI_NUM_IMAGES
,
1771 null_image_descriptor
, &ce_offset
);
1774 si_init_buffer_resources(&sctx
->rw_buffers
,
1775 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
1776 SI_NUM_RW_BUFFERS
, SI_SGPR_RW_BUFFERS
,
1777 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
,
1779 si_init_descriptors(&sctx
->vertex_buffers
, SI_SGPR_VERTEX_BUFFERS
,
1780 4, SI_NUM_VERTEX_BUFFERS
, NULL
, NULL
);
1782 sctx
->descriptors_dirty
= u_bit_consecutive(0, SI_NUM_DESCS
);
1784 assert(ce_offset
<= 32768);
1786 /* Set pipe_context functions. */
1787 sctx
->b
.b
.bind_sampler_states
= si_bind_sampler_states
;
1788 sctx
->b
.b
.set_shader_images
= si_set_shader_images
;
1789 sctx
->b
.b
.set_constant_buffer
= si_pipe_set_constant_buffer
;
1790 sctx
->b
.b
.set_polygon_stipple
= si_set_polygon_stipple
;
1791 sctx
->b
.b
.set_shader_buffers
= si_set_shader_buffers
;
1792 sctx
->b
.b
.set_sampler_views
= si_set_sampler_views
;
1793 sctx
->b
.b
.set_stream_output_targets
= si_set_streamout_targets
;
1794 sctx
->b
.invalidate_buffer
= si_invalidate_buffer
;
1796 /* Shader user data. */
1797 si_init_atom(sctx
, &sctx
->shader_userdata
.atom
, &sctx
->atoms
.s
.shader_userdata
,
1798 si_emit_graphics_shader_userdata
);
1800 /* Set default and immutable mappings. */
1801 si_set_user_data_base(sctx
, PIPE_SHADER_VERTEX
, R_00B130_SPI_SHADER_USER_DATA_VS_0
);
1802 si_set_user_data_base(sctx
, PIPE_SHADER_TESS_CTRL
, R_00B430_SPI_SHADER_USER_DATA_HS_0
);
1803 si_set_user_data_base(sctx
, PIPE_SHADER_GEOMETRY
, R_00B230_SPI_SHADER_USER_DATA_GS_0
);
1804 si_set_user_data_base(sctx
, PIPE_SHADER_FRAGMENT
, R_00B030_SPI_SHADER_USER_DATA_PS_0
);
1807 bool si_upload_graphics_shader_descriptors(struct si_context
*sctx
)
1809 const unsigned mask
= u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE
);
1810 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
1813 unsigned i
= u_bit_scan(&dirty
);
1815 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
],
1816 &sctx
->shader_userdata
.atom
))
1820 sctx
->descriptors_dirty
&= ~mask
;
1824 bool si_upload_compute_shader_descriptors(struct si_context
*sctx
)
1826 /* Does not update rw_buffers as that is not needed for compute shaders
1827 * and the input buffer is using the same SGPR's anyway.
1829 const unsigned mask
= u_bit_consecutive(SI_DESCS_FIRST_COMPUTE
,
1830 SI_NUM_DESCS
- SI_DESCS_FIRST_COMPUTE
);
1831 unsigned dirty
= sctx
->descriptors_dirty
& mask
;
1834 unsigned i
= u_bit_scan(&dirty
);
1836 if (!si_upload_descriptors(sctx
, &sctx
->descriptors
[i
], NULL
))
1840 sctx
->descriptors_dirty
&= ~mask
;
1845 void si_release_all_descriptors(struct si_context
*sctx
)
1849 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
1850 si_release_buffer_resources(&sctx
->const_buffers
[i
],
1851 si_const_buffer_descriptors(sctx
, i
));
1852 si_release_buffer_resources(&sctx
->shader_buffers
[i
],
1853 si_shader_buffer_descriptors(sctx
, i
));
1854 si_release_sampler_views(&sctx
->samplers
[i
].views
);
1855 si_release_image_views(&sctx
->images
[i
]);
1857 si_release_buffer_resources(&sctx
->rw_buffers
,
1858 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
]);
1860 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
1861 si_release_descriptors(&sctx
->descriptors
[i
]);
1862 si_release_descriptors(&sctx
->vertex_buffers
);
1865 void si_all_descriptors_begin_new_cs(struct si_context
*sctx
)
1869 for (i
= 0; i
< SI_NUM_SHADERS
; i
++) {
1870 si_buffer_resources_begin_new_cs(sctx
, &sctx
->const_buffers
[i
]);
1871 si_buffer_resources_begin_new_cs(sctx
, &sctx
->shader_buffers
[i
]);
1872 si_sampler_views_begin_new_cs(sctx
, &sctx
->samplers
[i
].views
);
1873 si_image_views_begin_new_cs(sctx
, &sctx
->images
[i
]);
1875 si_buffer_resources_begin_new_cs(sctx
, &sctx
->rw_buffers
);
1876 si_vertex_buffers_begin_new_cs(sctx
);
1878 for (i
= 0; i
< SI_NUM_DESCS
; ++i
)
1879 si_descriptors_begin_new_cs(sctx
, &sctx
->descriptors
[i
]);
1881 si_shader_userdata_begin_new_cs(sctx
);