src/gallium/drivers/radeonsi/si_dma.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26
  27 #include "sid.h"
  28 #include "si_pipe.h"
  29 #include "radeon/r600_cs.h"
  30
  31 #include "util/u_format.h"
  32
  33 static void si_dma_copy_buffer(struct si_context *ctx,
  34                                 struct pipe_resource *dst,
  35                                 struct pipe_resource *src,
  36                                 uint64_t dst_offset,
  37                                 uint64_t src_offset,
  38                                 uint64_t size)
  39 {
  40         struct radeon_winsys_cs *cs = ctx->b.dma.cs;
  41         unsigned i, ncopy, csize, max_csize, sub_cmd, shift;
  42         struct r600_resource *rdst = (struct r600_resource*)dst;
  43         struct r600_resource *rsrc = (struct r600_resource*)src;
  44
  45         /* Mark the buffer range of destination as valid (initialized),
  46          * so that transfer_map knows it should wait for the GPU when mapping
  47          * that range. */
  48         util_range_add(&rdst->valid_buffer_range, dst_offset,
  49                        dst_offset + size);
  50
  51         dst_offset += rdst->gpu_address;
  52         src_offset += rsrc->gpu_address;
  53
  54         /* see if we use dword or byte copy */
  55         if (!(dst_offset % 4) && !(src_offset % 4) && !(size % 4)) {
  56                 size >>= 2;
  57                 sub_cmd = SI_DMA_COPY_DWORD_ALIGNED;
  58                 shift = 2;
  59                 max_csize = SI_DMA_COPY_MAX_SIZE_DW;
  60         } else {
  61                 sub_cmd = SI_DMA_COPY_BYTE_ALIGNED;
  62                 shift = 0;
  63                 max_csize = SI_DMA_COPY_MAX_SIZE;
  64         }
  65         ncopy = (size / max_csize) + !!(size % max_csize);
  66
  67         r600_need_dma_space(&ctx->b, ncopy * 5);
  68
  69         radeon_add_to_buffer_list(&ctx->b, &ctx->b.dma, rsrc, RADEON_USAGE_READ,
  70                               RADEON_PRIO_SDMA_BUFFER);
  71         radeon_add_to_buffer_list(&ctx->b, &ctx->b.dma, rdst, RADEON_USAGE_WRITE,
  72                               RADEON_PRIO_SDMA_BUFFER);
  73
  74         for (i = 0; i < ncopy; i++) {
  75                 csize = size < max_csize ? size : max_csize;
  76                 cs->buf[cs->cdw++] = SI_DMA_PACKET(SI_DMA_PACKET_COPY, sub_cmd, csize);
  77                 cs->buf[cs->cdw++] = dst_offset;
  78                 cs->buf[cs->cdw++] = src_offset;
  79                 cs->buf[cs->cdw++] = (dst_offset >> 32UL) & 0xff;
  80                 cs->buf[cs->cdw++] = (src_offset >> 32UL) & 0xff;
  81                 dst_offset += csize << shift;
  82                 src_offset += csize << shift;
  83                 size -= csize;
  84         }
  85         r600_dma_emit_wait_idle(&ctx->b);
  86 }
  87
  88 static void si_dma_copy_tile(struct si_context *ctx,
  89                              struct pipe_resource *dst,
  90                              unsigned dst_level,
  91                              unsigned dst_x,
  92                              unsigned dst_y,
  93                              unsigned dst_z,
  94                              struct pipe_resource *src,
  95                              unsigned src_level,
  96                              unsigned src_x,
  97                              unsigned src_y,
  98                              unsigned src_z,
  99                              unsigned copy_height,
 100                              unsigned pitch,
 101                              unsigned bpp)
 102 {
 103         struct radeon_winsys_cs *cs = ctx->b.dma.cs;
 104         struct r600_texture *rsrc = (struct r600_texture*)src;
 105         struct r600_texture *rdst = (struct r600_texture*)dst;
 106         unsigned dst_mode = rdst->surface.level[dst_level].mode;
 107         unsigned src_mode = rsrc->surface.level[src_level].mode;
 108         bool detile = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
 109         struct r600_texture *rlinear = detile ? rdst : rsrc;
 110         struct r600_texture *rtiled = detile ? rsrc : rdst;
 111         unsigned linear_lvl = detile ? dst_level : src_level;
 112         unsigned tiled_lvl = detile ? src_level : dst_level;
 113         struct radeon_info *info = &ctx->screen->b.info;
 114         unsigned index = rtiled->surface.tiling_index[tiled_lvl];
 115         unsigned tile_mode = info->si_tile_mode_array[index];
 116         unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
 117         unsigned ncopy, height, cheight, i;
 118         unsigned linear_x, linear_y, linear_z,  tiled_x, tiled_y, tiled_z;
 119         unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, mt;
 120         uint64_t base, addr;
 121         unsigned pipe_config;
 122
 123         assert(dst_mode != src_mode);
 124
 125         sub_cmd = SI_DMA_COPY_TILED;
 126         lbpp = util_logbase2(bpp);
 127         pitch_tile_max = ((pitch / bpp) / 8) - 1;
 128
 129         linear_x = detile ? dst_x : src_x;
 130         linear_y = detile ? dst_y : src_y;
 131         linear_z = detile ? dst_z : src_z;
 132         tiled_x = detile ? src_x : dst_x;
 133         tiled_y = detile ? src_y : dst_y;
 134         tiled_z = detile ? src_z : dst_z;
 135
 136         assert(!util_format_is_depth_and_stencil(rtiled->resource.b.b.format));
 137
 138         array_mode = G_009910_ARRAY_MODE(tile_mode);
 139         slice_tile_max = (rtiled->surface.level[tiled_lvl].nblk_x *
 140                           rtiled->surface.level[tiled_lvl].nblk_y) / (8*8) - 1;
 141         /* linear height must be the same as the slice tile max height, it's ok even
 142          * if the linear destination/source have smaller heigh as the size of the
 143          * dma packet will be using the copy_height which is always smaller or equal
 144          * to the linear height
 145          */
 146         height = rtiled->surface.level[tiled_lvl].nblk_y;
 147         base = rtiled->surface.level[tiled_lvl].offset;
 148         addr = rlinear->surface.level[linear_lvl].offset;
 149         addr += rlinear->surface.level[linear_lvl].slice_size * linear_z;
 150         addr += linear_y * pitch + linear_x * bpp;
 151         bank_h = G_009910_BANK_HEIGHT(tile_mode);
 152         bank_w = G_009910_BANK_WIDTH(tile_mode);
 153         mt_aspect = G_009910_MACRO_TILE_ASPECT(tile_mode);
 154         /* Non-depth modes don't have TILE_SPLIT set. */
 155         tile_split = util_logbase2(rtiled->surface.tile_split >> 6);
 156         nbanks = G_009910_NUM_BANKS(tile_mode);
 157         base += rtiled->resource.gpu_address;
 158         addr += rlinear->resource.gpu_address;
 159
 160         pipe_config = G_009910_PIPE_CONFIG(tile_mode);
 161         mt = G_009910_MICRO_TILE_MODE(tile_mode);
 162         size = (copy_height * pitch) / 4;
 163         ncopy = (size / SI_DMA_COPY_MAX_SIZE_DW) + !!(size % SI_DMA_COPY_MAX_SIZE_DW);
 164         r600_need_dma_space(&ctx->b, ncopy * 9);
 165
 166         radeon_add_to_buffer_list(&ctx->b, &ctx->b.dma, &rsrc->resource,
 167                               RADEON_USAGE_READ, RADEON_PRIO_SDMA_TEXTURE);
 168         radeon_add_to_buffer_list(&ctx->b, &ctx->b.dma, &rdst->resource,
 169                               RADEON_USAGE_WRITE, RADEON_PRIO_SDMA_TEXTURE);
 170
 171         for (i = 0; i < ncopy; i++) {
 172                 cheight = copy_height;
 173                 if (((cheight * pitch) / 4) > SI_DMA_COPY_MAX_SIZE_DW) {
 174                         cheight = (SI_DMA_COPY_MAX_SIZE_DW * 4) / pitch;
 175                 }
 176                 size = (cheight * pitch) / 4;
 177                 cs->buf[cs->cdw++] = SI_DMA_PACKET(SI_DMA_PACKET_COPY, sub_cmd, size);
 178                 cs->buf[cs->cdw++] = base >> 8;
 179                 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
 180                                         (lbpp << 24) | (bank_h << 21) |
 181                                         (bank_w << 18) | (mt_aspect << 16);
 182                 cs->buf[cs->cdw++] = (pitch_tile_max << 0) | ((height - 1) << 16);
 183                 cs->buf[cs->cdw++] = (slice_tile_max << 0) | (pipe_config << 26);
 184                 cs->buf[cs->cdw++] = (tiled_x << 0) | (tiled_z << 18);
 185                 cs->buf[cs->cdw++] = (tiled_y << 0) | (tile_split << 21) | (nbanks << 25) | (mt << 27);
 186                 cs->buf[cs->cdw++] = addr & 0xfffffffc;
 187                 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
 188                 copy_height -= cheight;
 189                 addr += cheight * pitch;
 190                 tiled_y += cheight;
 191         }
 192         r600_dma_emit_wait_idle(&ctx->b);
 193 }
 194
 195 static void si_dma_copy(struct pipe_context *ctx,
 196                         struct pipe_resource *dst,
 197                         unsigned dst_level,
 198                         unsigned dstx, unsigned dsty, unsigned dstz,
 199                         struct pipe_resource *src,
 200                         unsigned src_level,
 201                         const struct pipe_box *src_box)
 202 {
 203         struct si_context *sctx = (struct si_context *)ctx;
 204         struct r600_texture *rsrc = (struct r600_texture*)src;
 205         struct r600_texture *rdst = (struct r600_texture*)dst;
 206         unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode;
 207         unsigned src_w, dst_w;
 208         unsigned src_x, src_y;
 209         unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
 210
 211         if (sctx->b.dma.cs == NULL) {
 212                 goto fallback;
 213         }
 214
 215         if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
 216                 si_dma_copy_buffer(sctx, dst, src, dst_x, src_box->x, src_box->width);
 217                 return;
 218         }
 219
 220         /* XXX: Using the asynchronous DMA engine for multi-dimensional
 221          * operations seems to cause random GPU lockups for various people.
 222          * While the root cause for this might need to be fixed in the kernel,
 223          * let's disable it for now.
 224          *
 225          * Before re-enabling this, please make sure you can hit all newly
 226          * enabled paths in your testing, preferably with both piglit and real
 227          * world apps, and get in touch with people on the bug reports below
 228          * for stability testing.
 229          *
 230          * https://bugs.freedesktop.org/show_bug.cgi?id=85647
 231          * https://bugs.freedesktop.org/show_bug.cgi?id=83500
 232          */
 233         goto fallback;
 234
 235         if (src_box->depth > 1 ||
 236             !r600_prepare_for_dma_blit(&sctx->b, rdst, dst_level, dstx, dsty,
 237                                         dstz, rsrc, src_level, src_box))
 238                 goto fallback;
 239
 240         src_x = util_format_get_nblocksx(src->format, src_box->x);
 241         dst_x = util_format_get_nblocksx(src->format, dst_x);
 242         src_y = util_format_get_nblocksy(src->format, src_box->y);
 243         dst_y = util_format_get_nblocksy(src->format, dst_y);
 244
 245         bpp = rdst->surface.bpe;
 246         dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
 247         src_pitch = rsrc->surface.level[src_level].pitch_bytes;
 248         src_w = rsrc->surface.level[src_level].npix_x;
 249         dst_w = rdst->surface.level[dst_level].npix_x;
 250
 251         dst_mode = rdst->surface.level[dst_level].mode;
 252         src_mode = rsrc->surface.level[src_level].mode;
 253
 254         if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w ||
 255             src_box->width != src_w ||
 256             src_box->height != rsrc->surface.level[src_level].npix_y ||
 257             src_box->height != rdst->surface.level[dst_level].npix_y ||
 258             rsrc->surface.level[src_level].nblk_y !=
 259             rdst->surface.level[dst_level].nblk_y) {
 260                 /* FIXME si can do partial blit */
 261                 goto fallback;
 262         }
 263         /* the x test here are currently useless (because we don't support partial blit)
 264          * but keep them around so we don't forget about those
 265          */
 266         if ((src_pitch % 8) || (src_box->x % 8) || (dst_x % 8) ||
 267             (src_box->y % 8) || (dst_y % 8) || (src_box->height % 8)) {
 268                 goto fallback;
 269         }
 270
 271         if (src_mode == dst_mode) {
 272                 uint64_t dst_offset, src_offset;
 273                 /* simple dma blit would do NOTE code here assume :
 274                  *   src_box.x/y == 0
 275                  *   dst_x/y == 0
 276                  *   dst_pitch == src_pitch
 277                  */
 278                 src_offset= rsrc->surface.level[src_level].offset;
 279                 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
 280                 src_offset += src_y * src_pitch + src_x * bpp;
 281                 dst_offset = rdst->surface.level[dst_level].offset;
 282                 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
 283                 dst_offset += dst_y * dst_pitch + dst_x * bpp;
 284                 si_dma_copy_buffer(sctx, dst, src, dst_offset, src_offset,
 285                                    rsrc->surface.level[src_level].slice_size);
 286         } else {
 287                 si_dma_copy_tile(sctx, dst, dst_level, dst_x, dst_y, dst_z,
 288                                  src, src_level, src_x, src_y, src_box->z,
 289                                  src_box->height / rsrc->surface.blk_h,
 290                                  dst_pitch, bpp);
 291         }
 292         return;
 293
 294 fallback:
 295         si_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
 296                                 src, src_level, src_box);
 297 }
 298
 299 void si_init_dma_functions(struct si_context *sctx)
 300 {
 301         sctx->b.dma_copy = si_dma_copy;
 302 }