src/gallium/drivers/radeonsi/si_dma.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26
  27 #include "sid.h"
  28 #include "si_pipe.h"
  29
  30 #include "util/u_format.h"
  31
  32 static void si_dma_copy_buffer(struct si_context *ctx,
  33                                 struct pipe_resource *dst,
  34                                 struct pipe_resource *src,
  35                                 uint64_t dst_offset,
  36                                 uint64_t src_offset,
  37                                 uint64_t size)
  38 {
  39         struct radeon_winsys_cs *cs = ctx->b.dma.cs;
  40         unsigned i, ncopy, csize, max_csize, sub_cmd, shift;
  41         struct r600_resource *rdst = (struct r600_resource*)dst;
  42         struct r600_resource *rsrc = (struct r600_resource*)src;
  43
  44         /* Mark the buffer range of destination as valid (initialized),
  45          * so that transfer_map knows it should wait for the GPU when mapping
  46          * that range. */
  47         util_range_add(&rdst->valid_buffer_range, dst_offset,
  48                        dst_offset + size);
  49
  50         dst_offset += rdst->gpu_address;
  51         src_offset += rsrc->gpu_address;
  52
  53         /* see if we use dword or byte copy */
  54         if (!(dst_offset % 4) && !(src_offset % 4) && !(size % 4)) {
  55                 size >>= 2;
  56                 sub_cmd = SI_DMA_COPY_DWORD_ALIGNED;
  57                 shift = 2;
  58                 max_csize = SI_DMA_COPY_MAX_SIZE_DW;
  59         } else {
  60                 sub_cmd = SI_DMA_COPY_BYTE_ALIGNED;
  61                 shift = 0;
  62                 max_csize = SI_DMA_COPY_MAX_SIZE;
  63         }
  64         ncopy = (size / max_csize) + !!(size % max_csize);
  65
  66         r600_need_dma_space(&ctx->b, ncopy * 5, rdst, rsrc);
  67
  68         for (i = 0; i < ncopy; i++) {
  69                 csize = size < max_csize ? size : max_csize;
  70                 radeon_emit(cs, SI_DMA_PACKET(SI_DMA_PACKET_COPY, sub_cmd, csize));
  71                 radeon_emit(cs, dst_offset);
  72                 radeon_emit(cs, src_offset);
  73                 radeon_emit(cs, (dst_offset >> 32UL) & 0xff);
  74                 radeon_emit(cs, (src_offset >> 32UL) & 0xff);
  75                 dst_offset += csize << shift;
  76                 src_offset += csize << shift;
  77                 size -= csize;
  78         }
  79         r600_dma_emit_wait_idle(&ctx->b);
  80 }
  81
  82 static void si_dma_copy_tile(struct si_context *ctx,
  83                              struct pipe_resource *dst,
  84                              unsigned dst_level,
  85                              unsigned dst_x,
  86                              unsigned dst_y,
  87                              unsigned dst_z,
  88                              struct pipe_resource *src,
  89                              unsigned src_level,
  90                              unsigned src_x,
  91                              unsigned src_y,
  92                              unsigned src_z,
  93                              unsigned copy_height,
  94                              unsigned pitch,
  95                              unsigned bpp)
  96 {
  97         struct radeon_winsys_cs *cs = ctx->b.dma.cs;
  98         struct r600_texture *rsrc = (struct r600_texture*)src;
  99         struct r600_texture *rdst = (struct r600_texture*)dst;
 100         unsigned dst_mode = rdst->surface.level[dst_level].mode;
 101         unsigned src_mode = rsrc->surface.level[src_level].mode;
 102         bool detile = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
 103         struct r600_texture *rlinear = detile ? rdst : rsrc;
 104         struct r600_texture *rtiled = detile ? rsrc : rdst;
 105         unsigned linear_lvl = detile ? dst_level : src_level;
 106         unsigned tiled_lvl = detile ? src_level : dst_level;
 107         struct radeon_info *info = &ctx->screen->b.info;
 108         unsigned index = rtiled->surface.tiling_index[tiled_lvl];
 109         unsigned tile_mode = info->si_tile_mode_array[index];
 110         unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
 111         unsigned ncopy, height, cheight, i;
 112         unsigned linear_x, linear_y, linear_z,  tiled_x, tiled_y, tiled_z;
 113         unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, mt;
 114         uint64_t base, addr;
 115         unsigned pipe_config;
 116
 117         assert(dst_mode != src_mode);
 118
 119         sub_cmd = SI_DMA_COPY_TILED;
 120         lbpp = util_logbase2(bpp);
 121         pitch_tile_max = ((pitch / bpp) / 8) - 1;
 122
 123         linear_x = detile ? dst_x : src_x;
 124         linear_y = detile ? dst_y : src_y;
 125         linear_z = detile ? dst_z : src_z;
 126         tiled_x = detile ? src_x : dst_x;
 127         tiled_y = detile ? src_y : dst_y;
 128         tiled_z = detile ? src_z : dst_z;
 129
 130         assert(!util_format_is_depth_and_stencil(rtiled->resource.b.b.format));
 131
 132         array_mode = G_009910_ARRAY_MODE(tile_mode);
 133         slice_tile_max = (rtiled->surface.level[tiled_lvl].nblk_x *
 134                           rtiled->surface.level[tiled_lvl].nblk_y) / (8*8) - 1;
 135         /* linear height must be the same as the slice tile max height, it's ok even
 136          * if the linear destination/source have smaller heigh as the size of the
 137          * dma packet will be using the copy_height which is always smaller or equal
 138          * to the linear height
 139          */
 140         height = rtiled->surface.level[tiled_lvl].nblk_y;
 141         base = rtiled->surface.level[tiled_lvl].offset;
 142         addr = rlinear->surface.level[linear_lvl].offset;
 143         addr += rlinear->surface.level[linear_lvl].slice_size * linear_z;
 144         addr += linear_y * pitch + linear_x * bpp;
 145         bank_h = G_009910_BANK_HEIGHT(tile_mode);
 146         bank_w = G_009910_BANK_WIDTH(tile_mode);
 147         mt_aspect = G_009910_MACRO_TILE_ASPECT(tile_mode);
 148         /* Non-depth modes don't have TILE_SPLIT set. */
 149         tile_split = util_logbase2(rtiled->surface.tile_split >> 6);
 150         nbanks = G_009910_NUM_BANKS(tile_mode);
 151         base += rtiled->resource.gpu_address;
 152         addr += rlinear->resource.gpu_address;
 153
 154         pipe_config = G_009910_PIPE_CONFIG(tile_mode);
 155         mt = G_009910_MICRO_TILE_MODE(tile_mode);
 156         size = (copy_height * pitch) / 4;
 157         ncopy = (size / SI_DMA_COPY_MAX_SIZE_DW) + !!(size % SI_DMA_COPY_MAX_SIZE_DW);
 158         r600_need_dma_space(&ctx->b, ncopy * 9, &rdst->resource, &rsrc->resource);
 159
 160         for (i = 0; i < ncopy; i++) {
 161                 cheight = copy_height;
 162                 if (((cheight * pitch) / 4) > SI_DMA_COPY_MAX_SIZE_DW) {
 163                         cheight = (SI_DMA_COPY_MAX_SIZE_DW * 4) / pitch;
 164                 }
 165                 size = (cheight * pitch) / 4;
 166                 radeon_emit(cs, SI_DMA_PACKET(SI_DMA_PACKET_COPY, sub_cmd, size));
 167                 radeon_emit(cs, base >> 8);
 168                 radeon_emit(cs, (detile << 31) | (array_mode << 27) |
 169                                 (lbpp << 24) | (bank_h << 21) |
 170                                 (bank_w << 18) | (mt_aspect << 16));
 171                 radeon_emit(cs, (pitch_tile_max << 0) | ((height - 1) << 16));
 172                 radeon_emit(cs, (slice_tile_max << 0) | (pipe_config << 26));
 173                 radeon_emit(cs, (tiled_x << 0) | (tiled_z << 18));
 174                 radeon_emit(cs, (tiled_y << 0) | (tile_split << 21) | (nbanks << 25) | (mt << 27));
 175                 radeon_emit(cs, addr & 0xfffffffc);
 176                 radeon_emit(cs, (addr >> 32UL) & 0xff);
 177                 copy_height -= cheight;
 178                 addr += cheight * pitch;
 179                 tiled_y += cheight;
 180         }
 181         r600_dma_emit_wait_idle(&ctx->b);
 182 }
 183
 184 static void si_dma_copy(struct pipe_context *ctx,
 185                         struct pipe_resource *dst,
 186                         unsigned dst_level,
 187                         unsigned dstx, unsigned dsty, unsigned dstz,
 188                         struct pipe_resource *src,
 189                         unsigned src_level,
 190                         const struct pipe_box *src_box)
 191 {
 192         struct si_context *sctx = (struct si_context *)ctx;
 193         struct r600_texture *rsrc = (struct r600_texture*)src;
 194         struct r600_texture *rdst = (struct r600_texture*)dst;
 195         unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode;
 196         unsigned src_w, dst_w;
 197         unsigned src_x, src_y;
 198         unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
 199
 200         if (sctx->b.dma.cs == NULL) {
 201                 goto fallback;
 202         }
 203
 204         if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
 205                 si_dma_copy_buffer(sctx, dst, src, dst_x, src_box->x, src_box->width);
 206                 return;
 207         }
 208
 209         /* XXX: Using the asynchronous DMA engine for multi-dimensional
 210          * operations seems to cause random GPU lockups for various people.
 211          * While the root cause for this might need to be fixed in the kernel,
 212          * let's disable it for now.
 213          *
 214          * Before re-enabling this, please make sure you can hit all newly
 215          * enabled paths in your testing, preferably with both piglit and real
 216          * world apps, and get in touch with people on the bug reports below
 217          * for stability testing.
 218          *
 219          * https://bugs.freedesktop.org/show_bug.cgi?id=85647
 220          * https://bugs.freedesktop.org/show_bug.cgi?id=83500
 221          */
 222         goto fallback;
 223
 224         if (src_box->depth > 1 ||
 225             !r600_prepare_for_dma_blit(&sctx->b, rdst, dst_level, dstx, dsty,
 226                                         dstz, rsrc, src_level, src_box))
 227                 goto fallback;
 228
 229         src_x = util_format_get_nblocksx(src->format, src_box->x);
 230         dst_x = util_format_get_nblocksx(src->format, dst_x);
 231         src_y = util_format_get_nblocksy(src->format, src_box->y);
 232         dst_y = util_format_get_nblocksy(src->format, dst_y);
 233
 234         bpp = rdst->surface.bpe;
 235         dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
 236         src_pitch = rsrc->surface.level[src_level].pitch_bytes;
 237         src_w = u_minify(rsrc->resource.b.b.width0, src_level);
 238         dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
 239
 240         dst_mode = rdst->surface.level[dst_level].mode;
 241         src_mode = rsrc->surface.level[src_level].mode;
 242
 243         if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w ||
 244             src_box->width != src_w ||
 245             src_box->height != u_minify(rsrc->resource.b.b.height0, src_level) ||
 246             src_box->height != u_minify(rdst->resource.b.b.height0, dst_level) ||
 247             rsrc->surface.level[src_level].nblk_y !=
 248             rdst->surface.level[dst_level].nblk_y) {
 249                 /* FIXME si can do partial blit */
 250                 goto fallback;
 251         }
 252         /* the x test here are currently useless (because we don't support partial blit)
 253          * but keep them around so we don't forget about those
 254          */
 255         if ((src_pitch % 8) || (src_box->x % 8) || (dst_x % 8) ||
 256             (src_box->y % 8) || (dst_y % 8) || (src_box->height % 8)) {
 257                 goto fallback;
 258         }
 259
 260         if (src_mode == dst_mode) {
 261                 uint64_t dst_offset, src_offset;
 262                 /* simple dma blit would do NOTE code here assume :
 263                  *   src_box.x/y == 0
 264                  *   dst_x/y == 0
 265                  *   dst_pitch == src_pitch
 266                  */
 267                 src_offset= rsrc->surface.level[src_level].offset;
 268                 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
 269                 src_offset += src_y * src_pitch + src_x * bpp;
 270                 dst_offset = rdst->surface.level[dst_level].offset;
 271                 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
 272                 dst_offset += dst_y * dst_pitch + dst_x * bpp;
 273                 si_dma_copy_buffer(sctx, dst, src, dst_offset, src_offset,
 274                                    rsrc->surface.level[src_level].slice_size);
 275         } else {
 276                 si_dma_copy_tile(sctx, dst, dst_level, dst_x, dst_y, dst_z,
 277                                  src, src_level, src_x, src_y, src_box->z,
 278                                  src_box->height / rsrc->surface.blk_h,
 279                                  dst_pitch, bpp);
 280         }
 281         return;
 282
 283 fallback:
 284         si_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
 285                                 src, src_level, src_box);
 286 }
 287
 288 void si_init_dma_functions(struct si_context *sctx)
 289 {
 290         sctx->b.dma_copy = si_dma_copy;
 291 }