src/gallium/drivers/radeonsi/si_dma.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26
  27 #include "sid.h"
  28 #include "si_pipe.h"
  29
  30 #include "util/u_format.h"
  31
  32 static void si_dma_copy_buffer(struct si_context *ctx,
  33                                 struct pipe_resource *dst,
  34                                 struct pipe_resource *src,
  35                                 uint64_t dst_offset,
  36                                 uint64_t src_offset,
  37                                 uint64_t size)
  38 {
  39         struct radeon_winsys_cs *cs = ctx->b.dma.cs;
  40         unsigned i, ncopy, count, max_size, sub_cmd, shift;
  41         struct r600_resource *rdst = (struct r600_resource*)dst;
  42         struct r600_resource *rsrc = (struct r600_resource*)src;
  43
  44         /* Mark the buffer range of destination as valid (initialized),
  45          * so that transfer_map knows it should wait for the GPU when mapping
  46          * that range. */
  47         util_range_add(&rdst->valid_buffer_range, dst_offset,
  48                        dst_offset + size);
  49
  50         dst_offset += rdst->gpu_address;
  51         src_offset += rsrc->gpu_address;
  52
  53         /* see whether we should use the dword-aligned or byte-aligned copy */
  54         if (!(dst_offset % 4) && !(src_offset % 4) && !(size % 4)) {
  55                 sub_cmd = SI_DMA_COPY_DWORD_ALIGNED;
  56                 shift = 2;
  57                 max_size = SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE;
  58         } else {
  59                 sub_cmd = SI_DMA_COPY_BYTE_ALIGNED;
  60                 shift = 0;
  61                 max_size = SI_DMA_COPY_MAX_BYTE_ALIGNED_SIZE;
  62         }
  63
  64         ncopy = DIV_ROUND_UP(size, max_size);
  65         r600_need_dma_space(&ctx->b, ncopy * 5, rdst, rsrc);
  66
  67         for (i = 0; i < ncopy; i++) {
  68                 count = MIN2(size, max_size);
  69                 radeon_emit(cs, SI_DMA_PACKET(SI_DMA_PACKET_COPY, sub_cmd,
  70                                               count >> shift));
  71                 radeon_emit(cs, dst_offset);
  72                 radeon_emit(cs, src_offset);
  73                 radeon_emit(cs, (dst_offset >> 32UL) & 0xff);
  74                 radeon_emit(cs, (src_offset >> 32UL) & 0xff);
  75                 dst_offset += count;
  76                 src_offset += count;
  77                 size -= count;
  78         }
  79 }
  80
  81 static void si_dma_clear_buffer(struct pipe_context *ctx,
  82                                 struct pipe_resource *dst,
  83                                 uint64_t offset,
  84                                 uint64_t size,
  85                                 unsigned clear_value)
  86 {
  87         struct si_context *sctx = (struct si_context *)ctx;
  88         struct radeon_winsys_cs *cs = sctx->b.dma.cs;
  89         unsigned i, ncopy, csize;
  90         struct r600_resource *rdst = r600_resource(dst);
  91
  92         if (!cs || offset % 4 != 0 || size % 4 != 0 ||
  93             dst->flags & PIPE_RESOURCE_FLAG_SPARSE) {
  94                 ctx->clear_buffer(ctx, dst, offset, size, &clear_value, 4);
  95                 return;
  96         }
  97
  98         /* Mark the buffer range of destination as valid (initialized),
  99          * so that transfer_map knows it should wait for the GPU when mapping
 100          * that range. */
 101         util_range_add(&rdst->valid_buffer_range, offset, offset + size);
 102
 103         offset += rdst->gpu_address;
 104
 105         /* the same maximum size as for copying */
 106         ncopy = DIV_ROUND_UP(size, SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE);
 107         r600_need_dma_space(&sctx->b, ncopy * 4, rdst, NULL);
 108
 109         for (i = 0; i < ncopy; i++) {
 110                 csize = MIN2(size, SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE);
 111                 radeon_emit(cs, SI_DMA_PACKET(SI_DMA_PACKET_CONSTANT_FILL, 0,
 112                                               csize / 4));
 113                 radeon_emit(cs, offset);
 114                 radeon_emit(cs, clear_value);
 115                 radeon_emit(cs, (offset >> 32) << 16);
 116                 offset += csize;
 117                 size -= csize;
 118         }
 119 }
 120
 121 static void si_dma_copy_tile(struct si_context *ctx,
 122                              struct pipe_resource *dst,
 123                              unsigned dst_level,
 124                              unsigned dst_x,
 125                              unsigned dst_y,
 126                              unsigned dst_z,
 127                              struct pipe_resource *src,
 128                              unsigned src_level,
 129                              unsigned src_x,
 130                              unsigned src_y,
 131                              unsigned src_z,
 132                              unsigned copy_height,
 133                              unsigned pitch,
 134                              unsigned bpp)
 135 {
 136         struct radeon_winsys_cs *cs = ctx->b.dma.cs;
 137         struct r600_texture *rsrc = (struct r600_texture*)src;
 138         struct r600_texture *rdst = (struct r600_texture*)dst;
 139         unsigned dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
 140         bool detile = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
 141         struct r600_texture *rlinear = detile ? rdst : rsrc;
 142         struct r600_texture *rtiled = detile ? rsrc : rdst;
 143         unsigned linear_lvl = detile ? dst_level : src_level;
 144         unsigned tiled_lvl = detile ? src_level : dst_level;
 145         struct radeon_info *info = &ctx->screen->b.info;
 146         unsigned index = rtiled->surface.u.legacy.tiling_index[tiled_lvl];
 147         unsigned tile_mode = info->si_tile_mode_array[index];
 148         unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
 149         unsigned ncopy, height, cheight, i;
 150         unsigned linear_x, linear_y, linear_z,  tiled_x, tiled_y, tiled_z;
 151         unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, mt;
 152         uint64_t base, addr;
 153         unsigned pipe_config;
 154
 155         assert(dst_mode != rsrc->surface.u.legacy.level[src_level].mode);
 156
 157         sub_cmd = SI_DMA_COPY_TILED;
 158         lbpp = util_logbase2(bpp);
 159         pitch_tile_max = ((pitch / bpp) / 8) - 1;
 160
 161         linear_x = detile ? dst_x : src_x;
 162         linear_y = detile ? dst_y : src_y;
 163         linear_z = detile ? dst_z : src_z;
 164         tiled_x = detile ? src_x : dst_x;
 165         tiled_y = detile ? src_y : dst_y;
 166         tiled_z = detile ? src_z : dst_z;
 167
 168         assert(!util_format_is_depth_and_stencil(rtiled->resource.b.b.format));
 169
 170         array_mode = G_009910_ARRAY_MODE(tile_mode);
 171         slice_tile_max = (rtiled->surface.u.legacy.level[tiled_lvl].nblk_x *
 172                           rtiled->surface.u.legacy.level[tiled_lvl].nblk_y) / (8*8) - 1;
 173         /* linear height must be the same as the slice tile max height, it's ok even
 174          * if the linear destination/source have smaller heigh as the size of the
 175          * dma packet will be using the copy_height which is always smaller or equal
 176          * to the linear height
 177          */
 178         height = rtiled->surface.u.legacy.level[tiled_lvl].nblk_y;
 179         base = rtiled->surface.u.legacy.level[tiled_lvl].offset;
 180         addr = rlinear->surface.u.legacy.level[linear_lvl].offset;
 181         addr += rlinear->surface.u.legacy.level[linear_lvl].slice_size * linear_z;
 182         addr += linear_y * pitch + linear_x * bpp;
 183         bank_h = G_009910_BANK_HEIGHT(tile_mode);
 184         bank_w = G_009910_BANK_WIDTH(tile_mode);
 185         mt_aspect = G_009910_MACRO_TILE_ASPECT(tile_mode);
 186         /* Non-depth modes don't have TILE_SPLIT set. */
 187         tile_split = util_logbase2(rtiled->surface.u.legacy.tile_split >> 6);
 188         nbanks = G_009910_NUM_BANKS(tile_mode);
 189         base += rtiled->resource.gpu_address;
 190         addr += rlinear->resource.gpu_address;
 191
 192         pipe_config = G_009910_PIPE_CONFIG(tile_mode);
 193         mt = G_009910_MICRO_TILE_MODE(tile_mode);
 194         size = copy_height * pitch;
 195         ncopy = DIV_ROUND_UP(size, SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE);
 196         r600_need_dma_space(&ctx->b, ncopy * 9, &rdst->resource, &rsrc->resource);
 197
 198         for (i = 0; i < ncopy; i++) {
 199                 cheight = copy_height;
 200                 if (cheight * pitch > SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE) {
 201                         cheight = SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE / pitch;
 202                 }
 203                 size = cheight * pitch;
 204                 radeon_emit(cs, SI_DMA_PACKET(SI_DMA_PACKET_COPY, sub_cmd, size / 4));
 205                 radeon_emit(cs, base >> 8);
 206                 radeon_emit(cs, (detile << 31) | (array_mode << 27) |
 207                                 (lbpp << 24) | (bank_h << 21) |
 208                                 (bank_w << 18) | (mt_aspect << 16));
 209                 radeon_emit(cs, (pitch_tile_max << 0) | ((height - 1) << 16));
 210                 radeon_emit(cs, (slice_tile_max << 0) | (pipe_config << 26));
 211                 radeon_emit(cs, (tiled_x << 0) | (tiled_z << 18));
 212                 radeon_emit(cs, (tiled_y << 0) | (tile_split << 21) | (nbanks << 25) | (mt << 27));
 213                 radeon_emit(cs, addr & 0xfffffffc);
 214                 radeon_emit(cs, (addr >> 32UL) & 0xff);
 215                 copy_height -= cheight;
 216                 addr += cheight * pitch;
 217                 tiled_y += cheight;
 218         }
 219 }
 220
 221 static void si_dma_copy(struct pipe_context *ctx,
 222                         struct pipe_resource *dst,
 223                         unsigned dst_level,
 224                         unsigned dstx, unsigned dsty, unsigned dstz,
 225                         struct pipe_resource *src,
 226                         unsigned src_level,
 227                         const struct pipe_box *src_box)
 228 {
 229         struct si_context *sctx = (struct si_context *)ctx;
 230         struct r600_texture *rsrc = (struct r600_texture*)src;
 231         struct r600_texture *rdst = (struct r600_texture*)dst;
 232         unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode;
 233         unsigned src_w, dst_w;
 234         unsigned src_x, src_y;
 235         unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
 236
 237         if (sctx->b.dma.cs == NULL ||
 238             src->flags & PIPE_RESOURCE_FLAG_SPARSE ||
 239             dst->flags & PIPE_RESOURCE_FLAG_SPARSE) {
 240                 goto fallback;
 241         }
 242
 243         if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
 244                 si_dma_copy_buffer(sctx, dst, src, dst_x, src_box->x, src_box->width);
 245                 return;
 246         }
 247
 248         /* XXX: Using the asynchronous DMA engine for multi-dimensional
 249          * operations seems to cause random GPU lockups for various people.
 250          * While the root cause for this might need to be fixed in the kernel,
 251          * let's disable it for now.
 252          *
 253          * Before re-enabling this, please make sure you can hit all newly
 254          * enabled paths in your testing, preferably with both piglit and real
 255          * world apps, and get in touch with people on the bug reports below
 256          * for stability testing.
 257          *
 258          * https://bugs.freedesktop.org/show_bug.cgi?id=85647
 259          * https://bugs.freedesktop.org/show_bug.cgi?id=83500
 260          */
 261         goto fallback;
 262
 263         if (src_box->depth > 1 ||
 264             !r600_prepare_for_dma_blit(&sctx->b, rdst, dst_level, dstx, dsty,
 265                                         dstz, rsrc, src_level, src_box))
 266                 goto fallback;
 267
 268         src_x = util_format_get_nblocksx(src->format, src_box->x);
 269         dst_x = util_format_get_nblocksx(src->format, dst_x);
 270         src_y = util_format_get_nblocksy(src->format, src_box->y);
 271         dst_y = util_format_get_nblocksy(src->format, dst_y);
 272
 273         bpp = rdst->surface.bpe;
 274         dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe;
 275         src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe;
 276         src_w = u_minify(rsrc->resource.b.b.width0, src_level);
 277         dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
 278
 279         dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
 280         src_mode = rsrc->surface.u.legacy.level[src_level].mode;
 281
 282         if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w ||
 283             src_box->width != src_w ||
 284             src_box->height != u_minify(rsrc->resource.b.b.height0, src_level) ||
 285             src_box->height != u_minify(rdst->resource.b.b.height0, dst_level) ||
 286             rsrc->surface.u.legacy.level[src_level].nblk_y !=
 287             rdst->surface.u.legacy.level[dst_level].nblk_y) {
 288                 /* FIXME si can do partial blit */
 289                 goto fallback;
 290         }
 291         /* the x test here are currently useless (because we don't support partial blit)
 292          * but keep them around so we don't forget about those
 293          */
 294         if ((src_pitch % 8) || (src_box->x % 8) || (dst_x % 8) ||
 295             (src_box->y % 8) || (dst_y % 8) || (src_box->height % 8)) {
 296                 goto fallback;
 297         }
 298
 299         if (src_mode == dst_mode) {
 300                 uint64_t dst_offset, src_offset;
 301                 /* simple dma blit would do NOTE code here assume :
 302                  *   src_box.x/y == 0
 303                  *   dst_x/y == 0
 304                  *   dst_pitch == src_pitch
 305                  */
 306                 src_offset= rsrc->surface.u.legacy.level[src_level].offset;
 307                 src_offset += rsrc->surface.u.legacy.level[src_level].slice_size * src_box->z;
 308                 src_offset += src_y * src_pitch + src_x * bpp;
 309                 dst_offset = rdst->surface.u.legacy.level[dst_level].offset;
 310                 dst_offset += rdst->surface.u.legacy.level[dst_level].slice_size * dst_z;
 311                 dst_offset += dst_y * dst_pitch + dst_x * bpp;
 312                 si_dma_copy_buffer(sctx, dst, src, dst_offset, src_offset,
 313                                    rsrc->surface.u.legacy.level[src_level].slice_size);
 314         } else {
 315                 si_dma_copy_tile(sctx, dst, dst_level, dst_x, dst_y, dst_z,
 316                                  src, src_level, src_x, src_y, src_box->z,
 317                                  src_box->height / rsrc->surface.blk_h,
 318                                  dst_pitch, bpp);
 319         }
 320         return;
 321
 322 fallback:
 323         si_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
 324                                 src, src_level, src_box);
 325 }
 326
 327 void si_init_dma_functions(struct si_context *sctx)
 328 {
 329         sctx->b.dma_copy = si_dma_copy;
 330         sctx->b.dma_clear_buffer = si_dma_clear_buffer;
 331 }