src/gallium/drivers/radeonsi/si_dma.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26
  27 #include "sid.h"
  28 #include "si_pipe.h"
  29 #include "../radeon/r600_cs.h"
  30
  31 #include "util/u_format.h"
  32
  33 static unsigned si_array_mode(unsigned mode)
  34 {
  35         switch (mode) {
  36         case RADEON_SURF_MODE_LINEAR_ALIGNED:
  37                 return V_009910_ARRAY_LINEAR_ALIGNED;
  38         case RADEON_SURF_MODE_1D:
  39                 return V_009910_ARRAY_1D_TILED_THIN1;
  40         case RADEON_SURF_MODE_2D:
  41                 return V_009910_ARRAY_2D_TILED_THIN1;
  42         default:
  43         case RADEON_SURF_MODE_LINEAR:
  44                 return V_009910_ARRAY_LINEAR_GENERAL;
  45         }
  46 }
  47
  48 static uint32_t si_num_banks(uint32_t nbanks)
  49 {
  50         switch (nbanks) {
  51         case 2:
  52                 return V_009910_ADDR_SURF_2_BANK;
  53         case 4:
  54                 return V_009910_ADDR_SURF_4_BANK;
  55         case 8:
  56         default:
  57                 return V_009910_ADDR_SURF_8_BANK;
  58         case 16:
  59                 return V_009910_ADDR_SURF_16_BANK;
  60         }
  61 }
  62
  63 static uint32_t si_micro_tile_mode(struct si_screen *sscreen, unsigned tile_mode)
  64 {
  65         if (sscreen->b.info.si_tile_mode_array_valid) {
  66                 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
  67
  68                 return G_009910_MICRO_TILE_MODE(gb_tile_mode);
  69         }
  70
  71         /* The kernel cannod return the tile mode array. Guess? */
  72         return V_009910_ADDR_SURF_THIN_MICRO_TILING;
  73 }
  74
  75 static void si_dma_copy_buffer(struct si_context *ctx,
  76                                 struct pipe_resource *dst,
  77                                 struct pipe_resource *src,
  78                                 uint64_t dst_offset,
  79                                 uint64_t src_offset,
  80                                 uint64_t size)
  81 {
  82         struct radeon_winsys_cs *cs = ctx->b.rings.dma.cs;
  83         unsigned i, ncopy, csize, max_csize, sub_cmd, shift;
  84         struct r600_resource *rdst = (struct r600_resource*)dst;
  85         struct r600_resource *rsrc = (struct r600_resource*)src;
  86
  87         /* Mark the buffer range of destination as valid (initialized),
  88          * so that transfer_map knows it should wait for the GPU when mapping
  89          * that range. */
  90         util_range_add(&rdst->valid_buffer_range, dst_offset,
  91                        dst_offset + size);
  92
  93         dst_offset += r600_resource_va(&ctx->screen->b.b, dst);
  94         src_offset += r600_resource_va(&ctx->screen->b.b, src);
  95
  96         /* see if we use dword or byte copy */
  97         if (!(dst_offset % 4) && !(src_offset % 4) && !(size % 4)) {
  98                 size >>= 2;
  99                 sub_cmd = SI_DMA_COPY_DWORD_ALIGNED;
 100                 shift = 2;
 101                 max_csize = SI_DMA_COPY_MAX_SIZE_DW;
 102         } else {
 103                 sub_cmd = SI_DMA_COPY_BYTE_ALIGNED;
 104                 shift = 0;
 105                 max_csize = SI_DMA_COPY_MAX_SIZE;
 106         }
 107         ncopy = (size / max_csize) + !!(size % max_csize);
 108
 109         r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, rsrc, RADEON_USAGE_READ,
 110                               RADEON_PRIO_MIN);
 111         r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, rdst, RADEON_USAGE_WRITE,
 112                               RADEON_PRIO_MIN);
 113
 114         r600_need_dma_space(&ctx->b, ncopy * 5);
 115         for (i = 0; i < ncopy; i++) {
 116                 csize = size < max_csize ? size : max_csize;
 117                 cs->buf[cs->cdw++] = SI_DMA_PACKET(SI_DMA_PACKET_COPY, sub_cmd, csize);
 118                 cs->buf[cs->cdw++] = dst_offset & 0xffffffff;
 119                 cs->buf[cs->cdw++] = src_offset & 0xffffffff;
 120                 cs->buf[cs->cdw++] = (dst_offset >> 32UL) & 0xff;
 121                 cs->buf[cs->cdw++] = (src_offset >> 32UL) & 0xff;
 122                 dst_offset += csize << shift;
 123                 src_offset += csize << shift;
 124                 size -= csize;
 125         }
 126 }
 127
 128 static void si_dma_copy_tile(struct si_context *ctx,
 129                              struct pipe_resource *dst,
 130                              unsigned dst_level,
 131                              unsigned dst_x,
 132                              unsigned dst_y,
 133                              unsigned dst_z,
 134                              struct pipe_resource *src,
 135                              unsigned src_level,
 136                              unsigned src_x,
 137                              unsigned src_y,
 138                              unsigned src_z,
 139                              unsigned copy_height,
 140                              unsigned pitch,
 141                              unsigned bpp)
 142 {
 143         struct radeon_winsys_cs *cs = ctx->b.rings.dma.cs;
 144         struct si_screen *sscreen = ctx->screen;
 145         struct r600_texture *rsrc = (struct r600_texture*)src;
 146         struct r600_texture *rdst = (struct r600_texture*)dst;
 147         unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
 148         unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
 149         unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, mt;
 150         uint64_t base, addr;
 151         unsigned pipe_config, tile_mode_index;
 152
 153         dst_mode = rdst->surface.level[dst_level].mode;
 154         src_mode = rsrc->surface.level[src_level].mode;
 155         /* downcast linear aligned to linear to simplify test */
 156         src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
 157         dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
 158         assert(dst_mode != src_mode);
 159
 160         y = 0;
 161         sub_cmd = SI_DMA_COPY_TILED;
 162         lbpp = util_logbase2(bpp);
 163         pitch_tile_max = ((pitch / bpp) / 8) - 1;
 164         nbanks = si_num_banks(ctx->screen->b.tiling_info.num_banks);
 165
 166         if (dst_mode == RADEON_SURF_MODE_LINEAR) {
 167                 /* T2L */
 168                 array_mode = si_array_mode(src_mode);
 169                 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
 170                 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
 171                 /* linear height must be the same as the slice tile max height, it's ok even
 172                  * if the linear destination/source have smaller heigh as the size of the
 173                  * dma packet will be using the copy_height which is always smaller or equal
 174                  * to the linear height
 175                  */
 176                 height = rsrc->surface.level[src_level].npix_y;
 177                 detile = 1;
 178                 x = src_x;
 179                 y = src_y;
 180                 z = src_z;
 181                 base = rsrc->surface.level[src_level].offset;
 182                 addr = rdst->surface.level[dst_level].offset;
 183                 addr += rdst->surface.level[dst_level].slice_size * dst_z;
 184                 addr += dst_y * pitch + dst_x * bpp;
 185                 bank_h = cik_bank_wh(rsrc->surface.bankh);
 186                 bank_w = cik_bank_wh(rsrc->surface.bankw);
 187                 mt_aspect = cik_macro_tile_aspect(rsrc->surface.mtilea);
 188                 tile_split = cik_tile_split(rsrc->surface.tile_split);
 189                 tile_mode_index = si_tile_mode_index(rsrc, src_level,
 190                                                      util_format_has_stencil(util_format_description(src->format)));
 191                 base += r600_resource_va(&ctx->screen->b.b, src);
 192                 addr += r600_resource_va(&ctx->screen->b.b, dst);
 193         } else {
 194                 /* L2T */
 195                 array_mode = si_array_mode(dst_mode);
 196                 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
 197                 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
 198                 /* linear height must be the same as the slice tile max height, it's ok even
 199                  * if the linear destination/source have smaller heigh as the size of the
 200                  * dma packet will be using the copy_height which is always smaller or equal
 201                  * to the linear height
 202                  */
 203                 height = rdst->surface.level[dst_level].npix_y;
 204                 detile = 0;
 205                 x = dst_x;
 206                 y = dst_y;
 207                 z = dst_z;
 208                 base = rdst->surface.level[dst_level].offset;
 209                 addr = rsrc->surface.level[src_level].offset;
 210                 addr += rsrc->surface.level[src_level].slice_size * src_z;
 211                 addr += src_y * pitch + src_x * bpp;
 212                 bank_h = cik_bank_wh(rdst->surface.bankh);
 213                 bank_w = cik_bank_wh(rdst->surface.bankw);
 214                 mt_aspect = cik_macro_tile_aspect(rdst->surface.mtilea);
 215                 tile_split = cik_tile_split(rdst->surface.tile_split);
 216                 tile_mode_index = si_tile_mode_index(rdst, dst_level,
 217                                                      util_format_has_stencil(util_format_description(dst->format)));
 218                 base += r600_resource_va(&ctx->screen->b.b, dst);
 219                 addr += r600_resource_va(&ctx->screen->b.b, src);
 220         }
 221
 222         pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
 223         mt = si_micro_tile_mode(sscreen, tile_mode_index);
 224         size = (copy_height * pitch) / 4;
 225         ncopy = (size / SI_DMA_COPY_MAX_SIZE_DW) + !!(size % SI_DMA_COPY_MAX_SIZE_DW);
 226         r600_need_dma_space(&ctx->b, ncopy * 9);
 227
 228         r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, &rsrc->resource,
 229                               RADEON_USAGE_READ, RADEON_PRIO_MIN);
 230         r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, &rdst->resource,
 231                               RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
 232
 233         for (i = 0; i < ncopy; i++) {
 234                 cheight = copy_height;
 235                 if (((cheight * pitch) / 4) > SI_DMA_COPY_MAX_SIZE_DW) {
 236                         cheight = (SI_DMA_COPY_MAX_SIZE_DW * 4) / pitch;
 237                 }
 238                 size = (cheight * pitch) / 4;
 239                 cs->buf[cs->cdw++] = SI_DMA_PACKET(SI_DMA_PACKET_COPY, sub_cmd, size);
 240                 cs->buf[cs->cdw++] = base >> 8;
 241                 cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
 242                                         (lbpp << 24) | (bank_h << 21) |
 243                                         (bank_w << 18) | (mt_aspect << 16);
 244                 cs->buf[cs->cdw++] = (pitch_tile_max << 0) | ((height - 1) << 16);
 245                 cs->buf[cs->cdw++] = (slice_tile_max << 0) | (pipe_config << 26);
 246                 cs->buf[cs->cdw++] = (x << 0) | (z << 18);
 247                 cs->buf[cs->cdw++] = (y << 0) | (tile_split << 21) | (nbanks << 25) | (mt << 27);
 248                 cs->buf[cs->cdw++] = addr & 0xfffffffc;
 249                 cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff;
 250                 copy_height -= cheight;
 251                 addr += cheight * pitch;
 252                 y += cheight;
 253         }
 254 }
 255
 256 void si_dma_copy(struct pipe_context *ctx,
 257                  struct pipe_resource *dst,
 258                  unsigned dst_level,
 259                  unsigned dstx, unsigned dsty, unsigned dstz,
 260                  struct pipe_resource *src,
 261                  unsigned src_level,
 262                  const struct pipe_box *src_box)
 263 {
 264         struct si_context *sctx = (struct si_context *)ctx;
 265         struct r600_texture *rsrc = (struct r600_texture*)src;
 266         struct r600_texture *rdst = (struct r600_texture*)dst;
 267         unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
 268         unsigned src_w, dst_w;
 269         unsigned src_x, src_y;
 270         unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
 271
 272         if (sctx->b.rings.dma.cs == NULL) {
 273                 goto fallback;
 274         }
 275
 276         /* TODO: Implement DMA copy for CIK */
 277         if (sctx->b.chip_class >= CIK) {
 278                 goto fallback;
 279         }
 280
 281         if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
 282                 si_dma_copy_buffer(sctx, dst, src, dst_x, src_box->x, src_box->width);
 283                 return;
 284         }
 285
 286         if (src->format != dst->format || src_box->depth > 1 ||
 287             rdst->dirty_level_mask != 0) {
 288                 goto fallback;
 289         }
 290
 291         if (rsrc->dirty_level_mask) {
 292                 ctx->flush_resource(ctx, src);
 293         }
 294
 295         src_x = util_format_get_nblocksx(src->format, src_box->x);
 296         dst_x = util_format_get_nblocksx(src->format, dst_x);
 297         src_y = util_format_get_nblocksy(src->format, src_box->y);
 298         dst_y = util_format_get_nblocksy(src->format, dst_y);
 299
 300         bpp = rdst->surface.bpe;
 301         dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
 302         src_pitch = rsrc->surface.level[src_level].pitch_bytes;
 303         src_w = rsrc->surface.level[src_level].npix_x;
 304         dst_w = rdst->surface.level[dst_level].npix_x;
 305         copy_height = src_box->height / rsrc->surface.blk_h;
 306
 307         dst_mode = rdst->surface.level[dst_level].mode;
 308         src_mode = rsrc->surface.level[src_level].mode;
 309         /* downcast linear aligned to linear to simplify test */
 310         src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
 311         dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
 312
 313         if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
 314                 /* FIXME si can do partial blit */
 315                 goto fallback;
 316         }
 317         /* the x test here are currently useless (because we don't support partial blit)
 318          * but keep them around so we don't forget about those
 319          */
 320         if ((src_pitch % 8) || (src_box->x % 8) || (dst_x % 8) || (src_box->y % 8) || (dst_y % 8)) {
 321                 goto fallback;
 322         }
 323
 324         if (src_mode == dst_mode) {
 325                 uint64_t dst_offset, src_offset;
 326                 /* simple dma blit would do NOTE code here assume :
 327                  *   src_box.x/y == 0
 328                  *   dst_x/y == 0
 329                  *   dst_pitch == src_pitch
 330                  */
 331                 src_offset= rsrc->surface.level[src_level].offset;
 332                 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
 333                 src_offset += src_y * src_pitch + src_x * bpp;
 334                 dst_offset = rdst->surface.level[dst_level].offset;
 335                 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
 336                 dst_offset += dst_y * dst_pitch + dst_x * bpp;
 337                 si_dma_copy_buffer(sctx, dst, src, dst_offset, src_offset,
 338                             src_box->height * src_pitch);
 339         } else {
 340                 si_dma_copy_tile(sctx, dst, dst_level, dst_x, dst_y, dst_z,
 341                                  src, src_level, src_x, src_y, src_box->z,
 342                                  copy_height, dst_pitch, bpp);
 343         }
 344         return;
 345
 346 fallback:
 347         ctx->resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
 348                                   src, src_level, src_box);
 349 }