2 * Copyright 2013-2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "util/os_time.h"
29 #include "util/u_memory.h"
30 #include "util/u_queue.h"
31 #include "util/u_upload_mgr.h"
33 #include "si_build_pm4.h"
35 struct si_fine_fence
{
36 struct si_resource
*buf
;
40 struct si_multi_fence
{
41 struct pipe_reference reference
;
42 struct pipe_fence_handle
*gfx
;
43 struct pipe_fence_handle
*sdma
;
44 struct tc_unflushed_batch_token
*tc_token
;
45 struct util_queue_fence ready
;
47 /* If the context wasn't flushed at fence creation, this is non-NULL. */
49 struct si_context
*ctx
;
53 struct si_fine_fence fine
;
59 * \param event EVENT_TYPE_*
60 * \param event_flags Optional cache flush flags (TC)
61 * \param dst_sel MEM or TC_L2
62 * \param int_sel NONE or SEND_DATA_AFTER_WR_CONFIRM
63 * \param data_sel DISCARD, VALUE_32BIT, TIMESTAMP, or GDS
65 * \param va GPU address
66 * \param old_value Previous fence value (for a bug workaround)
67 * \param new_value Fence value to write for this event.
69 void si_cp_release_mem(struct si_context
*ctx
, struct radeon_cmdbuf
*cs
,
70 unsigned event
, unsigned event_flags
,
71 unsigned dst_sel
, unsigned int_sel
, unsigned data_sel
,
72 struct si_resource
*buf
, uint64_t va
,
73 uint32_t new_fence
, unsigned query_type
)
75 unsigned op
= EVENT_TYPE(event
) |
76 EVENT_INDEX(event
== V_028A90_CS_DONE
||
77 event
== V_028A90_PS_DONE
? 6 : 5) |
79 unsigned sel
= EOP_DST_SEL(dst_sel
) |
80 EOP_INT_SEL(int_sel
) |
81 EOP_DATA_SEL(data_sel
);
82 bool compute_ib
= !ctx
->has_graphics
||
83 cs
== ctx
->prim_discard_compute_cs
;
85 if (ctx
->chip_class
>= GFX9
||
86 (compute_ib
&& ctx
->chip_class
>= GFX7
)) {
87 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
88 * counters) must immediately precede every timestamp event to
89 * prevent a GPU hang on GFX9.
91 * Occlusion queries don't need to do it here, because they
92 * always do ZPASS_DONE before the timestamp.
94 if (ctx
->chip_class
== GFX9
&& !compute_ib
&&
95 query_type
!= PIPE_QUERY_OCCLUSION_COUNTER
&&
96 query_type
!= PIPE_QUERY_OCCLUSION_PREDICATE
&&
97 query_type
!= PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
) {
98 struct si_resource
*scratch
= ctx
->eop_bug_scratch
;
100 assert(16 * ctx
->screen
->info
.num_render_backends
<=
101 scratch
->b
.b
.width0
);
102 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
103 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE
) | EVENT_INDEX(1));
104 radeon_emit(cs
, scratch
->gpu_address
);
105 radeon_emit(cs
, scratch
->gpu_address
>> 32);
107 radeon_add_to_buffer_list(ctx
, ctx
->gfx_cs
, scratch
,
108 RADEON_USAGE_WRITE
, RADEON_PRIO_QUERY
);
111 radeon_emit(cs
, PKT3(PKT3_RELEASE_MEM
, ctx
->chip_class
>= GFX9
? 6 : 5, 0));
113 radeon_emit(cs
, sel
);
114 radeon_emit(cs
, va
); /* address lo */
115 radeon_emit(cs
, va
>> 32); /* address hi */
116 radeon_emit(cs
, new_fence
); /* immediate data lo */
117 radeon_emit(cs
, 0); /* immediate data hi */
118 if (ctx
->chip_class
>= GFX9
)
119 radeon_emit(cs
, 0); /* unused */
121 if (ctx
->chip_class
== GFX7
||
122 ctx
->chip_class
== GFX8
) {
123 struct si_resource
*scratch
= ctx
->eop_bug_scratch
;
124 uint64_t va
= scratch
->gpu_address
;
126 /* Two EOP events are required to make all engines go idle
127 * (and optional cache flushes executed) before the timestamp
130 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, 0));
133 radeon_emit(cs
, ((va
>> 32) & 0xffff) | sel
);
134 radeon_emit(cs
, 0); /* immediate data */
135 radeon_emit(cs
, 0); /* unused */
137 radeon_add_to_buffer_list(ctx
, ctx
->gfx_cs
, scratch
,
138 RADEON_USAGE_WRITE
, RADEON_PRIO_QUERY
);
141 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, 0));
144 radeon_emit(cs
, ((va
>> 32) & 0xffff) | sel
);
145 radeon_emit(cs
, new_fence
); /* immediate data */
146 radeon_emit(cs
, 0); /* unused */
150 radeon_add_to_buffer_list(ctx
, ctx
->gfx_cs
, buf
, RADEON_USAGE_WRITE
,
155 unsigned si_cp_write_fence_dwords(struct si_screen
*screen
)
159 if (screen
->info
.chip_class
== GFX7
||
160 screen
->info
.chip_class
== GFX8
)
166 void si_cp_wait_mem(struct si_context
*ctx
, struct radeon_cmdbuf
*cs
,
167 uint64_t va
, uint32_t ref
, uint32_t mask
, unsigned flags
)
169 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
170 radeon_emit(cs
, WAIT_REG_MEM_MEM_SPACE(1) | flags
);
172 radeon_emit(cs
, va
>> 32);
173 radeon_emit(cs
, ref
); /* reference value */
174 radeon_emit(cs
, mask
); /* mask */
175 radeon_emit(cs
, 4); /* poll interval */
178 static void si_add_fence_dependency(struct si_context
*sctx
,
179 struct pipe_fence_handle
*fence
)
181 struct radeon_winsys
*ws
= sctx
->ws
;
184 ws
->cs_add_fence_dependency(sctx
->dma_cs
, fence
, 0);
185 ws
->cs_add_fence_dependency(sctx
->gfx_cs
, fence
, 0);
188 static void si_add_syncobj_signal(struct si_context
*sctx
,
189 struct pipe_fence_handle
*fence
)
191 sctx
->ws
->cs_add_syncobj_signal(sctx
->gfx_cs
, fence
);
194 static void si_fence_reference(struct pipe_screen
*screen
,
195 struct pipe_fence_handle
**dst
,
196 struct pipe_fence_handle
*src
)
198 struct radeon_winsys
*ws
= ((struct si_screen
*)screen
)->ws
;
199 struct si_multi_fence
**sdst
= (struct si_multi_fence
**)dst
;
200 struct si_multi_fence
*ssrc
= (struct si_multi_fence
*)src
;
202 if (pipe_reference(&(*sdst
)->reference
, &ssrc
->reference
)) {
203 ws
->fence_reference(&(*sdst
)->gfx
, NULL
);
204 ws
->fence_reference(&(*sdst
)->sdma
, NULL
);
205 tc_unflushed_batch_token_reference(&(*sdst
)->tc_token
, NULL
);
206 si_resource_reference(&(*sdst
)->fine
.buf
, NULL
);
212 static struct si_multi_fence
*si_create_multi_fence()
214 struct si_multi_fence
*fence
= CALLOC_STRUCT(si_multi_fence
);
218 pipe_reference_init(&fence
->reference
, 1);
219 util_queue_fence_init(&fence
->ready
);
224 struct pipe_fence_handle
*si_create_fence(struct pipe_context
*ctx
,
225 struct tc_unflushed_batch_token
*tc_token
)
227 struct si_multi_fence
*fence
= si_create_multi_fence();
231 util_queue_fence_reset(&fence
->ready
);
232 tc_unflushed_batch_token_reference(&fence
->tc_token
, tc_token
);
234 return (struct pipe_fence_handle
*)fence
;
237 static bool si_fine_fence_signaled(struct radeon_winsys
*rws
,
238 const struct si_fine_fence
*fine
)
240 char *map
= rws
->buffer_map(fine
->buf
->buf
, NULL
, PIPE_TRANSFER_READ
|
241 PIPE_TRANSFER_UNSYNCHRONIZED
);
245 uint32_t *fence
= (uint32_t*)(map
+ fine
->offset
);
249 static void si_fine_fence_set(struct si_context
*ctx
,
250 struct si_fine_fence
*fine
,
255 assert(util_bitcount(flags
& (PIPE_FLUSH_TOP_OF_PIPE
| PIPE_FLUSH_BOTTOM_OF_PIPE
)) == 1);
257 /* Use cached system memory for the fence. */
258 u_upload_alloc(ctx
->cached_gtt_allocator
, 0, 4, 4,
259 &fine
->offset
, (struct pipe_resource
**)&fine
->buf
, (void **)&fence_ptr
);
265 if (flags
& PIPE_FLUSH_TOP_OF_PIPE
) {
266 uint32_t value
= 0x80000000;
268 si_cp_write_data(ctx
, fine
->buf
, fine
->offset
, 4,
269 V_370_MEM
, V_370_PFP
, &value
);
270 } else if (flags
& PIPE_FLUSH_BOTTOM_OF_PIPE
) {
271 uint64_t fence_va
= fine
->buf
->gpu_address
+ fine
->offset
;
273 radeon_add_to_buffer_list(ctx
, ctx
->gfx_cs
, fine
->buf
,
274 RADEON_USAGE_WRITE
, RADEON_PRIO_QUERY
);
275 si_cp_release_mem(ctx
, ctx
->gfx_cs
,
276 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
277 EOP_DST_SEL_MEM
, EOP_INT_SEL_NONE
,
278 EOP_DATA_SEL_VALUE_32BIT
,
279 NULL
, fence_va
, 0x80000000,
280 PIPE_QUERY_GPU_FINISHED
);
286 static bool si_fence_finish(struct pipe_screen
*screen
,
287 struct pipe_context
*ctx
,
288 struct pipe_fence_handle
*fence
,
291 struct radeon_winsys
*rws
= ((struct si_screen
*)screen
)->ws
;
292 struct si_multi_fence
*sfence
= (struct si_multi_fence
*)fence
;
293 struct si_context
*sctx
;
294 int64_t abs_timeout
= os_time_get_absolute_timeout(timeout
);
296 ctx
= threaded_context_unwrap_sync(ctx
);
297 sctx
= (struct si_context
*)(ctx
? ctx
: NULL
);
299 if (!util_queue_fence_is_signalled(&sfence
->ready
)) {
300 if (sfence
->tc_token
) {
301 /* Ensure that si_flush_from_st will be called for
302 * this fence, but only if we're in the API thread
303 * where the context is current.
305 * Note that the batch containing the flush may already
306 * be in flight in the driver thread, so the fence
307 * may not be ready yet when this call returns.
309 threaded_context_flush(ctx
, sfence
->tc_token
,
316 if (timeout
== PIPE_TIMEOUT_INFINITE
) {
317 util_queue_fence_wait(&sfence
->ready
);
319 if (!util_queue_fence_wait_timeout(&sfence
->ready
, abs_timeout
))
323 if (timeout
&& timeout
!= PIPE_TIMEOUT_INFINITE
) {
324 int64_t time
= os_time_get_nano();
325 timeout
= abs_timeout
> time
? abs_timeout
- time
: 0;
330 if (!rws
->fence_wait(rws
, sfence
->sdma
, timeout
))
333 /* Recompute the timeout after waiting. */
334 if (timeout
&& timeout
!= PIPE_TIMEOUT_INFINITE
) {
335 int64_t time
= os_time_get_nano();
336 timeout
= abs_timeout
> time
? abs_timeout
- time
: 0;
343 if (sfence
->fine
.buf
&&
344 si_fine_fence_signaled(rws
, &sfence
->fine
)) {
345 rws
->fence_reference(&sfence
->gfx
, NULL
);
346 si_resource_reference(&sfence
->fine
.buf
, NULL
);
350 /* Flush the gfx IB if it hasn't been flushed yet. */
351 if (sctx
&& sfence
->gfx_unflushed
.ctx
== sctx
&&
352 sfence
->gfx_unflushed
.ib_index
== sctx
->num_gfx_cs_flushes
) {
353 /* Section 4.1.2 (Signaling) of the OpenGL 4.6 (Core profile)
356 * "If the sync object being blocked upon will not be
357 * signaled in finite time (for example, by an associated
358 * fence command issued previously, but not yet flushed to
359 * the graphics pipeline), then ClientWaitSync may hang
360 * forever. To help prevent this behavior, if
361 * ClientWaitSync is called and all of the following are
364 * * the SYNC_FLUSH_COMMANDS_BIT bit is set in flags,
365 * * sync is unsignaled when ClientWaitSync is called,
366 * * and the calls to ClientWaitSync and FenceSync were
367 * issued from the same context,
369 * then the GL will behave as if the equivalent of Flush
370 * were inserted immediately after the creation of sync."
372 * This means we need to flush for such fences even when we're
375 si_flush_gfx_cs(sctx
,
376 (timeout
? 0 : PIPE_FLUSH_ASYNC
) |
377 RADEON_FLUSH_START_NEXT_GFX_IB_NOW
,
379 sfence
->gfx_unflushed
.ctx
= NULL
;
384 /* Recompute the timeout after all that. */
385 if (timeout
&& timeout
!= PIPE_TIMEOUT_INFINITE
) {
386 int64_t time
= os_time_get_nano();
387 timeout
= abs_timeout
> time
? abs_timeout
- time
: 0;
391 if (rws
->fence_wait(rws
, sfence
->gfx
, timeout
))
394 /* Re-check in case the GPU is slow or hangs, but the commands before
395 * the fine-grained fence have completed. */
396 if (sfence
->fine
.buf
&&
397 si_fine_fence_signaled(rws
, &sfence
->fine
))
403 static void si_create_fence_fd(struct pipe_context
*ctx
,
404 struct pipe_fence_handle
**pfence
, int fd
,
405 enum pipe_fd_type type
)
407 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
408 struct radeon_winsys
*ws
= sscreen
->ws
;
409 struct si_multi_fence
*sfence
;
413 sfence
= si_create_multi_fence();
418 case PIPE_FD_TYPE_NATIVE_SYNC
:
419 if (!sscreen
->info
.has_fence_to_handle
)
422 sfence
->gfx
= ws
->fence_import_sync_file(ws
, fd
);
425 case PIPE_FD_TYPE_SYNCOBJ
:
426 if (!sscreen
->info
.has_syncobj
)
429 sfence
->gfx
= ws
->fence_import_syncobj(ws
, fd
);
433 unreachable("bad fence fd type when importing");
442 *pfence
= (struct pipe_fence_handle
*)sfence
;
445 static int si_fence_get_fd(struct pipe_screen
*screen
,
446 struct pipe_fence_handle
*fence
)
448 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
449 struct radeon_winsys
*ws
= sscreen
->ws
;
450 struct si_multi_fence
*sfence
= (struct si_multi_fence
*)fence
;
451 int gfx_fd
= -1, sdma_fd
= -1;
453 if (!sscreen
->info
.has_fence_to_handle
)
456 util_queue_fence_wait(&sfence
->ready
);
458 /* Deferred fences aren't supported. */
459 assert(!sfence
->gfx_unflushed
.ctx
);
460 if (sfence
->gfx_unflushed
.ctx
)
464 sdma_fd
= ws
->fence_export_sync_file(ws
, sfence
->sdma
);
469 gfx_fd
= ws
->fence_export_sync_file(ws
, sfence
->gfx
);
477 /* If we don't have FDs at this point, it means we don't have fences
479 if (sdma_fd
== -1 && gfx_fd
== -1)
480 return ws
->export_signalled_sync_file(ws
);
486 /* Get a fence that will be a combination of both fences. */
487 sync_accumulate("radeonsi", &gfx_fd
, sdma_fd
);
492 static void si_flush_from_st(struct pipe_context
*ctx
,
493 struct pipe_fence_handle
**fence
,
496 struct pipe_screen
*screen
= ctx
->screen
;
497 struct si_context
*sctx
= (struct si_context
*)ctx
;
498 struct radeon_winsys
*ws
= sctx
->ws
;
499 struct pipe_fence_handle
*gfx_fence
= NULL
;
500 struct pipe_fence_handle
*sdma_fence
= NULL
;
501 bool deferred_fence
= false;
502 struct si_fine_fence fine
= {};
503 unsigned rflags
= PIPE_FLUSH_ASYNC
;
505 if (flags
& PIPE_FLUSH_END_OF_FRAME
)
506 rflags
|= PIPE_FLUSH_END_OF_FRAME
;
508 if (flags
& (PIPE_FLUSH_TOP_OF_PIPE
| PIPE_FLUSH_BOTTOM_OF_PIPE
)) {
509 assert(flags
& PIPE_FLUSH_DEFERRED
);
512 si_fine_fence_set(sctx
, &fine
, flags
);
515 /* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
517 si_flush_dma_cs(sctx
, rflags
, fence
? &sdma_fence
: NULL
);
519 if (!radeon_emitted(sctx
->gfx_cs
, sctx
->initial_gfx_cs_size
)) {
521 ws
->fence_reference(&gfx_fence
, sctx
->last_gfx_fence
);
522 if (!(flags
& PIPE_FLUSH_DEFERRED
))
523 ws
->cs_sync_flush(sctx
->gfx_cs
);
525 /* Instead of flushing, create a deferred fence. Constraints:
526 * - The state tracker must allow a deferred flush.
527 * - The state tracker must request a fence.
528 * - fence_get_fd is not allowed.
529 * Thread safety in fence_finish must be ensured by the state tracker.
531 if (flags
& PIPE_FLUSH_DEFERRED
&&
532 !(flags
& PIPE_FLUSH_FENCE_FD
) &&
534 gfx_fence
= sctx
->ws
->cs_get_next_fence(sctx
->gfx_cs
);
535 deferred_fence
= true;
537 si_flush_gfx_cs(sctx
, rflags
, fence
? &gfx_fence
: NULL
);
541 /* Both engines can signal out of order, so we need to keep both fences. */
543 struct si_multi_fence
*multi_fence
;
545 if (flags
& TC_FLUSH_ASYNC
) {
546 multi_fence
= (struct si_multi_fence
*)*fence
;
549 multi_fence
= si_create_multi_fence();
551 ws
->fence_reference(&sdma_fence
, NULL
);
552 ws
->fence_reference(&gfx_fence
, NULL
);
556 screen
->fence_reference(screen
, fence
, NULL
);
557 *fence
= (struct pipe_fence_handle
*)multi_fence
;
560 /* If both fences are NULL, fence_finish will always return true. */
561 multi_fence
->gfx
= gfx_fence
;
562 multi_fence
->sdma
= sdma_fence
;
564 if (deferred_fence
) {
565 multi_fence
->gfx_unflushed
.ctx
= sctx
;
566 multi_fence
->gfx_unflushed
.ib_index
= sctx
->num_gfx_cs_flushes
;
569 multi_fence
->fine
= fine
;
572 if (flags
& TC_FLUSH_ASYNC
) {
573 util_queue_fence_signal(&multi_fence
->ready
);
574 tc_unflushed_batch_token_reference(&multi_fence
->tc_token
, NULL
);
579 if (!(flags
& (PIPE_FLUSH_DEFERRED
| PIPE_FLUSH_ASYNC
))) {
581 ws
->cs_sync_flush(sctx
->dma_cs
);
582 ws
->cs_sync_flush(sctx
->gfx_cs
);
586 static void si_fence_server_signal(struct pipe_context
*ctx
,
587 struct pipe_fence_handle
*fence
)
589 struct si_context
*sctx
= (struct si_context
*)ctx
;
590 struct si_multi_fence
*sfence
= (struct si_multi_fence
*)fence
;
592 /* We should have at least one syncobj to signal */
593 assert(sfence
->sdma
|| sfence
->gfx
);
596 si_add_syncobj_signal(sctx
, sfence
->sdma
);
598 si_add_syncobj_signal(sctx
, sfence
->gfx
);
601 * The spec does not require a flush here. We insert a flush
602 * because syncobj based signals are not directly placed into
603 * the command stream. Instead the signal happens when the
604 * submission associated with the syncobj finishes execution.
606 * Therefore, we must make sure that we flush the pipe to avoid
607 * new work being emitted and getting executed before the signal
610 si_flush_from_st(ctx
, NULL
, PIPE_FLUSH_ASYNC
);
613 static void si_fence_server_sync(struct pipe_context
*ctx
,
614 struct pipe_fence_handle
*fence
)
616 struct si_context
*sctx
= (struct si_context
*)ctx
;
617 struct si_multi_fence
*sfence
= (struct si_multi_fence
*)fence
;
619 util_queue_fence_wait(&sfence
->ready
);
621 /* Unflushed fences from the same context are no-ops. */
622 if (sfence
->gfx_unflushed
.ctx
&&
623 sfence
->gfx_unflushed
.ctx
== sctx
)
626 /* All unflushed commands will not start execution before
627 * this fence dependency is signalled.
629 * Therefore we must flush before inserting the dependency
631 si_flush_from_st(ctx
, NULL
, PIPE_FLUSH_ASYNC
);
634 si_add_fence_dependency(sctx
, sfence
->sdma
);
636 si_add_fence_dependency(sctx
, sfence
->gfx
);
639 void si_init_fence_functions(struct si_context
*ctx
)
641 ctx
->b
.flush
= si_flush_from_st
;
642 ctx
->b
.create_fence_fd
= si_create_fence_fd
;
643 ctx
->b
.fence_server_sync
= si_fence_server_sync
;
644 ctx
->b
.fence_server_signal
= si_fence_server_signal
;
647 void si_init_screen_fence_functions(struct si_screen
*screen
)
649 screen
->b
.fence_finish
= si_fence_finish
;
650 screen
->b
.fence_reference
= si_fence_reference
;
651 screen
->b
.fence_get_fd
= si_fence_get_fd
;