2 * Copyright 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "compiler/nir/nir.h"
26 #include "radeon/radeon_uvd_enc.h"
27 #include "radeon/radeon_vce.h"
28 #include "radeon/radeon_video.h"
30 #include "util/u_screen.h"
31 #include "util/u_video.h"
32 #include "vl/vl_decoder.h"
33 #include "vl/vl_video_buffer.h"
34 #include <sys/utsname.h>
36 static const char *si_get_vendor(struct pipe_screen
*pscreen
)
38 /* Don't change this. Games such as Alien Isolation are broken if this
39 * returns "Advanced Micro Devices, Inc."
44 static const char *si_get_device_vendor(struct pipe_screen
*pscreen
)
49 static int si_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
51 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
54 /* Supported features (boolean caps). */
55 case PIPE_CAP_ACCELERATED
:
56 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
57 case PIPE_CAP_ANISOTROPIC_FILTER
:
58 case PIPE_CAP_POINT_SPRITE
:
59 case PIPE_CAP_OCCLUSION_QUERY
:
60 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
61 case PIPE_CAP_TEXTURE_SHADOW_LOD
:
62 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE
:
63 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
64 case PIPE_CAP_TEXTURE_SWIZZLE
:
65 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
66 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE
:
67 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
68 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
69 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
70 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
71 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
72 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
73 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
74 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES
:
75 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
76 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
77 case PIPE_CAP_PRIMITIVE_RESTART
:
78 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX
:
79 case PIPE_CAP_CONDITIONAL_RENDER
:
80 case PIPE_CAP_TEXTURE_BARRIER
:
81 case PIPE_CAP_INDEP_BLEND_ENABLE
:
82 case PIPE_CAP_INDEP_BLEND_FUNC
:
83 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
84 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
85 case PIPE_CAP_START_INSTANCE
:
86 case PIPE_CAP_NPOT_TEXTURES
:
87 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
88 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
89 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
90 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
91 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
92 case PIPE_CAP_TGSI_INSTANCEID
:
93 case PIPE_CAP_COMPUTE
:
94 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
95 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
96 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
97 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
98 case PIPE_CAP_CUBE_MAP_ARRAY
:
99 case PIPE_CAP_SAMPLE_SHADING
:
100 case PIPE_CAP_DRAW_INDIRECT
:
101 case PIPE_CAP_CLIP_HALFZ
:
102 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
103 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
104 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
105 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
106 case PIPE_CAP_TGSI_TEXCOORD
:
107 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
108 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
109 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
110 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
111 case PIPE_CAP_SHAREABLE_SHADERS
:
112 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
113 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
114 case PIPE_CAP_TEXTURE_QUERY_LOD
:
115 case PIPE_CAP_TEXTURE_GATHER_SM5
:
116 case PIPE_CAP_TGSI_TXQS
:
117 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
118 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
119 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
120 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
121 case PIPE_CAP_INVALIDATE_BUFFER
:
122 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
123 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
124 case PIPE_CAP_QUERY_MEMORY_INFO
:
125 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
126 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
127 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
128 case PIPE_CAP_GENERATE_MIPMAP
:
129 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
130 case PIPE_CAP_STRING_MARKER
:
131 case PIPE_CAP_CLEAR_TEXTURE
:
132 case PIPE_CAP_CULL_DISTANCE
:
133 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
134 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
135 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
136 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
137 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
138 case PIPE_CAP_DOUBLES
:
139 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
140 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
141 case PIPE_CAP_BINDLESS_TEXTURE
:
142 case PIPE_CAP_QUERY_TIMESTAMP
:
143 case PIPE_CAP_QUERY_TIME_ELAPSED
:
144 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
145 case PIPE_CAP_MEMOBJ
:
146 case PIPE_CAP_LOAD_CONSTBUF
:
148 case PIPE_CAP_INT64_DIVMOD
:
149 case PIPE_CAP_TGSI_CLOCK
:
150 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
151 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
152 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
153 case PIPE_CAP_TGSI_BALLOT
:
154 case PIPE_CAP_TGSI_VOTE
:
155 case PIPE_CAP_FBFETCH
:
156 case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK
:
157 case PIPE_CAP_IMAGE_LOAD_FORMATTED
:
158 case PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA
:
159 case PIPE_CAP_TGSI_DIV
:
160 case PIPE_CAP_PACKED_UNIFORMS
:
161 case PIPE_CAP_SHADER_SAMPLES_IDENTICAL
:
162 case PIPE_CAP_GL_SPIRV
:
163 case PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES
:
164 case PIPE_CAP_ALPHA_TO_COVERAGE_DITHER_CONTROL
:
165 case PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE
:
166 case PIPE_CAP_NO_CLIP_ON_COPY_TEX
:
169 case PIPE_CAP_GLSL_ZERO_INIT
:
172 case PIPE_CAP_QUERY_SO_OVERFLOW
:
173 return !sscreen
->use_ngg_streamout
;
175 case PIPE_CAP_POST_DEPTH_COVERAGE
:
176 return sscreen
->info
.chip_class
>= GFX10
;
178 case PIPE_CAP_GRAPHICS
:
179 return sscreen
->info
.has_graphics
;
181 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
182 return !SI_BIG_ENDIAN
&& sscreen
->info
.has_userptr
;
184 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
185 return sscreen
->info
.has_gpu_reset_status_query
;
187 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
188 return sscreen
->info
.has_2d_tiling
;
190 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
191 return SI_MAP_BUFFER_ALIGNMENT
;
193 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
194 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
195 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
196 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
197 case PIPE_CAP_MAX_VERTEX_STREAMS
:
198 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
199 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
202 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
203 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
204 if (!sscreen
->info
.has_indirect_compute_dispatch
)
208 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET
:
209 /* Optimal number for good TexSubImage performance on Polaris10. */
210 return 64 * 1024 * 1024;
212 case PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE
:
215 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
216 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE
:
217 /* Align it down to 256 bytes. I've chosen the number randomly. */
218 return ROUND_DOWN_TO(MIN2(sscreen
->info
.max_alloc_size
, INT_MAX
), 256);
220 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
221 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
222 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
223 return LLVM_VERSION_MAJOR
< 9 && !sscreen
->info
.has_unaligned_shader_loads
;
225 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
226 return sscreen
->info
.has_sparse_vm_mappings
? RADEON_SPARSE_PAGE_SIZE
: 0;
229 case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF
:
232 case PIPE_CAP_FENCE_SIGNAL
:
233 return sscreen
->info
.has_syncobj
;
235 case PIPE_CAP_CONSTBUF0_FLAGS
:
236 return SI_RESOURCE_FLAG_32BIT
;
238 case PIPE_CAP_NATIVE_FENCE_FD
:
239 return sscreen
->info
.has_fence_to_handle
;
241 case PIPE_CAP_DRAW_PARAMETERS
:
242 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
243 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
244 return sscreen
->has_draw_indirect_multi
;
246 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
249 case PIPE_CAP_MAX_VARYINGS
:
252 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
253 return sscreen
->info
.chip_class
<= GFX8
? PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600
: 0;
256 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
257 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
260 /* Geometry shader output. */
261 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
262 /* gfx9 has to report 256 to make piglit/gs-max-output pass.
263 * gfx8 and earlier can do 1024.
266 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
268 case PIPE_CAP_MAX_GS_INVOCATIONS
:
269 /* Even though the hw supports more, we officially wanna expose only 32. */
272 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
276 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
278 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
279 return 15; /* 16384 */
280 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
281 if (sscreen
->info
.chip_class
>= GFX10
)
283 /* textures support 8192, but layered rendering supports 2048 */
285 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
286 if (sscreen
->info
.chip_class
>= GFX10
)
288 /* textures support 8192, but layered rendering supports 2048 */
291 /* Viewports and render targets. */
292 case PIPE_CAP_MAX_VIEWPORTS
:
293 return SI_MAX_VIEWPORTS
;
294 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
295 case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS
:
296 case PIPE_CAP_MAX_RENDER_TARGETS
:
298 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS
:
299 return sscreen
->info
.has_eqaa_surface_allocator
? 2 : 0;
301 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
302 case PIPE_CAP_MIN_TEXEL_OFFSET
:
305 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
306 case PIPE_CAP_MAX_TEXEL_OFFSET
:
309 case PIPE_CAP_ENDIANNESS
:
310 return PIPE_ENDIAN_LITTLE
;
312 case PIPE_CAP_VENDOR_ID
:
313 return ATI_VENDOR_ID
;
314 case PIPE_CAP_DEVICE_ID
:
315 return sscreen
->info
.pci_id
;
316 case PIPE_CAP_VIDEO_MEMORY
:
317 return sscreen
->info
.vram_size
>> 20;
318 case PIPE_CAP_PCI_GROUP
:
319 return sscreen
->info
.pci_domain
;
320 case PIPE_CAP_PCI_BUS
:
321 return sscreen
->info
.pci_bus
;
322 case PIPE_CAP_PCI_DEVICE
:
323 return sscreen
->info
.pci_dev
;
324 case PIPE_CAP_PCI_FUNCTION
:
325 return sscreen
->info
.pci_func
;
326 case PIPE_CAP_TGSI_ATOMINC_WRAP
:
327 return LLVM_VERSION_MAJOR
>= 10;
330 return u_pipe_screen_get_param_defaults(pscreen
, param
);
334 static float si_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
337 case PIPE_CAPF_MAX_LINE_WIDTH
:
338 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
339 /* This depends on the quant mode, though the precise interactions
342 case PIPE_CAPF_MAX_POINT_WIDTH
:
343 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
344 return SI_MAX_POINT_SIZE
;
345 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
347 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
349 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
350 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
351 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
357 static int si_get_shader_param(struct pipe_screen
*pscreen
, enum pipe_shader_type shader
,
358 enum pipe_shader_cap param
)
360 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
363 case PIPE_SHADER_FRAGMENT
:
364 case PIPE_SHADER_VERTEX
:
365 case PIPE_SHADER_GEOMETRY
:
366 case PIPE_SHADER_TESS_CTRL
:
367 case PIPE_SHADER_TESS_EVAL
:
369 case PIPE_SHADER_COMPUTE
:
371 case PIPE_SHADER_CAP_SUPPORTED_IRS
: {
372 int ir
= 1 << PIPE_SHADER_IR_NATIVE
;
374 if (sscreen
->info
.has_indirect_compute_dispatch
)
375 ir
|= 1 << PIPE_SHADER_IR_NIR
;
380 /* If compute shaders don't require a special value
381 * for this cap, we can return the same value we
382 * do for other shader types. */
392 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
393 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
394 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
395 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
396 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
398 case PIPE_SHADER_CAP_MAX_INPUTS
:
399 return shader
== PIPE_SHADER_VERTEX
? SI_MAX_ATTRIBS
: 32;
400 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
401 return shader
== PIPE_SHADER_FRAGMENT
? 8 : 32;
402 case PIPE_SHADER_CAP_MAX_TEMPS
:
403 return 256; /* Max native temporaries. */
404 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
405 return si_get_param(pscreen
, PIPE_CAP_MAX_SHADER_BUFFER_SIZE
);
406 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
407 return SI_NUM_CONST_BUFFERS
;
408 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
409 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
410 return SI_NUM_SAMPLERS
;
411 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
412 return SI_NUM_SHADER_BUFFERS
;
413 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
414 return SI_NUM_IMAGES
;
415 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
417 case PIPE_SHADER_CAP_PREFERRED_IR
:
418 return PIPE_SHADER_IR_NIR
;
419 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
422 /* Supported boolean features. */
423 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
424 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
425 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
426 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
427 case PIPE_SHADER_CAP_INTEGERS
:
428 case PIPE_SHADER_CAP_INT64_ATOMICS
:
429 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
430 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
431 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
432 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
433 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
434 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
435 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
: /* lowered in finalize_nir */
436 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
: /* lowered in finalize_nir */
439 /* Unsupported boolean features. */
440 case PIPE_SHADER_CAP_FP16
:
441 case PIPE_SHADER_CAP_FP16_DERIVATIVES
:
442 case PIPE_SHADER_CAP_INT16
:
443 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS
:
444 case PIPE_SHADER_CAP_SUBROUTINES
:
445 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
446 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
447 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
453 static const void *si_get_compiler_options(struct pipe_screen
*screen
, enum pipe_shader_ir ir
,
454 enum pipe_shader_type shader
)
456 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
458 assert(ir
== PIPE_SHADER_IR_NIR
);
459 return &sscreen
->nir_options
;
462 static void si_get_driver_uuid(struct pipe_screen
*pscreen
, char *uuid
)
464 ac_compute_driver_uuid(uuid
, PIPE_UUID_SIZE
);
467 static void si_get_device_uuid(struct pipe_screen
*pscreen
, char *uuid
)
469 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
471 ac_compute_device_uuid(&sscreen
->info
, uuid
, PIPE_UUID_SIZE
);
474 static const char *si_get_name(struct pipe_screen
*pscreen
)
476 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
478 return sscreen
->renderer_string
;
481 static int si_get_video_param_no_decode(struct pipe_screen
*screen
, enum pipe_video_profile profile
,
482 enum pipe_video_entrypoint entrypoint
,
483 enum pipe_video_cap param
)
486 case PIPE_VIDEO_CAP_SUPPORTED
:
487 return vl_profile_supported(screen
, profile
, entrypoint
);
488 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
490 case PIPE_VIDEO_CAP_MAX_WIDTH
:
491 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
492 return vl_video_buffer_max_size(screen
);
493 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
494 return PIPE_FORMAT_NV12
;
495 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
497 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
499 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
501 case PIPE_VIDEO_CAP_MAX_LEVEL
:
502 return vl_level_supported(screen
, profile
);
508 static int si_get_video_param(struct pipe_screen
*screen
, enum pipe_video_profile profile
,
509 enum pipe_video_entrypoint entrypoint
, enum pipe_video_cap param
)
511 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
512 enum pipe_video_format codec
= u_reduce_video_profile(profile
);
514 if (entrypoint
== PIPE_VIDEO_ENTRYPOINT_ENCODE
) {
516 case PIPE_VIDEO_CAP_SUPPORTED
:
518 (codec
== PIPE_VIDEO_FORMAT_MPEG4_AVC
&&
519 (sscreen
->info
.family
>= CHIP_RAVEN
|| si_vce_is_fw_version_supported(sscreen
))) ||
520 (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
&&
521 (sscreen
->info
.family
>= CHIP_RAVEN
|| si_radeon_uvd_enc_supported(sscreen
))) ||
522 (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
&& sscreen
->info
.family
>= CHIP_RENOIR
));
523 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
525 case PIPE_VIDEO_CAP_MAX_WIDTH
:
526 return (sscreen
->info
.family
< CHIP_TONGA
) ? 2048 : 4096;
527 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
528 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1152 : 2304;
529 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
530 return PIPE_FORMAT_NV12
;
531 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
533 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
535 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
537 case PIPE_VIDEO_CAP_STACKED_FRAMES
:
538 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1 : 2;
545 case PIPE_VIDEO_CAP_SUPPORTED
:
547 case PIPE_VIDEO_FORMAT_MPEG12
:
548 return profile
!= PIPE_VIDEO_PROFILE_MPEG1
;
549 case PIPE_VIDEO_FORMAT_MPEG4
:
551 case PIPE_VIDEO_FORMAT_MPEG4_AVC
:
552 if ((sscreen
->info
.family
== CHIP_POLARIS10
|| sscreen
->info
.family
== CHIP_POLARIS11
) &&
553 sscreen
->info
.uvd_fw_version
< UVD_FW_1_66_16
) {
554 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
558 case PIPE_VIDEO_FORMAT_VC1
:
560 case PIPE_VIDEO_FORMAT_HEVC
:
561 /* Carrizo only supports HEVC Main */
562 if (sscreen
->info
.family
>= CHIP_STONEY
)
563 return (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
||
564 profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
);
565 else if (sscreen
->info
.family
>= CHIP_CARRIZO
)
566 return profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
;
568 case PIPE_VIDEO_FORMAT_JPEG
:
569 if (sscreen
->info
.family
>= CHIP_RAVEN
)
571 if (sscreen
->info
.family
< CHIP_CARRIZO
|| sscreen
->info
.family
>= CHIP_VEGA10
)
573 if (!(sscreen
->info
.is_amdgpu
&& sscreen
->info
.drm_minor
>= 19)) {
574 RVID_ERR("No MJPEG support for the kernel version\n");
578 case PIPE_VIDEO_FORMAT_VP9
:
579 if (sscreen
->info
.family
< CHIP_RAVEN
)
585 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
587 case PIPE_VIDEO_CAP_MAX_WIDTH
:
589 case PIPE_VIDEO_FORMAT_HEVC
:
590 case PIPE_VIDEO_FORMAT_VP9
:
591 return (sscreen
->info
.family
< CHIP_RENOIR
)
592 ? ((sscreen
->info
.family
< CHIP_TONGA
) ? 2048 : 4096)
595 return (sscreen
->info
.family
< CHIP_TONGA
) ? 2048 : 4096;
597 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
599 case PIPE_VIDEO_FORMAT_HEVC
:
600 case PIPE_VIDEO_FORMAT_VP9
:
601 return (sscreen
->info
.family
< CHIP_RENOIR
)
602 ? ((sscreen
->info
.family
< CHIP_TONGA
) ? 1152 : 4096)
605 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1152 : 4096;
607 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
608 if (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
)
609 return PIPE_FORMAT_P010
;
610 else if (profile
== PIPE_VIDEO_PROFILE_VP9_PROFILE2
)
611 return PIPE_FORMAT_P010
;
613 return PIPE_FORMAT_NV12
;
615 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
616 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
: {
617 enum pipe_video_format format
= u_reduce_video_profile(profile
);
619 if (format
== PIPE_VIDEO_FORMAT_HEVC
)
620 return false; // The firmware doesn't support interlaced HEVC.
621 else if (format
== PIPE_VIDEO_FORMAT_JPEG
)
623 else if (format
== PIPE_VIDEO_FORMAT_VP9
)
627 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
629 case PIPE_VIDEO_CAP_MAX_LEVEL
:
631 case PIPE_VIDEO_PROFILE_MPEG1
:
633 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE
:
634 case PIPE_VIDEO_PROFILE_MPEG2_MAIN
:
636 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE
:
638 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE
:
640 case PIPE_VIDEO_PROFILE_VC1_SIMPLE
:
642 case PIPE_VIDEO_PROFILE_VC1_MAIN
:
644 case PIPE_VIDEO_PROFILE_VC1_ADVANCED
:
646 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE
:
647 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN
:
648 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH
:
649 return (sscreen
->info
.family
< CHIP_TONGA
) ? 41 : 52;
650 case PIPE_VIDEO_PROFILE_HEVC_MAIN
:
651 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10
:
661 static bool si_vid_is_format_supported(struct pipe_screen
*screen
, enum pipe_format format
,
662 enum pipe_video_profile profile
,
663 enum pipe_video_entrypoint entrypoint
)
665 /* HEVC 10 bit decoding should use P010 instead of NV12 if possible */
666 if (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
)
667 return (format
== PIPE_FORMAT_NV12
) || (format
== PIPE_FORMAT_P010
) ||
668 (format
== PIPE_FORMAT_P016
);
670 /* Vp9 profile 2 supports 10 bit decoding using P016 */
671 if (profile
== PIPE_VIDEO_PROFILE_VP9_PROFILE2
)
672 return (format
== PIPE_FORMAT_P010
) || (format
== PIPE_FORMAT_P016
);
674 /* we can only handle this one with UVD */
675 if (profile
!= PIPE_VIDEO_PROFILE_UNKNOWN
)
676 return format
== PIPE_FORMAT_NV12
;
678 return vl_video_buffer_is_format_supported(screen
, format
, profile
, entrypoint
);
681 static unsigned get_max_threads_per_block(struct si_screen
*screen
, enum pipe_shader_ir ir_type
)
683 if (ir_type
== PIPE_SHADER_IR_NATIVE
)
686 /* LLVM 10 only supports 1024 threads per block. */
690 static int si_get_compute_param(struct pipe_screen
*screen
, enum pipe_shader_ir ir_type
,
691 enum pipe_compute_cap param
, void *ret
)
693 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
695 // TODO: select these params by asic
697 case PIPE_COMPUTE_CAP_IR_TARGET
: {
698 const char *gpu
, *triple
;
700 triple
= "amdgcn-mesa-mesa3d";
701 gpu
= ac_get_llvm_processor_name(sscreen
->info
.family
);
703 sprintf(ret
, "%s-%s", gpu
, triple
);
705 /* +2 for dash and terminating NIL byte */
706 return (strlen(triple
) + strlen(gpu
) + 2) * sizeof(char);
708 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
710 uint64_t *grid_dimension
= ret
;
711 grid_dimension
[0] = 3;
713 return 1 * sizeof(uint64_t);
715 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
717 uint64_t *grid_size
= ret
;
718 grid_size
[0] = 65535;
719 grid_size
[1] = 65535;
720 grid_size
[2] = 65535;
722 return 3 * sizeof(uint64_t);
724 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
726 uint64_t *block_size
= ret
;
727 unsigned threads_per_block
= get_max_threads_per_block(sscreen
, ir_type
);
728 block_size
[0] = threads_per_block
;
729 block_size
[1] = threads_per_block
;
730 block_size
[2] = threads_per_block
;
732 return 3 * sizeof(uint64_t);
734 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
736 uint64_t *max_threads_per_block
= ret
;
737 *max_threads_per_block
= get_max_threads_per_block(sscreen
, ir_type
);
739 return sizeof(uint64_t);
740 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
742 uint32_t *address_bits
= ret
;
743 address_bits
[0] = 64;
745 return 1 * sizeof(uint32_t);
747 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
749 uint64_t *max_global_size
= ret
;
750 uint64_t max_mem_alloc_size
;
752 si_get_compute_param(screen
, ir_type
, PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
753 &max_mem_alloc_size
);
755 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
756 * 1/4 of the MAX_GLOBAL_SIZE. Since the
757 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
758 * make sure we never report more than
759 * 4 * MAX_MEM_ALLOC_SIZE.
762 MIN2(4 * max_mem_alloc_size
, MAX2(sscreen
->info
.gart_size
, sscreen
->info
.vram_size
));
764 return sizeof(uint64_t);
766 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
768 uint64_t *max_local_size
= ret
;
769 /* Value reported by the closed source driver. */
770 *max_local_size
= 32768;
772 return sizeof(uint64_t);
774 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
776 uint64_t *max_input_size
= ret
;
777 /* Value reported by the closed source driver. */
778 *max_input_size
= 1024;
780 return sizeof(uint64_t);
782 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
784 uint64_t *max_mem_alloc_size
= ret
;
786 *max_mem_alloc_size
= sscreen
->info
.max_alloc_size
;
788 return sizeof(uint64_t);
790 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
792 uint32_t *max_clock_frequency
= ret
;
793 *max_clock_frequency
= sscreen
->info
.max_shader_clock
;
795 return sizeof(uint32_t);
797 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
799 uint32_t *max_compute_units
= ret
;
800 *max_compute_units
= sscreen
->info
.num_good_compute_units
;
802 return sizeof(uint32_t);
804 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
806 uint32_t *images_supported
= ret
;
807 *images_supported
= 0;
809 return sizeof(uint32_t);
810 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
812 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
814 uint32_t *subgroup_size
= ret
;
815 *subgroup_size
= sscreen
->compute_wave_size
;
817 return sizeof(uint32_t);
818 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
820 uint64_t *max_variable_threads_per_block
= ret
;
821 if (ir_type
== PIPE_SHADER_IR_NATIVE
)
822 *max_variable_threads_per_block
= 0;
824 *max_variable_threads_per_block
= SI_MAX_VARIABLE_THREADS_PER_BLOCK
;
826 return sizeof(uint64_t);
829 fprintf(stderr
, "unknown PIPE_COMPUTE_CAP %d\n", param
);
833 static uint64_t si_get_timestamp(struct pipe_screen
*screen
)
835 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
837 return 1000000 * sscreen
->ws
->query_value(sscreen
->ws
, RADEON_TIMESTAMP
) /
838 sscreen
->info
.clock_crystal_freq
;
841 static void si_query_memory_info(struct pipe_screen
*screen
, struct pipe_memory_info
*info
)
843 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
844 struct radeon_winsys
*ws
= sscreen
->ws
;
845 unsigned vram_usage
, gtt_usage
;
847 info
->total_device_memory
= sscreen
->info
.vram_size
/ 1024;
848 info
->total_staging_memory
= sscreen
->info
.gart_size
/ 1024;
850 /* The real TTM memory usage is somewhat random, because:
852 * 1) TTM delays freeing memory, because it can only free it after
855 * 2) The memory usage can be really low if big VRAM evictions are
856 * taking place, but the real usage is well above the size of VRAM.
858 * Instead, return statistics of this process.
860 vram_usage
= ws
->query_value(ws
, RADEON_VRAM_USAGE
) / 1024;
861 gtt_usage
= ws
->query_value(ws
, RADEON_GTT_USAGE
) / 1024;
863 info
->avail_device_memory
=
864 vram_usage
<= info
->total_device_memory
? info
->total_device_memory
- vram_usage
: 0;
865 info
->avail_staging_memory
=
866 gtt_usage
<= info
->total_staging_memory
? info
->total_staging_memory
- gtt_usage
: 0;
868 info
->device_memory_evicted
= ws
->query_value(ws
, RADEON_NUM_BYTES_MOVED
) / 1024;
870 if (sscreen
->info
.is_amdgpu
&& sscreen
->info
.drm_minor
>= 4)
871 info
->nr_device_memory_evictions
= ws
->query_value(ws
, RADEON_NUM_EVICTIONS
);
873 /* Just return the number of evicted 64KB pages. */
874 info
->nr_device_memory_evictions
= info
->device_memory_evicted
/ 64;
877 static struct disk_cache
*si_get_disk_shader_cache(struct pipe_screen
*pscreen
)
879 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
881 return sscreen
->disk_shader_cache
;
884 static void si_init_renderer_string(struct si_screen
*sscreen
)
886 char first_name
[256], second_name
[32] = {}, kernel_version
[128] = {};
887 struct utsname uname_data
;
889 if (sscreen
->info
.marketing_name
) {
890 snprintf(first_name
, sizeof(first_name
), "%s", sscreen
->info
.marketing_name
);
891 snprintf(second_name
, sizeof(second_name
), "%s, ", sscreen
->info
.name
);
893 snprintf(first_name
, sizeof(first_name
), "AMD %s", sscreen
->info
.name
);
896 if (uname(&uname_data
) == 0)
897 snprintf(kernel_version
, sizeof(kernel_version
), ", %s", uname_data
.release
);
899 snprintf(sscreen
->renderer_string
, sizeof(sscreen
->renderer_string
),
900 "%s (%sDRM %i.%i.%i%s, LLVM " MESA_LLVM_VERSION_STRING
")", first_name
, second_name
,
901 sscreen
->info
.drm_major
, sscreen
->info
.drm_minor
, sscreen
->info
.drm_patchlevel
,
905 void si_init_screen_get_functions(struct si_screen
*sscreen
)
907 sscreen
->b
.get_name
= si_get_name
;
908 sscreen
->b
.get_vendor
= si_get_vendor
;
909 sscreen
->b
.get_device_vendor
= si_get_device_vendor
;
910 sscreen
->b
.get_param
= si_get_param
;
911 sscreen
->b
.get_paramf
= si_get_paramf
;
912 sscreen
->b
.get_compute_param
= si_get_compute_param
;
913 sscreen
->b
.get_timestamp
= si_get_timestamp
;
914 sscreen
->b
.get_shader_param
= si_get_shader_param
;
915 sscreen
->b
.get_compiler_options
= si_get_compiler_options
;
916 sscreen
->b
.get_device_uuid
= si_get_device_uuid
;
917 sscreen
->b
.get_driver_uuid
= si_get_driver_uuid
;
918 sscreen
->b
.query_memory_info
= si_query_memory_info
;
919 sscreen
->b
.get_disk_shader_cache
= si_get_disk_shader_cache
;
921 if (sscreen
->info
.has_hw_decode
) {
922 sscreen
->b
.get_video_param
= si_get_video_param
;
923 sscreen
->b
.is_video_format_supported
= si_vid_is_format_supported
;
925 sscreen
->b
.get_video_param
= si_get_video_param_no_decode
;
926 sscreen
->b
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
929 si_init_renderer_string(sscreen
);
931 const struct nir_shader_compiler_options nir_options
= {
933 .lower_flrp32
= true,
934 .lower_flrp64
= true,
937 .lower_bitfield_insert_to_bitfield_select
= true,
938 .lower_bitfield_extract
= true,
942 .lower_pack_snorm_4x8
= true,
943 .lower_pack_unorm_4x8
= true,
944 .lower_unpack_snorm_2x16
= true,
945 .lower_unpack_snorm_4x8
= true,
946 .lower_unpack_unorm_2x16
= true,
947 .lower_unpack_unorm_4x8
= true,
948 .lower_extract_byte
= true,
949 .lower_extract_word
= true,
950 .lower_rotate
= true,
951 .lower_to_scalar
= true,
952 .optimize_sample_mask_in
= true,
953 .max_unroll_iterations
= 32,
954 .use_interpolated_input_intrinsics
= true,
956 sscreen
->nir_options
= nir_options
;