src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "radeon/radeon_video.h"
  26 #include "radeon/radeon_vce.h"
  27 #include "ac_llvm_util.h"
  28 #include "vl/vl_decoder.h"
  29 #include "vl/vl_video_buffer.h"
  30 #include "util/u_video.h"
  31 #include "compiler/nir/nir.h"
  32
  33 #include <sys/utsname.h>
  34
  35 static const char *si_get_vendor(struct pipe_screen *pscreen)
  36 {
  37         /* Don't change this. Games such as Alien Isolation are broken if this
  38          * returns "Advanced Micro Devices, Inc."
  39          */
  40         return "X.Org";
  41 }
  42
  43 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  44 {
  45         return "AMD";
  46 }
  47
  48 static const char *si_get_marketing_name(struct radeon_winsys *ws)
  49 {
  50         if (!ws->get_chip_name)
  51                 return NULL;
  52         return ws->get_chip_name(ws);
  53 }
  54
  55 const char *si_get_family_name(const struct si_screen *sscreen)
  56 {
  57         switch (sscreen->info.family) {
  58         case CHIP_TAHITI: return "AMD TAHITI";
  59         case CHIP_PITCAIRN: return "AMD PITCAIRN";
  60         case CHIP_VERDE: return "AMD CAPE VERDE";
  61         case CHIP_OLAND: return "AMD OLAND";
  62         case CHIP_HAINAN: return "AMD HAINAN";
  63         case CHIP_BONAIRE: return "AMD BONAIRE";
  64         case CHIP_KAVERI: return "AMD KAVERI";
  65         case CHIP_KABINI: return "AMD KABINI";
  66         case CHIP_HAWAII: return "AMD HAWAII";
  67         case CHIP_MULLINS: return "AMD MULLINS";
  68         case CHIP_TONGA: return "AMD TONGA";
  69         case CHIP_ICELAND: return "AMD ICELAND";
  70         case CHIP_CARRIZO: return "AMD CARRIZO";
  71         case CHIP_FIJI: return "AMD FIJI";
  72         case CHIP_POLARIS10: return "AMD POLARIS10";
  73         case CHIP_POLARIS11: return "AMD POLARIS11";
  74         case CHIP_POLARIS12: return "AMD POLARIS12";
  75         case CHIP_STONEY: return "AMD STONEY";
  76         case CHIP_VEGA10: return "AMD VEGA10";
  77         case CHIP_RAVEN: return "AMD RAVEN";
  78         default: return "AMD unknown";
  79         }
  80 }
  81
  82 static bool si_have_tgsi_compute(struct si_screen *sscreen)
  83 {
  84         /* Old kernels disallowed some register writes for SI
  85          * that are used for indirect dispatches. */
  86         return (sscreen->info.chip_class >= CIK ||
  87                 sscreen->info.drm_major == 3 ||
  88                 (sscreen->info.drm_major == 2 &&
  89                  sscreen->info.drm_minor >= 45));
  90 }
  91
  92 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  93 {
  94         struct si_screen *sscreen = (struct si_screen *)pscreen;
  95
  96         switch (param) {
  97         /* Supported features (boolean caps). */
  98         case PIPE_CAP_ACCELERATED:
  99         case PIPE_CAP_TWO_SIDED_STENCIL:
 100         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 101         case PIPE_CAP_ANISOTROPIC_FILTER:
 102         case PIPE_CAP_POINT_SPRITE:
 103         case PIPE_CAP_OCCLUSION_QUERY:
 104         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 105         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 106         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 107         case PIPE_CAP_TEXTURE_SWIZZLE:
 108         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 109         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 110         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 111         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 112         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 113         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 114         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 115         case PIPE_CAP_SM3:
 116         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 117         case PIPE_CAP_PRIMITIVE_RESTART:
 118         case PIPE_CAP_CONDITIONAL_RENDER:
 119         case PIPE_CAP_TEXTURE_BARRIER:
 120         case PIPE_CAP_INDEP_BLEND_ENABLE:
 121         case PIPE_CAP_INDEP_BLEND_FUNC:
 122         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 123         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 124         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 125         case PIPE_CAP_START_INSTANCE:
 126         case PIPE_CAP_NPOT_TEXTURES:
 127         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 128         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 129         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 130         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 131         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 132         case PIPE_CAP_TGSI_INSTANCEID:
 133         case PIPE_CAP_COMPUTE:
 134         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 135         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 136         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 137         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 138         case PIPE_CAP_CUBE_MAP_ARRAY:
 139         case PIPE_CAP_SAMPLE_SHADING:
 140         case PIPE_CAP_DRAW_INDIRECT:
 141         case PIPE_CAP_CLIP_HALFZ:
 142         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 143         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 144         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 145         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 146         case PIPE_CAP_TGSI_TEXCOORD:
 147         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 148         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 149         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 150         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 151         case PIPE_CAP_SHAREABLE_SHADERS:
 152         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 153         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 154         case PIPE_CAP_TEXTURE_QUERY_LOD:
 155         case PIPE_CAP_TEXTURE_GATHER_SM5:
 156         case PIPE_CAP_TGSI_TXQS:
 157         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 158         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 159         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 160         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 161         case PIPE_CAP_INVALIDATE_BUFFER:
 162         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 163         case PIPE_CAP_QUERY_MEMORY_INFO:
 164         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 165         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 166         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 167         case PIPE_CAP_GENERATE_MIPMAP:
 168         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 169         case PIPE_CAP_STRING_MARKER:
 170         case PIPE_CAP_CLEAR_TEXTURE:
 171         case PIPE_CAP_CULL_DISTANCE:
 172         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 173         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 174         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 175         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 176         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 177         case PIPE_CAP_DOUBLES:
 178         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 179         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 180         case PIPE_CAP_BINDLESS_TEXTURE:
 181         case PIPE_CAP_QUERY_TIMESTAMP:
 182         case PIPE_CAP_QUERY_TIME_ELAPSED:
 183         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 184         case PIPE_CAP_QUERY_SO_OVERFLOW:
 185         case PIPE_CAP_MEMOBJ:
 186         case PIPE_CAP_LOAD_CONSTBUF:
 187         case PIPE_CAP_INT64:
 188         case PIPE_CAP_INT64_DIVMOD:
 189         case PIPE_CAP_TGSI_CLOCK:
 190         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 191         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 192         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 193         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 194                 return 1;
 195
 196         case PIPE_CAP_TGSI_VOTE:
 197                 return HAVE_LLVM >= 0x0400;
 198
 199         case PIPE_CAP_TGSI_BALLOT:
 200                 return HAVE_LLVM >= 0x0500;
 201
 202         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 203                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 204
 205         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 206                 return (sscreen->info.drm_major == 2 &&
 207                         sscreen->info.drm_minor >= 43) ||
 208                        sscreen->info.drm_major == 3;
 209
 210         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 211                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 212                 return sscreen->info.chip_class < CIK ||
 213                        (sscreen->info.drm_major == 2 &&
 214                         sscreen->info.drm_minor >= 35) ||
 215                        sscreen->info.drm_major == 3;
 216
 217         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 218                 return R600_MAP_BUFFER_ALIGNMENT;
 219
 220         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 221         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 222         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 223         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 224         case PIPE_CAP_MAX_VERTEX_STREAMS:
 225         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 226                 return 4;
 227
 228         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 229                 if (sscreen->debug_flags & DBG(NIR))
 230                         return 150; /* no tessellation shaders yet */
 231                 if (si_have_tgsi_compute(sscreen))
 232                         return 450;
 233                 return 420;
 234
 235         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 236                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 237
 238         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 239         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 240         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 241                 /* SI doesn't support unaligned loads.
 242                  * CIK needs DRM 2.50.0 on radeon. */
 243                 return sscreen->info.chip_class == SI ||
 244                        (sscreen->info.drm_major == 2 &&
 245                         sscreen->info.drm_minor < 50);
 246
 247         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 248                 /* TODO: GFX9 hangs. */
 249                 if (sscreen->info.chip_class >= GFX9)
 250                         return 0;
 251                 /* Disable on SI due to VM faults in CP DMA. Enable once these
 252                  * faults are mitigated in software.
 253                  */
 254                 if (sscreen->info.chip_class >= CIK &&
 255                     sscreen->info.drm_major == 3 &&
 256                     sscreen->info.drm_minor >= 13)
 257                         return RADEON_SPARSE_PAGE_SIZE;
 258                 return 0;
 259
 260         /* Unsupported features. */
 261         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 262         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 263         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 264         case PIPE_CAP_USER_VERTEX_BUFFERS:
 265         case PIPE_CAP_FAKE_SW_MSAA:
 266         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 267         case PIPE_CAP_VERTEXID_NOBASE:
 268         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 269         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 270         case PIPE_CAP_TGSI_FS_FBFETCH:
 271         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 272         case PIPE_CAP_UMA:
 273         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 274         case PIPE_CAP_POST_DEPTH_COVERAGE:
 275         case PIPE_CAP_TILE_RASTER_ORDER:
 276         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 277                 return 0;
 278
 279         case PIPE_CAP_NATIVE_FENCE_FD:
 280                 return sscreen->info.has_sync_file;
 281
 282         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 283                 return si_have_tgsi_compute(sscreen);
 284
 285         case PIPE_CAP_DRAW_PARAMETERS:
 286         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 287         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 288                 return sscreen->has_draw_indirect_multi;
 289
 290         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 291                 return 30;
 292
 293         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 294                 return sscreen->info.chip_class <= VI ?
 295                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 296
 297         /* Stream output. */
 298         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 299         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 300                 return 32*4;
 301
 302         /* Geometry shader output. */
 303         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 304                 return 1024;
 305         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 306                 return 4095;
 307
 308         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 309                 return 2048;
 310
 311         /* Texturing. */
 312         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 313         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 314                 return 15; /* 16384 */
 315         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 316                 /* textures support 8192, but layered rendering supports 2048 */
 317                 return 12;
 318         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 319                 /* textures support 8192, but layered rendering supports 2048 */
 320                 return 2048;
 321
 322         /* Viewports and render targets. */
 323         case PIPE_CAP_MAX_VIEWPORTS:
 324                 return SI_MAX_VIEWPORTS;
 325         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 326         case PIPE_CAP_MAX_RENDER_TARGETS:
 327                 return 8;
 328
 329         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 330         case PIPE_CAP_MIN_TEXEL_OFFSET:
 331                 return -32;
 332
 333         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 334         case PIPE_CAP_MAX_TEXEL_OFFSET:
 335                 return 31;
 336
 337         case PIPE_CAP_ENDIANNESS:
 338                 return PIPE_ENDIAN_LITTLE;
 339
 340         case PIPE_CAP_VENDOR_ID:
 341                 return ATI_VENDOR_ID;
 342         case PIPE_CAP_DEVICE_ID:
 343                 return sscreen->info.pci_id;
 344         case PIPE_CAP_VIDEO_MEMORY:
 345                 return sscreen->info.vram_size >> 20;
 346         case PIPE_CAP_PCI_GROUP:
 347                 return sscreen->info.pci_domain;
 348         case PIPE_CAP_PCI_BUS:
 349                 return sscreen->info.pci_bus;
 350         case PIPE_CAP_PCI_DEVICE:
 351                 return sscreen->info.pci_dev;
 352         case PIPE_CAP_PCI_FUNCTION:
 353                 return sscreen->info.pci_func;
 354         }
 355         return 0;
 356 }
 357
 358 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 359 {
 360         switch (param) {
 361         case PIPE_CAPF_MAX_LINE_WIDTH:
 362         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 363         case PIPE_CAPF_MAX_POINT_WIDTH:
 364         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 365                 return 8192.0f;
 366         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 367                 return 16.0f;
 368         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 369                 return 16.0f;
 370         case PIPE_CAPF_GUARD_BAND_LEFT:
 371         case PIPE_CAPF_GUARD_BAND_TOP:
 372         case PIPE_CAPF_GUARD_BAND_RIGHT:
 373         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 374                 return 0.0f;
 375         }
 376         return 0.0f;
 377 }
 378
 379 static int si_get_shader_param(struct pipe_screen* pscreen,
 380                                enum pipe_shader_type shader,
 381                                enum pipe_shader_cap param)
 382 {
 383         struct si_screen *sscreen = (struct si_screen *)pscreen;
 384
 385         switch(shader)
 386         {
 387         case PIPE_SHADER_FRAGMENT:
 388         case PIPE_SHADER_VERTEX:
 389         case PIPE_SHADER_GEOMETRY:
 390         case PIPE_SHADER_TESS_CTRL:
 391         case PIPE_SHADER_TESS_EVAL:
 392                 break;
 393         case PIPE_SHADER_COMPUTE:
 394                 switch (param) {
 395                 case PIPE_SHADER_CAP_PREFERRED_IR:
 396                         return PIPE_SHADER_IR_NATIVE;
 397
 398                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 399                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 400
 401                         if (si_have_tgsi_compute(sscreen))
 402                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 403
 404                         return ir;
 405                 }
 406
 407                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 408                         uint64_t max_const_buffer_size;
 409                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 410                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 411                                 &max_const_buffer_size);
 412                         return MIN2(max_const_buffer_size, INT_MAX);
 413                 }
 414                 default:
 415                         /* If compute shaders don't require a special value
 416                          * for this cap, we can return the same value we
 417                          * do for other shader types. */
 418                         break;
 419                 }
 420                 break;
 421         default:
 422                 return 0;
 423         }
 424
 425         switch (param) {
 426         /* Shader limits. */
 427         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 428         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 429         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 430         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 431         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 432                 return 16384;
 433         case PIPE_SHADER_CAP_MAX_INPUTS:
 434                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 435         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 436                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 437         case PIPE_SHADER_CAP_MAX_TEMPS:
 438                 return 256; /* Max native temporaries. */
 439         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 440                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 441         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 442                 return SI_NUM_CONST_BUFFERS;
 443         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 444         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 445                 return SI_NUM_SAMPLERS;
 446         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 447                 return SI_NUM_SHADER_BUFFERS;
 448         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 449                 return SI_NUM_IMAGES;
 450         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 451                 return 32;
 452         case PIPE_SHADER_CAP_PREFERRED_IR:
 453                 if (sscreen->debug_flags & DBG(NIR) &&
 454                     (shader == PIPE_SHADER_VERTEX ||
 455                      shader == PIPE_SHADER_GEOMETRY ||
 456                      shader == PIPE_SHADER_FRAGMENT))
 457                         return PIPE_SHADER_IR_NIR;
 458                 return PIPE_SHADER_IR_TGSI;
 459         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 460                 return 4;
 461
 462         /* Supported boolean features. */
 463         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 464         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 465         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 466         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 467         case PIPE_SHADER_CAP_INTEGERS:
 468         case PIPE_SHADER_CAP_INT64_ATOMICS:
 469         case PIPE_SHADER_CAP_FP16:
 470         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 471         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 472         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 473         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 474         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 475         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 476                 return 1;
 477
 478         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 479                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 480                 return shader != PIPE_SHADER_GEOMETRY &&
 481                        (sscreen->llvm_has_working_vgpr_indexing ||
 482                         /* TCS and TES load inputs directly from LDS or
 483                          * offchip memory, so indirect indexing is trivial. */
 484                         shader == PIPE_SHADER_TESS_CTRL ||
 485                         shader == PIPE_SHADER_TESS_EVAL);
 486
 487         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 488                 return sscreen->llvm_has_working_vgpr_indexing ||
 489                        /* TCS stores outputs directly to memory. */
 490                        shader == PIPE_SHADER_TESS_CTRL;
 491
 492         /* Unsupported boolean features. */
 493         case PIPE_SHADER_CAP_SUBROUTINES:
 494         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 495         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 496         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 497                 return 0;
 498         }
 499         return 0;
 500 }
 501
 502 static const struct nir_shader_compiler_options nir_options = {
 503         .vertex_id_zero_based = true,
 504         .lower_scmp = true,
 505         .lower_flrp32 = true,
 506         .lower_fsat = true,
 507         .lower_fdiv = true,
 508         .lower_sub = true,
 509         .lower_ffma = true,
 510         .lower_pack_snorm_2x16 = true,
 511         .lower_pack_snorm_4x8 = true,
 512         .lower_pack_unorm_2x16 = true,
 513         .lower_pack_unorm_4x8 = true,
 514         .lower_unpack_snorm_2x16 = true,
 515         .lower_unpack_snorm_4x8 = true,
 516         .lower_unpack_unorm_2x16 = true,
 517         .lower_unpack_unorm_4x8 = true,
 518         .lower_extract_byte = true,
 519         .lower_extract_word = true,
 520         .max_unroll_iterations = 32,
 521         .native_integers = true,
 522 };
 523
 524 static const void *
 525 si_get_compiler_options(struct pipe_screen *screen,
 526                         enum pipe_shader_ir ir,
 527                         enum pipe_shader_type shader)
 528 {
 529         assert(ir == PIPE_SHADER_IR_NIR);
 530         return &nir_options;
 531 }
 532
 533 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 534 {
 535         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 536 }
 537
 538 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 539 {
 540         struct si_screen *sscreen = (struct si_screen *)pscreen;
 541
 542         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 543 }
 544
 545 static const char* si_get_name(struct pipe_screen *pscreen)
 546 {
 547         struct si_screen *sscreen = (struct si_screen*)pscreen;
 548
 549         return sscreen->renderer_string;
 550 }
 551
 552 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 553                                         enum pipe_video_profile profile,
 554                                         enum pipe_video_entrypoint entrypoint,
 555                                         enum pipe_video_cap param)
 556 {
 557         switch (param) {
 558         case PIPE_VIDEO_CAP_SUPPORTED:
 559                 return vl_profile_supported(screen, profile, entrypoint);
 560         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 561                 return 1;
 562         case PIPE_VIDEO_CAP_MAX_WIDTH:
 563         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 564                 return vl_video_buffer_max_size(screen);
 565         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 566                 return PIPE_FORMAT_NV12;
 567         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 568                 return false;
 569         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 570                 return false;
 571         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 572                 return true;
 573         case PIPE_VIDEO_CAP_MAX_LEVEL:
 574                 return vl_level_supported(screen, profile);
 575         default:
 576                 return 0;
 577         }
 578 }
 579
 580 static int si_get_video_param(struct pipe_screen *screen,
 581                               enum pipe_video_profile profile,
 582                               enum pipe_video_entrypoint entrypoint,
 583                               enum pipe_video_cap param)
 584 {
 585         struct si_screen *sscreen = (struct si_screen *)screen;
 586         enum pipe_video_format codec = u_reduce_video_profile(profile);
 587
 588         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 589                 switch (param) {
 590                 case PIPE_VIDEO_CAP_SUPPORTED:
 591                         return codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 592                                 (si_vce_is_fw_version_supported(sscreen) ||
 593                                 sscreen->info.family == CHIP_RAVEN);
 594                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 595                         return 1;
 596                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 597                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 598                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 599                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 600                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 601                         return PIPE_FORMAT_NV12;
 602                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 603                         return false;
 604                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 605                         return false;
 606                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 607                         return true;
 608                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 609                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 610                 default:
 611                         return 0;
 612                 }
 613         }
 614
 615         switch (param) {
 616         case PIPE_VIDEO_CAP_SUPPORTED:
 617                 switch (codec) {
 618                 case PIPE_VIDEO_FORMAT_MPEG12:
 619                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 620                 case PIPE_VIDEO_FORMAT_MPEG4:
 621                         return 1;
 622                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 623                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 624                              sscreen->info.family == CHIP_POLARIS11) &&
 625                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 626                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 627                                 return false;
 628                         }
 629                         return true;
 630                 case PIPE_VIDEO_FORMAT_VC1:
 631                         return true;
 632                 case PIPE_VIDEO_FORMAT_HEVC:
 633                         /* Carrizo only supports HEVC Main */
 634                         if (sscreen->info.family >= CHIP_STONEY)
 635                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 636                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 637                         else if (sscreen->info.family >= CHIP_CARRIZO)
 638                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 639                         return false;
 640                 case PIPE_VIDEO_FORMAT_JPEG:
 641                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 642                                 return false;
 643                         if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
 644                                 RVID_ERR("No MJPEG support for the kernel version\n");
 645                                 return false;
 646                         }
 647                         return true;
 648                 default:
 649                         return false;
 650                 }
 651         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 652                 return 1;
 653         case PIPE_VIDEO_CAP_MAX_WIDTH:
 654                 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 655         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 656                 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 657         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 658                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 659                         return PIPE_FORMAT_P016;
 660                 else
 661                         return PIPE_FORMAT_NV12;
 662
 663         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 664         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 665                 enum pipe_video_format format = u_reduce_video_profile(profile);
 666
 667                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 668                         return false; //The firmware doesn't support interlaced HEVC.
 669                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 670                         return false;
 671                 return true;
 672         }
 673         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 674                 return true;
 675         case PIPE_VIDEO_CAP_MAX_LEVEL:
 676                 switch (profile) {
 677                 case PIPE_VIDEO_PROFILE_MPEG1:
 678                         return 0;
 679                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 680                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 681                         return 3;
 682                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 683                         return 3;
 684                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 685                         return 5;
 686                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 687                         return 1;
 688                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 689                         return 2;
 690                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 691                         return 4;
 692                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 693                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 694                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 695                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 696                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 697                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 698                         return 186;
 699                 default:
 700                         return 0;
 701                 }
 702         default:
 703                 return 0;
 704         }
 705 }
 706
 707 static boolean si_vid_is_format_supported(struct pipe_screen *screen,
 708                                           enum pipe_format format,
 709                                           enum pipe_video_profile profile,
 710                                           enum pipe_video_entrypoint entrypoint)
 711 {
 712         /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
 713         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 714                 return (format == PIPE_FORMAT_NV12) ||
 715                         (format == PIPE_FORMAT_P016);
 716
 717         /* we can only handle this one with UVD */
 718         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 719                 return format == PIPE_FORMAT_NV12;
 720
 721         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 722 }
 723
 724 static unsigned get_max_threads_per_block(struct si_screen *screen,
 725                                           enum pipe_shader_ir ir_type)
 726 {
 727         if (ir_type != PIPE_SHADER_IR_TGSI)
 728                 return 256;
 729
 730         /* Only 16 waves per thread-group on gfx9. */
 731         if (screen->info.chip_class >= GFX9)
 732                 return 1024;
 733
 734         /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
 735          * round number.
 736          */
 737         return 2048;
 738 }
 739
 740 static int si_get_compute_param(struct pipe_screen *screen,
 741                                 enum pipe_shader_ir ir_type,
 742                                 enum pipe_compute_cap param,
 743                                 void *ret)
 744 {
 745         struct si_screen *sscreen = (struct si_screen *)screen;
 746
 747         //TODO: select these params by asic
 748         switch (param) {
 749         case PIPE_COMPUTE_CAP_IR_TARGET: {
 750                 const char *gpu;
 751                 const char *triple;
 752
 753                 if (HAVE_LLVM < 0x0400)
 754                         triple = "amdgcn--";
 755                 else
 756                         triple = "amdgcn-mesa-mesa3d";
 757
 758                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 759                 if (ret) {
 760                         sprintf(ret, "%s-%s", gpu, triple);
 761                 }
 762                 /* +2 for dash and terminating NIL byte */
 763                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 764         }
 765         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 766                 if (ret) {
 767                         uint64_t *grid_dimension = ret;
 768                         grid_dimension[0] = 3;
 769                 }
 770                 return 1 * sizeof(uint64_t);
 771
 772         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 773                 if (ret) {
 774                         uint64_t *grid_size = ret;
 775                         grid_size[0] = 65535;
 776                         grid_size[1] = 65535;
 777                         grid_size[2] = 65535;
 778                 }
 779                 return 3 * sizeof(uint64_t) ;
 780
 781         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 782                 if (ret) {
 783                         uint64_t *block_size = ret;
 784                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 785                         block_size[0] = threads_per_block;
 786                         block_size[1] = threads_per_block;
 787                         block_size[2] = threads_per_block;
 788                 }
 789                 return 3 * sizeof(uint64_t);
 790
 791         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 792                 if (ret) {
 793                         uint64_t *max_threads_per_block = ret;
 794                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 795                 }
 796                 return sizeof(uint64_t);
 797         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 798                 if (ret) {
 799                         uint32_t *address_bits = ret;
 800                         address_bits[0] = 64;
 801                 }
 802                 return 1 * sizeof(uint32_t);
 803
 804         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 805                 if (ret) {
 806                         uint64_t *max_global_size = ret;
 807                         uint64_t max_mem_alloc_size;
 808
 809                         si_get_compute_param(screen, ir_type,
 810                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 811                                 &max_mem_alloc_size);
 812
 813                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 814                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 815                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 816                          * make sure we never report more than
 817                          * 4 * MAX_MEM_ALLOC_SIZE.
 818                          */
 819                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 820                                                 MAX2(sscreen->info.gart_size,
 821                                                      sscreen->info.vram_size));
 822                 }
 823                 return sizeof(uint64_t);
 824
 825         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 826                 if (ret) {
 827                         uint64_t *max_local_size = ret;
 828                         /* Value reported by the closed source driver. */
 829                         *max_local_size = 32768;
 830                 }
 831                 return sizeof(uint64_t);
 832
 833         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 834                 if (ret) {
 835                         uint64_t *max_input_size = ret;
 836                         /* Value reported by the closed source driver. */
 837                         *max_input_size = 1024;
 838                 }
 839                 return sizeof(uint64_t);
 840
 841         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 842                 if (ret) {
 843                         uint64_t *max_mem_alloc_size = ret;
 844
 845                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 846                 }
 847                 return sizeof(uint64_t);
 848
 849         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 850                 if (ret) {
 851                         uint32_t *max_clock_frequency = ret;
 852                         *max_clock_frequency = sscreen->info.max_shader_clock;
 853                 }
 854                 return sizeof(uint32_t);
 855
 856         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 857                 if (ret) {
 858                         uint32_t *max_compute_units = ret;
 859                         *max_compute_units = sscreen->info.num_good_compute_units;
 860                 }
 861                 return sizeof(uint32_t);
 862
 863         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 864                 if (ret) {
 865                         uint32_t *images_supported = ret;
 866                         *images_supported = 0;
 867                 }
 868                 return sizeof(uint32_t);
 869         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 870                 break; /* unused */
 871         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 872                 if (ret) {
 873                         uint32_t *subgroup_size = ret;
 874                         *subgroup_size = 64;
 875                 }
 876                 return sizeof(uint32_t);
 877         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 878                 if (ret) {
 879                         uint64_t *max_variable_threads_per_block = ret;
 880                         if (ir_type == PIPE_SHADER_IR_TGSI)
 881                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 882                         else
 883                                 *max_variable_threads_per_block = 0;
 884                 }
 885                 return sizeof(uint64_t);
 886         }
 887
 888         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 889         return 0;
 890 }
 891
 892 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 893 {
 894         struct si_screen *sscreen = (struct si_screen*)screen;
 895
 896         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 897                         sscreen->info.clock_crystal_freq;
 898 }
 899
 900 static void si_query_memory_info(struct pipe_screen *screen,
 901                                  struct pipe_memory_info *info)
 902 {
 903         struct si_screen *sscreen = (struct si_screen*)screen;
 904         struct radeon_winsys *ws = sscreen->ws;
 905         unsigned vram_usage, gtt_usage;
 906
 907         info->total_device_memory = sscreen->info.vram_size / 1024;
 908         info->total_staging_memory = sscreen->info.gart_size / 1024;
 909
 910         /* The real TTM memory usage is somewhat random, because:
 911          *
 912          * 1) TTM delays freeing memory, because it can only free it after
 913          *    fences expire.
 914          *
 915          * 2) The memory usage can be really low if big VRAM evictions are
 916          *    taking place, but the real usage is well above the size of VRAM.
 917          *
 918          * Instead, return statistics of this process.
 919          */
 920         vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
 921         gtt_usage =  ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
 922
 923         info->avail_device_memory =
 924                 vram_usage <= info->total_device_memory ?
 925                                 info->total_device_memory - vram_usage : 0;
 926         info->avail_staging_memory =
 927                 gtt_usage <= info->total_staging_memory ?
 928                                 info->total_staging_memory - gtt_usage : 0;
 929
 930         info->device_memory_evicted =
 931                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 932
 933         if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
 934                 info->nr_device_memory_evictions =
 935                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 936         else
 937                 /* Just return the number of evicted 64KB pages. */
 938                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 939 }
 940
 941 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 942 {
 943         struct si_screen *sscreen = (struct si_screen*)pscreen;
 944
 945         return sscreen->disk_shader_cache;
 946 }
 947
 948 static void si_init_renderer_string(struct si_screen *sscreen)
 949 {
 950         struct radeon_winsys *ws = sscreen->ws;
 951         char family_name[32] = {}, llvm_string[32] = {}, kernel_version[128] = {};
 952         struct utsname uname_data;
 953
 954         const char *chip_name = si_get_marketing_name(ws);
 955
 956         if (chip_name)
 957                 snprintf(family_name, sizeof(family_name), "%s / ",
 958                          si_get_family_name(sscreen) + 4);
 959         else
 960                 chip_name = si_get_family_name(sscreen);
 961
 962         if (uname(&uname_data) == 0)
 963                 snprintf(kernel_version, sizeof(kernel_version),
 964                          " / %s", uname_data.release);
 965
 966         if (HAVE_LLVM > 0) {
 967                 snprintf(llvm_string, sizeof(llvm_string),
 968                          ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
 969                          HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
 970         }
 971
 972         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 973                  "%s (%sDRM %i.%i.%i%s%s)",
 974                  chip_name, family_name, sscreen->info.drm_major,
 975                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 976                  kernel_version, llvm_string);
 977 }
 978
 979 void si_init_screen_get_functions(struct si_screen *sscreen)
 980 {
 981         sscreen->b.get_name = si_get_name;
 982         sscreen->b.get_vendor = si_get_vendor;
 983         sscreen->b.get_device_vendor = si_get_device_vendor;
 984         sscreen->b.get_param = si_get_param;
 985         sscreen->b.get_paramf = si_get_paramf;
 986         sscreen->b.get_compute_param = si_get_compute_param;
 987         sscreen->b.get_timestamp = si_get_timestamp;
 988         sscreen->b.get_shader_param = si_get_shader_param;
 989         sscreen->b.get_compiler_options = si_get_compiler_options;
 990         sscreen->b.get_device_uuid = si_get_device_uuid;
 991         sscreen->b.get_driver_uuid = si_get_driver_uuid;
 992         sscreen->b.query_memory_info = si_query_memory_info;
 993         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
 994
 995         if (sscreen->info.has_hw_decode) {
 996                 sscreen->b.get_video_param = si_get_video_param;
 997                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
 998         } else {
 999                 sscreen->b.get_video_param = si_get_video_param_no_decode;
1000                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1001         }
1002
1003         si_init_renderer_string(sscreen);
1004 }