2 * Copyright 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "radeon/radeon_video.h"
27 #include "radeon/radeon_vce.h"
28 #include "radeon/radeon_uvd_enc.h"
29 #include "vl/vl_decoder.h"
30 #include "vl/vl_video_buffer.h"
31 #include "util/u_screen.h"
32 #include "util/u_video.h"
33 #include "compiler/nir/nir.h"
35 #include <sys/utsname.h>
37 static const char *si_get_vendor(struct pipe_screen
*pscreen
)
39 /* Don't change this. Games such as Alien Isolation are broken if this
40 * returns "Advanced Micro Devices, Inc."
45 static const char *si_get_device_vendor(struct pipe_screen
*pscreen
)
50 static int si_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
52 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
55 /* Supported features (boolean caps). */
56 case PIPE_CAP_ACCELERATED
:
57 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
58 case PIPE_CAP_ANISOTROPIC_FILTER
:
59 case PIPE_CAP_POINT_SPRITE
:
60 case PIPE_CAP_OCCLUSION_QUERY
:
61 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
62 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE
:
63 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
64 case PIPE_CAP_TEXTURE_SWIZZLE
:
65 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
66 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE
:
67 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
68 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
69 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
70 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
71 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
72 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
73 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
74 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES
:
75 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
76 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
77 case PIPE_CAP_PRIMITIVE_RESTART
:
78 case PIPE_CAP_CONDITIONAL_RENDER
:
79 case PIPE_CAP_TEXTURE_BARRIER
:
80 case PIPE_CAP_INDEP_BLEND_ENABLE
:
81 case PIPE_CAP_INDEP_BLEND_FUNC
:
82 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
83 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
84 case PIPE_CAP_START_INSTANCE
:
85 case PIPE_CAP_NPOT_TEXTURES
:
86 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
87 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
88 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
89 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
90 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
91 case PIPE_CAP_TGSI_INSTANCEID
:
92 case PIPE_CAP_COMPUTE
:
93 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
94 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
95 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
96 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
97 case PIPE_CAP_CUBE_MAP_ARRAY
:
98 case PIPE_CAP_SAMPLE_SHADING
:
99 case PIPE_CAP_DRAW_INDIRECT
:
100 case PIPE_CAP_CLIP_HALFZ
:
101 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
102 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
103 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
104 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
105 case PIPE_CAP_TGSI_TEXCOORD
:
106 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
107 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
108 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
109 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
110 case PIPE_CAP_SHAREABLE_SHADERS
:
111 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
112 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
113 case PIPE_CAP_TEXTURE_QUERY_LOD
:
114 case PIPE_CAP_TEXTURE_GATHER_SM5
:
115 case PIPE_CAP_TGSI_TXQS
:
116 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
117 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
118 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
119 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
120 case PIPE_CAP_INVALIDATE_BUFFER
:
121 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
122 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
123 case PIPE_CAP_QUERY_MEMORY_INFO
:
124 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
125 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
126 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
127 case PIPE_CAP_GENERATE_MIPMAP
:
128 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
129 case PIPE_CAP_STRING_MARKER
:
130 case PIPE_CAP_CLEAR_TEXTURE
:
131 case PIPE_CAP_CULL_DISTANCE
:
132 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
133 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
134 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
135 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
136 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
137 case PIPE_CAP_DOUBLES
:
138 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
139 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
140 case PIPE_CAP_BINDLESS_TEXTURE
:
141 case PIPE_CAP_QUERY_TIMESTAMP
:
142 case PIPE_CAP_QUERY_TIME_ELAPSED
:
143 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
144 case PIPE_CAP_MEMOBJ
:
145 case PIPE_CAP_LOAD_CONSTBUF
:
147 case PIPE_CAP_INT64_DIVMOD
:
148 case PIPE_CAP_TGSI_CLOCK
:
149 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
150 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
151 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
:
152 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
153 case PIPE_CAP_TGSI_BALLOT
:
154 case PIPE_CAP_TGSI_VOTE
:
155 case PIPE_CAP_FBFETCH
:
156 case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK
:
157 case PIPE_CAP_IMAGE_LOAD_FORMATTED
:
158 case PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA
:
159 case PIPE_CAP_TGSI_DIV
:
160 case PIPE_CAP_PACKED_UNIFORMS
:
161 case PIPE_CAP_SHADER_SAMPLES_IDENTICAL
:
162 case PIPE_CAP_GL_SPIRV
:
165 case PIPE_CAP_QUERY_SO_OVERFLOW
:
166 return !sscreen
->use_ngg_streamout
;
168 case PIPE_CAP_POST_DEPTH_COVERAGE
:
169 return sscreen
->info
.chip_class
>= GFX10
;
171 case PIPE_CAP_GRAPHICS
:
172 return sscreen
->info
.has_graphics
;
174 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
175 return !SI_BIG_ENDIAN
&& sscreen
->info
.has_userptr
;
177 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
178 return sscreen
->info
.has_gpu_reset_status_query
;
180 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
181 return sscreen
->info
.has_2d_tiling
;
183 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
184 return SI_MAP_BUFFER_ALIGNMENT
;
186 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
187 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
188 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
189 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
190 case PIPE_CAP_MAX_VERTEX_STREAMS
:
191 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
192 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
195 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
196 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
197 if (!sscreen
->info
.has_indirect_compute_dispatch
)
201 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET
:
202 /* Optimal number for good TexSubImage performance on Polaris10. */
203 return 64 * 1024 * 1024;
205 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
206 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE
:
207 return MIN2(sscreen
->info
.max_alloc_size
, INT_MAX
);
209 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
210 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
211 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
212 return LLVM_VERSION_MAJOR
< 9 && !sscreen
->info
.has_unaligned_shader_loads
;
214 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
215 return sscreen
->info
.has_sparse_vm_mappings
?
216 RADEON_SPARSE_PAGE_SIZE
: 0;
222 case PIPE_CAP_FENCE_SIGNAL
:
223 return sscreen
->info
.has_syncobj
;
225 case PIPE_CAP_CONSTBUF0_FLAGS
:
226 return SI_RESOURCE_FLAG_32BIT
;
228 case PIPE_CAP_NATIVE_FENCE_FD
:
229 return sscreen
->info
.has_fence_to_handle
;
231 case PIPE_CAP_DRAW_PARAMETERS
:
232 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
233 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
234 return sscreen
->has_draw_indirect_multi
;
236 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
239 case PIPE_CAP_MAX_VARYINGS
:
242 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
243 return sscreen
->info
.chip_class
<= GFX8
?
244 PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600
: 0;
247 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
248 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
251 /* Geometry shader output. */
252 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
253 /* gfx9 has to report 256 to make piglit/gs-max-output pass.
254 * gfx8 and earlier can do 1024.
257 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
259 case PIPE_CAP_MAX_GS_INVOCATIONS
:
260 /* The closed driver exposes 127, but 125 is the greatest
261 * number that works. */
264 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
268 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
270 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
271 return 15; /* 16384 */
272 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
273 if (sscreen
->info
.chip_class
>= GFX10
)
275 /* textures support 8192, but layered rendering supports 2048 */
277 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
278 if (sscreen
->info
.chip_class
>= GFX10
)
280 /* textures support 8192, but layered rendering supports 2048 */
283 /* Viewports and render targets. */
284 case PIPE_CAP_MAX_VIEWPORTS
:
285 return SI_MAX_VIEWPORTS
;
286 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
287 case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS
:
288 case PIPE_CAP_MAX_RENDER_TARGETS
:
290 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS
:
291 return sscreen
->info
.has_eqaa_surface_allocator
? 2 : 0;
293 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
294 case PIPE_CAP_MIN_TEXEL_OFFSET
:
297 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
298 case PIPE_CAP_MAX_TEXEL_OFFSET
:
301 case PIPE_CAP_ENDIANNESS
:
302 return PIPE_ENDIAN_LITTLE
;
304 case PIPE_CAP_VENDOR_ID
:
305 return ATI_VENDOR_ID
;
306 case PIPE_CAP_DEVICE_ID
:
307 return sscreen
->info
.pci_id
;
308 case PIPE_CAP_VIDEO_MEMORY
:
309 return sscreen
->info
.vram_size
>> 20;
310 case PIPE_CAP_PCI_GROUP
:
311 return sscreen
->info
.pci_domain
;
312 case PIPE_CAP_PCI_BUS
:
313 return sscreen
->info
.pci_bus
;
314 case PIPE_CAP_PCI_DEVICE
:
315 return sscreen
->info
.pci_dev
;
316 case PIPE_CAP_PCI_FUNCTION
:
317 return sscreen
->info
.pci_func
;
318 case PIPE_CAP_TGSI_ATOMINC_WRAP
:
319 return LLVM_VERSION_MAJOR
>= 10;
322 return u_pipe_screen_get_param_defaults(pscreen
, param
);
326 static float si_get_paramf(struct pipe_screen
* pscreen
, enum pipe_capf param
)
329 case PIPE_CAPF_MAX_LINE_WIDTH
:
330 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
331 /* This depends on the quant mode, though the precise interactions
334 case PIPE_CAPF_MAX_POINT_WIDTH
:
335 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
336 return SI_MAX_POINT_SIZE
;
337 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
339 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
341 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
342 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
343 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
349 static int si_get_shader_param(struct pipe_screen
* pscreen
,
350 enum pipe_shader_type shader
,
351 enum pipe_shader_cap param
)
353 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
357 case PIPE_SHADER_FRAGMENT
:
358 case PIPE_SHADER_VERTEX
:
359 case PIPE_SHADER_GEOMETRY
:
360 case PIPE_SHADER_TESS_CTRL
:
361 case PIPE_SHADER_TESS_EVAL
:
363 case PIPE_SHADER_COMPUTE
:
365 case PIPE_SHADER_CAP_SUPPORTED_IRS
: {
366 int ir
= 1 << PIPE_SHADER_IR_NATIVE
;
368 if (sscreen
->info
.has_indirect_compute_dispatch
)
369 ir
|= 1 << PIPE_SHADER_IR_NIR
;
374 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
: {
375 uint64_t max_const_buffer_size
;
376 pscreen
->get_compute_param(pscreen
, PIPE_SHADER_IR_NIR
,
377 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
378 &max_const_buffer_size
);
379 return MIN2(max_const_buffer_size
, INT_MAX
);
382 /* If compute shaders don't require a special value
383 * for this cap, we can return the same value we
384 * do for other shader types. */
394 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
395 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
396 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
397 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
398 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
400 case PIPE_SHADER_CAP_MAX_INPUTS
:
401 return shader
== PIPE_SHADER_VERTEX
? SI_MAX_ATTRIBS
: 32;
402 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
403 return shader
== PIPE_SHADER_FRAGMENT
? 8 : 32;
404 case PIPE_SHADER_CAP_MAX_TEMPS
:
405 return 256; /* Max native temporaries. */
406 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
407 return MIN2(sscreen
->info
.max_alloc_size
, INT_MAX
- 3); /* aligned to 4 */
408 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
409 return SI_NUM_CONST_BUFFERS
;
410 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
411 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
412 return SI_NUM_SAMPLERS
;
413 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
414 return SI_NUM_SHADER_BUFFERS
;
415 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
416 return SI_NUM_IMAGES
;
417 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
419 case PIPE_SHADER_CAP_PREFERRED_IR
:
420 return PIPE_SHADER_IR_NIR
;
421 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
424 /* Supported boolean features. */
425 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
426 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
427 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
428 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
429 case PIPE_SHADER_CAP_INTEGERS
:
430 case PIPE_SHADER_CAP_INT64_ATOMICS
:
431 case PIPE_SHADER_CAP_FP16
:
432 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
433 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
434 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
435 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
436 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
437 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
440 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
441 /* TODO: Indirect indexing of GS inputs is unimplemented. */
442 if (shader
== PIPE_SHADER_GEOMETRY
)
445 if (shader
== PIPE_SHADER_VERTEX
&&
446 !sscreen
->llvm_has_working_vgpr_indexing
)
449 /* TCS and TES load inputs directly from LDS or offchip
450 * memory, so indirect indexing is always supported.
451 * PS has to support indirect indexing, because we can't
452 * lower that to TEMPs for INTERP instructions.
456 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
457 return sscreen
->llvm_has_working_vgpr_indexing
||
458 /* TCS stores outputs directly to memory. */
459 shader
== PIPE_SHADER_TESS_CTRL
;
461 /* Unsupported boolean features. */
462 case PIPE_SHADER_CAP_SUBROUTINES
:
463 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
464 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
465 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
471 static const struct nir_shader_compiler_options nir_options
= {
473 .lower_flrp32
= true,
474 .lower_flrp64
= true,
477 .lower_bitfield_insert_to_bitfield_select
= true,
478 .lower_bitfield_extract
= true,
482 .lower_pack_snorm_4x8
= true,
483 .lower_pack_unorm_4x8
= true,
484 .lower_unpack_snorm_2x16
= true,
485 .lower_unpack_snorm_4x8
= true,
486 .lower_unpack_unorm_2x16
= true,
487 .lower_unpack_unorm_4x8
= true,
488 .lower_extract_byte
= true,
489 .lower_extract_word
= true,
490 .lower_rotate
= true,
491 .lower_to_scalar
= true,
492 .optimize_sample_mask_in
= true,
493 .max_unroll_iterations
= 32,
494 .use_interpolated_input_intrinsics
= true,
498 si_get_compiler_options(struct pipe_screen
*screen
,
499 enum pipe_shader_ir ir
,
500 enum pipe_shader_type shader
)
502 assert(ir
== PIPE_SHADER_IR_NIR
);
506 static void si_get_driver_uuid(struct pipe_screen
*pscreen
, char *uuid
)
508 ac_compute_driver_uuid(uuid
, PIPE_UUID_SIZE
);
511 static void si_get_device_uuid(struct pipe_screen
*pscreen
, char *uuid
)
513 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
515 ac_compute_device_uuid(&sscreen
->info
, uuid
, PIPE_UUID_SIZE
);
518 static const char* si_get_name(struct pipe_screen
*pscreen
)
520 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
522 return sscreen
->renderer_string
;
525 static int si_get_video_param_no_decode(struct pipe_screen
*screen
,
526 enum pipe_video_profile profile
,
527 enum pipe_video_entrypoint entrypoint
,
528 enum pipe_video_cap param
)
531 case PIPE_VIDEO_CAP_SUPPORTED
:
532 return vl_profile_supported(screen
, profile
, entrypoint
);
533 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
535 case PIPE_VIDEO_CAP_MAX_WIDTH
:
536 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
537 return vl_video_buffer_max_size(screen
);
538 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
539 return PIPE_FORMAT_NV12
;
540 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
542 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
544 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
546 case PIPE_VIDEO_CAP_MAX_LEVEL
:
547 return vl_level_supported(screen
, profile
);
553 static int si_get_video_param(struct pipe_screen
*screen
,
554 enum pipe_video_profile profile
,
555 enum pipe_video_entrypoint entrypoint
,
556 enum pipe_video_cap param
)
558 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
559 enum pipe_video_format codec
= u_reduce_video_profile(profile
);
561 if (entrypoint
== PIPE_VIDEO_ENTRYPOINT_ENCODE
) {
563 case PIPE_VIDEO_CAP_SUPPORTED
:
564 return (codec
== PIPE_VIDEO_FORMAT_MPEG4_AVC
&&
565 (si_vce_is_fw_version_supported(sscreen
) ||
566 sscreen
->info
.family
>= CHIP_RAVEN
)) ||
567 (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
&&
568 (sscreen
->info
.family
>= CHIP_RAVEN
||
569 si_radeon_uvd_enc_supported(sscreen
)));
570 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
572 case PIPE_VIDEO_CAP_MAX_WIDTH
:
573 return (sscreen
->info
.family
< CHIP_TONGA
) ? 2048 : 4096;
574 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
575 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1152 : 2304;
576 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
577 return PIPE_FORMAT_NV12
;
578 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
580 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
582 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
584 case PIPE_VIDEO_CAP_STACKED_FRAMES
:
585 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1 : 2;
592 case PIPE_VIDEO_CAP_SUPPORTED
:
594 case PIPE_VIDEO_FORMAT_MPEG12
:
595 return profile
!= PIPE_VIDEO_PROFILE_MPEG1
;
596 case PIPE_VIDEO_FORMAT_MPEG4
:
598 case PIPE_VIDEO_FORMAT_MPEG4_AVC
:
599 if ((sscreen
->info
.family
== CHIP_POLARIS10
||
600 sscreen
->info
.family
== CHIP_POLARIS11
) &&
601 sscreen
->info
.uvd_fw_version
< UVD_FW_1_66_16
) {
602 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
606 case PIPE_VIDEO_FORMAT_VC1
:
608 case PIPE_VIDEO_FORMAT_HEVC
:
609 /* Carrizo only supports HEVC Main */
610 if (sscreen
->info
.family
>= CHIP_STONEY
)
611 return (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
||
612 profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
);
613 else if (sscreen
->info
.family
>= CHIP_CARRIZO
)
614 return profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
;
616 case PIPE_VIDEO_FORMAT_JPEG
:
617 if (sscreen
->info
.family
>= CHIP_RAVEN
)
619 if (sscreen
->info
.family
< CHIP_CARRIZO
|| sscreen
->info
.family
>= CHIP_VEGA10
)
621 if (!(sscreen
->info
.is_amdgpu
&& sscreen
->info
.drm_minor
>= 19)) {
622 RVID_ERR("No MJPEG support for the kernel version\n");
626 case PIPE_VIDEO_FORMAT_VP9
:
627 if (sscreen
->info
.family
< CHIP_RAVEN
)
633 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
635 case PIPE_VIDEO_CAP_MAX_WIDTH
:
637 case PIPE_VIDEO_FORMAT_HEVC
:
638 case PIPE_VIDEO_FORMAT_VP9
:
639 return (sscreen
->info
.family
< CHIP_RENOIR
) ?
640 ((sscreen
->info
.family
< CHIP_TONGA
) ? 2048 : 4096) :
643 return (sscreen
->info
.family
< CHIP_TONGA
) ? 2048 : 4096;
645 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
647 case PIPE_VIDEO_FORMAT_HEVC
:
648 case PIPE_VIDEO_FORMAT_VP9
:
649 return (sscreen
->info
.family
< CHIP_RENOIR
) ?
650 ((sscreen
->info
.family
< CHIP_TONGA
) ? 1152 : 4096) :
653 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1152 : 4096;
655 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
656 if (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
)
657 return PIPE_FORMAT_P010
;
658 else if (profile
== PIPE_VIDEO_PROFILE_VP9_PROFILE2
)
659 return PIPE_FORMAT_P016
;
661 return PIPE_FORMAT_NV12
;
663 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
664 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
: {
665 enum pipe_video_format format
= u_reduce_video_profile(profile
);
667 if (format
== PIPE_VIDEO_FORMAT_HEVC
)
668 return false; //The firmware doesn't support interlaced HEVC.
669 else if (format
== PIPE_VIDEO_FORMAT_JPEG
)
671 else if (format
== PIPE_VIDEO_FORMAT_VP9
)
675 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
677 case PIPE_VIDEO_CAP_MAX_LEVEL
:
679 case PIPE_VIDEO_PROFILE_MPEG1
:
681 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE
:
682 case PIPE_VIDEO_PROFILE_MPEG2_MAIN
:
684 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE
:
686 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE
:
688 case PIPE_VIDEO_PROFILE_VC1_SIMPLE
:
690 case PIPE_VIDEO_PROFILE_VC1_MAIN
:
692 case PIPE_VIDEO_PROFILE_VC1_ADVANCED
:
694 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE
:
695 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN
:
696 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH
:
697 return (sscreen
->info
.family
< CHIP_TONGA
) ? 41 : 52;
698 case PIPE_VIDEO_PROFILE_HEVC_MAIN
:
699 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10
:
709 static bool si_vid_is_format_supported(struct pipe_screen
*screen
,
710 enum pipe_format format
,
711 enum pipe_video_profile profile
,
712 enum pipe_video_entrypoint entrypoint
)
714 /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
715 if (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
)
716 return (format
== PIPE_FORMAT_NV12
) ||
717 (format
== PIPE_FORMAT_P016
);
719 /* Vp9 profile 2 supports 10 bit decoding using P016 */
720 if (profile
== PIPE_VIDEO_PROFILE_VP9_PROFILE2
)
721 return format
== PIPE_FORMAT_P016
;
724 /* we can only handle this one with UVD */
725 if (profile
!= PIPE_VIDEO_PROFILE_UNKNOWN
)
726 return format
== PIPE_FORMAT_NV12
;
728 return vl_video_buffer_is_format_supported(screen
, format
, profile
, entrypoint
);
731 static unsigned get_max_threads_per_block(struct si_screen
*screen
,
732 enum pipe_shader_ir ir_type
)
734 if (ir_type
== PIPE_SHADER_IR_NATIVE
)
737 /* LLVM 10 only supports 1024 threads per block. */
741 static int si_get_compute_param(struct pipe_screen
*screen
,
742 enum pipe_shader_ir ir_type
,
743 enum pipe_compute_cap param
,
746 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
748 //TODO: select these params by asic
750 case PIPE_COMPUTE_CAP_IR_TARGET
: {
751 const char *gpu
, *triple
;
753 triple
= "amdgcn-mesa-mesa3d";
754 gpu
= ac_get_llvm_processor_name(sscreen
->info
.family
);
756 sprintf(ret
, "%s-%s", gpu
, triple
);
758 /* +2 for dash and terminating NIL byte */
759 return (strlen(triple
) + strlen(gpu
) + 2) * sizeof(char);
761 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
763 uint64_t *grid_dimension
= ret
;
764 grid_dimension
[0] = 3;
766 return 1 * sizeof(uint64_t);
768 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
770 uint64_t *grid_size
= ret
;
771 grid_size
[0] = 65535;
772 grid_size
[1] = 65535;
773 grid_size
[2] = 65535;
775 return 3 * sizeof(uint64_t) ;
777 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
779 uint64_t *block_size
= ret
;
780 unsigned threads_per_block
= get_max_threads_per_block(sscreen
, ir_type
);
781 block_size
[0] = threads_per_block
;
782 block_size
[1] = threads_per_block
;
783 block_size
[2] = threads_per_block
;
785 return 3 * sizeof(uint64_t);
787 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
789 uint64_t *max_threads_per_block
= ret
;
790 *max_threads_per_block
= get_max_threads_per_block(sscreen
, ir_type
);
792 return sizeof(uint64_t);
793 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
795 uint32_t *address_bits
= ret
;
796 address_bits
[0] = 64;
798 return 1 * sizeof(uint32_t);
800 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
802 uint64_t *max_global_size
= ret
;
803 uint64_t max_mem_alloc_size
;
805 si_get_compute_param(screen
, ir_type
,
806 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
807 &max_mem_alloc_size
);
809 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
810 * 1/4 of the MAX_GLOBAL_SIZE. Since the
811 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
812 * make sure we never report more than
813 * 4 * MAX_MEM_ALLOC_SIZE.
815 *max_global_size
= MIN2(4 * max_mem_alloc_size
,
816 MAX2(sscreen
->info
.gart_size
,
817 sscreen
->info
.vram_size
));
819 return sizeof(uint64_t);
821 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
823 uint64_t *max_local_size
= ret
;
824 /* Value reported by the closed source driver. */
825 *max_local_size
= 32768;
827 return sizeof(uint64_t);
829 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
831 uint64_t *max_input_size
= ret
;
832 /* Value reported by the closed source driver. */
833 *max_input_size
= 1024;
835 return sizeof(uint64_t);
837 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
839 uint64_t *max_mem_alloc_size
= ret
;
841 *max_mem_alloc_size
= sscreen
->info
.max_alloc_size
;
843 return sizeof(uint64_t);
845 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
847 uint32_t *max_clock_frequency
= ret
;
848 *max_clock_frequency
= sscreen
->info
.max_shader_clock
;
850 return sizeof(uint32_t);
852 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
854 uint32_t *max_compute_units
= ret
;
855 *max_compute_units
= sscreen
->info
.num_good_compute_units
;
857 return sizeof(uint32_t);
859 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
861 uint32_t *images_supported
= ret
;
862 *images_supported
= 0;
864 return sizeof(uint32_t);
865 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
867 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
869 uint32_t *subgroup_size
= ret
;
870 *subgroup_size
= sscreen
->compute_wave_size
;
872 return sizeof(uint32_t);
873 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
875 uint64_t *max_variable_threads_per_block
= ret
;
876 if (ir_type
== PIPE_SHADER_IR_NATIVE
)
877 *max_variable_threads_per_block
= 0;
879 *max_variable_threads_per_block
= SI_MAX_VARIABLE_THREADS_PER_BLOCK
;
881 return sizeof(uint64_t);
884 fprintf(stderr
, "unknown PIPE_COMPUTE_CAP %d\n", param
);
888 static uint64_t si_get_timestamp(struct pipe_screen
*screen
)
890 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
892 return 1000000 * sscreen
->ws
->query_value(sscreen
->ws
, RADEON_TIMESTAMP
) /
893 sscreen
->info
.clock_crystal_freq
;
896 static void si_query_memory_info(struct pipe_screen
*screen
,
897 struct pipe_memory_info
*info
)
899 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
900 struct radeon_winsys
*ws
= sscreen
->ws
;
901 unsigned vram_usage
, gtt_usage
;
903 info
->total_device_memory
= sscreen
->info
.vram_size
/ 1024;
904 info
->total_staging_memory
= sscreen
->info
.gart_size
/ 1024;
906 /* The real TTM memory usage is somewhat random, because:
908 * 1) TTM delays freeing memory, because it can only free it after
911 * 2) The memory usage can be really low if big VRAM evictions are
912 * taking place, but the real usage is well above the size of VRAM.
914 * Instead, return statistics of this process.
916 vram_usage
= ws
->query_value(ws
, RADEON_VRAM_USAGE
) / 1024;
917 gtt_usage
= ws
->query_value(ws
, RADEON_GTT_USAGE
) / 1024;
919 info
->avail_device_memory
=
920 vram_usage
<= info
->total_device_memory
?
921 info
->total_device_memory
- vram_usage
: 0;
922 info
->avail_staging_memory
=
923 gtt_usage
<= info
->total_staging_memory
?
924 info
->total_staging_memory
- gtt_usage
: 0;
926 info
->device_memory_evicted
=
927 ws
->query_value(ws
, RADEON_NUM_BYTES_MOVED
) / 1024;
929 if (sscreen
->info
.is_amdgpu
&& sscreen
->info
.drm_minor
>= 4)
930 info
->nr_device_memory_evictions
=
931 ws
->query_value(ws
, RADEON_NUM_EVICTIONS
);
933 /* Just return the number of evicted 64KB pages. */
934 info
->nr_device_memory_evictions
= info
->device_memory_evicted
/ 64;
937 static struct disk_cache
*si_get_disk_shader_cache(struct pipe_screen
*pscreen
)
939 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
941 return sscreen
->disk_shader_cache
;
944 static void si_init_renderer_string(struct si_screen
*sscreen
)
946 char first_name
[256], second_name
[32] = {}, kernel_version
[128] = {};
947 struct utsname uname_data
;
949 if (sscreen
->info
.marketing_name
) {
950 snprintf(first_name
, sizeof(first_name
), "%s",
951 sscreen
->info
.marketing_name
);
952 snprintf(second_name
, sizeof(second_name
), "%s, ",
955 snprintf(first_name
, sizeof(first_name
), "AMD %s",
959 if (uname(&uname_data
) == 0)
960 snprintf(kernel_version
, sizeof(kernel_version
),
961 ", %s", uname_data
.release
);
963 snprintf(sscreen
->renderer_string
, sizeof(sscreen
->renderer_string
),
964 "%s (%sDRM %i.%i.%i%s, LLVM " MESA_LLVM_VERSION_STRING
")",
965 first_name
, second_name
, sscreen
->info
.drm_major
,
966 sscreen
->info
.drm_minor
, sscreen
->info
.drm_patchlevel
,
970 void si_init_screen_get_functions(struct si_screen
*sscreen
)
972 sscreen
->b
.get_name
= si_get_name
;
973 sscreen
->b
.get_vendor
= si_get_vendor
;
974 sscreen
->b
.get_device_vendor
= si_get_device_vendor
;
975 sscreen
->b
.get_param
= si_get_param
;
976 sscreen
->b
.get_paramf
= si_get_paramf
;
977 sscreen
->b
.get_compute_param
= si_get_compute_param
;
978 sscreen
->b
.get_timestamp
= si_get_timestamp
;
979 sscreen
->b
.get_shader_param
= si_get_shader_param
;
980 sscreen
->b
.get_compiler_options
= si_get_compiler_options
;
981 sscreen
->b
.get_device_uuid
= si_get_device_uuid
;
982 sscreen
->b
.get_driver_uuid
= si_get_driver_uuid
;
983 sscreen
->b
.query_memory_info
= si_query_memory_info
;
984 sscreen
->b
.get_disk_shader_cache
= si_get_disk_shader_cache
;
986 if (sscreen
->info
.has_hw_decode
) {
987 sscreen
->b
.get_video_param
= si_get_video_param
;
988 sscreen
->b
.is_video_format_supported
= si_vid_is_format_supported
;
990 sscreen
->b
.get_video_param
= si_get_video_param_no_decode
;
991 sscreen
->b
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
994 si_init_renderer_string(sscreen
);