src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "radeon/radeon_video.h"
  26 #include "ac_llvm_util.h"
  27 #include "vl/vl_decoder.h"
  28 #include "vl/vl_video_buffer.h"
  29 #include "compiler/nir/nir.h"
  30
  31 #include <sys/utsname.h>
  32
  33 static const char *si_get_vendor(struct pipe_screen *pscreen)
  34 {
  35         return "X.Org";
  36 }
  37
  38 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  39 {
  40         return "AMD";
  41 }
  42
  43 static const char *si_get_marketing_name(struct radeon_winsys *ws)
  44 {
  45         if (!ws->get_chip_name)
  46                 return NULL;
  47         return ws->get_chip_name(ws);
  48 }
  49
  50 const char *si_get_family_name(const struct si_screen *sscreen)
  51 {
  52         switch (sscreen->b.info.family) {
  53         case CHIP_TAHITI: return "AMD TAHITI";
  54         case CHIP_PITCAIRN: return "AMD PITCAIRN";
  55         case CHIP_VERDE: return "AMD CAPE VERDE";
  56         case CHIP_OLAND: return "AMD OLAND";
  57         case CHIP_HAINAN: return "AMD HAINAN";
  58         case CHIP_BONAIRE: return "AMD BONAIRE";
  59         case CHIP_KAVERI: return "AMD KAVERI";
  60         case CHIP_KABINI: return "AMD KABINI";
  61         case CHIP_HAWAII: return "AMD HAWAII";
  62         case CHIP_MULLINS: return "AMD MULLINS";
  63         case CHIP_TONGA: return "AMD TONGA";
  64         case CHIP_ICELAND: return "AMD ICELAND";
  65         case CHIP_CARRIZO: return "AMD CARRIZO";
  66         case CHIP_FIJI: return "AMD FIJI";
  67         case CHIP_POLARIS10: return "AMD POLARIS10";
  68         case CHIP_POLARIS11: return "AMD POLARIS11";
  69         case CHIP_POLARIS12: return "AMD POLARIS12";
  70         case CHIP_STONEY: return "AMD STONEY";
  71         case CHIP_VEGA10: return "AMD VEGA10";
  72         case CHIP_RAVEN: return "AMD RAVEN";
  73         default: return "AMD unknown";
  74         }
  75 }
  76
  77 static bool si_have_tgsi_compute(struct si_screen *sscreen)
  78 {
  79         /* Old kernels disallowed some register writes for SI
  80          * that are used for indirect dispatches. */
  81         return (sscreen->b.chip_class >= CIK ||
  82                 sscreen->b.info.drm_major == 3 ||
  83                 (sscreen->b.info.drm_major == 2 &&
  84                  sscreen->b.info.drm_minor >= 45));
  85 }
  86
  87 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  88 {
  89         struct si_screen *sscreen = (struct si_screen *)pscreen;
  90
  91         switch (param) {
  92         /* Supported features (boolean caps). */
  93         case PIPE_CAP_ACCELERATED:
  94         case PIPE_CAP_TWO_SIDED_STENCIL:
  95         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  96         case PIPE_CAP_ANISOTROPIC_FILTER:
  97         case PIPE_CAP_POINT_SPRITE:
  98         case PIPE_CAP_OCCLUSION_QUERY:
  99         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 100         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 101         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 102         case PIPE_CAP_TEXTURE_SWIZZLE:
 103         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 104         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 105         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 106         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 107         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 108         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 109         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 110         case PIPE_CAP_SM3:
 111         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 112         case PIPE_CAP_PRIMITIVE_RESTART:
 113         case PIPE_CAP_CONDITIONAL_RENDER:
 114         case PIPE_CAP_TEXTURE_BARRIER:
 115         case PIPE_CAP_INDEP_BLEND_ENABLE:
 116         case PIPE_CAP_INDEP_BLEND_FUNC:
 117         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 118         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 119         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 120         case PIPE_CAP_START_INSTANCE:
 121         case PIPE_CAP_NPOT_TEXTURES:
 122         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 123         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 124         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 125         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 126         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 127         case PIPE_CAP_TGSI_INSTANCEID:
 128         case PIPE_CAP_COMPUTE:
 129         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 130         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 131         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 132         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 133         case PIPE_CAP_CUBE_MAP_ARRAY:
 134         case PIPE_CAP_SAMPLE_SHADING:
 135         case PIPE_CAP_DRAW_INDIRECT:
 136         case PIPE_CAP_CLIP_HALFZ:
 137         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 138         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 139         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 140         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 141         case PIPE_CAP_TGSI_TEXCOORD:
 142         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 143         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 144         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 145         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 146         case PIPE_CAP_SHAREABLE_SHADERS:
 147         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 148         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 149         case PIPE_CAP_TEXTURE_QUERY_LOD:
 150         case PIPE_CAP_TEXTURE_GATHER_SM5:
 151         case PIPE_CAP_TGSI_TXQS:
 152         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 153         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 154         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 155         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 156         case PIPE_CAP_INVALIDATE_BUFFER:
 157         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 158         case PIPE_CAP_QUERY_MEMORY_INFO:
 159         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 160         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 161         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 162         case PIPE_CAP_GENERATE_MIPMAP:
 163         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 164         case PIPE_CAP_STRING_MARKER:
 165         case PIPE_CAP_CLEAR_TEXTURE:
 166         case PIPE_CAP_CULL_DISTANCE:
 167         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 168         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 169         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 170         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 171         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 172         case PIPE_CAP_DOUBLES:
 173         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 174         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 175         case PIPE_CAP_BINDLESS_TEXTURE:
 176         case PIPE_CAP_QUERY_TIMESTAMP:
 177         case PIPE_CAP_QUERY_TIME_ELAPSED:
 178         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 179         case PIPE_CAP_QUERY_SO_OVERFLOW:
 180         case PIPE_CAP_MEMOBJ:
 181         case PIPE_CAP_LOAD_CONSTBUF:
 182         case PIPE_CAP_INT64:
 183         case PIPE_CAP_INT64_DIVMOD:
 184         case PIPE_CAP_TGSI_CLOCK:
 185         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 186         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 187         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 188         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 189                 return 1;
 190
 191         case PIPE_CAP_TGSI_VOTE:
 192                 return HAVE_LLVM >= 0x0400;
 193
 194         case PIPE_CAP_TGSI_BALLOT:
 195                 return HAVE_LLVM >= 0x0500;
 196
 197         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 198                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 199
 200         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 201                 return (sscreen->b.info.drm_major == 2 &&
 202                         sscreen->b.info.drm_minor >= 43) ||
 203                        sscreen->b.info.drm_major == 3;
 204
 205         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 206                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 207                 return sscreen->b.chip_class < CIK ||
 208                        (sscreen->b.info.drm_major == 2 &&
 209                         sscreen->b.info.drm_minor >= 35) ||
 210                        sscreen->b.info.drm_major == 3;
 211
 212         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 213                 return R600_MAP_BUFFER_ALIGNMENT;
 214
 215         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 216         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 217         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 218         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 219         case PIPE_CAP_MAX_VERTEX_STREAMS:
 220         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 221                 return 4;
 222
 223         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 224                 if (sscreen->b.debug_flags & DBG(NIR))
 225                         return 140; /* no geometry and tessellation shaders yet */
 226                 if (si_have_tgsi_compute(sscreen))
 227                         return 450;
 228                 return 420;
 229
 230         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 231                 return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
 232
 233         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 234         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 235         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 236                 /* SI doesn't support unaligned loads.
 237                  * CIK needs DRM 2.50.0 on radeon. */
 238                 return sscreen->b.chip_class == SI ||
 239                        (sscreen->b.info.drm_major == 2 &&
 240                         sscreen->b.info.drm_minor < 50);
 241
 242         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 243                 /* TODO: GFX9 hangs. */
 244                 if (sscreen->b.chip_class >= GFX9)
 245                         return 0;
 246                 /* Disable on SI due to VM faults in CP DMA. Enable once these
 247                  * faults are mitigated in software.
 248                  */
 249                 if (sscreen->b.chip_class >= CIK &&
 250                     sscreen->b.info.drm_major == 3 &&
 251                     sscreen->b.info.drm_minor >= 13)
 252                         return RADEON_SPARSE_PAGE_SIZE;
 253                 return 0;
 254
 255         /* Unsupported features. */
 256         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 257         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 258         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 259         case PIPE_CAP_USER_VERTEX_BUFFERS:
 260         case PIPE_CAP_FAKE_SW_MSAA:
 261         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 262         case PIPE_CAP_VERTEXID_NOBASE:
 263         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 264         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 265         case PIPE_CAP_TGSI_FS_FBFETCH:
 266         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 267         case PIPE_CAP_UMA:
 268         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 269         case PIPE_CAP_POST_DEPTH_COVERAGE:
 270         case PIPE_CAP_TILE_RASTER_ORDER:
 271         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 272                 return 0;
 273
 274         case PIPE_CAP_NATIVE_FENCE_FD:
 275                 return sscreen->b.info.has_sync_file;
 276
 277         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 278                 return si_have_tgsi_compute(sscreen);
 279
 280         case PIPE_CAP_DRAW_PARAMETERS:
 281         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 282         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 283                 return sscreen->has_draw_indirect_multi;
 284
 285         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 286                 return 30;
 287
 288         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 289                 return sscreen->b.chip_class <= VI ?
 290                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 291
 292         /* Stream output. */
 293         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 294         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 295                 return 32*4;
 296
 297         /* Geometry shader output. */
 298         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 299                 return 1024;
 300         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 301                 return 4095;
 302
 303         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 304                 return 2048;
 305
 306         /* Texturing. */
 307         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 308         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 309                 return 15; /* 16384 */
 310         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 311                 /* textures support 8192, but layered rendering supports 2048 */
 312                 return 12;
 313         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 314                 /* textures support 8192, but layered rendering supports 2048 */
 315                 return 2048;
 316
 317         /* Viewports and render targets. */
 318         case PIPE_CAP_MAX_VIEWPORTS:
 319                 return SI_MAX_VIEWPORTS;
 320         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 321         case PIPE_CAP_MAX_RENDER_TARGETS:
 322                 return 8;
 323
 324         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 325         case PIPE_CAP_MIN_TEXEL_OFFSET:
 326                 return -32;
 327
 328         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 329         case PIPE_CAP_MAX_TEXEL_OFFSET:
 330                 return 31;
 331
 332         case PIPE_CAP_ENDIANNESS:
 333                 return PIPE_ENDIAN_LITTLE;
 334
 335         case PIPE_CAP_VENDOR_ID:
 336                 return ATI_VENDOR_ID;
 337         case PIPE_CAP_DEVICE_ID:
 338                 return sscreen->b.info.pci_id;
 339         case PIPE_CAP_VIDEO_MEMORY:
 340                 return sscreen->b.info.vram_size >> 20;
 341         case PIPE_CAP_PCI_GROUP:
 342                 return sscreen->b.info.pci_domain;
 343         case PIPE_CAP_PCI_BUS:
 344                 return sscreen->b.info.pci_bus;
 345         case PIPE_CAP_PCI_DEVICE:
 346                 return sscreen->b.info.pci_dev;
 347         case PIPE_CAP_PCI_FUNCTION:
 348                 return sscreen->b.info.pci_func;
 349         }
 350         return 0;
 351 }
 352
 353 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 354 {
 355         switch (param) {
 356         case PIPE_CAPF_MAX_LINE_WIDTH:
 357         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 358         case PIPE_CAPF_MAX_POINT_WIDTH:
 359         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 360                 return 8192.0f;
 361         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 362                 return 16.0f;
 363         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 364                 return 16.0f;
 365         case PIPE_CAPF_GUARD_BAND_LEFT:
 366         case PIPE_CAPF_GUARD_BAND_TOP:
 367         case PIPE_CAPF_GUARD_BAND_RIGHT:
 368         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 369                 return 0.0f;
 370         }
 371         return 0.0f;
 372 }
 373
 374 static int si_get_shader_param(struct pipe_screen* pscreen,
 375                                enum pipe_shader_type shader,
 376                                enum pipe_shader_cap param)
 377 {
 378         struct si_screen *sscreen = (struct si_screen *)pscreen;
 379
 380         switch(shader)
 381         {
 382         case PIPE_SHADER_FRAGMENT:
 383         case PIPE_SHADER_VERTEX:
 384         case PIPE_SHADER_GEOMETRY:
 385         case PIPE_SHADER_TESS_CTRL:
 386         case PIPE_SHADER_TESS_EVAL:
 387                 break;
 388         case PIPE_SHADER_COMPUTE:
 389                 switch (param) {
 390                 case PIPE_SHADER_CAP_PREFERRED_IR:
 391                         return PIPE_SHADER_IR_NATIVE;
 392
 393                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 394                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 395
 396                         if (si_have_tgsi_compute(sscreen))
 397                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 398
 399                         return ir;
 400                 }
 401
 402                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 403                         uint64_t max_const_buffer_size;
 404                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 405                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 406                                 &max_const_buffer_size);
 407                         return MIN2(max_const_buffer_size, INT_MAX);
 408                 }
 409                 default:
 410                         /* If compute shaders don't require a special value
 411                          * for this cap, we can return the same value we
 412                          * do for other shader types. */
 413                         break;
 414                 }
 415                 break;
 416         default:
 417                 return 0;
 418         }
 419
 420         switch (param) {
 421         /* Shader limits. */
 422         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 423         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 424         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 425         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 426         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 427                 return 16384;
 428         case PIPE_SHADER_CAP_MAX_INPUTS:
 429                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 430         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 431                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 432         case PIPE_SHADER_CAP_MAX_TEMPS:
 433                 return 256; /* Max native temporaries. */
 434         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 435                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 436         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 437                 return SI_NUM_CONST_BUFFERS;
 438         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 439         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 440                 return SI_NUM_SAMPLERS;
 441         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 442                 return SI_NUM_SHADER_BUFFERS;
 443         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 444                 return SI_NUM_IMAGES;
 445         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 446                 return 32;
 447         case PIPE_SHADER_CAP_PREFERRED_IR:
 448                 if (sscreen->b.debug_flags & DBG(NIR) &&
 449                     (shader == PIPE_SHADER_VERTEX ||
 450                      shader == PIPE_SHADER_FRAGMENT))
 451                         return PIPE_SHADER_IR_NIR;
 452                 return PIPE_SHADER_IR_TGSI;
 453         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 454                 return 4;
 455
 456         /* Supported boolean features. */
 457         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 458         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 459         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 460         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 461         case PIPE_SHADER_CAP_INTEGERS:
 462         case PIPE_SHADER_CAP_INT64_ATOMICS:
 463         case PIPE_SHADER_CAP_FP16:
 464         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 465         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 466         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 467         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 468         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 469         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 470                 return 1;
 471
 472         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 473                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 474                 return shader != PIPE_SHADER_GEOMETRY &&
 475                        (sscreen->llvm_has_working_vgpr_indexing ||
 476                         /* TCS and TES load inputs directly from LDS or
 477                          * offchip memory, so indirect indexing is trivial. */
 478                         shader == PIPE_SHADER_TESS_CTRL ||
 479                         shader == PIPE_SHADER_TESS_EVAL);
 480
 481         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 482                 return sscreen->llvm_has_working_vgpr_indexing ||
 483                        /* TCS stores outputs directly to memory. */
 484                        shader == PIPE_SHADER_TESS_CTRL;
 485
 486         /* Unsupported boolean features. */
 487         case PIPE_SHADER_CAP_SUBROUTINES:
 488         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 489         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 490         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 491                 return 0;
 492         }
 493         return 0;
 494 }
 495
 496 static const struct nir_shader_compiler_options nir_options = {
 497         .vertex_id_zero_based = true,
 498         .lower_scmp = true,
 499         .lower_flrp32 = true,
 500         .lower_fsat = true,
 501         .lower_fdiv = true,
 502         .lower_sub = true,
 503         .lower_ffma = true,
 504         .lower_pack_snorm_2x16 = true,
 505         .lower_pack_snorm_4x8 = true,
 506         .lower_pack_unorm_2x16 = true,
 507         .lower_pack_unorm_4x8 = true,
 508         .lower_unpack_snorm_2x16 = true,
 509         .lower_unpack_snorm_4x8 = true,
 510         .lower_unpack_unorm_2x16 = true,
 511         .lower_unpack_unorm_4x8 = true,
 512         .lower_extract_byte = true,
 513         .lower_extract_word = true,
 514         .max_unroll_iterations = 32,
 515         .native_integers = true,
 516 };
 517
 518 static const void *
 519 si_get_compiler_options(struct pipe_screen *screen,
 520                         enum pipe_shader_ir ir,
 521                         enum pipe_shader_type shader)
 522 {
 523         assert(ir == PIPE_SHADER_IR_NIR);
 524         return &nir_options;
 525 }
 526
 527 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 528 {
 529         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 530 }
 531
 532 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 533 {
 534         struct si_screen *sscreen = (struct si_screen *)pscreen;
 535
 536         ac_compute_device_uuid(&sscreen->b.info, uuid, PIPE_UUID_SIZE);
 537 }
 538
 539 static const char* si_get_name(struct pipe_screen *pscreen)
 540 {
 541         struct si_screen *sscreen = (struct si_screen*)pscreen;
 542
 543         return sscreen->b.renderer_string;
 544 }
 545
 546 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 547                                         enum pipe_video_profile profile,
 548                                         enum pipe_video_entrypoint entrypoint,
 549                                         enum pipe_video_cap param)
 550 {
 551         switch (param) {
 552         case PIPE_VIDEO_CAP_SUPPORTED:
 553                 return vl_profile_supported(screen, profile, entrypoint);
 554         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 555                 return 1;
 556         case PIPE_VIDEO_CAP_MAX_WIDTH:
 557         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 558                 return vl_video_buffer_max_size(screen);
 559         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 560                 return PIPE_FORMAT_NV12;
 561         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 562                 return false;
 563         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 564                 return false;
 565         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 566                 return true;
 567         case PIPE_VIDEO_CAP_MAX_LEVEL:
 568                 return vl_level_supported(screen, profile);
 569         default:
 570                 return 0;
 571         }
 572 }
 573
 574 static unsigned get_max_threads_per_block(struct si_screen *screen,
 575                                           enum pipe_shader_ir ir_type)
 576 {
 577         if (ir_type != PIPE_SHADER_IR_TGSI)
 578                 return 256;
 579
 580         /* Only 16 waves per thread-group on gfx9. */
 581         if (screen->b.chip_class >= GFX9)
 582                 return 1024;
 583
 584         /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
 585          * round number.
 586          */
 587         return 2048;
 588 }
 589
 590 static int si_get_compute_param(struct pipe_screen *screen,
 591                                 enum pipe_shader_ir ir_type,
 592                                 enum pipe_compute_cap param,
 593                                 void *ret)
 594 {
 595         struct si_screen *sscreen = (struct si_screen *)screen;
 596
 597         //TODO: select these params by asic
 598         switch (param) {
 599         case PIPE_COMPUTE_CAP_IR_TARGET: {
 600                 const char *gpu;
 601                 const char *triple;
 602
 603                 if (HAVE_LLVM < 0x0400)
 604                         triple = "amdgcn--";
 605                 else
 606                         triple = "amdgcn-mesa-mesa3d";
 607
 608                 gpu = ac_get_llvm_processor_name(sscreen->b.family);
 609                 if (ret) {
 610                         sprintf(ret, "%s-%s", gpu, triple);
 611                 }
 612                 /* +2 for dash and terminating NIL byte */
 613                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 614         }
 615         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 616                 if (ret) {
 617                         uint64_t *grid_dimension = ret;
 618                         grid_dimension[0] = 3;
 619                 }
 620                 return 1 * sizeof(uint64_t);
 621
 622         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 623                 if (ret) {
 624                         uint64_t *grid_size = ret;
 625                         grid_size[0] = 65535;
 626                         grid_size[1] = 65535;
 627                         grid_size[2] = 65535;
 628                 }
 629                 return 3 * sizeof(uint64_t) ;
 630
 631         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 632                 if (ret) {
 633                         uint64_t *block_size = ret;
 634                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 635                         block_size[0] = threads_per_block;
 636                         block_size[1] = threads_per_block;
 637                         block_size[2] = threads_per_block;
 638                 }
 639                 return 3 * sizeof(uint64_t);
 640
 641         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 642                 if (ret) {
 643                         uint64_t *max_threads_per_block = ret;
 644                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 645                 }
 646                 return sizeof(uint64_t);
 647         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 648                 if (ret) {
 649                         uint32_t *address_bits = ret;
 650                         address_bits[0] = 64;
 651                 }
 652                 return 1 * sizeof(uint32_t);
 653
 654         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 655                 if (ret) {
 656                         uint64_t *max_global_size = ret;
 657                         uint64_t max_mem_alloc_size;
 658
 659                         si_get_compute_param(screen, ir_type,
 660                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 661                                 &max_mem_alloc_size);
 662
 663                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 664                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 665                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 666                          * make sure we never report more than
 667                          * 4 * MAX_MEM_ALLOC_SIZE.
 668                          */
 669                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 670                                                 MAX2(sscreen->b.info.gart_size,
 671                                                      sscreen->b.info.vram_size));
 672                 }
 673                 return sizeof(uint64_t);
 674
 675         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 676                 if (ret) {
 677                         uint64_t *max_local_size = ret;
 678                         /* Value reported by the closed source driver. */
 679                         *max_local_size = 32768;
 680                 }
 681                 return sizeof(uint64_t);
 682
 683         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 684                 if (ret) {
 685                         uint64_t *max_input_size = ret;
 686                         /* Value reported by the closed source driver. */
 687                         *max_input_size = 1024;
 688                 }
 689                 return sizeof(uint64_t);
 690
 691         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 692                 if (ret) {
 693                         uint64_t *max_mem_alloc_size = ret;
 694
 695                         *max_mem_alloc_size = sscreen->b.info.max_alloc_size;
 696                 }
 697                 return sizeof(uint64_t);
 698
 699         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 700                 if (ret) {
 701                         uint32_t *max_clock_frequency = ret;
 702                         *max_clock_frequency = sscreen->b.info.max_shader_clock;
 703                 }
 704                 return sizeof(uint32_t);
 705
 706         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 707                 if (ret) {
 708                         uint32_t *max_compute_units = ret;
 709                         *max_compute_units = sscreen->b.info.num_good_compute_units;
 710                 }
 711                 return sizeof(uint32_t);
 712
 713         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 714                 if (ret) {
 715                         uint32_t *images_supported = ret;
 716                         *images_supported = 0;
 717                 }
 718                 return sizeof(uint32_t);
 719         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 720                 break; /* unused */
 721         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 722                 if (ret) {
 723                         uint32_t *subgroup_size = ret;
 724                         *subgroup_size = 64;
 725                 }
 726                 return sizeof(uint32_t);
 727         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 728                 if (ret) {
 729                         uint64_t *max_variable_threads_per_block = ret;
 730                         if (ir_type == PIPE_SHADER_IR_TGSI)
 731                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 732                         else
 733                                 *max_variable_threads_per_block = 0;
 734                 }
 735                 return sizeof(uint64_t);
 736         }
 737
 738         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 739         return 0;
 740 }
 741
 742 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 743 {
 744         struct si_screen *sscreen = (struct si_screen*)screen;
 745
 746         return 1000000 * sscreen->b.ws->query_value(sscreen->b.ws, RADEON_TIMESTAMP) /
 747                         sscreen->b.info.clock_crystal_freq;
 748 }
 749
 750 static void si_query_memory_info(struct pipe_screen *screen,
 751                                  struct pipe_memory_info *info)
 752 {
 753         struct si_screen *sscreen = (struct si_screen*)screen;
 754         struct radeon_winsys *ws = sscreen->b.ws;
 755         unsigned vram_usage, gtt_usage;
 756
 757         info->total_device_memory = sscreen->b.info.vram_size / 1024;
 758         info->total_staging_memory = sscreen->b.info.gart_size / 1024;
 759
 760         /* The real TTM memory usage is somewhat random, because:
 761          *
 762          * 1) TTM delays freeing memory, because it can only free it after
 763          *    fences expire.
 764          *
 765          * 2) The memory usage can be really low if big VRAM evictions are
 766          *    taking place, but the real usage is well above the size of VRAM.
 767          *
 768          * Instead, return statistics of this process.
 769          */
 770         vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
 771         gtt_usage =  ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
 772
 773         info->avail_device_memory =
 774                 vram_usage <= info->total_device_memory ?
 775                                 info->total_device_memory - vram_usage : 0;
 776         info->avail_staging_memory =
 777                 gtt_usage <= info->total_staging_memory ?
 778                                 info->total_staging_memory - gtt_usage : 0;
 779
 780         info->device_memory_evicted =
 781                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 782
 783         if (sscreen->b.info.drm_major == 3 && sscreen->b.info.drm_minor >= 4)
 784                 info->nr_device_memory_evictions =
 785                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 786         else
 787                 /* Just return the number of evicted 64KB pages. */
 788                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 789 }
 790
 791 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 792 {
 793         struct si_screen *sscreen = (struct si_screen*)pscreen;
 794
 795         return sscreen->b.disk_shader_cache;
 796 }
 797
 798 static void si_init_renderer_string(struct si_screen *sscreen)
 799 {
 800         struct radeon_winsys *ws = sscreen->b.ws;
 801         char family_name[32] = {}, llvm_string[32] = {}, kernel_version[128] = {};
 802         struct utsname uname_data;
 803
 804         const char *chip_name = si_get_marketing_name(ws);
 805
 806         if (chip_name)
 807                 snprintf(family_name, sizeof(family_name), "%s / ",
 808                          si_get_family_name(sscreen) + 4);
 809         else
 810                 chip_name = si_get_family_name(sscreen);
 811
 812         if (uname(&uname_data) == 0)
 813                 snprintf(kernel_version, sizeof(kernel_version),
 814                          " / %s", uname_data.release);
 815
 816         if (HAVE_LLVM > 0) {
 817                 snprintf(llvm_string, sizeof(llvm_string),
 818                          ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
 819                          HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
 820         }
 821
 822         snprintf(sscreen->b.renderer_string, sizeof(sscreen->b.renderer_string),
 823                  "%s (%sDRM %i.%i.%i%s%s)",
 824                  chip_name, family_name, sscreen->b.info.drm_major,
 825                  sscreen->b.info.drm_minor, sscreen->b.info.drm_patchlevel,
 826                  kernel_version, llvm_string);
 827 }
 828
 829 void si_init_screen_get_functions(struct si_screen *sscreen)
 830 {
 831         sscreen->b.b.get_name = si_get_name;
 832         sscreen->b.b.get_vendor = si_get_vendor;
 833         sscreen->b.b.get_device_vendor = si_get_device_vendor;
 834         sscreen->b.b.get_param = si_get_param;
 835         sscreen->b.b.get_paramf = si_get_paramf;
 836         sscreen->b.b.get_compute_param = si_get_compute_param;
 837         sscreen->b.b.get_timestamp = si_get_timestamp;
 838         sscreen->b.b.get_shader_param = si_get_shader_param;
 839         sscreen->b.b.get_compiler_options = si_get_compiler_options;
 840         sscreen->b.b.get_device_uuid = si_get_device_uuid;
 841         sscreen->b.b.get_driver_uuid = si_get_driver_uuid;
 842         sscreen->b.b.query_memory_info = si_query_memory_info;
 843         sscreen->b.b.get_disk_shader_cache = si_get_disk_shader_cache;
 844
 845         if (sscreen->b.info.has_hw_decode) {
 846                 sscreen->b.b.get_video_param = si_vid_get_video_param;
 847         } else {
 848                 sscreen->b.b.get_video_param = si_get_video_param_no_decode;
 849         }
 850
 851         si_init_renderer_string(sscreen);
 852 }