2 * Copyright 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "radeon/radeon_video.h"
27 #include "radeon/radeon_vce.h"
28 #include "radeon/radeon_uvd_enc.h"
29 #include "ac_llvm_util.h"
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32 #include "util/u_video.h"
33 #include "compiler/nir/nir.h"
35 #include <sys/utsname.h>
37 static const char *si_get_vendor(struct pipe_screen
*pscreen
)
39 /* Don't change this. Games such as Alien Isolation are broken if this
40 * returns "Advanced Micro Devices, Inc."
45 static const char *si_get_device_vendor(struct pipe_screen
*pscreen
)
50 static const char *si_get_marketing_name(struct radeon_winsys
*ws
)
52 if (!ws
->get_chip_name
)
54 return ws
->get_chip_name(ws
);
57 const char *si_get_family_name(const struct si_screen
*sscreen
)
59 switch (sscreen
->info
.family
) {
60 case CHIP_TAHITI
: return "AMD TAHITI";
61 case CHIP_PITCAIRN
: return "AMD PITCAIRN";
62 case CHIP_VERDE
: return "AMD CAPE VERDE";
63 case CHIP_OLAND
: return "AMD OLAND";
64 case CHIP_HAINAN
: return "AMD HAINAN";
65 case CHIP_BONAIRE
: return "AMD BONAIRE";
66 case CHIP_KAVERI
: return "AMD KAVERI";
67 case CHIP_KABINI
: return "AMD KABINI";
68 case CHIP_HAWAII
: return "AMD HAWAII";
69 case CHIP_MULLINS
: return "AMD MULLINS";
70 case CHIP_TONGA
: return "AMD TONGA";
71 case CHIP_ICELAND
: return "AMD ICELAND";
72 case CHIP_CARRIZO
: return "AMD CARRIZO";
73 case CHIP_FIJI
: return "AMD FIJI";
74 case CHIP_POLARIS10
: return "AMD POLARIS10";
75 case CHIP_POLARIS11
: return "AMD POLARIS11";
76 case CHIP_POLARIS12
: return "AMD POLARIS12";
77 case CHIP_STONEY
: return "AMD STONEY";
78 case CHIP_VEGA10
: return "AMD VEGA10";
79 case CHIP_VEGA12
: return "AMD VEGA12";
80 case CHIP_RAVEN
: return "AMD RAVEN";
81 default: return "AMD unknown";
85 static bool si_have_tgsi_compute(struct si_screen
*sscreen
)
87 /* Old kernels disallowed some register writes for SI
88 * that are used for indirect dispatches. */
89 return (sscreen
->info
.chip_class
>= CIK
||
90 sscreen
->info
.drm_major
== 3 ||
91 (sscreen
->info
.drm_major
== 2 &&
92 sscreen
->info
.drm_minor
>= 45));
95 static int si_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
97 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
100 /* Supported features (boolean caps). */
101 case PIPE_CAP_ACCELERATED
:
102 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
103 case PIPE_CAP_ANISOTROPIC_FILTER
:
104 case PIPE_CAP_POINT_SPRITE
:
105 case PIPE_CAP_OCCLUSION_QUERY
:
106 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
107 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
108 case PIPE_CAP_TEXTURE_SWIZZLE
:
109 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
110 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
111 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
112 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
113 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
114 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
115 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
117 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
118 case PIPE_CAP_PRIMITIVE_RESTART
:
119 case PIPE_CAP_CONDITIONAL_RENDER
:
120 case PIPE_CAP_TEXTURE_BARRIER
:
121 case PIPE_CAP_INDEP_BLEND_ENABLE
:
122 case PIPE_CAP_INDEP_BLEND_FUNC
:
123 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
124 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
125 case PIPE_CAP_START_INSTANCE
:
126 case PIPE_CAP_NPOT_TEXTURES
:
127 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
128 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
129 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
130 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
131 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
132 case PIPE_CAP_TGSI_INSTANCEID
:
133 case PIPE_CAP_COMPUTE
:
134 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
135 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
136 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
137 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
138 case PIPE_CAP_CUBE_MAP_ARRAY
:
139 case PIPE_CAP_SAMPLE_SHADING
:
140 case PIPE_CAP_DRAW_INDIRECT
:
141 case PIPE_CAP_CLIP_HALFZ
:
142 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
143 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
144 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
145 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
146 case PIPE_CAP_TGSI_TEXCOORD
:
147 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
148 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
149 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
150 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
151 case PIPE_CAP_SHAREABLE_SHADERS
:
152 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
153 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
154 case PIPE_CAP_TEXTURE_QUERY_LOD
:
155 case PIPE_CAP_TEXTURE_GATHER_SM5
:
156 case PIPE_CAP_TGSI_TXQS
:
157 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
158 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
159 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
160 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
161 case PIPE_CAP_INVALIDATE_BUFFER
:
162 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
163 case PIPE_CAP_QUERY_MEMORY_INFO
:
164 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
165 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
166 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
167 case PIPE_CAP_GENERATE_MIPMAP
:
168 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
169 case PIPE_CAP_STRING_MARKER
:
170 case PIPE_CAP_CLEAR_TEXTURE
:
171 case PIPE_CAP_CULL_DISTANCE
:
172 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
173 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
174 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
175 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
176 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
177 case PIPE_CAP_DOUBLES
:
178 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
179 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
180 case PIPE_CAP_BINDLESS_TEXTURE
:
181 case PIPE_CAP_QUERY_TIMESTAMP
:
182 case PIPE_CAP_QUERY_TIME_ELAPSED
:
183 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
184 case PIPE_CAP_QUERY_SO_OVERFLOW
:
185 case PIPE_CAP_MEMOBJ
:
186 case PIPE_CAP_LOAD_CONSTBUF
:
188 case PIPE_CAP_INT64_DIVMOD
:
189 case PIPE_CAP_TGSI_CLOCK
:
190 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
191 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
192 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
:
193 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
194 case PIPE_CAP_TGSI_VOTE
:
195 case PIPE_CAP_TGSI_FS_FBFETCH
:
198 case PIPE_CAP_TGSI_BALLOT
:
199 return HAVE_LLVM
>= 0x0500;
201 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
202 return !SI_BIG_ENDIAN
&& sscreen
->info
.has_userptr
;
204 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
205 return (sscreen
->info
.drm_major
== 2 &&
206 sscreen
->info
.drm_minor
>= 43) ||
207 sscreen
->info
.drm_major
== 3;
209 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
210 /* 2D tiling on CIK is supported since DRM 2.35.0 */
211 return sscreen
->info
.chip_class
< CIK
||
212 (sscreen
->info
.drm_major
== 2 &&
213 sscreen
->info
.drm_minor
>= 35) ||
214 sscreen
->info
.drm_major
== 3;
216 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
217 return SI_MAP_BUFFER_ALIGNMENT
;
219 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
220 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
221 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
222 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
223 case PIPE_CAP_MAX_VERTEX_STREAMS
:
224 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
227 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
228 if (si_have_tgsi_compute(sscreen
))
232 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
233 return MIN2(sscreen
->info
.max_alloc_size
, INT_MAX
);
235 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
236 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
237 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
238 /* SI doesn't support unaligned loads.
239 * CIK needs DRM 2.50.0 on radeon. */
240 return sscreen
->info
.chip_class
== SI
||
241 (sscreen
->info
.drm_major
== 2 &&
242 sscreen
->info
.drm_minor
< 50);
244 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
245 /* TODO: GFX9 hangs. */
246 if (sscreen
->info
.chip_class
>= GFX9
)
248 /* Disable on SI due to VM faults in CP DMA. Enable once these
249 * faults are mitigated in software.
251 if (sscreen
->info
.chip_class
>= CIK
&&
252 sscreen
->info
.drm_major
== 3 &&
253 sscreen
->info
.drm_minor
>= 13)
254 return RADEON_SPARSE_PAGE_SIZE
;
257 case PIPE_CAP_PACKED_UNIFORMS
:
258 if (sscreen
->debug_flags
& DBG(NIR
))
262 /* Unsupported features. */
263 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
264 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
265 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
266 case PIPE_CAP_USER_VERTEX_BUFFERS
:
267 case PIPE_CAP_FAKE_SW_MSAA
:
268 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
269 case PIPE_CAP_VERTEXID_NOBASE
:
270 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
271 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
272 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
274 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
275 case PIPE_CAP_POST_DEPTH_COVERAGE
:
276 case PIPE_CAP_TILE_RASTER_ORDER
:
277 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES
:
278 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
281 case PIPE_CAP_FENCE_SIGNAL
:
282 return sscreen
->info
.has_syncobj
;
284 case PIPE_CAP_CONSTBUF0_FLAGS
:
285 return SI_RESOURCE_FLAG_32BIT
;
287 case PIPE_CAP_NATIVE_FENCE_FD
:
288 return sscreen
->info
.has_fence_to_handle
;
290 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
291 return si_have_tgsi_compute(sscreen
);
293 case PIPE_CAP_DRAW_PARAMETERS
:
294 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
295 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
296 return sscreen
->has_draw_indirect_multi
;
298 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
301 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
302 return sscreen
->info
.chip_class
<= VI
?
303 PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600
: 0;
306 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
307 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
310 /* Geometry shader output. */
311 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
313 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
316 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
320 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
321 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
322 return 15; /* 16384 */
323 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
324 /* textures support 8192, but layered rendering supports 2048 */
326 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
327 /* textures support 8192, but layered rendering supports 2048 */
330 /* Viewports and render targets. */
331 case PIPE_CAP_MAX_VIEWPORTS
:
332 return SI_MAX_VIEWPORTS
;
333 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
334 case PIPE_CAP_MAX_RENDER_TARGETS
:
337 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
338 case PIPE_CAP_MIN_TEXEL_OFFSET
:
341 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
342 case PIPE_CAP_MAX_TEXEL_OFFSET
:
345 case PIPE_CAP_ENDIANNESS
:
346 return PIPE_ENDIAN_LITTLE
;
348 case PIPE_CAP_VENDOR_ID
:
349 return ATI_VENDOR_ID
;
350 case PIPE_CAP_DEVICE_ID
:
351 return sscreen
->info
.pci_id
;
352 case PIPE_CAP_VIDEO_MEMORY
:
353 return sscreen
->info
.vram_size
>> 20;
354 case PIPE_CAP_PCI_GROUP
:
355 return sscreen
->info
.pci_domain
;
356 case PIPE_CAP_PCI_BUS
:
357 return sscreen
->info
.pci_bus
;
358 case PIPE_CAP_PCI_DEVICE
:
359 return sscreen
->info
.pci_dev
;
360 case PIPE_CAP_PCI_FUNCTION
:
361 return sscreen
->info
.pci_func
;
366 static float si_get_paramf(struct pipe_screen
* pscreen
, enum pipe_capf param
)
369 case PIPE_CAPF_MAX_LINE_WIDTH
:
370 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
371 case PIPE_CAPF_MAX_POINT_WIDTH
:
372 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
374 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
376 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
382 static int si_get_shader_param(struct pipe_screen
* pscreen
,
383 enum pipe_shader_type shader
,
384 enum pipe_shader_cap param
)
386 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
390 case PIPE_SHADER_FRAGMENT
:
391 case PIPE_SHADER_VERTEX
:
392 case PIPE_SHADER_GEOMETRY
:
393 case PIPE_SHADER_TESS_CTRL
:
394 case PIPE_SHADER_TESS_EVAL
:
396 case PIPE_SHADER_COMPUTE
:
398 case PIPE_SHADER_CAP_SUPPORTED_IRS
: {
399 int ir
= 1 << PIPE_SHADER_IR_NATIVE
;
401 if (si_have_tgsi_compute(sscreen
))
402 ir
|= 1 << PIPE_SHADER_IR_TGSI
;
407 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
: {
408 uint64_t max_const_buffer_size
;
409 pscreen
->get_compute_param(pscreen
, PIPE_SHADER_IR_TGSI
,
410 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
411 &max_const_buffer_size
);
412 return MIN2(max_const_buffer_size
, INT_MAX
);
415 /* If compute shaders don't require a special value
416 * for this cap, we can return the same value we
417 * do for other shader types. */
427 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
428 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
429 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
430 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
431 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
433 case PIPE_SHADER_CAP_MAX_INPUTS
:
434 return shader
== PIPE_SHADER_VERTEX
? SI_MAX_ATTRIBS
: 32;
435 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
436 return shader
== PIPE_SHADER_FRAGMENT
? 8 : 32;
437 case PIPE_SHADER_CAP_MAX_TEMPS
:
438 return 256; /* Max native temporaries. */
439 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
440 return 4096 * sizeof(float[4]); /* actually only memory limits this */
441 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
442 return SI_NUM_CONST_BUFFERS
;
443 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
444 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
445 return SI_NUM_SAMPLERS
;
446 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
447 return SI_NUM_SHADER_BUFFERS
;
448 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
449 return SI_NUM_IMAGES
;
450 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
451 if (sscreen
->debug_flags
& DBG(NIR
))
454 case PIPE_SHADER_CAP_PREFERRED_IR
:
455 if (sscreen
->debug_flags
& DBG(NIR
))
456 return PIPE_SHADER_IR_NIR
;
457 return PIPE_SHADER_IR_TGSI
;
458 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
461 /* Supported boolean features. */
462 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
463 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
464 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
465 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
466 case PIPE_SHADER_CAP_INTEGERS
:
467 case PIPE_SHADER_CAP_INT64_ATOMICS
:
468 case PIPE_SHADER_CAP_FP16
:
469 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
470 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
471 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
472 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
473 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
474 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
477 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
478 /* TODO: Indirect indexing of GS inputs is unimplemented. */
479 return shader
!= PIPE_SHADER_GEOMETRY
&&
480 (sscreen
->llvm_has_working_vgpr_indexing
||
481 /* TCS and TES load inputs directly from LDS or
482 * offchip memory, so indirect indexing is trivial. */
483 shader
== PIPE_SHADER_TESS_CTRL
||
484 shader
== PIPE_SHADER_TESS_EVAL
);
486 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
487 return sscreen
->llvm_has_working_vgpr_indexing
||
488 /* TCS stores outputs directly to memory. */
489 shader
== PIPE_SHADER_TESS_CTRL
;
491 /* Unsupported boolean features. */
492 case PIPE_SHADER_CAP_SUBROUTINES
:
493 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
494 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
495 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
501 static const struct nir_shader_compiler_options nir_options
= {
503 .lower_flrp32
= true,
504 .lower_flrp64
= true,
510 .lower_pack_snorm_2x16
= true,
511 .lower_pack_snorm_4x8
= true,
512 .lower_pack_unorm_2x16
= true,
513 .lower_pack_unorm_4x8
= true,
514 .lower_unpack_snorm_2x16
= true,
515 .lower_unpack_snorm_4x8
= true,
516 .lower_unpack_unorm_2x16
= true,
517 .lower_unpack_unorm_4x8
= true,
518 .lower_extract_byte
= true,
519 .lower_extract_word
= true,
520 .max_unroll_iterations
= 32,
521 .native_integers
= true,
525 si_get_compiler_options(struct pipe_screen
*screen
,
526 enum pipe_shader_ir ir
,
527 enum pipe_shader_type shader
)
529 assert(ir
== PIPE_SHADER_IR_NIR
);
533 static void si_get_driver_uuid(struct pipe_screen
*pscreen
, char *uuid
)
535 ac_compute_driver_uuid(uuid
, PIPE_UUID_SIZE
);
538 static void si_get_device_uuid(struct pipe_screen
*pscreen
, char *uuid
)
540 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
542 ac_compute_device_uuid(&sscreen
->info
, uuid
, PIPE_UUID_SIZE
);
545 static const char* si_get_name(struct pipe_screen
*pscreen
)
547 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
549 return sscreen
->renderer_string
;
552 static int si_get_video_param_no_decode(struct pipe_screen
*screen
,
553 enum pipe_video_profile profile
,
554 enum pipe_video_entrypoint entrypoint
,
555 enum pipe_video_cap param
)
558 case PIPE_VIDEO_CAP_SUPPORTED
:
559 return vl_profile_supported(screen
, profile
, entrypoint
);
560 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
562 case PIPE_VIDEO_CAP_MAX_WIDTH
:
563 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
564 return vl_video_buffer_max_size(screen
);
565 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
566 return PIPE_FORMAT_NV12
;
567 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
569 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
571 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
573 case PIPE_VIDEO_CAP_MAX_LEVEL
:
574 return vl_level_supported(screen
, profile
);
580 static int si_get_video_param(struct pipe_screen
*screen
,
581 enum pipe_video_profile profile
,
582 enum pipe_video_entrypoint entrypoint
,
583 enum pipe_video_cap param
)
585 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
586 enum pipe_video_format codec
= u_reduce_video_profile(profile
);
588 if (entrypoint
== PIPE_VIDEO_ENTRYPOINT_ENCODE
) {
590 case PIPE_VIDEO_CAP_SUPPORTED
:
591 return (codec
== PIPE_VIDEO_FORMAT_MPEG4_AVC
&&
592 (si_vce_is_fw_version_supported(sscreen
) ||
593 sscreen
->info
.family
== CHIP_RAVEN
)) ||
594 (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
&&
595 (sscreen
->info
.family
== CHIP_RAVEN
||
596 si_radeon_uvd_enc_supported(sscreen
)));
597 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
599 case PIPE_VIDEO_CAP_MAX_WIDTH
:
600 return (sscreen
->info
.family
< CHIP_TONGA
) ? 2048 : 4096;
601 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
602 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1152 : 2304;
603 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
604 return PIPE_FORMAT_NV12
;
605 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
607 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
609 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
611 case PIPE_VIDEO_CAP_STACKED_FRAMES
:
612 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1 : 2;
619 case PIPE_VIDEO_CAP_SUPPORTED
:
621 case PIPE_VIDEO_FORMAT_MPEG12
:
622 return profile
!= PIPE_VIDEO_PROFILE_MPEG1
;
623 case PIPE_VIDEO_FORMAT_MPEG4
:
625 case PIPE_VIDEO_FORMAT_MPEG4_AVC
:
626 if ((sscreen
->info
.family
== CHIP_POLARIS10
||
627 sscreen
->info
.family
== CHIP_POLARIS11
) &&
628 sscreen
->info
.uvd_fw_version
< UVD_FW_1_66_16
) {
629 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
633 case PIPE_VIDEO_FORMAT_VC1
:
635 case PIPE_VIDEO_FORMAT_HEVC
:
636 /* Carrizo only supports HEVC Main */
637 if (sscreen
->info
.family
>= CHIP_STONEY
)
638 return (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
||
639 profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
);
640 else if (sscreen
->info
.family
>= CHIP_CARRIZO
)
641 return profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
;
643 case PIPE_VIDEO_FORMAT_JPEG
:
644 if (sscreen
->info
.family
< CHIP_CARRIZO
|| sscreen
->info
.family
>= CHIP_VEGA10
)
646 if (!(sscreen
->info
.drm_major
== 3 && sscreen
->info
.drm_minor
>= 19)) {
647 RVID_ERR("No MJPEG support for the kernel version\n");
651 case PIPE_VIDEO_FORMAT_VP9
:
652 if (sscreen
->info
.family
< CHIP_RAVEN
)
658 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
660 case PIPE_VIDEO_CAP_MAX_WIDTH
:
661 return (sscreen
->info
.family
< CHIP_TONGA
) ? 2048 : 4096;
662 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
663 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1152 : 4096;
664 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
665 if (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
)
666 return PIPE_FORMAT_P016
;
668 return PIPE_FORMAT_NV12
;
670 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
671 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
: {
672 enum pipe_video_format format
= u_reduce_video_profile(profile
);
674 if (format
== PIPE_VIDEO_FORMAT_HEVC
)
675 return false; //The firmware doesn't support interlaced HEVC.
676 else if (format
== PIPE_VIDEO_FORMAT_JPEG
)
678 else if (format
== PIPE_VIDEO_FORMAT_VP9
)
682 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
684 case PIPE_VIDEO_CAP_MAX_LEVEL
:
686 case PIPE_VIDEO_PROFILE_MPEG1
:
688 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE
:
689 case PIPE_VIDEO_PROFILE_MPEG2_MAIN
:
691 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE
:
693 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE
:
695 case PIPE_VIDEO_PROFILE_VC1_SIMPLE
:
697 case PIPE_VIDEO_PROFILE_VC1_MAIN
:
699 case PIPE_VIDEO_PROFILE_VC1_ADVANCED
:
701 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE
:
702 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN
:
703 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH
:
704 return (sscreen
->info
.family
< CHIP_TONGA
) ? 41 : 52;
705 case PIPE_VIDEO_PROFILE_HEVC_MAIN
:
706 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10
:
716 static boolean
si_vid_is_format_supported(struct pipe_screen
*screen
,
717 enum pipe_format format
,
718 enum pipe_video_profile profile
,
719 enum pipe_video_entrypoint entrypoint
)
721 /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
722 if (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
)
723 return (format
== PIPE_FORMAT_NV12
) ||
724 (format
== PIPE_FORMAT_P016
);
726 /* we can only handle this one with UVD */
727 if (profile
!= PIPE_VIDEO_PROFILE_UNKNOWN
)
728 return format
== PIPE_FORMAT_NV12
;
730 return vl_video_buffer_is_format_supported(screen
, format
, profile
, entrypoint
);
733 static unsigned get_max_threads_per_block(struct si_screen
*screen
,
734 enum pipe_shader_ir ir_type
)
736 if (ir_type
== PIPE_SHADER_IR_NATIVE
)
739 /* Only 16 waves per thread-group on gfx9. */
740 if (screen
->info
.chip_class
>= GFX9
)
743 /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
749 static int si_get_compute_param(struct pipe_screen
*screen
,
750 enum pipe_shader_ir ir_type
,
751 enum pipe_compute_cap param
,
754 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
756 //TODO: select these params by asic
758 case PIPE_COMPUTE_CAP_IR_TARGET
: {
759 const char *gpu
, *triple
;
761 triple
= "amdgcn-mesa-mesa3d";
762 gpu
= ac_get_llvm_processor_name(sscreen
->info
.family
);
764 sprintf(ret
, "%s-%s", gpu
, triple
);
766 /* +2 for dash and terminating NIL byte */
767 return (strlen(triple
) + strlen(gpu
) + 2) * sizeof(char);
769 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
771 uint64_t *grid_dimension
= ret
;
772 grid_dimension
[0] = 3;
774 return 1 * sizeof(uint64_t);
776 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
778 uint64_t *grid_size
= ret
;
779 grid_size
[0] = 65535;
780 grid_size
[1] = 65535;
781 grid_size
[2] = 65535;
783 return 3 * sizeof(uint64_t) ;
785 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
787 uint64_t *block_size
= ret
;
788 unsigned threads_per_block
= get_max_threads_per_block(sscreen
, ir_type
);
789 block_size
[0] = threads_per_block
;
790 block_size
[1] = threads_per_block
;
791 block_size
[2] = threads_per_block
;
793 return 3 * sizeof(uint64_t);
795 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
797 uint64_t *max_threads_per_block
= ret
;
798 *max_threads_per_block
= get_max_threads_per_block(sscreen
, ir_type
);
800 return sizeof(uint64_t);
801 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
803 uint32_t *address_bits
= ret
;
804 address_bits
[0] = 64;
806 return 1 * sizeof(uint32_t);
808 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
810 uint64_t *max_global_size
= ret
;
811 uint64_t max_mem_alloc_size
;
813 si_get_compute_param(screen
, ir_type
,
814 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
815 &max_mem_alloc_size
);
817 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
818 * 1/4 of the MAX_GLOBAL_SIZE. Since the
819 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
820 * make sure we never report more than
821 * 4 * MAX_MEM_ALLOC_SIZE.
823 *max_global_size
= MIN2(4 * max_mem_alloc_size
,
824 MAX2(sscreen
->info
.gart_size
,
825 sscreen
->info
.vram_size
));
827 return sizeof(uint64_t);
829 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
831 uint64_t *max_local_size
= ret
;
832 /* Value reported by the closed source driver. */
833 *max_local_size
= 32768;
835 return sizeof(uint64_t);
837 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
839 uint64_t *max_input_size
= ret
;
840 /* Value reported by the closed source driver. */
841 *max_input_size
= 1024;
843 return sizeof(uint64_t);
845 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
847 uint64_t *max_mem_alloc_size
= ret
;
849 *max_mem_alloc_size
= sscreen
->info
.max_alloc_size
;
851 return sizeof(uint64_t);
853 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
855 uint32_t *max_clock_frequency
= ret
;
856 *max_clock_frequency
= sscreen
->info
.max_shader_clock
;
858 return sizeof(uint32_t);
860 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
862 uint32_t *max_compute_units
= ret
;
863 *max_compute_units
= sscreen
->info
.num_good_compute_units
;
865 return sizeof(uint32_t);
867 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
869 uint32_t *images_supported
= ret
;
870 *images_supported
= 0;
872 return sizeof(uint32_t);
873 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
875 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
877 uint32_t *subgroup_size
= ret
;
880 return sizeof(uint32_t);
881 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
883 uint64_t *max_variable_threads_per_block
= ret
;
884 if (ir_type
== PIPE_SHADER_IR_NATIVE
)
885 *max_variable_threads_per_block
= 0;
887 *max_variable_threads_per_block
= SI_MAX_VARIABLE_THREADS_PER_BLOCK
;
889 return sizeof(uint64_t);
892 fprintf(stderr
, "unknown PIPE_COMPUTE_CAP %d\n", param
);
896 static uint64_t si_get_timestamp(struct pipe_screen
*screen
)
898 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
900 return 1000000 * sscreen
->ws
->query_value(sscreen
->ws
, RADEON_TIMESTAMP
) /
901 sscreen
->info
.clock_crystal_freq
;
904 static void si_query_memory_info(struct pipe_screen
*screen
,
905 struct pipe_memory_info
*info
)
907 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
908 struct radeon_winsys
*ws
= sscreen
->ws
;
909 unsigned vram_usage
, gtt_usage
;
911 info
->total_device_memory
= sscreen
->info
.vram_size
/ 1024;
912 info
->total_staging_memory
= sscreen
->info
.gart_size
/ 1024;
914 /* The real TTM memory usage is somewhat random, because:
916 * 1) TTM delays freeing memory, because it can only free it after
919 * 2) The memory usage can be really low if big VRAM evictions are
920 * taking place, but the real usage is well above the size of VRAM.
922 * Instead, return statistics of this process.
924 vram_usage
= ws
->query_value(ws
, RADEON_REQUESTED_VRAM_MEMORY
) / 1024;
925 gtt_usage
= ws
->query_value(ws
, RADEON_REQUESTED_GTT_MEMORY
) / 1024;
927 info
->avail_device_memory
=
928 vram_usage
<= info
->total_device_memory
?
929 info
->total_device_memory
- vram_usage
: 0;
930 info
->avail_staging_memory
=
931 gtt_usage
<= info
->total_staging_memory
?
932 info
->total_staging_memory
- gtt_usage
: 0;
934 info
->device_memory_evicted
=
935 ws
->query_value(ws
, RADEON_NUM_BYTES_MOVED
) / 1024;
937 if (sscreen
->info
.drm_major
== 3 && sscreen
->info
.drm_minor
>= 4)
938 info
->nr_device_memory_evictions
=
939 ws
->query_value(ws
, RADEON_NUM_EVICTIONS
);
941 /* Just return the number of evicted 64KB pages. */
942 info
->nr_device_memory_evictions
= info
->device_memory_evicted
/ 64;
945 static struct disk_cache
*si_get_disk_shader_cache(struct pipe_screen
*pscreen
)
947 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
949 return sscreen
->disk_shader_cache
;
952 static void si_init_renderer_string(struct si_screen
*sscreen
)
954 struct radeon_winsys
*ws
= sscreen
->ws
;
955 char family_name
[32] = {}, llvm_string
[32] = {}, kernel_version
[128] = {};
956 struct utsname uname_data
;
958 const char *chip_name
= si_get_marketing_name(ws
);
961 snprintf(family_name
, sizeof(family_name
), "%s / ",
962 si_get_family_name(sscreen
) + 4);
964 chip_name
= si_get_family_name(sscreen
);
966 if (uname(&uname_data
) == 0)
967 snprintf(kernel_version
, sizeof(kernel_version
),
968 " / %s", uname_data
.release
);
971 snprintf(llvm_string
, sizeof(llvm_string
),
972 ", LLVM %i.%i.%i", (HAVE_LLVM
>> 8) & 0xff,
973 HAVE_LLVM
& 0xff, MESA_LLVM_VERSION_PATCH
);
976 snprintf(sscreen
->renderer_string
, sizeof(sscreen
->renderer_string
),
977 "%s (%sDRM %i.%i.%i%s%s)",
978 chip_name
, family_name
, sscreen
->info
.drm_major
,
979 sscreen
->info
.drm_minor
, sscreen
->info
.drm_patchlevel
,
980 kernel_version
, llvm_string
);
983 void si_init_screen_get_functions(struct si_screen
*sscreen
)
985 sscreen
->b
.get_name
= si_get_name
;
986 sscreen
->b
.get_vendor
= si_get_vendor
;
987 sscreen
->b
.get_device_vendor
= si_get_device_vendor
;
988 sscreen
->b
.get_param
= si_get_param
;
989 sscreen
->b
.get_paramf
= si_get_paramf
;
990 sscreen
->b
.get_compute_param
= si_get_compute_param
;
991 sscreen
->b
.get_timestamp
= si_get_timestamp
;
992 sscreen
->b
.get_shader_param
= si_get_shader_param
;
993 sscreen
->b
.get_compiler_options
= si_get_compiler_options
;
994 sscreen
->b
.get_device_uuid
= si_get_device_uuid
;
995 sscreen
->b
.get_driver_uuid
= si_get_driver_uuid
;
996 sscreen
->b
.query_memory_info
= si_query_memory_info
;
997 sscreen
->b
.get_disk_shader_cache
= si_get_disk_shader_cache
;
999 if (sscreen
->info
.has_hw_decode
) {
1000 sscreen
->b
.get_video_param
= si_get_video_param
;
1001 sscreen
->b
.is_video_format_supported
= si_vid_is_format_supported
;
1003 sscreen
->b
.get_video_param
= si_get_video_param_no_decode
;
1004 sscreen
->b
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
1007 si_init_renderer_string(sscreen
);