src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "compiler/nir/nir.h"
  26 #include "radeon/radeon_uvd_enc.h"
  27 #include "radeon/radeon_vce.h"
  28 #include "radeon/radeon_video.h"
  29 #include "si_pipe.h"
  30 #include "util/u_screen.h"
  31 #include "util/u_video.h"
  32 #include "vl/vl_decoder.h"
  33 #include "vl/vl_video_buffer.h"
  34 #include <sys/utsname.h>
  35
  36 static const char *si_get_vendor(struct pipe_screen *pscreen)
  37 {
  38    /* Don't change this. Games such as Alien Isolation are broken if this
  39     * returns "Advanced Micro Devices, Inc."
  40     */
  41    return "X.Org";
  42 }
  43
  44 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  45 {
  46    return "AMD";
  47 }
  48
  49 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  50 {
  51    struct si_screen *sscreen = (struct si_screen *)pscreen;
  52
  53    switch (param) {
  54    /* Supported features (boolean caps). */
  55    case PIPE_CAP_ACCELERATED:
  56    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  57    case PIPE_CAP_ANISOTROPIC_FILTER:
  58    case PIPE_CAP_POINT_SPRITE:
  59    case PIPE_CAP_OCCLUSION_QUERY:
  60    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  61    case PIPE_CAP_TEXTURE_SHADOW_LOD:
  62    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  63    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  64    case PIPE_CAP_TEXTURE_SWIZZLE:
  65    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  66    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
  67    case PIPE_CAP_SHADER_STENCIL_EXPORT:
  68    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  69    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  70    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  71    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  72    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  73    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
  74    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
  75    case PIPE_CAP_VERTEX_SHADER_SATURATE:
  76    case PIPE_CAP_SEAMLESS_CUBE_MAP:
  77    case PIPE_CAP_PRIMITIVE_RESTART:
  78    case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
  79    case PIPE_CAP_CONDITIONAL_RENDER:
  80    case PIPE_CAP_TEXTURE_BARRIER:
  81    case PIPE_CAP_INDEP_BLEND_ENABLE:
  82    case PIPE_CAP_INDEP_BLEND_FUNC:
  83    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  84    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  85    case PIPE_CAP_START_INSTANCE:
  86    case PIPE_CAP_NPOT_TEXTURES:
  87    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  88    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  89    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
  90    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
  91    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  92    case PIPE_CAP_TGSI_INSTANCEID:
  93    case PIPE_CAP_COMPUTE:
  94    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  95    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
  96    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
  97    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  98    case PIPE_CAP_CUBE_MAP_ARRAY:
  99    case PIPE_CAP_SAMPLE_SHADING:
 100    case PIPE_CAP_DRAW_INDIRECT:
 101    case PIPE_CAP_CLIP_HALFZ:
 102    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 103    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 104    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 105    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 106    case PIPE_CAP_TGSI_TEXCOORD:
 107    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 108    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 109    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 110    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 111    case PIPE_CAP_SHAREABLE_SHADERS:
 112    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 113    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 114    case PIPE_CAP_TEXTURE_QUERY_LOD:
 115    case PIPE_CAP_TEXTURE_GATHER_SM5:
 116    case PIPE_CAP_TGSI_TXQS:
 117    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 118    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 119    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 120    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 121    case PIPE_CAP_INVALIDATE_BUFFER:
 122    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 123    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 124    case PIPE_CAP_QUERY_MEMORY_INFO:
 125    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 126    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 127    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 128    case PIPE_CAP_GENERATE_MIPMAP:
 129    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 130    case PIPE_CAP_STRING_MARKER:
 131    case PIPE_CAP_CLEAR_TEXTURE:
 132    case PIPE_CAP_CULL_DISTANCE:
 133    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 134    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 135    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 136    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 137    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 138    case PIPE_CAP_DOUBLES:
 139    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 140    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 141    case PIPE_CAP_BINDLESS_TEXTURE:
 142    case PIPE_CAP_QUERY_TIMESTAMP:
 143    case PIPE_CAP_QUERY_TIME_ELAPSED:
 144    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 145    case PIPE_CAP_MEMOBJ:
 146    case PIPE_CAP_LOAD_CONSTBUF:
 147    case PIPE_CAP_INT64:
 148    case PIPE_CAP_INT64_DIVMOD:
 149    case PIPE_CAP_TGSI_CLOCK:
 150    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 151    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 152    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 153    case PIPE_CAP_TGSI_BALLOT:
 154    case PIPE_CAP_TGSI_VOTE:
 155    case PIPE_CAP_FBFETCH:
 156    case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
 157    case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 158    case PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA:
 159    case PIPE_CAP_TGSI_DIV:
 160    case PIPE_CAP_PACKED_UNIFORMS:
 161    case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
 162    case PIPE_CAP_GL_SPIRV:
 163    case PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES:
 164    case PIPE_CAP_ALPHA_TO_COVERAGE_DITHER_CONTROL:
 165    case PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE:
 166    case PIPE_CAP_NO_CLIP_ON_COPY_TEX:
 167       return 1;
 168
 169    case PIPE_CAP_GLSL_ZERO_INIT:
 170       return 2;
 171
 172    case PIPE_CAP_QUERY_SO_OVERFLOW:
 173       return !sscreen->use_ngg_streamout;
 174
 175    case PIPE_CAP_POST_DEPTH_COVERAGE:
 176       return sscreen->info.chip_class >= GFX10;
 177
 178    case PIPE_CAP_GRAPHICS:
 179       return sscreen->info.has_graphics;
 180
 181    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 182       return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 183
 184    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 185       return sscreen->info.has_gpu_reset_status_query;
 186
 187    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 188       return sscreen->info.has_2d_tiling;
 189
 190    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 191       return SI_MAP_BUFFER_ALIGNMENT;
 192
 193    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 194    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 195    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 196    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 197    case PIPE_CAP_MAX_VERTEX_STREAMS:
 198    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 199    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 200       return 4;
 201
 202    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 203    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 204       if (!sscreen->info.has_indirect_compute_dispatch)
 205          return 420;
 206       return 460;
 207
 208    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 209       /* Optimal number for good TexSubImage performance on Polaris10. */
 210       return 64 * 1024 * 1024;
 211
 212    case PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE:
 213       return 4096 * 1024;
 214
 215    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 216    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 217       /* Align it down to 256 bytes. I've chosen the number randomly. */
 218       return ROUND_DOWN_TO(MIN2(sscreen->info.max_alloc_size, INT_MAX), 256);
 219
 220    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 221    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 222    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 223       return LLVM_VERSION_MAJOR < 9 && !sscreen->info.has_unaligned_shader_loads;
 224
 225    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 226       return sscreen->info.has_sparse_vm_mappings ? RADEON_SPARSE_PAGE_SIZE : 0;
 227
 228    case PIPE_CAP_UMA:
 229    case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
 230       return 0;
 231
 232    case PIPE_CAP_FENCE_SIGNAL:
 233       return sscreen->info.has_syncobj;
 234
 235    case PIPE_CAP_CONSTBUF0_FLAGS:
 236       return SI_RESOURCE_FLAG_32BIT;
 237
 238    case PIPE_CAP_NATIVE_FENCE_FD:
 239       return sscreen->info.has_fence_to_handle;
 240
 241    case PIPE_CAP_DRAW_PARAMETERS:
 242    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 243    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 244       return sscreen->has_draw_indirect_multi;
 245
 246    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 247       return 30;
 248
 249    case PIPE_CAP_MAX_VARYINGS:
 250       return 32;
 251
 252    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 253       return sscreen->info.chip_class <= GFX8 ? PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 254
 255    /* Stream output. */
 256    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 257    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 258       return 32 * 4;
 259
 260    /* Geometry shader output. */
 261    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 262       /* gfx9 has to report 256 to make piglit/gs-max-output pass.
 263        * gfx8 and earlier can do 1024.
 264        */
 265       return 256;
 266    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 267       return 4095;
 268    case PIPE_CAP_MAX_GS_INVOCATIONS:
 269       /* Even though the hw supports more, we officially wanna expose only 32. */
 270       return 32;
 271
 272    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 273       return 2048;
 274
 275    /* Texturing. */
 276    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 277       return 16384;
 278    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 279       return 15; /* 16384 */
 280    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 281       if (sscreen->info.chip_class >= GFX10)
 282          return 14;
 283       /* textures support 8192, but layered rendering supports 2048 */
 284       return 12;
 285    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 286       if (sscreen->info.chip_class >= GFX10)
 287          return 8192;
 288       /* textures support 8192, but layered rendering supports 2048 */
 289       return 2048;
 290
 291    /* Viewports and render targets. */
 292    case PIPE_CAP_MAX_VIEWPORTS:
 293       return SI_MAX_VIEWPORTS;
 294    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 295    case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 296    case PIPE_CAP_MAX_RENDER_TARGETS:
 297       return 8;
 298    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 299       return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
 300
 301    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 302    case PIPE_CAP_MIN_TEXEL_OFFSET:
 303       return -32;
 304
 305    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 306    case PIPE_CAP_MAX_TEXEL_OFFSET:
 307       return 31;
 308
 309    case PIPE_CAP_ENDIANNESS:
 310       return PIPE_ENDIAN_LITTLE;
 311
 312    case PIPE_CAP_VENDOR_ID:
 313       return ATI_VENDOR_ID;
 314    case PIPE_CAP_DEVICE_ID:
 315       return sscreen->info.pci_id;
 316    case PIPE_CAP_VIDEO_MEMORY:
 317       return sscreen->info.vram_size >> 20;
 318    case PIPE_CAP_PCI_GROUP:
 319       return sscreen->info.pci_domain;
 320    case PIPE_CAP_PCI_BUS:
 321       return sscreen->info.pci_bus;
 322    case PIPE_CAP_PCI_DEVICE:
 323       return sscreen->info.pci_dev;
 324    case PIPE_CAP_PCI_FUNCTION:
 325       return sscreen->info.pci_func;
 326    case PIPE_CAP_TGSI_ATOMINC_WRAP:
 327       return LLVM_VERSION_MAJOR >= 10;
 328
 329    default:
 330       return u_pipe_screen_get_param_defaults(pscreen, param);
 331    }
 332 }
 333
 334 static float si_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 335 {
 336    switch (param) {
 337    case PIPE_CAPF_MAX_LINE_WIDTH:
 338    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 339       /* This depends on the quant mode, though the precise interactions
 340        * are unknown. */
 341       return 2048;
 342    case PIPE_CAPF_MAX_POINT_WIDTH:
 343    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 344       return SI_MAX_POINT_SIZE;
 345    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 346       return 16.0f;
 347    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 348       return 16.0f;
 349    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 350    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 351    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 352       return 0.0f;
 353    }
 354    return 0.0f;
 355 }
 356
 357 static int si_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_type shader,
 358                                enum pipe_shader_cap param)
 359 {
 360    struct si_screen *sscreen = (struct si_screen *)pscreen;
 361
 362    switch (shader) {
 363    case PIPE_SHADER_FRAGMENT:
 364    case PIPE_SHADER_VERTEX:
 365    case PIPE_SHADER_GEOMETRY:
 366    case PIPE_SHADER_TESS_CTRL:
 367    case PIPE_SHADER_TESS_EVAL:
 368       break;
 369    case PIPE_SHADER_COMPUTE:
 370       switch (param) {
 371       case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 372          int ir = 1 << PIPE_SHADER_IR_NATIVE;
 373
 374          if (sscreen->info.has_indirect_compute_dispatch)
 375             ir |= 1 << PIPE_SHADER_IR_NIR;
 376
 377          return ir;
 378       }
 379       default:
 380          /* If compute shaders don't require a special value
 381           * for this cap, we can return the same value we
 382           * do for other shader types. */
 383          break;
 384       }
 385       break;
 386    default:
 387       return 0;
 388    }
 389
 390    switch (param) {
 391    /* Shader limits. */
 392    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 393    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 394    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 395    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 396    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 397       return 16384;
 398    case PIPE_SHADER_CAP_MAX_INPUTS:
 399       return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 400    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 401       return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 402    case PIPE_SHADER_CAP_MAX_TEMPS:
 403       return 256; /* Max native temporaries. */
 404    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 405       return si_get_param(pscreen, PIPE_CAP_MAX_SHADER_BUFFER_SIZE);
 406    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 407       return SI_NUM_CONST_BUFFERS;
 408    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 409    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 410       return SI_NUM_SAMPLERS;
 411    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 412       return SI_NUM_SHADER_BUFFERS;
 413    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 414       return SI_NUM_IMAGES;
 415    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 416       return 0;
 417    case PIPE_SHADER_CAP_PREFERRED_IR:
 418       return PIPE_SHADER_IR_NIR;
 419    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 420       return 4;
 421
 422    /* Supported boolean features. */
 423    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 424    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 425    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 426    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 427    case PIPE_SHADER_CAP_INTEGERS:
 428    case PIPE_SHADER_CAP_INT64_ATOMICS:
 429    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 430    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 431    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 432    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 433    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 434    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 435    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: /* lowered in finalize_nir */
 436    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: /* lowered in finalize_nir */
 437       return 1;
 438
 439    /* Unsupported boolean features. */
 440    case PIPE_SHADER_CAP_FP16:
 441    case PIPE_SHADER_CAP_FP16_DERIVATIVES:
 442    case PIPE_SHADER_CAP_INT16:
 443    case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
 444    case PIPE_SHADER_CAP_SUBROUTINES:
 445    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 446    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 447    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 448       return 0;
 449    }
 450    return 0;
 451 }
 452
 453 static const struct nir_shader_compiler_options nir_options = {
 454    .lower_scmp = true,
 455    .lower_flrp32 = true,
 456    .lower_flrp64 = true,
 457    .lower_fsat = true,
 458    .lower_fdiv = true,
 459    .lower_bitfield_insert_to_bitfield_select = true,
 460    .lower_bitfield_extract = true,
 461    .lower_sub = true,
 462    .fuse_ffma = true,
 463    .lower_fmod = true,
 464    .lower_pack_snorm_4x8 = true,
 465    .lower_pack_unorm_4x8 = true,
 466    .lower_unpack_snorm_2x16 = true,
 467    .lower_unpack_snorm_4x8 = true,
 468    .lower_unpack_unorm_2x16 = true,
 469    .lower_unpack_unorm_4x8 = true,
 470    .lower_extract_byte = true,
 471    .lower_extract_word = true,
 472    .lower_rotate = true,
 473    .lower_to_scalar = true,
 474    .optimize_sample_mask_in = true,
 475    .max_unroll_iterations = 32,
 476    .use_interpolated_input_intrinsics = true,
 477 };
 478
 479 static const void *si_get_compiler_options(struct pipe_screen *screen, enum pipe_shader_ir ir,
 480                                            enum pipe_shader_type shader)
 481 {
 482    assert(ir == PIPE_SHADER_IR_NIR);
 483    return &nir_options;
 484 }
 485
 486 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 487 {
 488    ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 489 }
 490
 491 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 492 {
 493    struct si_screen *sscreen = (struct si_screen *)pscreen;
 494
 495    ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 496 }
 497
 498 static const char *si_get_name(struct pipe_screen *pscreen)
 499 {
 500    struct si_screen *sscreen = (struct si_screen *)pscreen;
 501
 502    return sscreen->renderer_string;
 503 }
 504
 505 static int si_get_video_param_no_decode(struct pipe_screen *screen, enum pipe_video_profile profile,
 506                                         enum pipe_video_entrypoint entrypoint,
 507                                         enum pipe_video_cap param)
 508 {
 509    switch (param) {
 510    case PIPE_VIDEO_CAP_SUPPORTED:
 511       return vl_profile_supported(screen, profile, entrypoint);
 512    case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 513       return 1;
 514    case PIPE_VIDEO_CAP_MAX_WIDTH:
 515    case PIPE_VIDEO_CAP_MAX_HEIGHT:
 516       return vl_video_buffer_max_size(screen);
 517    case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 518       return PIPE_FORMAT_NV12;
 519    case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 520       return false;
 521    case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 522       return false;
 523    case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 524       return true;
 525    case PIPE_VIDEO_CAP_MAX_LEVEL:
 526       return vl_level_supported(screen, profile);
 527    default:
 528       return 0;
 529    }
 530 }
 531
 532 static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profile profile,
 533                               enum pipe_video_entrypoint entrypoint, enum pipe_video_cap param)
 534 {
 535    struct si_screen *sscreen = (struct si_screen *)screen;
 536    enum pipe_video_format codec = u_reduce_video_profile(profile);
 537
 538    if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 539       switch (param) {
 540       case PIPE_VIDEO_CAP_SUPPORTED:
 541          return (
 542             (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 543              (sscreen->info.family >= CHIP_RAVEN || si_vce_is_fw_version_supported(sscreen))) ||
 544             (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 545              (sscreen->info.family >= CHIP_RAVEN || si_radeon_uvd_enc_supported(sscreen))) ||
 546             (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 && sscreen->info.family >= CHIP_RENOIR));
 547       case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 548          return 1;
 549       case PIPE_VIDEO_CAP_MAX_WIDTH:
 550          return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 551       case PIPE_VIDEO_CAP_MAX_HEIGHT:
 552          return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 553       case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 554          return PIPE_FORMAT_NV12;
 555       case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 556          return false;
 557       case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 558          return false;
 559       case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 560          return true;
 561       case PIPE_VIDEO_CAP_STACKED_FRAMES:
 562          return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 563       default:
 564          return 0;
 565       }
 566    }
 567
 568    switch (param) {
 569    case PIPE_VIDEO_CAP_SUPPORTED:
 570       switch (codec) {
 571       case PIPE_VIDEO_FORMAT_MPEG12:
 572          return profile != PIPE_VIDEO_PROFILE_MPEG1;
 573       case PIPE_VIDEO_FORMAT_MPEG4:
 574          return 1;
 575       case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 576          if ((sscreen->info.family == CHIP_POLARIS10 || sscreen->info.family == CHIP_POLARIS11) &&
 577              sscreen->info.uvd_fw_version < UVD_FW_1_66_16) {
 578             RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 579             return false;
 580          }
 581          return true;
 582       case PIPE_VIDEO_FORMAT_VC1:
 583          return true;
 584       case PIPE_VIDEO_FORMAT_HEVC:
 585          /* Carrizo only supports HEVC Main */
 586          if (sscreen->info.family >= CHIP_STONEY)
 587             return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 588                     profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 589          else if (sscreen->info.family >= CHIP_CARRIZO)
 590             return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 591          return false;
 592       case PIPE_VIDEO_FORMAT_JPEG:
 593          if (sscreen->info.family >= CHIP_RAVEN)
 594             return true;
 595          if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 596             return false;
 597          if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 19)) {
 598             RVID_ERR("No MJPEG support for the kernel version\n");
 599             return false;
 600          }
 601          return true;
 602       case PIPE_VIDEO_FORMAT_VP9:
 603          if (sscreen->info.family < CHIP_RAVEN)
 604             return false;
 605          return true;
 606       default:
 607          return false;
 608       }
 609    case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 610       return 1;
 611    case PIPE_VIDEO_CAP_MAX_WIDTH:
 612       switch (codec) {
 613       case PIPE_VIDEO_FORMAT_HEVC:
 614       case PIPE_VIDEO_FORMAT_VP9:
 615          return (sscreen->info.family < CHIP_RENOIR)
 616                    ? ((sscreen->info.family < CHIP_TONGA) ? 2048 : 4096)
 617                    : 8192;
 618       default:
 619          return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 620       }
 621    case PIPE_VIDEO_CAP_MAX_HEIGHT:
 622       switch (codec) {
 623       case PIPE_VIDEO_FORMAT_HEVC:
 624       case PIPE_VIDEO_FORMAT_VP9:
 625          return (sscreen->info.family < CHIP_RENOIR)
 626                    ? ((sscreen->info.family < CHIP_TONGA) ? 1152 : 4096)
 627                    : 4352;
 628       default:
 629          return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 630       }
 631    case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 632       if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 633          return PIPE_FORMAT_P010;
 634       else if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 635          return PIPE_FORMAT_P010;
 636       else
 637          return PIPE_FORMAT_NV12;
 638
 639    case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 640    case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 641       enum pipe_video_format format = u_reduce_video_profile(profile);
 642
 643       if (format == PIPE_VIDEO_FORMAT_HEVC)
 644          return false; // The firmware doesn't support interlaced HEVC.
 645       else if (format == PIPE_VIDEO_FORMAT_JPEG)
 646          return false;
 647       else if (format == PIPE_VIDEO_FORMAT_VP9)
 648          return false;
 649       return true;
 650    }
 651    case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 652       return true;
 653    case PIPE_VIDEO_CAP_MAX_LEVEL:
 654       switch (profile) {
 655       case PIPE_VIDEO_PROFILE_MPEG1:
 656          return 0;
 657       case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 658       case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 659          return 3;
 660       case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 661          return 3;
 662       case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 663          return 5;
 664       case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 665          return 1;
 666       case PIPE_VIDEO_PROFILE_VC1_MAIN:
 667          return 2;
 668       case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 669          return 4;
 670       case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 671       case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 672       case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 673          return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 674       case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 675       case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 676          return 186;
 677       default:
 678          return 0;
 679       }
 680    default:
 681       return 0;
 682    }
 683 }
 684
 685 static bool si_vid_is_format_supported(struct pipe_screen *screen, enum pipe_format format,
 686                                        enum pipe_video_profile profile,
 687                                        enum pipe_video_entrypoint entrypoint)
 688 {
 689    /* HEVC 10 bit decoding should use P010 instead of NV12 if possible */
 690    if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 691       return (format == PIPE_FORMAT_NV12) || (format == PIPE_FORMAT_P010) ||
 692              (format == PIPE_FORMAT_P016);
 693
 694    /* Vp9 profile 2 supports 10 bit decoding using P016 */
 695    if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 696       return (format == PIPE_FORMAT_P010) || (format == PIPE_FORMAT_P016);
 697
 698    /* we can only handle this one with UVD */
 699    if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 700       return format == PIPE_FORMAT_NV12;
 701
 702    return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 703 }
 704
 705 static unsigned get_max_threads_per_block(struct si_screen *screen, enum pipe_shader_ir ir_type)
 706 {
 707    if (ir_type == PIPE_SHADER_IR_NATIVE)
 708       return 256;
 709
 710    /* LLVM 10 only supports 1024 threads per block. */
 711    return 1024;
 712 }
 713
 714 static int si_get_compute_param(struct pipe_screen *screen, enum pipe_shader_ir ir_type,
 715                                 enum pipe_compute_cap param, void *ret)
 716 {
 717    struct si_screen *sscreen = (struct si_screen *)screen;
 718
 719    // TODO: select these params by asic
 720    switch (param) {
 721    case PIPE_COMPUTE_CAP_IR_TARGET: {
 722       const char *gpu, *triple;
 723
 724       triple = "amdgcn-mesa-mesa3d";
 725       gpu = ac_get_llvm_processor_name(sscreen->info.family);
 726       if (ret) {
 727          sprintf(ret, "%s-%s", gpu, triple);
 728       }
 729       /* +2 for dash and terminating NIL byte */
 730       return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 731    }
 732    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 733       if (ret) {
 734          uint64_t *grid_dimension = ret;
 735          grid_dimension[0] = 3;
 736       }
 737       return 1 * sizeof(uint64_t);
 738
 739    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 740       if (ret) {
 741          uint64_t *grid_size = ret;
 742          grid_size[0] = 65535;
 743          grid_size[1] = 65535;
 744          grid_size[2] = 65535;
 745       }
 746       return 3 * sizeof(uint64_t);
 747
 748    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 749       if (ret) {
 750          uint64_t *block_size = ret;
 751          unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 752          block_size[0] = threads_per_block;
 753          block_size[1] = threads_per_block;
 754          block_size[2] = threads_per_block;
 755       }
 756       return 3 * sizeof(uint64_t);
 757
 758    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 759       if (ret) {
 760          uint64_t *max_threads_per_block = ret;
 761          *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 762       }
 763       return sizeof(uint64_t);
 764    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 765       if (ret) {
 766          uint32_t *address_bits = ret;
 767          address_bits[0] = 64;
 768       }
 769       return 1 * sizeof(uint32_t);
 770
 771    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 772       if (ret) {
 773          uint64_t *max_global_size = ret;
 774          uint64_t max_mem_alloc_size;
 775
 776          si_get_compute_param(screen, ir_type, PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 777                               &max_mem_alloc_size);
 778
 779          /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 780           * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 781           * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 782           * make sure we never report more than
 783           * 4 * MAX_MEM_ALLOC_SIZE.
 784           */
 785          *max_global_size =
 786             MIN2(4 * max_mem_alloc_size, MAX2(sscreen->info.gart_size, sscreen->info.vram_size));
 787       }
 788       return sizeof(uint64_t);
 789
 790    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 791       if (ret) {
 792          uint64_t *max_local_size = ret;
 793          /* Value reported by the closed source driver. */
 794          *max_local_size = 32768;
 795       }
 796       return sizeof(uint64_t);
 797
 798    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 799       if (ret) {
 800          uint64_t *max_input_size = ret;
 801          /* Value reported by the closed source driver. */
 802          *max_input_size = 1024;
 803       }
 804       return sizeof(uint64_t);
 805
 806    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 807       if (ret) {
 808          uint64_t *max_mem_alloc_size = ret;
 809
 810          *max_mem_alloc_size = sscreen->info.max_alloc_size;
 811       }
 812       return sizeof(uint64_t);
 813
 814    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 815       if (ret) {
 816          uint32_t *max_clock_frequency = ret;
 817          *max_clock_frequency = sscreen->info.max_shader_clock;
 818       }
 819       return sizeof(uint32_t);
 820
 821    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 822       if (ret) {
 823          uint32_t *max_compute_units = ret;
 824          *max_compute_units = sscreen->info.num_good_compute_units;
 825       }
 826       return sizeof(uint32_t);
 827
 828    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 829       if (ret) {
 830          uint32_t *images_supported = ret;
 831          *images_supported = 0;
 832       }
 833       return sizeof(uint32_t);
 834    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 835       break; /* unused */
 836    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 837       if (ret) {
 838          uint32_t *subgroup_size = ret;
 839          *subgroup_size = sscreen->compute_wave_size;
 840       }
 841       return sizeof(uint32_t);
 842    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 843       if (ret) {
 844          uint64_t *max_variable_threads_per_block = ret;
 845          if (ir_type == PIPE_SHADER_IR_NATIVE)
 846             *max_variable_threads_per_block = 0;
 847          else
 848             *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 849       }
 850       return sizeof(uint64_t);
 851    }
 852
 853    fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 854    return 0;
 855 }
 856
 857 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 858 {
 859    struct si_screen *sscreen = (struct si_screen *)screen;
 860
 861    return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 862           sscreen->info.clock_crystal_freq;
 863 }
 864
 865 static void si_query_memory_info(struct pipe_screen *screen, struct pipe_memory_info *info)
 866 {
 867    struct si_screen *sscreen = (struct si_screen *)screen;
 868    struct radeon_winsys *ws = sscreen->ws;
 869    unsigned vram_usage, gtt_usage;
 870
 871    info->total_device_memory = sscreen->info.vram_size / 1024;
 872    info->total_staging_memory = sscreen->info.gart_size / 1024;
 873
 874    /* The real TTM memory usage is somewhat random, because:
 875     *
 876     * 1) TTM delays freeing memory, because it can only free it after
 877     *    fences expire.
 878     *
 879     * 2) The memory usage can be really low if big VRAM evictions are
 880     *    taking place, but the real usage is well above the size of VRAM.
 881     *
 882     * Instead, return statistics of this process.
 883     */
 884    vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
 885    gtt_usage = ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
 886
 887    info->avail_device_memory =
 888       vram_usage <= info->total_device_memory ? info->total_device_memory - vram_usage : 0;
 889    info->avail_staging_memory =
 890       gtt_usage <= info->total_staging_memory ? info->total_staging_memory - gtt_usage : 0;
 891
 892    info->device_memory_evicted = ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 893
 894    if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 4)
 895       info->nr_device_memory_evictions = ws->query_value(ws, RADEON_NUM_EVICTIONS);
 896    else
 897       /* Just return the number of evicted 64KB pages. */
 898       info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 899 }
 900
 901 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 902 {
 903    struct si_screen *sscreen = (struct si_screen *)pscreen;
 904
 905    return sscreen->disk_shader_cache;
 906 }
 907
 908 static void si_init_renderer_string(struct si_screen *sscreen)
 909 {
 910    char first_name[256], second_name[32] = {}, kernel_version[128] = {};
 911    struct utsname uname_data;
 912
 913    if (sscreen->info.marketing_name) {
 914       snprintf(first_name, sizeof(first_name), "%s", sscreen->info.marketing_name);
 915       snprintf(second_name, sizeof(second_name), "%s, ", sscreen->info.name);
 916    } else {
 917       snprintf(first_name, sizeof(first_name), "AMD %s", sscreen->info.name);
 918    }
 919
 920    if (uname(&uname_data) == 0)
 921       snprintf(kernel_version, sizeof(kernel_version), ", %s", uname_data.release);
 922
 923    snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 924             "%s (%sDRM %i.%i.%i%s, LLVM " MESA_LLVM_VERSION_STRING ")", first_name, second_name,
 925             sscreen->info.drm_major, sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 926             kernel_version);
 927 }
 928
 929 void si_init_screen_get_functions(struct si_screen *sscreen)
 930 {
 931    sscreen->b.get_name = si_get_name;
 932    sscreen->b.get_vendor = si_get_vendor;
 933    sscreen->b.get_device_vendor = si_get_device_vendor;
 934    sscreen->b.get_param = si_get_param;
 935    sscreen->b.get_paramf = si_get_paramf;
 936    sscreen->b.get_compute_param = si_get_compute_param;
 937    sscreen->b.get_timestamp = si_get_timestamp;
 938    sscreen->b.get_shader_param = si_get_shader_param;
 939    sscreen->b.get_compiler_options = si_get_compiler_options;
 940    sscreen->b.get_device_uuid = si_get_device_uuid;
 941    sscreen->b.get_driver_uuid = si_get_driver_uuid;
 942    sscreen->b.query_memory_info = si_query_memory_info;
 943    sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
 944
 945    if (sscreen->info.has_hw_decode) {
 946       sscreen->b.get_video_param = si_get_video_param;
 947       sscreen->b.is_video_format_supported = si_vid_is_format_supported;
 948    } else {
 949       sscreen->b.get_video_param = si_get_video_param_no_decode;
 950       sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 951    }
 952
 953    si_init_renderer_string(sscreen);
 954 }