2 * Copyright 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "radeon/radeon_video.h"
27 #include "radeon/radeon_vce.h"
28 #include "radeon/radeon_uvd_enc.h"
29 #include "ac_llvm_util.h"
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32 #include "util/u_screen.h"
33 #include "util/u_video.h"
34 #include "compiler/nir/nir.h"
36 #include <sys/utsname.h>
38 static const char *si_get_vendor(struct pipe_screen
*pscreen
)
40 /* Don't change this. Games such as Alien Isolation are broken if this
41 * returns "Advanced Micro Devices, Inc."
46 static const char *si_get_device_vendor(struct pipe_screen
*pscreen
)
51 static int si_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
53 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
56 /* Supported features (boolean caps). */
57 case PIPE_CAP_ACCELERATED
:
58 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
59 case PIPE_CAP_ANISOTROPIC_FILTER
:
60 case PIPE_CAP_POINT_SPRITE
:
61 case PIPE_CAP_OCCLUSION_QUERY
:
62 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
63 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE
:
64 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
65 case PIPE_CAP_TEXTURE_SWIZZLE
:
66 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
67 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE
:
68 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
69 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
70 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
71 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
72 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
73 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
75 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
76 case PIPE_CAP_PRIMITIVE_RESTART
:
77 case PIPE_CAP_CONDITIONAL_RENDER
:
78 case PIPE_CAP_TEXTURE_BARRIER
:
79 case PIPE_CAP_INDEP_BLEND_ENABLE
:
80 case PIPE_CAP_INDEP_BLEND_FUNC
:
81 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
82 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
83 case PIPE_CAP_START_INSTANCE
:
84 case PIPE_CAP_NPOT_TEXTURES
:
85 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
86 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
87 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
88 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
89 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
90 case PIPE_CAP_TGSI_INSTANCEID
:
91 case PIPE_CAP_COMPUTE
:
92 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
93 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
94 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
95 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
96 case PIPE_CAP_CUBE_MAP_ARRAY
:
97 case PIPE_CAP_SAMPLE_SHADING
:
98 case PIPE_CAP_DRAW_INDIRECT
:
99 case PIPE_CAP_CLIP_HALFZ
:
100 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
101 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
102 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
103 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
104 case PIPE_CAP_TGSI_TEXCOORD
:
105 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
106 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
107 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
108 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
109 case PIPE_CAP_SHAREABLE_SHADERS
:
110 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
111 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
112 case PIPE_CAP_TEXTURE_QUERY_LOD
:
113 case PIPE_CAP_TEXTURE_GATHER_SM5
:
114 case PIPE_CAP_TGSI_TXQS
:
115 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
116 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
117 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
118 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
119 case PIPE_CAP_INVALIDATE_BUFFER
:
120 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
121 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
122 case PIPE_CAP_QUERY_MEMORY_INFO
:
123 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
124 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
125 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
126 case PIPE_CAP_GENERATE_MIPMAP
:
127 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
128 case PIPE_CAP_STRING_MARKER
:
129 case PIPE_CAP_CLEAR_TEXTURE
:
130 case PIPE_CAP_CULL_DISTANCE
:
131 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
132 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
133 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
134 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
135 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
136 case PIPE_CAP_DOUBLES
:
137 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
138 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
139 case PIPE_CAP_BINDLESS_TEXTURE
:
140 case PIPE_CAP_QUERY_TIMESTAMP
:
141 case PIPE_CAP_QUERY_TIME_ELAPSED
:
142 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
143 case PIPE_CAP_QUERY_SO_OVERFLOW
:
144 case PIPE_CAP_MEMOBJ
:
145 case PIPE_CAP_LOAD_CONSTBUF
:
147 case PIPE_CAP_INT64_DIVMOD
:
148 case PIPE_CAP_TGSI_CLOCK
:
149 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
150 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
151 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
:
152 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
153 case PIPE_CAP_TGSI_BALLOT
:
154 case PIPE_CAP_TGSI_VOTE
:
155 case PIPE_CAP_FBFETCH
:
156 case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK
:
157 case PIPE_CAP_IMAGE_LOAD_FORMATTED
:
158 case PIPE_CAP_PREFER_COMPUTE_BLIT_FOR_MULTIMEDIA
:
161 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
162 return !SI_BIG_ENDIAN
&& sscreen
->info
.has_userptr
;
164 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
165 return sscreen
->info
.has_gpu_reset_status_query
;
167 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
168 return sscreen
->info
.has_2d_tiling
;
170 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
171 return SI_MAP_BUFFER_ALIGNMENT
;
173 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
174 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
175 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
176 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
177 case PIPE_CAP_MAX_VERTEX_STREAMS
:
178 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
179 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
182 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
183 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
184 if (sscreen
->info
.has_indirect_compute_dispatch
)
188 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET
:
189 /* Optimal number for good TexSubImage performance on Polaris10. */
190 return 64 * 1024 * 1024;
192 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
193 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE
:
194 return MIN2(sscreen
->info
.max_alloc_size
, INT_MAX
);
196 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
197 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
198 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
199 return HAVE_LLVM
< 0x0900 && !sscreen
->info
.has_unaligned_shader_loads
;
201 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
202 return sscreen
->info
.has_sparse_vm_mappings
?
203 RADEON_SPARSE_PAGE_SIZE
: 0;
205 case PIPE_CAP_PACKED_UNIFORMS
:
206 if (sscreen
->options
.enable_nir
)
210 /* Unsupported features. */
211 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
212 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
213 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
214 case PIPE_CAP_USER_VERTEX_BUFFERS
:
215 case PIPE_CAP_FAKE_SW_MSAA
:
216 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
217 case PIPE_CAP_VERTEXID_NOBASE
:
218 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
219 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
221 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
222 case PIPE_CAP_POST_DEPTH_COVERAGE
:
223 case PIPE_CAP_TILE_RASTER_ORDER
:
224 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES
:
225 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
226 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES
:
227 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES
:
228 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES
:
229 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES
:
230 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE
:
231 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS
:
232 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS
:
235 case PIPE_CAP_FENCE_SIGNAL
:
236 return sscreen
->info
.has_syncobj
;
238 case PIPE_CAP_CONSTBUF0_FLAGS
:
239 return SI_RESOURCE_FLAG_32BIT
;
241 case PIPE_CAP_NATIVE_FENCE_FD
:
242 return sscreen
->info
.has_fence_to_handle
;
244 case PIPE_CAP_DRAW_PARAMETERS
:
245 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
246 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
247 return sscreen
->has_draw_indirect_multi
;
249 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
252 case PIPE_CAP_MAX_VARYINGS
:
255 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
256 return sscreen
->info
.chip_class
<= GFX8
?
257 PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600
: 0;
260 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
261 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
264 /* Geometry shader output. */
265 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
266 /* gfx9 has to report 256 to make piglit/gs-max-output pass.
267 * gfx8 and earlier can do 1024.
270 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
272 case PIPE_CAP_MAX_GS_INVOCATIONS
:
273 /* The closed driver exposes 127, but 125 is the greatest
274 * number that works. */
277 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
281 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
283 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
284 return 15; /* 16384 */
285 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
286 /* textures support 8192, but layered rendering supports 2048 */
288 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
289 /* textures support 8192, but layered rendering supports 2048 */
292 /* Viewports and render targets. */
293 case PIPE_CAP_MAX_VIEWPORTS
:
294 return SI_MAX_VIEWPORTS
;
295 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
296 case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS
:
297 case PIPE_CAP_MAX_RENDER_TARGETS
:
299 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS
:
300 return sscreen
->info
.has_eqaa_surface_allocator
? 2 : 0;
302 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
303 case PIPE_CAP_MIN_TEXEL_OFFSET
:
306 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
307 case PIPE_CAP_MAX_TEXEL_OFFSET
:
310 case PIPE_CAP_ENDIANNESS
:
311 return PIPE_ENDIAN_LITTLE
;
313 case PIPE_CAP_VENDOR_ID
:
314 return ATI_VENDOR_ID
;
315 case PIPE_CAP_DEVICE_ID
:
316 return sscreen
->info
.pci_id
;
317 case PIPE_CAP_VIDEO_MEMORY
:
318 return sscreen
->info
.vram_size
>> 20;
319 case PIPE_CAP_PCI_GROUP
:
320 return sscreen
->info
.pci_domain
;
321 case PIPE_CAP_PCI_BUS
:
322 return sscreen
->info
.pci_bus
;
323 case PIPE_CAP_PCI_DEVICE
:
324 return sscreen
->info
.pci_dev
;
325 case PIPE_CAP_PCI_FUNCTION
:
326 return sscreen
->info
.pci_func
;
329 return u_pipe_screen_get_param_defaults(pscreen
, param
);
333 static float si_get_paramf(struct pipe_screen
* pscreen
, enum pipe_capf param
)
336 case PIPE_CAPF_MAX_LINE_WIDTH
:
337 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
338 /* This depends on the quant mode, though the precise interactions
341 case PIPE_CAPF_MAX_POINT_WIDTH
:
342 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
343 return SI_MAX_POINT_SIZE
;
344 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
346 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
348 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
349 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
350 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
356 static int si_get_shader_param(struct pipe_screen
* pscreen
,
357 enum pipe_shader_type shader
,
358 enum pipe_shader_cap param
)
360 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
364 case PIPE_SHADER_FRAGMENT
:
365 case PIPE_SHADER_VERTEX
:
366 case PIPE_SHADER_GEOMETRY
:
367 case PIPE_SHADER_TESS_CTRL
:
368 case PIPE_SHADER_TESS_EVAL
:
370 case PIPE_SHADER_COMPUTE
:
372 case PIPE_SHADER_CAP_SUPPORTED_IRS
: {
373 int ir
= 1 << PIPE_SHADER_IR_NATIVE
;
375 if (sscreen
->info
.has_indirect_compute_dispatch
)
376 ir
|= 1 << PIPE_SHADER_IR_TGSI
;
381 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
: {
382 uint64_t max_const_buffer_size
;
383 pscreen
->get_compute_param(pscreen
, PIPE_SHADER_IR_TGSI
,
384 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
385 &max_const_buffer_size
);
386 return MIN2(max_const_buffer_size
, INT_MAX
);
389 /* If compute shaders don't require a special value
390 * for this cap, we can return the same value we
391 * do for other shader types. */
401 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
402 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
403 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
404 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
405 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
407 case PIPE_SHADER_CAP_MAX_INPUTS
:
408 return shader
== PIPE_SHADER_VERTEX
? SI_MAX_ATTRIBS
: 32;
409 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
410 return shader
== PIPE_SHADER_FRAGMENT
? 8 : 32;
411 case PIPE_SHADER_CAP_MAX_TEMPS
:
412 return 256; /* Max native temporaries. */
413 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
414 return MIN2(sscreen
->info
.max_alloc_size
, INT_MAX
- 3); /* aligned to 4 */
415 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
416 return SI_NUM_CONST_BUFFERS
;
417 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
418 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
419 return SI_NUM_SAMPLERS
;
420 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
421 return SI_NUM_SHADER_BUFFERS
;
422 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
423 return SI_NUM_IMAGES
;
424 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
425 if (sscreen
->options
.enable_nir
)
428 case PIPE_SHADER_CAP_PREFERRED_IR
:
429 if (sscreen
->options
.enable_nir
)
430 return PIPE_SHADER_IR_NIR
;
431 return PIPE_SHADER_IR_TGSI
;
432 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
435 /* Supported boolean features. */
436 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
437 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
438 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
439 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
440 case PIPE_SHADER_CAP_INTEGERS
:
441 case PIPE_SHADER_CAP_INT64_ATOMICS
:
442 case PIPE_SHADER_CAP_FP16
:
443 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
444 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
445 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
446 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
447 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
448 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
451 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
452 /* TODO: Indirect indexing of GS inputs is unimplemented. */
453 if (shader
== PIPE_SHADER_GEOMETRY
)
456 if (shader
== PIPE_SHADER_VERTEX
&&
457 !sscreen
->llvm_has_working_vgpr_indexing
)
460 /* TCS and TES load inputs directly from LDS or offchip
461 * memory, so indirect indexing is always supported.
462 * PS has to support indirect indexing, because we can't
463 * lower that to TEMPs for INTERP instructions.
467 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
468 return sscreen
->llvm_has_working_vgpr_indexing
||
469 /* TCS stores outputs directly to memory. */
470 shader
== PIPE_SHADER_TESS_CTRL
;
472 /* Unsupported boolean features. */
473 case PIPE_SHADER_CAP_SUBROUTINES
:
474 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
475 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
476 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
478 case PIPE_SHADER_CAP_SCALAR_ISA
:
484 static const struct nir_shader_compiler_options nir_options
= {
486 .lower_flrp32
= true,
487 .lower_flrp64
= true,
490 .lower_bitfield_insert_to_bitfield_select
= true,
494 .lower_pack_snorm_2x16
= true,
495 .lower_pack_snorm_4x8
= true,
496 .lower_pack_unorm_2x16
= true,
497 .lower_pack_unorm_4x8
= true,
498 .lower_unpack_snorm_2x16
= true,
499 .lower_unpack_snorm_4x8
= true,
500 .lower_unpack_unorm_2x16
= true,
501 .lower_unpack_unorm_4x8
= true,
502 .lower_extract_byte
= true,
503 .lower_extract_word
= true,
504 .optimize_sample_mask_in
= true,
505 .max_unroll_iterations
= 32,
509 si_get_compiler_options(struct pipe_screen
*screen
,
510 enum pipe_shader_ir ir
,
511 enum pipe_shader_type shader
)
513 assert(ir
== PIPE_SHADER_IR_NIR
);
517 static void si_get_driver_uuid(struct pipe_screen
*pscreen
, char *uuid
)
519 ac_compute_driver_uuid(uuid
, PIPE_UUID_SIZE
);
522 static void si_get_device_uuid(struct pipe_screen
*pscreen
, char *uuid
)
524 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
526 ac_compute_device_uuid(&sscreen
->info
, uuid
, PIPE_UUID_SIZE
);
529 static const char* si_get_name(struct pipe_screen
*pscreen
)
531 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
533 return sscreen
->renderer_string
;
536 static int si_get_video_param_no_decode(struct pipe_screen
*screen
,
537 enum pipe_video_profile profile
,
538 enum pipe_video_entrypoint entrypoint
,
539 enum pipe_video_cap param
)
542 case PIPE_VIDEO_CAP_SUPPORTED
:
543 return vl_profile_supported(screen
, profile
, entrypoint
);
544 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
546 case PIPE_VIDEO_CAP_MAX_WIDTH
:
547 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
548 return vl_video_buffer_max_size(screen
);
549 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
550 return PIPE_FORMAT_NV12
;
551 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
553 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
555 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
557 case PIPE_VIDEO_CAP_MAX_LEVEL
:
558 return vl_level_supported(screen
, profile
);
564 static int si_get_video_param(struct pipe_screen
*screen
,
565 enum pipe_video_profile profile
,
566 enum pipe_video_entrypoint entrypoint
,
567 enum pipe_video_cap param
)
569 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
570 enum pipe_video_format codec
= u_reduce_video_profile(profile
);
572 if (entrypoint
== PIPE_VIDEO_ENTRYPOINT_ENCODE
) {
574 case PIPE_VIDEO_CAP_SUPPORTED
:
575 return (codec
== PIPE_VIDEO_FORMAT_MPEG4_AVC
&&
576 (si_vce_is_fw_version_supported(sscreen
) ||
577 sscreen
->info
.family
== CHIP_RAVEN
||
578 sscreen
->info
.family
== CHIP_RAVEN2
)) ||
579 (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
&&
580 (sscreen
->info
.family
== CHIP_RAVEN
||
581 sscreen
->info
.family
== CHIP_RAVEN2
||
582 si_radeon_uvd_enc_supported(sscreen
)));
583 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
585 case PIPE_VIDEO_CAP_MAX_WIDTH
:
586 return (sscreen
->info
.family
< CHIP_TONGA
) ? 2048 : 4096;
587 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
588 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1152 : 2304;
589 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
590 return PIPE_FORMAT_NV12
;
591 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
593 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
595 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
597 case PIPE_VIDEO_CAP_STACKED_FRAMES
:
598 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1 : 2;
605 case PIPE_VIDEO_CAP_SUPPORTED
:
607 case PIPE_VIDEO_FORMAT_MPEG12
:
608 return profile
!= PIPE_VIDEO_PROFILE_MPEG1
;
609 case PIPE_VIDEO_FORMAT_MPEG4
:
611 case PIPE_VIDEO_FORMAT_MPEG4_AVC
:
612 if ((sscreen
->info
.family
== CHIP_POLARIS10
||
613 sscreen
->info
.family
== CHIP_POLARIS11
) &&
614 sscreen
->info
.uvd_fw_version
< UVD_FW_1_66_16
) {
615 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
619 case PIPE_VIDEO_FORMAT_VC1
:
621 case PIPE_VIDEO_FORMAT_HEVC
:
622 /* Carrizo only supports HEVC Main */
623 if (sscreen
->info
.family
>= CHIP_STONEY
)
624 return (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
||
625 profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
);
626 else if (sscreen
->info
.family
>= CHIP_CARRIZO
)
627 return profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
;
629 case PIPE_VIDEO_FORMAT_JPEG
:
630 if (sscreen
->info
.family
== CHIP_RAVEN
||
631 sscreen
->info
.family
== CHIP_RAVEN2
)
633 if (sscreen
->info
.family
< CHIP_CARRIZO
|| sscreen
->info
.family
>= CHIP_VEGA10
)
635 if (!(sscreen
->info
.is_amdgpu
&& sscreen
->info
.drm_minor
>= 19)) {
636 RVID_ERR("No MJPEG support for the kernel version\n");
640 case PIPE_VIDEO_FORMAT_VP9
:
641 if (sscreen
->info
.family
< CHIP_RAVEN
)
647 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
649 case PIPE_VIDEO_CAP_MAX_WIDTH
:
650 return (sscreen
->info
.family
< CHIP_TONGA
) ? 2048 : 4096;
651 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
652 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1152 : 4096;
653 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
654 if (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
||
655 profile
== PIPE_VIDEO_PROFILE_VP9_PROFILE2
)
656 return PIPE_FORMAT_P016
;
658 return PIPE_FORMAT_NV12
;
660 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
661 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
: {
662 enum pipe_video_format format
= u_reduce_video_profile(profile
);
664 if (format
== PIPE_VIDEO_FORMAT_HEVC
)
665 return false; //The firmware doesn't support interlaced HEVC.
666 else if (format
== PIPE_VIDEO_FORMAT_JPEG
)
668 else if (format
== PIPE_VIDEO_FORMAT_VP9
)
672 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
674 case PIPE_VIDEO_CAP_MAX_LEVEL
:
676 case PIPE_VIDEO_PROFILE_MPEG1
:
678 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE
:
679 case PIPE_VIDEO_PROFILE_MPEG2_MAIN
:
681 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE
:
683 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE
:
685 case PIPE_VIDEO_PROFILE_VC1_SIMPLE
:
687 case PIPE_VIDEO_PROFILE_VC1_MAIN
:
689 case PIPE_VIDEO_PROFILE_VC1_ADVANCED
:
691 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE
:
692 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN
:
693 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH
:
694 return (sscreen
->info
.family
< CHIP_TONGA
) ? 41 : 52;
695 case PIPE_VIDEO_PROFILE_HEVC_MAIN
:
696 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10
:
706 static boolean
si_vid_is_format_supported(struct pipe_screen
*screen
,
707 enum pipe_format format
,
708 enum pipe_video_profile profile
,
709 enum pipe_video_entrypoint entrypoint
)
711 /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
712 if (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
)
713 return (format
== PIPE_FORMAT_NV12
) ||
714 (format
== PIPE_FORMAT_P016
);
716 /* we can only handle this one with UVD */
717 if (profile
!= PIPE_VIDEO_PROFILE_UNKNOWN
)
718 return format
== PIPE_FORMAT_NV12
;
720 return vl_video_buffer_is_format_supported(screen
, format
, profile
, entrypoint
);
723 static unsigned get_max_threads_per_block(struct si_screen
*screen
,
724 enum pipe_shader_ir ir_type
)
726 if (ir_type
== PIPE_SHADER_IR_NATIVE
)
729 /* Only 16 waves per thread-group on gfx9. */
730 if (screen
->info
.chip_class
>= GFX9
)
733 /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
739 static int si_get_compute_param(struct pipe_screen
*screen
,
740 enum pipe_shader_ir ir_type
,
741 enum pipe_compute_cap param
,
744 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
746 //TODO: select these params by asic
748 case PIPE_COMPUTE_CAP_IR_TARGET
: {
749 const char *gpu
, *triple
;
751 triple
= "amdgcn-mesa-mesa3d";
752 gpu
= ac_get_llvm_processor_name(sscreen
->info
.family
);
754 sprintf(ret
, "%s-%s", gpu
, triple
);
756 /* +2 for dash and terminating NIL byte */
757 return (strlen(triple
) + strlen(gpu
) + 2) * sizeof(char);
759 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
761 uint64_t *grid_dimension
= ret
;
762 grid_dimension
[0] = 3;
764 return 1 * sizeof(uint64_t);
766 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
768 uint64_t *grid_size
= ret
;
769 grid_size
[0] = 65535;
770 grid_size
[1] = 65535;
771 grid_size
[2] = 65535;
773 return 3 * sizeof(uint64_t) ;
775 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
777 uint64_t *block_size
= ret
;
778 unsigned threads_per_block
= get_max_threads_per_block(sscreen
, ir_type
);
779 block_size
[0] = threads_per_block
;
780 block_size
[1] = threads_per_block
;
781 block_size
[2] = threads_per_block
;
783 return 3 * sizeof(uint64_t);
785 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
787 uint64_t *max_threads_per_block
= ret
;
788 *max_threads_per_block
= get_max_threads_per_block(sscreen
, ir_type
);
790 return sizeof(uint64_t);
791 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
793 uint32_t *address_bits
= ret
;
794 address_bits
[0] = 64;
796 return 1 * sizeof(uint32_t);
798 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
800 uint64_t *max_global_size
= ret
;
801 uint64_t max_mem_alloc_size
;
803 si_get_compute_param(screen
, ir_type
,
804 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
805 &max_mem_alloc_size
);
807 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
808 * 1/4 of the MAX_GLOBAL_SIZE. Since the
809 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
810 * make sure we never report more than
811 * 4 * MAX_MEM_ALLOC_SIZE.
813 *max_global_size
= MIN2(4 * max_mem_alloc_size
,
814 MAX2(sscreen
->info
.gart_size
,
815 sscreen
->info
.vram_size
));
817 return sizeof(uint64_t);
819 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
821 uint64_t *max_local_size
= ret
;
822 /* Value reported by the closed source driver. */
823 *max_local_size
= 32768;
825 return sizeof(uint64_t);
827 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
829 uint64_t *max_input_size
= ret
;
830 /* Value reported by the closed source driver. */
831 *max_input_size
= 1024;
833 return sizeof(uint64_t);
835 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
837 uint64_t *max_mem_alloc_size
= ret
;
839 *max_mem_alloc_size
= sscreen
->info
.max_alloc_size
;
841 return sizeof(uint64_t);
843 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
845 uint32_t *max_clock_frequency
= ret
;
846 *max_clock_frequency
= sscreen
->info
.max_shader_clock
;
848 return sizeof(uint32_t);
850 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
852 uint32_t *max_compute_units
= ret
;
853 *max_compute_units
= sscreen
->info
.num_good_compute_units
;
855 return sizeof(uint32_t);
857 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
859 uint32_t *images_supported
= ret
;
860 *images_supported
= 0;
862 return sizeof(uint32_t);
863 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
865 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
867 uint32_t *subgroup_size
= ret
;
870 return sizeof(uint32_t);
871 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
873 uint64_t *max_variable_threads_per_block
= ret
;
874 if (ir_type
== PIPE_SHADER_IR_NATIVE
)
875 *max_variable_threads_per_block
= 0;
877 *max_variable_threads_per_block
= SI_MAX_VARIABLE_THREADS_PER_BLOCK
;
879 return sizeof(uint64_t);
882 fprintf(stderr
, "unknown PIPE_COMPUTE_CAP %d\n", param
);
886 static uint64_t si_get_timestamp(struct pipe_screen
*screen
)
888 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
890 return 1000000 * sscreen
->ws
->query_value(sscreen
->ws
, RADEON_TIMESTAMP
) /
891 sscreen
->info
.clock_crystal_freq
;
894 static void si_query_memory_info(struct pipe_screen
*screen
,
895 struct pipe_memory_info
*info
)
897 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
898 struct radeon_winsys
*ws
= sscreen
->ws
;
899 unsigned vram_usage
, gtt_usage
;
901 info
->total_device_memory
= sscreen
->info
.vram_size
/ 1024;
902 info
->total_staging_memory
= sscreen
->info
.gart_size
/ 1024;
904 /* The real TTM memory usage is somewhat random, because:
906 * 1) TTM delays freeing memory, because it can only free it after
909 * 2) The memory usage can be really low if big VRAM evictions are
910 * taking place, but the real usage is well above the size of VRAM.
912 * Instead, return statistics of this process.
914 vram_usage
= ws
->query_value(ws
, RADEON_VRAM_USAGE
) / 1024;
915 gtt_usage
= ws
->query_value(ws
, RADEON_GTT_USAGE
) / 1024;
917 info
->avail_device_memory
=
918 vram_usage
<= info
->total_device_memory
?
919 info
->total_device_memory
- vram_usage
: 0;
920 info
->avail_staging_memory
=
921 gtt_usage
<= info
->total_staging_memory
?
922 info
->total_staging_memory
- gtt_usage
: 0;
924 info
->device_memory_evicted
=
925 ws
->query_value(ws
, RADEON_NUM_BYTES_MOVED
) / 1024;
927 if (sscreen
->info
.is_amdgpu
&& sscreen
->info
.drm_minor
>= 4)
928 info
->nr_device_memory_evictions
=
929 ws
->query_value(ws
, RADEON_NUM_EVICTIONS
);
931 /* Just return the number of evicted 64KB pages. */
932 info
->nr_device_memory_evictions
= info
->device_memory_evicted
/ 64;
935 static struct disk_cache
*si_get_disk_shader_cache(struct pipe_screen
*pscreen
)
937 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
939 return sscreen
->disk_shader_cache
;
942 static void si_init_renderer_string(struct si_screen
*sscreen
)
944 char first_name
[256], second_name
[32] = {}, kernel_version
[128] = {};
945 struct utsname uname_data
;
947 if (sscreen
->info
.marketing_name
) {
948 snprintf(first_name
, sizeof(first_name
), "%s",
949 sscreen
->info
.marketing_name
);
950 snprintf(second_name
, sizeof(second_name
), "%s, ",
953 snprintf(first_name
, sizeof(first_name
), "AMD %s",
957 if (uname(&uname_data
) == 0)
958 snprintf(kernel_version
, sizeof(kernel_version
),
959 ", %s", uname_data
.release
);
961 snprintf(sscreen
->renderer_string
, sizeof(sscreen
->renderer_string
),
962 "%s (%sDRM %i.%i.%i%s, LLVM " MESA_LLVM_VERSION_STRING
")",
963 first_name
, second_name
, sscreen
->info
.drm_major
,
964 sscreen
->info
.drm_minor
, sscreen
->info
.drm_patchlevel
,
968 void si_init_screen_get_functions(struct si_screen
*sscreen
)
970 sscreen
->b
.get_name
= si_get_name
;
971 sscreen
->b
.get_vendor
= si_get_vendor
;
972 sscreen
->b
.get_device_vendor
= si_get_device_vendor
;
973 sscreen
->b
.get_param
= si_get_param
;
974 sscreen
->b
.get_paramf
= si_get_paramf
;
975 sscreen
->b
.get_compute_param
= si_get_compute_param
;
976 sscreen
->b
.get_timestamp
= si_get_timestamp
;
977 sscreen
->b
.get_shader_param
= si_get_shader_param
;
978 sscreen
->b
.get_compiler_options
= si_get_compiler_options
;
979 sscreen
->b
.get_device_uuid
= si_get_device_uuid
;
980 sscreen
->b
.get_driver_uuid
= si_get_driver_uuid
;
981 sscreen
->b
.query_memory_info
= si_query_memory_info
;
982 sscreen
->b
.get_disk_shader_cache
= si_get_disk_shader_cache
;
984 if (sscreen
->info
.has_hw_decode
) {
985 sscreen
->b
.get_video_param
= si_get_video_param
;
986 sscreen
->b
.is_video_format_supported
= si_vid_is_format_supported
;
988 sscreen
->b
.get_video_param
= si_get_video_param_no_decode
;
989 sscreen
->b
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
992 si_init_renderer_string(sscreen
);