2 * Copyright 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "radeon/radeon_video.h"
27 #include "radeon/radeon_vce.h"
28 #include "radeon/radeon_uvd_enc.h"
29 #include "ac_llvm_util.h"
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32 #include "util/u_video.h"
33 #include "compiler/nir/nir.h"
35 #include <sys/utsname.h>
37 static const char *si_get_vendor(struct pipe_screen
*pscreen
)
39 /* Don't change this. Games such as Alien Isolation are broken if this
40 * returns "Advanced Micro Devices, Inc."
45 static const char *si_get_device_vendor(struct pipe_screen
*pscreen
)
50 static const char *si_get_marketing_name(struct radeon_winsys
*ws
)
52 if (!ws
->get_chip_name
)
54 return ws
->get_chip_name(ws
);
57 const char *si_get_family_name(const struct si_screen
*sscreen
)
59 switch (sscreen
->info
.family
) {
60 case CHIP_TAHITI
: return "AMD TAHITI";
61 case CHIP_PITCAIRN
: return "AMD PITCAIRN";
62 case CHIP_VERDE
: return "AMD CAPE VERDE";
63 case CHIP_OLAND
: return "AMD OLAND";
64 case CHIP_HAINAN
: return "AMD HAINAN";
65 case CHIP_BONAIRE
: return "AMD BONAIRE";
66 case CHIP_KAVERI
: return "AMD KAVERI";
67 case CHIP_KABINI
: return "AMD KABINI";
68 case CHIP_HAWAII
: return "AMD HAWAII";
69 case CHIP_MULLINS
: return "AMD MULLINS";
70 case CHIP_TONGA
: return "AMD TONGA";
71 case CHIP_ICELAND
: return "AMD ICELAND";
72 case CHIP_CARRIZO
: return "AMD CARRIZO";
73 case CHIP_FIJI
: return "AMD FIJI";
74 case CHIP_STONEY
: return "AMD STONEY";
75 case CHIP_POLARIS10
: return "AMD POLARIS10";
76 case CHIP_POLARIS11
: return "AMD POLARIS11";
77 case CHIP_POLARIS12
: return "AMD POLARIS12";
78 case CHIP_VEGAM
: return "AMD VEGAM";
79 case CHIP_VEGA10
: return "AMD VEGA10";
80 case CHIP_VEGA12
: return "AMD VEGA12";
81 case CHIP_RAVEN
: return "AMD RAVEN";
82 default: return "AMD unknown";
86 static bool si_have_tgsi_compute(struct si_screen
*sscreen
)
88 /* Old kernels disallowed some register writes for SI
89 * that are used for indirect dispatches. */
90 return (sscreen
->info
.chip_class
>= CIK
||
91 sscreen
->info
.drm_major
== 3 ||
92 (sscreen
->info
.drm_major
== 2 &&
93 sscreen
->info
.drm_minor
>= 45));
96 static int si_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
98 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
101 /* Supported features (boolean caps). */
102 case PIPE_CAP_ACCELERATED
:
103 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
104 case PIPE_CAP_ANISOTROPIC_FILTER
:
105 case PIPE_CAP_POINT_SPRITE
:
106 case PIPE_CAP_OCCLUSION_QUERY
:
107 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
108 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
109 case PIPE_CAP_TEXTURE_SWIZZLE
:
110 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
111 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
112 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
113 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
114 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
115 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
116 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
118 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
119 case PIPE_CAP_PRIMITIVE_RESTART
:
120 case PIPE_CAP_CONDITIONAL_RENDER
:
121 case PIPE_CAP_TEXTURE_BARRIER
:
122 case PIPE_CAP_INDEP_BLEND_ENABLE
:
123 case PIPE_CAP_INDEP_BLEND_FUNC
:
124 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
125 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
126 case PIPE_CAP_START_INSTANCE
:
127 case PIPE_CAP_NPOT_TEXTURES
:
128 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
129 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
130 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
131 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
132 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
133 case PIPE_CAP_TGSI_INSTANCEID
:
134 case PIPE_CAP_COMPUTE
:
135 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
136 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
137 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
138 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
139 case PIPE_CAP_CUBE_MAP_ARRAY
:
140 case PIPE_CAP_SAMPLE_SHADING
:
141 case PIPE_CAP_DRAW_INDIRECT
:
142 case PIPE_CAP_CLIP_HALFZ
:
143 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
144 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
145 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
146 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
147 case PIPE_CAP_TGSI_TEXCOORD
:
148 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
149 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
150 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
151 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
152 case PIPE_CAP_SHAREABLE_SHADERS
:
153 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
154 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
155 case PIPE_CAP_TEXTURE_QUERY_LOD
:
156 case PIPE_CAP_TEXTURE_GATHER_SM5
:
157 case PIPE_CAP_TGSI_TXQS
:
158 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
159 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
160 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
161 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
162 case PIPE_CAP_INVALIDATE_BUFFER
:
163 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
164 case PIPE_CAP_QUERY_MEMORY_INFO
:
165 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
166 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
167 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
168 case PIPE_CAP_GENERATE_MIPMAP
:
169 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
170 case PIPE_CAP_STRING_MARKER
:
171 case PIPE_CAP_CLEAR_TEXTURE
:
172 case PIPE_CAP_CULL_DISTANCE
:
173 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
174 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
175 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
176 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
177 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
178 case PIPE_CAP_DOUBLES
:
179 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
180 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
181 case PIPE_CAP_BINDLESS_TEXTURE
:
182 case PIPE_CAP_QUERY_TIMESTAMP
:
183 case PIPE_CAP_QUERY_TIME_ELAPSED
:
184 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
185 case PIPE_CAP_QUERY_SO_OVERFLOW
:
186 case PIPE_CAP_MEMOBJ
:
187 case PIPE_CAP_LOAD_CONSTBUF
:
189 case PIPE_CAP_INT64_DIVMOD
:
190 case PIPE_CAP_TGSI_CLOCK
:
191 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
192 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
193 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
:
194 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
195 case PIPE_CAP_TGSI_VOTE
:
196 case PIPE_CAP_TGSI_FS_FBFETCH
:
199 case PIPE_CAP_TGSI_BALLOT
:
200 return HAVE_LLVM
>= 0x0500;
202 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
203 return !SI_BIG_ENDIAN
&& sscreen
->info
.has_userptr
;
205 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
206 return sscreen
->info
.has_gpu_reset_status_query
||
207 sscreen
->info
.has_gpu_reset_counter_query
;
209 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
210 /* 2D tiling on CIK is supported since DRM 2.35.0 */
211 return sscreen
->info
.chip_class
< CIK
||
212 (sscreen
->info
.drm_major
== 2 &&
213 sscreen
->info
.drm_minor
>= 35) ||
214 sscreen
->info
.drm_major
== 3;
216 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
217 return SI_MAP_BUFFER_ALIGNMENT
;
219 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
220 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
221 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
222 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
223 case PIPE_CAP_MAX_VERTEX_STREAMS
:
224 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
227 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
228 if (si_have_tgsi_compute(sscreen
))
232 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
233 return MIN2(sscreen
->info
.max_alloc_size
, INT_MAX
);
235 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
236 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
237 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
238 /* SI doesn't support unaligned loads.
239 * CIK needs DRM 2.50.0 on radeon. */
240 return sscreen
->info
.chip_class
== SI
||
241 (sscreen
->info
.drm_major
== 2 &&
242 sscreen
->info
.drm_minor
< 50);
244 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
245 /* TODO: GFX9 hangs. */
246 if (sscreen
->info
.chip_class
>= GFX9
)
248 /* Disable on SI due to VM faults in CP DMA. Enable once these
249 * faults are mitigated in software.
251 if (sscreen
->info
.chip_class
>= CIK
&&
252 sscreen
->info
.drm_major
== 3 &&
253 sscreen
->info
.drm_minor
>= 13)
254 return RADEON_SPARSE_PAGE_SIZE
;
257 case PIPE_CAP_PACKED_UNIFORMS
:
258 if (sscreen
->debug_flags
& DBG(NIR
))
262 /* Unsupported features. */
263 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
264 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
265 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
266 case PIPE_CAP_USER_VERTEX_BUFFERS
:
267 case PIPE_CAP_FAKE_SW_MSAA
:
268 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
269 case PIPE_CAP_VERTEXID_NOBASE
:
270 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
271 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
272 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
274 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
275 case PIPE_CAP_POST_DEPTH_COVERAGE
:
276 case PIPE_CAP_TILE_RASTER_ORDER
:
277 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES
:
278 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
279 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES
:
280 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES
:
281 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES
:
282 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES
:
283 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE
:
284 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS
:
287 case PIPE_CAP_FENCE_SIGNAL
:
288 return sscreen
->info
.has_syncobj
;
290 case PIPE_CAP_CONSTBUF0_FLAGS
:
291 return SI_RESOURCE_FLAG_32BIT
;
293 case PIPE_CAP_NATIVE_FENCE_FD
:
294 return sscreen
->info
.has_fence_to_handle
;
296 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
297 return si_have_tgsi_compute(sscreen
);
299 case PIPE_CAP_DRAW_PARAMETERS
:
300 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
301 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
302 return sscreen
->has_draw_indirect_multi
;
304 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
307 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
308 return sscreen
->info
.chip_class
<= VI
?
309 PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600
: 0;
312 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
313 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
316 /* Geometry shader output. */
317 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
319 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
322 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
326 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
327 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
328 return 15; /* 16384 */
329 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
330 /* textures support 8192, but layered rendering supports 2048 */
332 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
333 /* textures support 8192, but layered rendering supports 2048 */
336 /* Viewports and render targets. */
337 case PIPE_CAP_MAX_VIEWPORTS
:
338 return SI_MAX_VIEWPORTS
;
339 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
340 case PIPE_CAP_MAX_RENDER_TARGETS
:
343 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
344 case PIPE_CAP_MIN_TEXEL_OFFSET
:
347 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
348 case PIPE_CAP_MAX_TEXEL_OFFSET
:
351 case PIPE_CAP_ENDIANNESS
:
352 return PIPE_ENDIAN_LITTLE
;
354 case PIPE_CAP_VENDOR_ID
:
355 return ATI_VENDOR_ID
;
356 case PIPE_CAP_DEVICE_ID
:
357 return sscreen
->info
.pci_id
;
358 case PIPE_CAP_VIDEO_MEMORY
:
359 return sscreen
->info
.vram_size
>> 20;
360 case PIPE_CAP_PCI_GROUP
:
361 return sscreen
->info
.pci_domain
;
362 case PIPE_CAP_PCI_BUS
:
363 return sscreen
->info
.pci_bus
;
364 case PIPE_CAP_PCI_DEVICE
:
365 return sscreen
->info
.pci_dev
;
366 case PIPE_CAP_PCI_FUNCTION
:
367 return sscreen
->info
.pci_func
;
372 static float si_get_paramf(struct pipe_screen
* pscreen
, enum pipe_capf param
)
375 case PIPE_CAPF_MAX_LINE_WIDTH
:
376 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
377 case PIPE_CAPF_MAX_POINT_WIDTH
:
378 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
380 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
382 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
384 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
385 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
386 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
392 static int si_get_shader_param(struct pipe_screen
* pscreen
,
393 enum pipe_shader_type shader
,
394 enum pipe_shader_cap param
)
396 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
400 case PIPE_SHADER_FRAGMENT
:
401 case PIPE_SHADER_VERTEX
:
402 case PIPE_SHADER_GEOMETRY
:
403 case PIPE_SHADER_TESS_CTRL
:
404 case PIPE_SHADER_TESS_EVAL
:
406 case PIPE_SHADER_COMPUTE
:
408 case PIPE_SHADER_CAP_SUPPORTED_IRS
: {
409 int ir
= 1 << PIPE_SHADER_IR_NATIVE
;
411 if (si_have_tgsi_compute(sscreen
))
412 ir
|= 1 << PIPE_SHADER_IR_TGSI
;
417 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
: {
418 uint64_t max_const_buffer_size
;
419 pscreen
->get_compute_param(pscreen
, PIPE_SHADER_IR_TGSI
,
420 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
421 &max_const_buffer_size
);
422 return MIN2(max_const_buffer_size
, INT_MAX
);
425 /* If compute shaders don't require a special value
426 * for this cap, we can return the same value we
427 * do for other shader types. */
437 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
438 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
439 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
440 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
441 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
443 case PIPE_SHADER_CAP_MAX_INPUTS
:
444 return shader
== PIPE_SHADER_VERTEX
? SI_MAX_ATTRIBS
: 32;
445 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
446 return shader
== PIPE_SHADER_FRAGMENT
? 8 : 32;
447 case PIPE_SHADER_CAP_MAX_TEMPS
:
448 return 256; /* Max native temporaries. */
449 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
450 return 4096 * sizeof(float[4]); /* actually only memory limits this */
451 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
452 return SI_NUM_CONST_BUFFERS
;
453 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
454 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
455 return SI_NUM_SAMPLERS
;
456 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
457 return SI_NUM_SHADER_BUFFERS
;
458 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
459 return SI_NUM_IMAGES
;
460 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
461 if (sscreen
->debug_flags
& DBG(NIR
))
464 case PIPE_SHADER_CAP_PREFERRED_IR
:
465 if (sscreen
->debug_flags
& DBG(NIR
))
466 return PIPE_SHADER_IR_NIR
;
467 return PIPE_SHADER_IR_TGSI
;
468 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
471 /* Supported boolean features. */
472 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
473 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
474 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
475 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
476 case PIPE_SHADER_CAP_INTEGERS
:
477 case PIPE_SHADER_CAP_INT64_ATOMICS
:
478 case PIPE_SHADER_CAP_FP16
:
479 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
480 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
481 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
482 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
483 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
484 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
487 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
488 /* TODO: Indirect indexing of GS inputs is unimplemented. */
489 if (shader
== PIPE_SHADER_GEOMETRY
)
492 if (shader
== PIPE_SHADER_VERTEX
&&
493 !sscreen
->llvm_has_working_vgpr_indexing
)
496 /* Doing indirect indexing on GFX9 with LLVM 6.0 hangs.
497 * This means we don't support INTERP instructions with
498 * indirect indexing on inputs.
500 if (shader
== PIPE_SHADER_FRAGMENT
&&
501 !sscreen
->llvm_has_working_vgpr_indexing
&&
505 /* TCS and TES load inputs directly from LDS or offchip
506 * memory, so indirect indexing is always supported.
507 * PS has to support indirect indexing, because we can't
508 * lower that to TEMPs for INTERP instructions.
512 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
513 return sscreen
->llvm_has_working_vgpr_indexing
||
514 /* TCS stores outputs directly to memory. */
515 shader
== PIPE_SHADER_TESS_CTRL
;
517 /* Unsupported boolean features. */
518 case PIPE_SHADER_CAP_SUBROUTINES
:
519 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
520 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
521 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
527 static const struct nir_shader_compiler_options nir_options
= {
529 .lower_flrp32
= true,
530 .lower_flrp64
= true,
536 .lower_pack_snorm_2x16
= true,
537 .lower_pack_snorm_4x8
= true,
538 .lower_pack_unorm_2x16
= true,
539 .lower_pack_unorm_4x8
= true,
540 .lower_unpack_snorm_2x16
= true,
541 .lower_unpack_snorm_4x8
= true,
542 .lower_unpack_unorm_2x16
= true,
543 .lower_unpack_unorm_4x8
= true,
544 .lower_extract_byte
= true,
545 .lower_extract_word
= true,
546 .max_unroll_iterations
= 32,
547 .native_integers
= true,
551 si_get_compiler_options(struct pipe_screen
*screen
,
552 enum pipe_shader_ir ir
,
553 enum pipe_shader_type shader
)
555 assert(ir
== PIPE_SHADER_IR_NIR
);
559 static void si_get_driver_uuid(struct pipe_screen
*pscreen
, char *uuid
)
561 ac_compute_driver_uuid(uuid
, PIPE_UUID_SIZE
);
564 static void si_get_device_uuid(struct pipe_screen
*pscreen
, char *uuid
)
566 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
568 ac_compute_device_uuid(&sscreen
->info
, uuid
, PIPE_UUID_SIZE
);
571 static const char* si_get_name(struct pipe_screen
*pscreen
)
573 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
575 return sscreen
->renderer_string
;
578 static int si_get_video_param_no_decode(struct pipe_screen
*screen
,
579 enum pipe_video_profile profile
,
580 enum pipe_video_entrypoint entrypoint
,
581 enum pipe_video_cap param
)
584 case PIPE_VIDEO_CAP_SUPPORTED
:
585 return vl_profile_supported(screen
, profile
, entrypoint
);
586 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
588 case PIPE_VIDEO_CAP_MAX_WIDTH
:
589 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
590 return vl_video_buffer_max_size(screen
);
591 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
592 return PIPE_FORMAT_NV12
;
593 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
595 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
597 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
599 case PIPE_VIDEO_CAP_MAX_LEVEL
:
600 return vl_level_supported(screen
, profile
);
606 static int si_get_video_param(struct pipe_screen
*screen
,
607 enum pipe_video_profile profile
,
608 enum pipe_video_entrypoint entrypoint
,
609 enum pipe_video_cap param
)
611 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
612 enum pipe_video_format codec
= u_reduce_video_profile(profile
);
614 if (entrypoint
== PIPE_VIDEO_ENTRYPOINT_ENCODE
) {
616 case PIPE_VIDEO_CAP_SUPPORTED
:
617 return (codec
== PIPE_VIDEO_FORMAT_MPEG4_AVC
&&
618 (si_vce_is_fw_version_supported(sscreen
) ||
619 sscreen
->info
.family
== CHIP_RAVEN
)) ||
620 (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
&&
621 (sscreen
->info
.family
== CHIP_RAVEN
||
622 si_radeon_uvd_enc_supported(sscreen
)));
623 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
625 case PIPE_VIDEO_CAP_MAX_WIDTH
:
626 return (sscreen
->info
.family
< CHIP_TONGA
) ? 2048 : 4096;
627 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
628 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1152 : 2304;
629 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
630 return PIPE_FORMAT_NV12
;
631 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
633 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
635 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
637 case PIPE_VIDEO_CAP_STACKED_FRAMES
:
638 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1 : 2;
645 case PIPE_VIDEO_CAP_SUPPORTED
:
647 case PIPE_VIDEO_FORMAT_MPEG12
:
648 return profile
!= PIPE_VIDEO_PROFILE_MPEG1
;
649 case PIPE_VIDEO_FORMAT_MPEG4
:
651 case PIPE_VIDEO_FORMAT_MPEG4_AVC
:
652 if ((sscreen
->info
.family
== CHIP_POLARIS10
||
653 sscreen
->info
.family
== CHIP_POLARIS11
) &&
654 sscreen
->info
.uvd_fw_version
< UVD_FW_1_66_16
) {
655 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
659 case PIPE_VIDEO_FORMAT_VC1
:
661 case PIPE_VIDEO_FORMAT_HEVC
:
662 /* Carrizo only supports HEVC Main */
663 if (sscreen
->info
.family
>= CHIP_STONEY
)
664 return (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
||
665 profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
);
666 else if (sscreen
->info
.family
>= CHIP_CARRIZO
)
667 return profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
;
669 case PIPE_VIDEO_FORMAT_JPEG
:
670 if (sscreen
->info
.family
< CHIP_CARRIZO
|| sscreen
->info
.family
>= CHIP_VEGA10
)
672 if (!(sscreen
->info
.drm_major
== 3 && sscreen
->info
.drm_minor
>= 19)) {
673 RVID_ERR("No MJPEG support for the kernel version\n");
677 case PIPE_VIDEO_FORMAT_VP9
:
678 if (sscreen
->info
.family
< CHIP_RAVEN
)
684 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
686 case PIPE_VIDEO_CAP_MAX_WIDTH
:
687 return (sscreen
->info
.family
< CHIP_TONGA
) ? 2048 : 4096;
688 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
689 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1152 : 4096;
690 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
691 if (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
||
692 profile
== PIPE_VIDEO_PROFILE_VP9_PROFILE2
)
693 return PIPE_FORMAT_P016
;
695 return PIPE_FORMAT_NV12
;
697 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
698 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
: {
699 enum pipe_video_format format
= u_reduce_video_profile(profile
);
701 if (format
== PIPE_VIDEO_FORMAT_HEVC
)
702 return false; //The firmware doesn't support interlaced HEVC.
703 else if (format
== PIPE_VIDEO_FORMAT_JPEG
)
705 else if (format
== PIPE_VIDEO_FORMAT_VP9
)
709 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
711 case PIPE_VIDEO_CAP_MAX_LEVEL
:
713 case PIPE_VIDEO_PROFILE_MPEG1
:
715 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE
:
716 case PIPE_VIDEO_PROFILE_MPEG2_MAIN
:
718 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE
:
720 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE
:
722 case PIPE_VIDEO_PROFILE_VC1_SIMPLE
:
724 case PIPE_VIDEO_PROFILE_VC1_MAIN
:
726 case PIPE_VIDEO_PROFILE_VC1_ADVANCED
:
728 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE
:
729 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN
:
730 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH
:
731 return (sscreen
->info
.family
< CHIP_TONGA
) ? 41 : 52;
732 case PIPE_VIDEO_PROFILE_HEVC_MAIN
:
733 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10
:
743 static boolean
si_vid_is_format_supported(struct pipe_screen
*screen
,
744 enum pipe_format format
,
745 enum pipe_video_profile profile
,
746 enum pipe_video_entrypoint entrypoint
)
748 /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
749 if (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
)
750 return (format
== PIPE_FORMAT_NV12
) ||
751 (format
== PIPE_FORMAT_P016
);
753 /* we can only handle this one with UVD */
754 if (profile
!= PIPE_VIDEO_PROFILE_UNKNOWN
)
755 return format
== PIPE_FORMAT_NV12
;
757 return vl_video_buffer_is_format_supported(screen
, format
, profile
, entrypoint
);
760 static unsigned get_max_threads_per_block(struct si_screen
*screen
,
761 enum pipe_shader_ir ir_type
)
763 if (ir_type
== PIPE_SHADER_IR_NATIVE
)
766 /* Only 16 waves per thread-group on gfx9. */
767 if (screen
->info
.chip_class
>= GFX9
)
770 /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
776 static int si_get_compute_param(struct pipe_screen
*screen
,
777 enum pipe_shader_ir ir_type
,
778 enum pipe_compute_cap param
,
781 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
783 //TODO: select these params by asic
785 case PIPE_COMPUTE_CAP_IR_TARGET
: {
786 const char *gpu
, *triple
;
788 triple
= "amdgcn-mesa-mesa3d";
789 gpu
= ac_get_llvm_processor_name(sscreen
->info
.family
);
791 sprintf(ret
, "%s-%s", gpu
, triple
);
793 /* +2 for dash and terminating NIL byte */
794 return (strlen(triple
) + strlen(gpu
) + 2) * sizeof(char);
796 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
798 uint64_t *grid_dimension
= ret
;
799 grid_dimension
[0] = 3;
801 return 1 * sizeof(uint64_t);
803 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
805 uint64_t *grid_size
= ret
;
806 grid_size
[0] = 65535;
807 grid_size
[1] = 65535;
808 grid_size
[2] = 65535;
810 return 3 * sizeof(uint64_t) ;
812 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
814 uint64_t *block_size
= ret
;
815 unsigned threads_per_block
= get_max_threads_per_block(sscreen
, ir_type
);
816 block_size
[0] = threads_per_block
;
817 block_size
[1] = threads_per_block
;
818 block_size
[2] = threads_per_block
;
820 return 3 * sizeof(uint64_t);
822 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
824 uint64_t *max_threads_per_block
= ret
;
825 *max_threads_per_block
= get_max_threads_per_block(sscreen
, ir_type
);
827 return sizeof(uint64_t);
828 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
830 uint32_t *address_bits
= ret
;
831 address_bits
[0] = 64;
833 return 1 * sizeof(uint32_t);
835 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
837 uint64_t *max_global_size
= ret
;
838 uint64_t max_mem_alloc_size
;
840 si_get_compute_param(screen
, ir_type
,
841 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
842 &max_mem_alloc_size
);
844 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
845 * 1/4 of the MAX_GLOBAL_SIZE. Since the
846 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
847 * make sure we never report more than
848 * 4 * MAX_MEM_ALLOC_SIZE.
850 *max_global_size
= MIN2(4 * max_mem_alloc_size
,
851 MAX2(sscreen
->info
.gart_size
,
852 sscreen
->info
.vram_size
));
854 return sizeof(uint64_t);
856 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
858 uint64_t *max_local_size
= ret
;
859 /* Value reported by the closed source driver. */
860 *max_local_size
= 32768;
862 return sizeof(uint64_t);
864 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
866 uint64_t *max_input_size
= ret
;
867 /* Value reported by the closed source driver. */
868 *max_input_size
= 1024;
870 return sizeof(uint64_t);
872 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
874 uint64_t *max_mem_alloc_size
= ret
;
876 *max_mem_alloc_size
= sscreen
->info
.max_alloc_size
;
878 return sizeof(uint64_t);
880 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
882 uint32_t *max_clock_frequency
= ret
;
883 *max_clock_frequency
= sscreen
->info
.max_shader_clock
;
885 return sizeof(uint32_t);
887 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
889 uint32_t *max_compute_units
= ret
;
890 *max_compute_units
= sscreen
->info
.num_good_compute_units
;
892 return sizeof(uint32_t);
894 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
896 uint32_t *images_supported
= ret
;
897 *images_supported
= 0;
899 return sizeof(uint32_t);
900 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
902 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
904 uint32_t *subgroup_size
= ret
;
907 return sizeof(uint32_t);
908 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
910 uint64_t *max_variable_threads_per_block
= ret
;
911 if (ir_type
== PIPE_SHADER_IR_NATIVE
)
912 *max_variable_threads_per_block
= 0;
914 *max_variable_threads_per_block
= SI_MAX_VARIABLE_THREADS_PER_BLOCK
;
916 return sizeof(uint64_t);
919 fprintf(stderr
, "unknown PIPE_COMPUTE_CAP %d\n", param
);
923 static uint64_t si_get_timestamp(struct pipe_screen
*screen
)
925 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
927 return 1000000 * sscreen
->ws
->query_value(sscreen
->ws
, RADEON_TIMESTAMP
) /
928 sscreen
->info
.clock_crystal_freq
;
931 static void si_query_memory_info(struct pipe_screen
*screen
,
932 struct pipe_memory_info
*info
)
934 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
935 struct radeon_winsys
*ws
= sscreen
->ws
;
936 unsigned vram_usage
, gtt_usage
;
938 info
->total_device_memory
= sscreen
->info
.vram_size
/ 1024;
939 info
->total_staging_memory
= sscreen
->info
.gart_size
/ 1024;
941 /* The real TTM memory usage is somewhat random, because:
943 * 1) TTM delays freeing memory, because it can only free it after
946 * 2) The memory usage can be really low if big VRAM evictions are
947 * taking place, but the real usage is well above the size of VRAM.
949 * Instead, return statistics of this process.
951 vram_usage
= ws
->query_value(ws
, RADEON_REQUESTED_VRAM_MEMORY
) / 1024;
952 gtt_usage
= ws
->query_value(ws
, RADEON_REQUESTED_GTT_MEMORY
) / 1024;
954 info
->avail_device_memory
=
955 vram_usage
<= info
->total_device_memory
?
956 info
->total_device_memory
- vram_usage
: 0;
957 info
->avail_staging_memory
=
958 gtt_usage
<= info
->total_staging_memory
?
959 info
->total_staging_memory
- gtt_usage
: 0;
961 info
->device_memory_evicted
=
962 ws
->query_value(ws
, RADEON_NUM_BYTES_MOVED
) / 1024;
964 if (sscreen
->info
.drm_major
== 3 && sscreen
->info
.drm_minor
>= 4)
965 info
->nr_device_memory_evictions
=
966 ws
->query_value(ws
, RADEON_NUM_EVICTIONS
);
968 /* Just return the number of evicted 64KB pages. */
969 info
->nr_device_memory_evictions
= info
->device_memory_evicted
/ 64;
972 static struct disk_cache
*si_get_disk_shader_cache(struct pipe_screen
*pscreen
)
974 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
976 return sscreen
->disk_shader_cache
;
979 static void si_init_renderer_string(struct si_screen
*sscreen
)
981 struct radeon_winsys
*ws
= sscreen
->ws
;
982 char family_name
[32] = {}, kernel_version
[128] = {};
983 struct utsname uname_data
;
985 const char *chip_name
= si_get_marketing_name(ws
);
988 snprintf(family_name
, sizeof(family_name
), "%s, ",
989 si_get_family_name(sscreen
) + 4);
991 chip_name
= si_get_family_name(sscreen
);
993 if (uname(&uname_data
) == 0)
994 snprintf(kernel_version
, sizeof(kernel_version
),
995 ", %s", uname_data
.release
);
997 snprintf(sscreen
->renderer_string
, sizeof(sscreen
->renderer_string
),
998 "%s (%sDRM %i.%i.%i%s, LLVM %i.%i.%i)",
999 chip_name
, family_name
, sscreen
->info
.drm_major
,
1000 sscreen
->info
.drm_minor
, sscreen
->info
.drm_patchlevel
,
1002 (HAVE_LLVM
>> 8) & 0xff,
1004 MESA_LLVM_VERSION_PATCH
);
1007 void si_init_screen_get_functions(struct si_screen
*sscreen
)
1009 sscreen
->b
.get_name
= si_get_name
;
1010 sscreen
->b
.get_vendor
= si_get_vendor
;
1011 sscreen
->b
.get_device_vendor
= si_get_device_vendor
;
1012 sscreen
->b
.get_param
= si_get_param
;
1013 sscreen
->b
.get_paramf
= si_get_paramf
;
1014 sscreen
->b
.get_compute_param
= si_get_compute_param
;
1015 sscreen
->b
.get_timestamp
= si_get_timestamp
;
1016 sscreen
->b
.get_shader_param
= si_get_shader_param
;
1017 sscreen
->b
.get_compiler_options
= si_get_compiler_options
;
1018 sscreen
->b
.get_device_uuid
= si_get_device_uuid
;
1019 sscreen
->b
.get_driver_uuid
= si_get_driver_uuid
;
1020 sscreen
->b
.query_memory_info
= si_query_memory_info
;
1021 sscreen
->b
.get_disk_shader_cache
= si_get_disk_shader_cache
;
1023 if (sscreen
->info
.has_hw_decode
) {
1024 sscreen
->b
.get_video_param
= si_get_video_param
;
1025 sscreen
->b
.is_video_format_supported
= si_vid_is_format_supported
;
1027 sscreen
->b
.get_video_param
= si_get_video_param_no_decode
;
1028 sscreen
->b
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
1031 si_init_renderer_string(sscreen
);