2 * Copyright 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "radeon/radeon_video.h"
26 #include "radeon/radeon_vce.h"
27 #include "radeon/radeon_uvd_enc.h"
28 #include "ac_llvm_util.h"
29 #include "vl/vl_decoder.h"
30 #include "vl/vl_video_buffer.h"
31 #include "util/u_video.h"
32 #include "compiler/nir/nir.h"
34 #include <sys/utsname.h>
36 static const char *si_get_vendor(struct pipe_screen
*pscreen
)
38 /* Don't change this. Games such as Alien Isolation are broken if this
39 * returns "Advanced Micro Devices, Inc."
44 static const char *si_get_device_vendor(struct pipe_screen
*pscreen
)
49 static const char *si_get_marketing_name(struct radeon_winsys
*ws
)
51 if (!ws
->get_chip_name
)
53 return ws
->get_chip_name(ws
);
56 const char *si_get_family_name(const struct si_screen
*sscreen
)
58 switch (sscreen
->info
.family
) {
59 case CHIP_TAHITI
: return "AMD TAHITI";
60 case CHIP_PITCAIRN
: return "AMD PITCAIRN";
61 case CHIP_VERDE
: return "AMD CAPE VERDE";
62 case CHIP_OLAND
: return "AMD OLAND";
63 case CHIP_HAINAN
: return "AMD HAINAN";
64 case CHIP_BONAIRE
: return "AMD BONAIRE";
65 case CHIP_KAVERI
: return "AMD KAVERI";
66 case CHIP_KABINI
: return "AMD KABINI";
67 case CHIP_HAWAII
: return "AMD HAWAII";
68 case CHIP_MULLINS
: return "AMD MULLINS";
69 case CHIP_TONGA
: return "AMD TONGA";
70 case CHIP_ICELAND
: return "AMD ICELAND";
71 case CHIP_CARRIZO
: return "AMD CARRIZO";
72 case CHIP_FIJI
: return "AMD FIJI";
73 case CHIP_POLARIS10
: return "AMD POLARIS10";
74 case CHIP_POLARIS11
: return "AMD POLARIS11";
75 case CHIP_POLARIS12
: return "AMD POLARIS12";
76 case CHIP_STONEY
: return "AMD STONEY";
77 case CHIP_VEGA10
: return "AMD VEGA10";
78 case CHIP_VEGA12
: return "AMD VEGA12";
79 case CHIP_RAVEN
: return "AMD RAVEN";
80 default: return "AMD unknown";
84 static bool si_have_tgsi_compute(struct si_screen
*sscreen
)
86 /* Old kernels disallowed some register writes for SI
87 * that are used for indirect dispatches. */
88 return (sscreen
->info
.chip_class
>= CIK
||
89 sscreen
->info
.drm_major
== 3 ||
90 (sscreen
->info
.drm_major
== 2 &&
91 sscreen
->info
.drm_minor
>= 45));
94 static int si_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
96 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
99 /* Supported features (boolean caps). */
100 case PIPE_CAP_ACCELERATED
:
101 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
102 case PIPE_CAP_ANISOTROPIC_FILTER
:
103 case PIPE_CAP_POINT_SPRITE
:
104 case PIPE_CAP_OCCLUSION_QUERY
:
105 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
106 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
107 case PIPE_CAP_TEXTURE_SWIZZLE
:
108 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
109 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
110 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
111 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
112 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
113 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
114 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
116 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
117 case PIPE_CAP_PRIMITIVE_RESTART
:
118 case PIPE_CAP_CONDITIONAL_RENDER
:
119 case PIPE_CAP_TEXTURE_BARRIER
:
120 case PIPE_CAP_INDEP_BLEND_ENABLE
:
121 case PIPE_CAP_INDEP_BLEND_FUNC
:
122 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
123 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
124 case PIPE_CAP_START_INSTANCE
:
125 case PIPE_CAP_NPOT_TEXTURES
:
126 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
127 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
128 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
129 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
130 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
131 case PIPE_CAP_TGSI_INSTANCEID
:
132 case PIPE_CAP_COMPUTE
:
133 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
134 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
135 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
136 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
137 case PIPE_CAP_CUBE_MAP_ARRAY
:
138 case PIPE_CAP_SAMPLE_SHADING
:
139 case PIPE_CAP_DRAW_INDIRECT
:
140 case PIPE_CAP_CLIP_HALFZ
:
141 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
142 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
143 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
144 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
145 case PIPE_CAP_TGSI_TEXCOORD
:
146 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
147 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
148 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
149 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
150 case PIPE_CAP_SHAREABLE_SHADERS
:
151 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
152 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
153 case PIPE_CAP_TEXTURE_QUERY_LOD
:
154 case PIPE_CAP_TEXTURE_GATHER_SM5
:
155 case PIPE_CAP_TGSI_TXQS
:
156 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
157 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
158 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
159 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
160 case PIPE_CAP_INVALIDATE_BUFFER
:
161 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
162 case PIPE_CAP_QUERY_MEMORY_INFO
:
163 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
164 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
165 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
166 case PIPE_CAP_GENERATE_MIPMAP
:
167 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
168 case PIPE_CAP_STRING_MARKER
:
169 case PIPE_CAP_CLEAR_TEXTURE
:
170 case PIPE_CAP_CULL_DISTANCE
:
171 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
172 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
173 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
174 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
175 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
176 case PIPE_CAP_DOUBLES
:
177 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
178 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
179 case PIPE_CAP_BINDLESS_TEXTURE
:
180 case PIPE_CAP_QUERY_TIMESTAMP
:
181 case PIPE_CAP_QUERY_TIME_ELAPSED
:
182 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
183 case PIPE_CAP_QUERY_SO_OVERFLOW
:
184 case PIPE_CAP_MEMOBJ
:
185 case PIPE_CAP_LOAD_CONSTBUF
:
187 case PIPE_CAP_INT64_DIVMOD
:
188 case PIPE_CAP_TGSI_CLOCK
:
189 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
190 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
191 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
:
192 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
193 case PIPE_CAP_TGSI_VOTE
:
196 case PIPE_CAP_TGSI_BALLOT
:
197 return HAVE_LLVM
>= 0x0500;
199 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
200 return !SI_BIG_ENDIAN
&& sscreen
->info
.has_userptr
;
202 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
203 return (sscreen
->info
.drm_major
== 2 &&
204 sscreen
->info
.drm_minor
>= 43) ||
205 sscreen
->info
.drm_major
== 3;
207 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
208 /* 2D tiling on CIK is supported since DRM 2.35.0 */
209 return sscreen
->info
.chip_class
< CIK
||
210 (sscreen
->info
.drm_major
== 2 &&
211 sscreen
->info
.drm_minor
>= 35) ||
212 sscreen
->info
.drm_major
== 3;
214 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
215 return R600_MAP_BUFFER_ALIGNMENT
;
217 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
218 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
219 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
220 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
221 case PIPE_CAP_MAX_VERTEX_STREAMS
:
222 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
225 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
226 if (si_have_tgsi_compute(sscreen
))
230 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
231 return MIN2(sscreen
->info
.max_alloc_size
, INT_MAX
);
233 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
234 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
235 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
236 /* SI doesn't support unaligned loads.
237 * CIK needs DRM 2.50.0 on radeon. */
238 return sscreen
->info
.chip_class
== SI
||
239 (sscreen
->info
.drm_major
== 2 &&
240 sscreen
->info
.drm_minor
< 50);
242 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
243 /* TODO: GFX9 hangs. */
244 if (sscreen
->info
.chip_class
>= GFX9
)
246 /* Disable on SI due to VM faults in CP DMA. Enable once these
247 * faults are mitigated in software.
249 if (sscreen
->info
.chip_class
>= CIK
&&
250 sscreen
->info
.drm_major
== 3 &&
251 sscreen
->info
.drm_minor
>= 13)
252 return RADEON_SPARSE_PAGE_SIZE
;
255 case PIPE_CAP_PACKED_UNIFORMS
:
256 if (sscreen
->debug_flags
& DBG(NIR
))
260 /* Unsupported features. */
261 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
262 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
263 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
264 case PIPE_CAP_USER_VERTEX_BUFFERS
:
265 case PIPE_CAP_FAKE_SW_MSAA
:
266 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
267 case PIPE_CAP_VERTEXID_NOBASE
:
268 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
269 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
270 case PIPE_CAP_TGSI_FS_FBFETCH
:
271 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
273 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
274 case PIPE_CAP_POST_DEPTH_COVERAGE
:
275 case PIPE_CAP_TILE_RASTER_ORDER
:
276 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES
:
277 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
280 case PIPE_CAP_FENCE_SIGNAL
:
281 return sscreen
->info
.has_syncobj
;
283 case PIPE_CAP_CONSTBUF0_FLAGS
:
284 return R600_RESOURCE_FLAG_32BIT
;
286 case PIPE_CAP_NATIVE_FENCE_FD
:
287 return sscreen
->info
.has_fence_to_handle
;
289 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
290 return si_have_tgsi_compute(sscreen
);
292 case PIPE_CAP_DRAW_PARAMETERS
:
293 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
294 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
295 return sscreen
->has_draw_indirect_multi
;
297 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
300 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
301 return sscreen
->info
.chip_class
<= VI
?
302 PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600
: 0;
305 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
306 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
309 /* Geometry shader output. */
310 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
312 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
315 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
319 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
320 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
321 return 15; /* 16384 */
322 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
323 /* textures support 8192, but layered rendering supports 2048 */
325 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
326 /* textures support 8192, but layered rendering supports 2048 */
329 /* Viewports and render targets. */
330 case PIPE_CAP_MAX_VIEWPORTS
:
331 return SI_MAX_VIEWPORTS
;
332 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
333 case PIPE_CAP_MAX_RENDER_TARGETS
:
336 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
337 case PIPE_CAP_MIN_TEXEL_OFFSET
:
340 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
341 case PIPE_CAP_MAX_TEXEL_OFFSET
:
344 case PIPE_CAP_ENDIANNESS
:
345 return PIPE_ENDIAN_LITTLE
;
347 case PIPE_CAP_VENDOR_ID
:
348 return ATI_VENDOR_ID
;
349 case PIPE_CAP_DEVICE_ID
:
350 return sscreen
->info
.pci_id
;
351 case PIPE_CAP_VIDEO_MEMORY
:
352 return sscreen
->info
.vram_size
>> 20;
353 case PIPE_CAP_PCI_GROUP
:
354 return sscreen
->info
.pci_domain
;
355 case PIPE_CAP_PCI_BUS
:
356 return sscreen
->info
.pci_bus
;
357 case PIPE_CAP_PCI_DEVICE
:
358 return sscreen
->info
.pci_dev
;
359 case PIPE_CAP_PCI_FUNCTION
:
360 return sscreen
->info
.pci_func
;
365 static float si_get_paramf(struct pipe_screen
* pscreen
, enum pipe_capf param
)
368 case PIPE_CAPF_MAX_LINE_WIDTH
:
369 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
370 case PIPE_CAPF_MAX_POINT_WIDTH
:
371 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
373 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
375 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
381 static int si_get_shader_param(struct pipe_screen
* pscreen
,
382 enum pipe_shader_type shader
,
383 enum pipe_shader_cap param
)
385 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
389 case PIPE_SHADER_FRAGMENT
:
390 case PIPE_SHADER_VERTEX
:
391 case PIPE_SHADER_GEOMETRY
:
392 case PIPE_SHADER_TESS_CTRL
:
393 case PIPE_SHADER_TESS_EVAL
:
395 case PIPE_SHADER_COMPUTE
:
397 case PIPE_SHADER_CAP_SUPPORTED_IRS
: {
398 int ir
= 1 << PIPE_SHADER_IR_NATIVE
;
400 if (si_have_tgsi_compute(sscreen
))
401 ir
|= 1 << PIPE_SHADER_IR_TGSI
;
406 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
: {
407 uint64_t max_const_buffer_size
;
408 pscreen
->get_compute_param(pscreen
, PIPE_SHADER_IR_TGSI
,
409 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
410 &max_const_buffer_size
);
411 return MIN2(max_const_buffer_size
, INT_MAX
);
414 /* If compute shaders don't require a special value
415 * for this cap, we can return the same value we
416 * do for other shader types. */
426 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
427 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
428 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
429 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
430 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
432 case PIPE_SHADER_CAP_MAX_INPUTS
:
433 return shader
== PIPE_SHADER_VERTEX
? SI_MAX_ATTRIBS
: 32;
434 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
435 return shader
== PIPE_SHADER_FRAGMENT
? 8 : 32;
436 case PIPE_SHADER_CAP_MAX_TEMPS
:
437 return 256; /* Max native temporaries. */
438 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
439 return 4096 * sizeof(float[4]); /* actually only memory limits this */
440 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
441 return SI_NUM_CONST_BUFFERS
;
442 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
443 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
444 return SI_NUM_SAMPLERS
;
445 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
446 return SI_NUM_SHADER_BUFFERS
;
447 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
448 return SI_NUM_IMAGES
;
449 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
450 if (sscreen
->debug_flags
& DBG(NIR
))
453 case PIPE_SHADER_CAP_PREFERRED_IR
:
454 if (sscreen
->debug_flags
& DBG(NIR
))
455 return PIPE_SHADER_IR_NIR
;
456 return PIPE_SHADER_IR_TGSI
;
457 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
460 /* Supported boolean features. */
461 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
462 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
463 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
464 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
465 case PIPE_SHADER_CAP_INTEGERS
:
466 case PIPE_SHADER_CAP_INT64_ATOMICS
:
467 case PIPE_SHADER_CAP_FP16
:
468 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
469 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
470 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
471 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
472 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
473 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
476 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
477 /* TODO: Indirect indexing of GS inputs is unimplemented. */
478 return shader
!= PIPE_SHADER_GEOMETRY
&&
479 (sscreen
->llvm_has_working_vgpr_indexing
||
480 /* TCS and TES load inputs directly from LDS or
481 * offchip memory, so indirect indexing is trivial. */
482 shader
== PIPE_SHADER_TESS_CTRL
||
483 shader
== PIPE_SHADER_TESS_EVAL
);
485 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
486 return sscreen
->llvm_has_working_vgpr_indexing
||
487 /* TCS stores outputs directly to memory. */
488 shader
== PIPE_SHADER_TESS_CTRL
;
490 /* Unsupported boolean features. */
491 case PIPE_SHADER_CAP_SUBROUTINES
:
492 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
493 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
494 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
500 static const struct nir_shader_compiler_options nir_options
= {
502 .lower_flrp32
= true,
503 .lower_flrp64
= true,
509 .lower_pack_snorm_2x16
= true,
510 .lower_pack_snorm_4x8
= true,
511 .lower_pack_unorm_2x16
= true,
512 .lower_pack_unorm_4x8
= true,
513 .lower_unpack_snorm_2x16
= true,
514 .lower_unpack_snorm_4x8
= true,
515 .lower_unpack_unorm_2x16
= true,
516 .lower_unpack_unorm_4x8
= true,
517 .lower_extract_byte
= true,
518 .lower_extract_word
= true,
519 .max_unroll_iterations
= 32,
520 .native_integers
= true,
524 si_get_compiler_options(struct pipe_screen
*screen
,
525 enum pipe_shader_ir ir
,
526 enum pipe_shader_type shader
)
528 assert(ir
== PIPE_SHADER_IR_NIR
);
532 static void si_get_driver_uuid(struct pipe_screen
*pscreen
, char *uuid
)
534 ac_compute_driver_uuid(uuid
, PIPE_UUID_SIZE
);
537 static void si_get_device_uuid(struct pipe_screen
*pscreen
, char *uuid
)
539 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
541 ac_compute_device_uuid(&sscreen
->info
, uuid
, PIPE_UUID_SIZE
);
544 static const char* si_get_name(struct pipe_screen
*pscreen
)
546 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
548 return sscreen
->renderer_string
;
551 static int si_get_video_param_no_decode(struct pipe_screen
*screen
,
552 enum pipe_video_profile profile
,
553 enum pipe_video_entrypoint entrypoint
,
554 enum pipe_video_cap param
)
557 case PIPE_VIDEO_CAP_SUPPORTED
:
558 return vl_profile_supported(screen
, profile
, entrypoint
);
559 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
561 case PIPE_VIDEO_CAP_MAX_WIDTH
:
562 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
563 return vl_video_buffer_max_size(screen
);
564 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
565 return PIPE_FORMAT_NV12
;
566 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
568 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
570 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
572 case PIPE_VIDEO_CAP_MAX_LEVEL
:
573 return vl_level_supported(screen
, profile
);
579 static int si_get_video_param(struct pipe_screen
*screen
,
580 enum pipe_video_profile profile
,
581 enum pipe_video_entrypoint entrypoint
,
582 enum pipe_video_cap param
)
584 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
585 enum pipe_video_format codec
= u_reduce_video_profile(profile
);
587 if (entrypoint
== PIPE_VIDEO_ENTRYPOINT_ENCODE
) {
589 case PIPE_VIDEO_CAP_SUPPORTED
:
590 return (codec
== PIPE_VIDEO_FORMAT_MPEG4_AVC
&&
591 (si_vce_is_fw_version_supported(sscreen
) ||
592 sscreen
->info
.family
== CHIP_RAVEN
)) ||
593 (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
&&
594 (sscreen
->info
.family
== CHIP_RAVEN
||
595 si_radeon_uvd_enc_supported(sscreen
)));
596 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
598 case PIPE_VIDEO_CAP_MAX_WIDTH
:
599 return (sscreen
->info
.family
< CHIP_TONGA
) ? 2048 : 4096;
600 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
601 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1152 : 2304;
602 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
603 return PIPE_FORMAT_NV12
;
604 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
606 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
608 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
610 case PIPE_VIDEO_CAP_STACKED_FRAMES
:
611 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1 : 2;
618 case PIPE_VIDEO_CAP_SUPPORTED
:
620 case PIPE_VIDEO_FORMAT_MPEG12
:
621 return profile
!= PIPE_VIDEO_PROFILE_MPEG1
;
622 case PIPE_VIDEO_FORMAT_MPEG4
:
624 case PIPE_VIDEO_FORMAT_MPEG4_AVC
:
625 if ((sscreen
->info
.family
== CHIP_POLARIS10
||
626 sscreen
->info
.family
== CHIP_POLARIS11
) &&
627 sscreen
->info
.uvd_fw_version
< UVD_FW_1_66_16
) {
628 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
632 case PIPE_VIDEO_FORMAT_VC1
:
634 case PIPE_VIDEO_FORMAT_HEVC
:
635 /* Carrizo only supports HEVC Main */
636 if (sscreen
->info
.family
>= CHIP_STONEY
)
637 return (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
||
638 profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
);
639 else if (sscreen
->info
.family
>= CHIP_CARRIZO
)
640 return profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
;
642 case PIPE_VIDEO_FORMAT_JPEG
:
643 if (sscreen
->info
.family
< CHIP_CARRIZO
|| sscreen
->info
.family
>= CHIP_VEGA10
)
645 if (!(sscreen
->info
.drm_major
== 3 && sscreen
->info
.drm_minor
>= 19)) {
646 RVID_ERR("No MJPEG support for the kernel version\n");
653 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
655 case PIPE_VIDEO_CAP_MAX_WIDTH
:
656 return (sscreen
->info
.family
< CHIP_TONGA
) ? 2048 : 4096;
657 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
658 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1152 : 4096;
659 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
660 if (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
)
661 return PIPE_FORMAT_P016
;
663 return PIPE_FORMAT_NV12
;
665 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
666 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
: {
667 enum pipe_video_format format
= u_reduce_video_profile(profile
);
669 if (format
== PIPE_VIDEO_FORMAT_HEVC
)
670 return false; //The firmware doesn't support interlaced HEVC.
671 else if (format
== PIPE_VIDEO_FORMAT_JPEG
)
675 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
677 case PIPE_VIDEO_CAP_MAX_LEVEL
:
679 case PIPE_VIDEO_PROFILE_MPEG1
:
681 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE
:
682 case PIPE_VIDEO_PROFILE_MPEG2_MAIN
:
684 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE
:
686 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE
:
688 case PIPE_VIDEO_PROFILE_VC1_SIMPLE
:
690 case PIPE_VIDEO_PROFILE_VC1_MAIN
:
692 case PIPE_VIDEO_PROFILE_VC1_ADVANCED
:
694 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE
:
695 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN
:
696 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH
:
697 return (sscreen
->info
.family
< CHIP_TONGA
) ? 41 : 52;
698 case PIPE_VIDEO_PROFILE_HEVC_MAIN
:
699 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10
:
709 static boolean
si_vid_is_format_supported(struct pipe_screen
*screen
,
710 enum pipe_format format
,
711 enum pipe_video_profile profile
,
712 enum pipe_video_entrypoint entrypoint
)
714 /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
715 if (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
)
716 return (format
== PIPE_FORMAT_NV12
) ||
717 (format
== PIPE_FORMAT_P016
);
719 /* we can only handle this one with UVD */
720 if (profile
!= PIPE_VIDEO_PROFILE_UNKNOWN
)
721 return format
== PIPE_FORMAT_NV12
;
723 return vl_video_buffer_is_format_supported(screen
, format
, profile
, entrypoint
);
726 static unsigned get_max_threads_per_block(struct si_screen
*screen
,
727 enum pipe_shader_ir ir_type
)
729 if (ir_type
== PIPE_SHADER_IR_NATIVE
)
732 /* Only 16 waves per thread-group on gfx9. */
733 if (screen
->info
.chip_class
>= GFX9
)
736 /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
742 static int si_get_compute_param(struct pipe_screen
*screen
,
743 enum pipe_shader_ir ir_type
,
744 enum pipe_compute_cap param
,
747 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
749 //TODO: select these params by asic
751 case PIPE_COMPUTE_CAP_IR_TARGET
: {
752 const char *gpu
, *triple
;
754 triple
= "amdgcn-mesa-mesa3d";
755 gpu
= ac_get_llvm_processor_name(sscreen
->info
.family
);
757 sprintf(ret
, "%s-%s", gpu
, triple
);
759 /* +2 for dash and terminating NIL byte */
760 return (strlen(triple
) + strlen(gpu
) + 2) * sizeof(char);
762 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
764 uint64_t *grid_dimension
= ret
;
765 grid_dimension
[0] = 3;
767 return 1 * sizeof(uint64_t);
769 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
771 uint64_t *grid_size
= ret
;
772 grid_size
[0] = 65535;
773 grid_size
[1] = 65535;
774 grid_size
[2] = 65535;
776 return 3 * sizeof(uint64_t) ;
778 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
780 uint64_t *block_size
= ret
;
781 unsigned threads_per_block
= get_max_threads_per_block(sscreen
, ir_type
);
782 block_size
[0] = threads_per_block
;
783 block_size
[1] = threads_per_block
;
784 block_size
[2] = threads_per_block
;
786 return 3 * sizeof(uint64_t);
788 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
790 uint64_t *max_threads_per_block
= ret
;
791 *max_threads_per_block
= get_max_threads_per_block(sscreen
, ir_type
);
793 return sizeof(uint64_t);
794 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
796 uint32_t *address_bits
= ret
;
797 address_bits
[0] = 64;
799 return 1 * sizeof(uint32_t);
801 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
803 uint64_t *max_global_size
= ret
;
804 uint64_t max_mem_alloc_size
;
806 si_get_compute_param(screen
, ir_type
,
807 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
808 &max_mem_alloc_size
);
810 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
811 * 1/4 of the MAX_GLOBAL_SIZE. Since the
812 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
813 * make sure we never report more than
814 * 4 * MAX_MEM_ALLOC_SIZE.
816 *max_global_size
= MIN2(4 * max_mem_alloc_size
,
817 MAX2(sscreen
->info
.gart_size
,
818 sscreen
->info
.vram_size
));
820 return sizeof(uint64_t);
822 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
824 uint64_t *max_local_size
= ret
;
825 /* Value reported by the closed source driver. */
826 *max_local_size
= 32768;
828 return sizeof(uint64_t);
830 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
832 uint64_t *max_input_size
= ret
;
833 /* Value reported by the closed source driver. */
834 *max_input_size
= 1024;
836 return sizeof(uint64_t);
838 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
840 uint64_t *max_mem_alloc_size
= ret
;
842 *max_mem_alloc_size
= sscreen
->info
.max_alloc_size
;
844 return sizeof(uint64_t);
846 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
848 uint32_t *max_clock_frequency
= ret
;
849 *max_clock_frequency
= sscreen
->info
.max_shader_clock
;
851 return sizeof(uint32_t);
853 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
855 uint32_t *max_compute_units
= ret
;
856 *max_compute_units
= sscreen
->info
.num_good_compute_units
;
858 return sizeof(uint32_t);
860 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
862 uint32_t *images_supported
= ret
;
863 *images_supported
= 0;
865 return sizeof(uint32_t);
866 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
868 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
870 uint32_t *subgroup_size
= ret
;
873 return sizeof(uint32_t);
874 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
876 uint64_t *max_variable_threads_per_block
= ret
;
877 if (ir_type
== PIPE_SHADER_IR_NATIVE
)
878 *max_variable_threads_per_block
= 0;
880 *max_variable_threads_per_block
= SI_MAX_VARIABLE_THREADS_PER_BLOCK
;
882 return sizeof(uint64_t);
885 fprintf(stderr
, "unknown PIPE_COMPUTE_CAP %d\n", param
);
889 static uint64_t si_get_timestamp(struct pipe_screen
*screen
)
891 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
893 return 1000000 * sscreen
->ws
->query_value(sscreen
->ws
, RADEON_TIMESTAMP
) /
894 sscreen
->info
.clock_crystal_freq
;
897 static void si_query_memory_info(struct pipe_screen
*screen
,
898 struct pipe_memory_info
*info
)
900 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
901 struct radeon_winsys
*ws
= sscreen
->ws
;
902 unsigned vram_usage
, gtt_usage
;
904 info
->total_device_memory
= sscreen
->info
.vram_size
/ 1024;
905 info
->total_staging_memory
= sscreen
->info
.gart_size
/ 1024;
907 /* The real TTM memory usage is somewhat random, because:
909 * 1) TTM delays freeing memory, because it can only free it after
912 * 2) The memory usage can be really low if big VRAM evictions are
913 * taking place, but the real usage is well above the size of VRAM.
915 * Instead, return statistics of this process.
917 vram_usage
= ws
->query_value(ws
, RADEON_REQUESTED_VRAM_MEMORY
) / 1024;
918 gtt_usage
= ws
->query_value(ws
, RADEON_REQUESTED_GTT_MEMORY
) / 1024;
920 info
->avail_device_memory
=
921 vram_usage
<= info
->total_device_memory
?
922 info
->total_device_memory
- vram_usage
: 0;
923 info
->avail_staging_memory
=
924 gtt_usage
<= info
->total_staging_memory
?
925 info
->total_staging_memory
- gtt_usage
: 0;
927 info
->device_memory_evicted
=
928 ws
->query_value(ws
, RADEON_NUM_BYTES_MOVED
) / 1024;
930 if (sscreen
->info
.drm_major
== 3 && sscreen
->info
.drm_minor
>= 4)
931 info
->nr_device_memory_evictions
=
932 ws
->query_value(ws
, RADEON_NUM_EVICTIONS
);
934 /* Just return the number of evicted 64KB pages. */
935 info
->nr_device_memory_evictions
= info
->device_memory_evicted
/ 64;
938 static struct disk_cache
*si_get_disk_shader_cache(struct pipe_screen
*pscreen
)
940 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
942 return sscreen
->disk_shader_cache
;
945 static void si_init_renderer_string(struct si_screen
*sscreen
)
947 struct radeon_winsys
*ws
= sscreen
->ws
;
948 char family_name
[32] = {}, llvm_string
[32] = {}, kernel_version
[128] = {};
949 struct utsname uname_data
;
951 const char *chip_name
= si_get_marketing_name(ws
);
954 snprintf(family_name
, sizeof(family_name
), "%s / ",
955 si_get_family_name(sscreen
) + 4);
957 chip_name
= si_get_family_name(sscreen
);
959 if (uname(&uname_data
) == 0)
960 snprintf(kernel_version
, sizeof(kernel_version
),
961 " / %s", uname_data
.release
);
964 snprintf(llvm_string
, sizeof(llvm_string
),
965 ", LLVM %i.%i.%i", (HAVE_LLVM
>> 8) & 0xff,
966 HAVE_LLVM
& 0xff, MESA_LLVM_VERSION_PATCH
);
969 snprintf(sscreen
->renderer_string
, sizeof(sscreen
->renderer_string
),
970 "%s (%sDRM %i.%i.%i%s%s)",
971 chip_name
, family_name
, sscreen
->info
.drm_major
,
972 sscreen
->info
.drm_minor
, sscreen
->info
.drm_patchlevel
,
973 kernel_version
, llvm_string
);
976 void si_init_screen_get_functions(struct si_screen
*sscreen
)
978 sscreen
->b
.get_name
= si_get_name
;
979 sscreen
->b
.get_vendor
= si_get_vendor
;
980 sscreen
->b
.get_device_vendor
= si_get_device_vendor
;
981 sscreen
->b
.get_param
= si_get_param
;
982 sscreen
->b
.get_paramf
= si_get_paramf
;
983 sscreen
->b
.get_compute_param
= si_get_compute_param
;
984 sscreen
->b
.get_timestamp
= si_get_timestamp
;
985 sscreen
->b
.get_shader_param
= si_get_shader_param
;
986 sscreen
->b
.get_compiler_options
= si_get_compiler_options
;
987 sscreen
->b
.get_device_uuid
= si_get_device_uuid
;
988 sscreen
->b
.get_driver_uuid
= si_get_driver_uuid
;
989 sscreen
->b
.query_memory_info
= si_query_memory_info
;
990 sscreen
->b
.get_disk_shader_cache
= si_get_disk_shader_cache
;
992 if (sscreen
->info
.has_hw_decode
) {
993 sscreen
->b
.get_video_param
= si_get_video_param
;
994 sscreen
->b
.is_video_format_supported
= si_vid_is_format_supported
;
996 sscreen
->b
.get_video_param
= si_get_video_param_no_decode
;
997 sscreen
->b
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
1000 si_init_renderer_string(sscreen
);