src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "radeon/radeon_video.h"
  27 #include "radeon/radeon_vce.h"
  28 #include "radeon/radeon_uvd_enc.h"
  29 #include "ac_llvm_util.h"
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32 #include "util/u_screen.h"
  33 #include "util/u_video.h"
  34 #include "compiler/nir/nir.h"
  35
  36 #include <sys/utsname.h>
  37
  38 static const char *si_get_vendor(struct pipe_screen *pscreen)
  39 {
  40         /* Don't change this. Games such as Alien Isolation are broken if this
  41          * returns "Advanced Micro Devices, Inc."
  42          */
  43         return "X.Org";
  44 }
  45
  46 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  47 {
  48         return "AMD";
  49 }
  50
  51 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  52 {
  53         struct si_screen *sscreen = (struct si_screen *)pscreen;
  54
  55         switch (param) {
  56         /* Supported features (boolean caps). */
  57         case PIPE_CAP_ACCELERATED:
  58         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  59         case PIPE_CAP_ANISOTROPIC_FILTER:
  60         case PIPE_CAP_POINT_SPRITE:
  61         case PIPE_CAP_OCCLUSION_QUERY:
  62         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  63         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  64         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  65         case PIPE_CAP_TEXTURE_SWIZZLE:
  66         case PIPE_CAP_DEPTH_CLIP_DISABLE:
  67         case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
  68         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  69         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  70         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  71         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  72         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  73         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  74         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
  75         case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
  76         case PIPE_CAP_VERTEX_SHADER_SATURATE:
  77         case PIPE_CAP_SEAMLESS_CUBE_MAP:
  78         case PIPE_CAP_PRIMITIVE_RESTART:
  79         case PIPE_CAP_CONDITIONAL_RENDER:
  80         case PIPE_CAP_TEXTURE_BARRIER:
  81         case PIPE_CAP_INDEP_BLEND_ENABLE:
  82         case PIPE_CAP_INDEP_BLEND_FUNC:
  83         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  84         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  85         case PIPE_CAP_START_INSTANCE:
  86         case PIPE_CAP_NPOT_TEXTURES:
  87         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  88         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  89         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
  90         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
  91         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  92         case PIPE_CAP_TGSI_INSTANCEID:
  93         case PIPE_CAP_COMPUTE:
  94         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  95         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
  96         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
  97         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  98         case PIPE_CAP_CUBE_MAP_ARRAY:
  99         case PIPE_CAP_SAMPLE_SHADING:
 100         case PIPE_CAP_DRAW_INDIRECT:
 101         case PIPE_CAP_CLIP_HALFZ:
 102         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 103         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 104         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 105         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 106         case PIPE_CAP_TGSI_TEXCOORD:
 107         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 108         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 109         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 110         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 111         case PIPE_CAP_SHAREABLE_SHADERS:
 112         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 113         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 114         case PIPE_CAP_TEXTURE_QUERY_LOD:
 115         case PIPE_CAP_TEXTURE_GATHER_SM5:
 116         case PIPE_CAP_TGSI_TXQS:
 117         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 118         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 119         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 120         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 121         case PIPE_CAP_INVALIDATE_BUFFER:
 122         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 123         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 124         case PIPE_CAP_QUERY_MEMORY_INFO:
 125         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 126         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 127         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 128         case PIPE_CAP_GENERATE_MIPMAP:
 129         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 130         case PIPE_CAP_STRING_MARKER:
 131         case PIPE_CAP_CLEAR_TEXTURE:
 132         case PIPE_CAP_CULL_DISTANCE:
 133         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 134         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 135         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 136         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 137         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 138         case PIPE_CAP_DOUBLES:
 139         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 140         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 141         case PIPE_CAP_BINDLESS_TEXTURE:
 142         case PIPE_CAP_QUERY_TIMESTAMP:
 143         case PIPE_CAP_QUERY_TIME_ELAPSED:
 144         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 145         case PIPE_CAP_MEMOBJ:
 146         case PIPE_CAP_LOAD_CONSTBUF:
 147         case PIPE_CAP_INT64:
 148         case PIPE_CAP_INT64_DIVMOD:
 149         case PIPE_CAP_TGSI_CLOCK:
 150         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 151         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 152         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 153         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 154         case PIPE_CAP_TGSI_BALLOT:
 155         case PIPE_CAP_TGSI_VOTE:
 156         case PIPE_CAP_FBFETCH:
 157         case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
 158         case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 159         case PIPE_CAP_PREFER_COMPUTE_BLIT_FOR_MULTIMEDIA:
 160         case PIPE_CAP_TGSI_DIV:
 161                 return 1;
 162
 163         case PIPE_CAP_QUERY_SO_OVERFLOW:
 164                 return sscreen->info.chip_class <= GFX9;
 165
 166         case PIPE_CAP_POST_DEPTH_COVERAGE:
 167                 return sscreen->info.chip_class >= GFX10;
 168
 169         case PIPE_CAP_GRAPHICS:
 170                 return sscreen->info.has_graphics;
 171
 172         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 173                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 174
 175         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 176                 return sscreen->info.has_gpu_reset_status_query;
 177
 178         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 179                 return sscreen->info.has_2d_tiling;
 180
 181         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 182                 return SI_MAP_BUFFER_ALIGNMENT;
 183
 184         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 185         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 186         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 187         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 188         case PIPE_CAP_MAX_VERTEX_STREAMS:
 189         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 190         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 191                 return 4;
 192
 193         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 194         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 195                 if (sscreen->info.has_indirect_compute_dispatch)
 196                                 return 450;
 197                 return 420;
 198
 199         case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 200                 /* Optimal number for good TexSubImage performance on Polaris10. */
 201                 return 64 * 1024 * 1024;
 202
 203         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 204         case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 205                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 206
 207         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 208         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 209         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 210                 return HAVE_LLVM < 0x0900 && !sscreen->info.has_unaligned_shader_loads;
 211
 212         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 213                 return sscreen->info.has_sparse_vm_mappings ?
 214                                 RADEON_SPARSE_PAGE_SIZE : 0;
 215
 216         case PIPE_CAP_PACKED_UNIFORMS:
 217                 if (sscreen->options.enable_nir)
 218                         return 1;
 219                 return 0;
 220
 221         /* Unsupported features. */
 222         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 223         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 224         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 225         case PIPE_CAP_USER_VERTEX_BUFFERS:
 226         case PIPE_CAP_FAKE_SW_MSAA:
 227         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 228         case PIPE_CAP_VERTEXID_NOBASE:
 229         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 230         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 231         case PIPE_CAP_UMA:
 232         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 233         case PIPE_CAP_TILE_RASTER_ORDER:
 234         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 235         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 236         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 237         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 238         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 239         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 240         case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 241         case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 242         case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 243                 return 0;
 244
 245         case PIPE_CAP_FENCE_SIGNAL:
 246                 return sscreen->info.has_syncobj;
 247
 248         case PIPE_CAP_CONSTBUF0_FLAGS:
 249                 return SI_RESOURCE_FLAG_32BIT;
 250
 251         case PIPE_CAP_NATIVE_FENCE_FD:
 252                 return sscreen->info.has_fence_to_handle;
 253
 254         case PIPE_CAP_DRAW_PARAMETERS:
 255         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 256         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 257                 return sscreen->has_draw_indirect_multi;
 258
 259         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 260                 return 30;
 261
 262         case PIPE_CAP_MAX_VARYINGS:
 263                 return 32;
 264
 265         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 266                 return sscreen->info.chip_class <= GFX8 ?
 267                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 268
 269         /* Stream output. */
 270         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 271         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 272                 return 32*4;
 273
 274         /* Geometry shader output. */
 275         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 276                 /* gfx9 has to report 256 to make piglit/gs-max-output pass.
 277                  * gfx8 and earlier can do 1024.
 278                  */
 279                 return 256;
 280         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 281                 return 4095;
 282         case PIPE_CAP_MAX_GS_INVOCATIONS:
 283                 /* The closed driver exposes 127, but 125 is the greatest
 284                  * number that works. */
 285                 return 125;
 286
 287         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 288                 return 2048;
 289
 290         /* Texturing. */
 291         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 292                 return 16384;
 293         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 294                 return 15; /* 16384 */
 295         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 296                 if (sscreen->info.chip_class >= GFX10)
 297                         return 14;
 298                 /* textures support 8192, but layered rendering supports 2048 */
 299                 return 12;
 300         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 301                 if (sscreen->info.chip_class >= GFX10)
 302                         return 8192;
 303                 /* textures support 8192, but layered rendering supports 2048 */
 304                 return 2048;
 305
 306         /* Viewports and render targets. */
 307         case PIPE_CAP_MAX_VIEWPORTS:
 308                 return SI_MAX_VIEWPORTS;
 309         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 310         case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 311         case PIPE_CAP_MAX_RENDER_TARGETS:
 312                 return 8;
 313         case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 314                 return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
 315
 316         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 317         case PIPE_CAP_MIN_TEXEL_OFFSET:
 318                 return -32;
 319
 320         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 321         case PIPE_CAP_MAX_TEXEL_OFFSET:
 322                 return 31;
 323
 324         case PIPE_CAP_ENDIANNESS:
 325                 return PIPE_ENDIAN_LITTLE;
 326
 327         case PIPE_CAP_VENDOR_ID:
 328                 return ATI_VENDOR_ID;
 329         case PIPE_CAP_DEVICE_ID:
 330                 return sscreen->info.pci_id;
 331         case PIPE_CAP_VIDEO_MEMORY:
 332                 return sscreen->info.vram_size >> 20;
 333         case PIPE_CAP_PCI_GROUP:
 334                 return sscreen->info.pci_domain;
 335         case PIPE_CAP_PCI_BUS:
 336                 return sscreen->info.pci_bus;
 337         case PIPE_CAP_PCI_DEVICE:
 338                 return sscreen->info.pci_dev;
 339         case PIPE_CAP_PCI_FUNCTION:
 340                 return sscreen->info.pci_func;
 341
 342         default:
 343                 return u_pipe_screen_get_param_defaults(pscreen, param);
 344         }
 345 }
 346
 347 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 348 {
 349         switch (param) {
 350         case PIPE_CAPF_MAX_LINE_WIDTH:
 351         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 352                 /* This depends on the quant mode, though the precise interactions
 353                  * are unknown. */
 354                 return 2048;
 355         case PIPE_CAPF_MAX_POINT_WIDTH:
 356         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 357                 return SI_MAX_POINT_SIZE;
 358         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 359                 return 16.0f;
 360         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 361                 return 16.0f;
 362         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 363         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 364         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 365                 return 0.0f;
 366         }
 367         return 0.0f;
 368 }
 369
 370 static int si_get_shader_param(struct pipe_screen* pscreen,
 371                                enum pipe_shader_type shader,
 372                                enum pipe_shader_cap param)
 373 {
 374         struct si_screen *sscreen = (struct si_screen *)pscreen;
 375
 376         switch(shader)
 377         {
 378         case PIPE_SHADER_FRAGMENT:
 379         case PIPE_SHADER_VERTEX:
 380         case PIPE_SHADER_GEOMETRY:
 381         case PIPE_SHADER_TESS_CTRL:
 382         case PIPE_SHADER_TESS_EVAL:
 383                 break;
 384         case PIPE_SHADER_COMPUTE:
 385                 switch (param) {
 386                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 387                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 388
 389                         if (sscreen->info.has_indirect_compute_dispatch)
 390                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 391
 392                         return ir;
 393                 }
 394
 395                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 396                         uint64_t max_const_buffer_size;
 397                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 398                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 399                                 &max_const_buffer_size);
 400                         return MIN2(max_const_buffer_size, INT_MAX);
 401                 }
 402                 default:
 403                         /* If compute shaders don't require a special value
 404                          * for this cap, we can return the same value we
 405                          * do for other shader types. */
 406                         break;
 407                 }
 408                 break;
 409         default:
 410                 return 0;
 411         }
 412
 413         switch (param) {
 414         /* Shader limits. */
 415         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 416         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 417         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 418         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 419         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 420                 return 16384;
 421         case PIPE_SHADER_CAP_MAX_INPUTS:
 422                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 423         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 424                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 425         case PIPE_SHADER_CAP_MAX_TEMPS:
 426                 return 256; /* Max native temporaries. */
 427         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 428                 return MIN2(sscreen->info.max_alloc_size, INT_MAX - 3); /* aligned to 4 */
 429         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 430                 return SI_NUM_CONST_BUFFERS;
 431         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 432         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 433                 return SI_NUM_SAMPLERS;
 434         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 435                 return SI_NUM_SHADER_BUFFERS;
 436         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 437                 return SI_NUM_IMAGES;
 438         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 439                 if (sscreen->options.enable_nir)
 440                         return 0;
 441                 return 32;
 442         case PIPE_SHADER_CAP_PREFERRED_IR:
 443                 if (sscreen->options.enable_nir)
 444                         return PIPE_SHADER_IR_NIR;
 445                 return PIPE_SHADER_IR_TGSI;
 446         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 447                 return 4;
 448
 449         /* Supported boolean features. */
 450         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 451         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 452         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 453         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 454         case PIPE_SHADER_CAP_INTEGERS:
 455         case PIPE_SHADER_CAP_INT64_ATOMICS:
 456         case PIPE_SHADER_CAP_FP16:
 457         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 458         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 459         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 460         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 461         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 462         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 463                 return 1;
 464
 465         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 466                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 467                 if (shader == PIPE_SHADER_GEOMETRY)
 468                         return 0;
 469
 470                 if (shader == PIPE_SHADER_VERTEX &&
 471                     !sscreen->llvm_has_working_vgpr_indexing)
 472                         return 0;
 473
 474                 /* TCS and TES load inputs directly from LDS or offchip
 475                  * memory, so indirect indexing is always supported.
 476                  * PS has to support indirect indexing, because we can't
 477                  * lower that to TEMPs for INTERP instructions.
 478                  */
 479                 return 1;
 480
 481         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 482                 return sscreen->llvm_has_working_vgpr_indexing ||
 483                        /* TCS stores outputs directly to memory. */
 484                        shader == PIPE_SHADER_TESS_CTRL;
 485
 486         /* Unsupported boolean features. */
 487         case PIPE_SHADER_CAP_SUBROUTINES:
 488         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 489         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 490         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 491                 return 0;
 492         case PIPE_SHADER_CAP_SCALAR_ISA:
 493                 return 1;
 494         }
 495         return 0;
 496 }
 497
 498 static const struct nir_shader_compiler_options nir_options = {
 499         .lower_scmp = true,
 500         .lower_flrp32 = true,
 501         .lower_flrp64 = true,
 502         .lower_fsat = true,
 503         .lower_fdiv = true,
 504         .lower_bitfield_insert_to_bitfield_select = true,
 505         .lower_bitfield_extract = true,
 506         .lower_sub = true,
 507         .lower_ffma = true,
 508         .lower_fmod = true,
 509         .lower_pack_snorm_4x8 = true,
 510         .lower_pack_unorm_4x8 = true,
 511         .lower_unpack_snorm_2x16 = true,
 512         .lower_unpack_snorm_4x8 = true,
 513         .lower_unpack_unorm_2x16 = true,
 514         .lower_unpack_unorm_4x8 = true,
 515         .lower_extract_byte = true,
 516         .lower_extract_word = true,
 517         .lower_rotate = true,
 518         .optimize_sample_mask_in = true,
 519         .max_unroll_iterations = 32,
 520         .use_interpolated_input_intrinsics = true,
 521 };
 522
 523 static const void *
 524 si_get_compiler_options(struct pipe_screen *screen,
 525                         enum pipe_shader_ir ir,
 526                         enum pipe_shader_type shader)
 527 {
 528         assert(ir == PIPE_SHADER_IR_NIR);
 529         return &nir_options;
 530 }
 531
 532 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 533 {
 534         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 535 }
 536
 537 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 538 {
 539         struct si_screen *sscreen = (struct si_screen *)pscreen;
 540
 541         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 542 }
 543
 544 static const char* si_get_name(struct pipe_screen *pscreen)
 545 {
 546         struct si_screen *sscreen = (struct si_screen*)pscreen;
 547
 548         return sscreen->renderer_string;
 549 }
 550
 551 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 552                                         enum pipe_video_profile profile,
 553                                         enum pipe_video_entrypoint entrypoint,
 554                                         enum pipe_video_cap param)
 555 {
 556         switch (param) {
 557         case PIPE_VIDEO_CAP_SUPPORTED:
 558                 return vl_profile_supported(screen, profile, entrypoint);
 559         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 560                 return 1;
 561         case PIPE_VIDEO_CAP_MAX_WIDTH:
 562         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 563                 return vl_video_buffer_max_size(screen);
 564         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 565                 return PIPE_FORMAT_NV12;
 566         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 567                 return false;
 568         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 569                 return false;
 570         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 571                 return true;
 572         case PIPE_VIDEO_CAP_MAX_LEVEL:
 573                 return vl_level_supported(screen, profile);
 574         default:
 575                 return 0;
 576         }
 577 }
 578
 579 static int si_get_video_param(struct pipe_screen *screen,
 580                               enum pipe_video_profile profile,
 581                               enum pipe_video_entrypoint entrypoint,
 582                               enum pipe_video_cap param)
 583 {
 584         struct si_screen *sscreen = (struct si_screen *)screen;
 585         enum pipe_video_format codec = u_reduce_video_profile(profile);
 586
 587         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 588                 switch (param) {
 589                 case PIPE_VIDEO_CAP_SUPPORTED:
 590                         return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 591                                 (si_vce_is_fw_version_supported(sscreen) ||
 592                                 sscreen->info.family >= CHIP_RAVEN)) ||
 593                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 594                                 (sscreen->info.family >= CHIP_RAVEN ||
 595                                 si_radeon_uvd_enc_supported(sscreen)));
 596                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 597                         return 1;
 598                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 599                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 600                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 601                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 602                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 603                         return PIPE_FORMAT_NV12;
 604                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 605                         return false;
 606                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 607                         return false;
 608                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 609                         return true;
 610                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 611                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 612                 default:
 613                         return 0;
 614                 }
 615         }
 616
 617         switch (param) {
 618         case PIPE_VIDEO_CAP_SUPPORTED:
 619                 switch (codec) {
 620                 case PIPE_VIDEO_FORMAT_MPEG12:
 621                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 622                 case PIPE_VIDEO_FORMAT_MPEG4:
 623                         return 1;
 624                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 625                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 626                              sscreen->info.family == CHIP_POLARIS11) &&
 627                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 628                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 629                                 return false;
 630                         }
 631                         return true;
 632                 case PIPE_VIDEO_FORMAT_VC1:
 633                         return true;
 634                 case PIPE_VIDEO_FORMAT_HEVC:
 635                         /* Carrizo only supports HEVC Main */
 636                         if (sscreen->info.family >= CHIP_STONEY)
 637                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 638                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 639                         else if (sscreen->info.family >= CHIP_CARRIZO)
 640                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 641                         return false;
 642                 case PIPE_VIDEO_FORMAT_JPEG:
 643                         if (sscreen->info.family == CHIP_RAVEN ||
 644                             sscreen->info.family == CHIP_RAVEN2 ||
 645                             sscreen->info.family == CHIP_NAVI10)
 646                                 return true;
 647                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 648                                 return false;
 649                         if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 19)) {
 650                                 RVID_ERR("No MJPEG support for the kernel version\n");
 651                                 return false;
 652                         }
 653                         return true;
 654                 case PIPE_VIDEO_FORMAT_VP9:
 655                         if (sscreen->info.family < CHIP_RAVEN)
 656                                 return false;
 657                         return true;
 658                 default:
 659                         return false;
 660                 }
 661         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 662                 return 1;
 663         case PIPE_VIDEO_CAP_MAX_WIDTH:
 664                 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 665         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 666                 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 667         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 668                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 ||
 669                     profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 670                         return PIPE_FORMAT_P016;
 671                 else
 672                         return PIPE_FORMAT_NV12;
 673
 674         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 675         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 676                 enum pipe_video_format format = u_reduce_video_profile(profile);
 677
 678                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 679                         return false; //The firmware doesn't support interlaced HEVC.
 680                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 681                         return false;
 682                 else if (format == PIPE_VIDEO_FORMAT_VP9)
 683                         return false;
 684                 return true;
 685         }
 686         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 687                 return true;
 688         case PIPE_VIDEO_CAP_MAX_LEVEL:
 689                 switch (profile) {
 690                 case PIPE_VIDEO_PROFILE_MPEG1:
 691                         return 0;
 692                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 693                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 694                         return 3;
 695                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 696                         return 3;
 697                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 698                         return 5;
 699                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 700                         return 1;
 701                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 702                         return 2;
 703                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 704                         return 4;
 705                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 706                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 707                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 708                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 709                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 710                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 711                         return 186;
 712                 default:
 713                         return 0;
 714                 }
 715         default:
 716                 return 0;
 717         }
 718 }
 719
 720 static bool si_vid_is_format_supported(struct pipe_screen *screen,
 721                                        enum pipe_format format,
 722                                        enum pipe_video_profile profile,
 723                                        enum pipe_video_entrypoint entrypoint)
 724 {
 725         /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
 726         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 727                 return (format == PIPE_FORMAT_NV12) ||
 728                         (format == PIPE_FORMAT_P016);
 729
 730         /* Vp9 profile 2 supports 10 bit decoding using P016 */
 731         if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 732                 return format == PIPE_FORMAT_P016;
 733
 734
 735         /* we can only handle this one with UVD */
 736         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 737                 return format == PIPE_FORMAT_NV12;
 738
 739         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 740 }
 741
 742 static unsigned get_max_threads_per_block(struct si_screen *screen,
 743                                           enum pipe_shader_ir ir_type)
 744 {
 745         if (ir_type == PIPE_SHADER_IR_NATIVE)
 746                 return 256;
 747
 748         /* Only 16 waves per thread-group on gfx9. */
 749         if (screen->info.chip_class >= GFX9)
 750                 return 1024;
 751
 752         /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
 753          * round number.
 754          */
 755         return 2048;
 756 }
 757
 758 static int si_get_compute_param(struct pipe_screen *screen,
 759                                 enum pipe_shader_ir ir_type,
 760                                 enum pipe_compute_cap param,
 761                                 void *ret)
 762 {
 763         struct si_screen *sscreen = (struct si_screen *)screen;
 764
 765         //TODO: select these params by asic
 766         switch (param) {
 767         case PIPE_COMPUTE_CAP_IR_TARGET: {
 768                 const char *gpu, *triple;
 769
 770                 triple = "amdgcn-mesa-mesa3d";
 771                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 772                 if (ret) {
 773                         sprintf(ret, "%s-%s", gpu, triple);
 774                 }
 775                 /* +2 for dash and terminating NIL byte */
 776                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 777         }
 778         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 779                 if (ret) {
 780                         uint64_t *grid_dimension = ret;
 781                         grid_dimension[0] = 3;
 782                 }
 783                 return 1 * sizeof(uint64_t);
 784
 785         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 786                 if (ret) {
 787                         uint64_t *grid_size = ret;
 788                         grid_size[0] = 65535;
 789                         grid_size[1] = 65535;
 790                         grid_size[2] = 65535;
 791                 }
 792                 return 3 * sizeof(uint64_t) ;
 793
 794         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 795                 if (ret) {
 796                         uint64_t *block_size = ret;
 797                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 798                         block_size[0] = threads_per_block;
 799                         block_size[1] = threads_per_block;
 800                         block_size[2] = threads_per_block;
 801                 }
 802                 return 3 * sizeof(uint64_t);
 803
 804         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 805                 if (ret) {
 806                         uint64_t *max_threads_per_block = ret;
 807                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 808                 }
 809                 return sizeof(uint64_t);
 810         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 811                 if (ret) {
 812                         uint32_t *address_bits = ret;
 813                         address_bits[0] = 64;
 814                 }
 815                 return 1 * sizeof(uint32_t);
 816
 817         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 818                 if (ret) {
 819                         uint64_t *max_global_size = ret;
 820                         uint64_t max_mem_alloc_size;
 821
 822                         si_get_compute_param(screen, ir_type,
 823                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 824                                 &max_mem_alloc_size);
 825
 826                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 827                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 828                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 829                          * make sure we never report more than
 830                          * 4 * MAX_MEM_ALLOC_SIZE.
 831                          */
 832                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 833                                                 MAX2(sscreen->info.gart_size,
 834                                                      sscreen->info.vram_size));
 835                 }
 836                 return sizeof(uint64_t);
 837
 838         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 839                 if (ret) {
 840                         uint64_t *max_local_size = ret;
 841                         /* Value reported by the closed source driver. */
 842                         *max_local_size = 32768;
 843                 }
 844                 return sizeof(uint64_t);
 845
 846         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 847                 if (ret) {
 848                         uint64_t *max_input_size = ret;
 849                         /* Value reported by the closed source driver. */
 850                         *max_input_size = 1024;
 851                 }
 852                 return sizeof(uint64_t);
 853
 854         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 855                 if (ret) {
 856                         uint64_t *max_mem_alloc_size = ret;
 857
 858                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 859                 }
 860                 return sizeof(uint64_t);
 861
 862         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 863                 if (ret) {
 864                         uint32_t *max_clock_frequency = ret;
 865                         *max_clock_frequency = sscreen->info.max_shader_clock;
 866                 }
 867                 return sizeof(uint32_t);
 868
 869         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 870                 if (ret) {
 871                         uint32_t *max_compute_units = ret;
 872                         *max_compute_units = sscreen->info.num_good_compute_units;
 873                 }
 874                 return sizeof(uint32_t);
 875
 876         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 877                 if (ret) {
 878                         uint32_t *images_supported = ret;
 879                         *images_supported = 0;
 880                 }
 881                 return sizeof(uint32_t);
 882         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 883                 break; /* unused */
 884         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 885                 if (ret) {
 886                         uint32_t *subgroup_size = ret;
 887                         *subgroup_size = sscreen->compute_wave_size;
 888                 }
 889                 return sizeof(uint32_t);
 890         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 891                 if (ret) {
 892                         uint64_t *max_variable_threads_per_block = ret;
 893                         if (ir_type == PIPE_SHADER_IR_NATIVE)
 894                                 *max_variable_threads_per_block = 0;
 895                         else
 896                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 897                 }
 898                 return sizeof(uint64_t);
 899         }
 900
 901         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 902         return 0;
 903 }
 904
 905 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 906 {
 907         struct si_screen *sscreen = (struct si_screen*)screen;
 908
 909         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 910                         sscreen->info.clock_crystal_freq;
 911 }
 912
 913 static void si_query_memory_info(struct pipe_screen *screen,
 914                                  struct pipe_memory_info *info)
 915 {
 916         struct si_screen *sscreen = (struct si_screen*)screen;
 917         struct radeon_winsys *ws = sscreen->ws;
 918         unsigned vram_usage, gtt_usage;
 919
 920         info->total_device_memory = sscreen->info.vram_size / 1024;
 921         info->total_staging_memory = sscreen->info.gart_size / 1024;
 922
 923         /* The real TTM memory usage is somewhat random, because:
 924          *
 925          * 1) TTM delays freeing memory, because it can only free it after
 926          *    fences expire.
 927          *
 928          * 2) The memory usage can be really low if big VRAM evictions are
 929          *    taking place, but the real usage is well above the size of VRAM.
 930          *
 931          * Instead, return statistics of this process.
 932          */
 933         vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
 934         gtt_usage =  ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
 935
 936         info->avail_device_memory =
 937                 vram_usage <= info->total_device_memory ?
 938                                 info->total_device_memory - vram_usage : 0;
 939         info->avail_staging_memory =
 940                 gtt_usage <= info->total_staging_memory ?
 941                                 info->total_staging_memory - gtt_usage : 0;
 942
 943         info->device_memory_evicted =
 944                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 945
 946         if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 4)
 947                 info->nr_device_memory_evictions =
 948                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 949         else
 950                 /* Just return the number of evicted 64KB pages. */
 951                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 952 }
 953
 954 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 955 {
 956         struct si_screen *sscreen = (struct si_screen*)pscreen;
 957
 958         return sscreen->disk_shader_cache;
 959 }
 960
 961 static void si_init_renderer_string(struct si_screen *sscreen)
 962 {
 963         char first_name[256], second_name[32] = {}, kernel_version[128] = {};
 964         struct utsname uname_data;
 965
 966         if (sscreen->info.marketing_name) {
 967                 snprintf(first_name, sizeof(first_name), "%s",
 968                          sscreen->info.marketing_name);
 969                 snprintf(second_name, sizeof(second_name), "%s, ",
 970                          sscreen->info.name);
 971         } else {
 972                 snprintf(first_name, sizeof(first_name), "AMD %s",
 973                          sscreen->info.name);
 974         }
 975
 976         if (uname(&uname_data) == 0)
 977                 snprintf(kernel_version, sizeof(kernel_version),
 978                          ", %s", uname_data.release);
 979
 980         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 981                  "%s (%sDRM %i.%i.%i%s, LLVM " MESA_LLVM_VERSION_STRING ")",
 982                  first_name, second_name, sscreen->info.drm_major,
 983                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 984                  kernel_version);
 985 }
 986
 987 void si_init_screen_get_functions(struct si_screen *sscreen)
 988 {
 989         sscreen->b.get_name = si_get_name;
 990         sscreen->b.get_vendor = si_get_vendor;
 991         sscreen->b.get_device_vendor = si_get_device_vendor;
 992         sscreen->b.get_param = si_get_param;
 993         sscreen->b.get_paramf = si_get_paramf;
 994         sscreen->b.get_compute_param = si_get_compute_param;
 995         sscreen->b.get_timestamp = si_get_timestamp;
 996         sscreen->b.get_shader_param = si_get_shader_param;
 997         sscreen->b.get_compiler_options = si_get_compiler_options;
 998         sscreen->b.get_device_uuid = si_get_device_uuid;
 999         sscreen->b.get_driver_uuid = si_get_driver_uuid;
1000         sscreen->b.query_memory_info = si_query_memory_info;
1001         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
1002
1003         if (sscreen->info.has_hw_decode) {
1004                 sscreen->b.get_video_param = si_get_video_param;
1005                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
1006         } else {
1007                 sscreen->b.get_video_param = si_get_video_param_no_decode;
1008                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1009         }
1010
1011         si_init_renderer_string(sscreen);
1012 }