src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "compiler/nir/nir.h"
  26 #include "radeon/radeon_uvd_enc.h"
  27 #include "radeon/radeon_vce.h"
  28 #include "radeon/radeon_video.h"
  29 #include "si_pipe.h"
  30 #include "util/u_screen.h"
  31 #include "util/u_video.h"
  32 #include "vl/vl_decoder.h"
  33 #include "vl/vl_video_buffer.h"
  34 #include <sys/utsname.h>
  35
  36 static const char *si_get_vendor(struct pipe_screen *pscreen)
  37 {
  38    /* Don't change this. Games such as Alien Isolation are broken if this
  39     * returns "Advanced Micro Devices, Inc."
  40     */
  41    return "X.Org";
  42 }
  43
  44 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  45 {
  46    return "AMD";
  47 }
  48
  49 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  50 {
  51    struct si_screen *sscreen = (struct si_screen *)pscreen;
  52
  53    switch (param) {
  54    /* Supported features (boolean caps). */
  55    case PIPE_CAP_ACCELERATED:
  56    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  57    case PIPE_CAP_ANISOTROPIC_FILTER:
  58    case PIPE_CAP_POINT_SPRITE:
  59    case PIPE_CAP_OCCLUSION_QUERY:
  60    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  61    case PIPE_CAP_TEXTURE_SHADOW_LOD:
  62    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  63    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  64    case PIPE_CAP_TEXTURE_SWIZZLE:
  65    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  66    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
  67    case PIPE_CAP_SHADER_STENCIL_EXPORT:
  68    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  69    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  70    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  71    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  72    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  73    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
  74    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
  75    case PIPE_CAP_VERTEX_SHADER_SATURATE:
  76    case PIPE_CAP_SEAMLESS_CUBE_MAP:
  77    case PIPE_CAP_PRIMITIVE_RESTART:
  78    case PIPE_CAP_CONDITIONAL_RENDER:
  79    case PIPE_CAP_TEXTURE_BARRIER:
  80    case PIPE_CAP_INDEP_BLEND_ENABLE:
  81    case PIPE_CAP_INDEP_BLEND_FUNC:
  82    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  83    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  84    case PIPE_CAP_START_INSTANCE:
  85    case PIPE_CAP_NPOT_TEXTURES:
  86    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  87    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  88    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
  89    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
  90    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  91    case PIPE_CAP_TGSI_INSTANCEID:
  92    case PIPE_CAP_COMPUTE:
  93    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  94    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
  95    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
  96    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  97    case PIPE_CAP_CUBE_MAP_ARRAY:
  98    case PIPE_CAP_SAMPLE_SHADING:
  99    case PIPE_CAP_DRAW_INDIRECT:
 100    case PIPE_CAP_CLIP_HALFZ:
 101    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 102    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 103    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 104    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 105    case PIPE_CAP_TGSI_TEXCOORD:
 106    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 107    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 108    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 109    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 110    case PIPE_CAP_SHAREABLE_SHADERS:
 111    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 112    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 113    case PIPE_CAP_TEXTURE_QUERY_LOD:
 114    case PIPE_CAP_TEXTURE_GATHER_SM5:
 115    case PIPE_CAP_TGSI_TXQS:
 116    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 117    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 118    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 119    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 120    case PIPE_CAP_INVALIDATE_BUFFER:
 121    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 122    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 123    case PIPE_CAP_QUERY_MEMORY_INFO:
 124    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 125    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 126    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 127    case PIPE_CAP_GENERATE_MIPMAP:
 128    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 129    case PIPE_CAP_STRING_MARKER:
 130    case PIPE_CAP_CLEAR_TEXTURE:
 131    case PIPE_CAP_CULL_DISTANCE:
 132    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 133    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 134    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 135    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 136    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 137    case PIPE_CAP_DOUBLES:
 138    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 139    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 140    case PIPE_CAP_BINDLESS_TEXTURE:
 141    case PIPE_CAP_QUERY_TIMESTAMP:
 142    case PIPE_CAP_QUERY_TIME_ELAPSED:
 143    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 144    case PIPE_CAP_MEMOBJ:
 145    case PIPE_CAP_LOAD_CONSTBUF:
 146    case PIPE_CAP_INT64:
 147    case PIPE_CAP_INT64_DIVMOD:
 148    case PIPE_CAP_TGSI_CLOCK:
 149    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 150    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 151    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 152    case PIPE_CAP_TGSI_BALLOT:
 153    case PIPE_CAP_TGSI_VOTE:
 154    case PIPE_CAP_FBFETCH:
 155    case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
 156    case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 157    case PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA:
 158    case PIPE_CAP_TGSI_DIV:
 159    case PIPE_CAP_PACKED_UNIFORMS:
 160    case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
 161    case PIPE_CAP_GL_SPIRV:
 162    case PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES:
 163       return 1;
 164
 165    case PIPE_CAP_QUERY_SO_OVERFLOW:
 166       return !sscreen->use_ngg_streamout;
 167
 168    case PIPE_CAP_POST_DEPTH_COVERAGE:
 169       return sscreen->info.chip_class >= GFX10;
 170
 171    case PIPE_CAP_GRAPHICS:
 172       return sscreen->info.has_graphics;
 173
 174    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 175       return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 176
 177    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 178       return sscreen->info.has_gpu_reset_status_query;
 179
 180    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 181       return sscreen->info.has_2d_tiling;
 182
 183    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 184       return SI_MAP_BUFFER_ALIGNMENT;
 185
 186    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 187    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 188    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 189    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 190    case PIPE_CAP_MAX_VERTEX_STREAMS:
 191    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 192    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 193       return 4;
 194
 195    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 196    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 197       if (!sscreen->info.has_indirect_compute_dispatch)
 198          return 420;
 199       return 460;
 200
 201    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 202       /* Optimal number for good TexSubImage performance on Polaris10. */
 203       return 64 * 1024 * 1024;
 204
 205    case PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE:
 206       return 4096 * 1024;
 207
 208    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 209    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 210       return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 211
 212    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 213    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 214    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 215       return LLVM_VERSION_MAJOR < 9 && !sscreen->info.has_unaligned_shader_loads;
 216
 217    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 218       return sscreen->info.has_sparse_vm_mappings ? RADEON_SPARSE_PAGE_SIZE : 0;
 219
 220    case PIPE_CAP_UMA:
 221    case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
 222       return 0;
 223
 224    case PIPE_CAP_FENCE_SIGNAL:
 225       return sscreen->info.has_syncobj;
 226
 227    case PIPE_CAP_CONSTBUF0_FLAGS:
 228       return SI_RESOURCE_FLAG_32BIT;
 229
 230    case PIPE_CAP_NATIVE_FENCE_FD:
 231       return sscreen->info.has_fence_to_handle;
 232
 233    case PIPE_CAP_DRAW_PARAMETERS:
 234    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 235    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 236       return sscreen->has_draw_indirect_multi;
 237
 238    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 239       return 30;
 240
 241    case PIPE_CAP_MAX_VARYINGS:
 242       return 32;
 243
 244    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 245       return sscreen->info.chip_class <= GFX8 ? PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 246
 247    /* Stream output. */
 248    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 249    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 250       return 32 * 4;
 251
 252    /* Geometry shader output. */
 253    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 254       /* gfx9 has to report 256 to make piglit/gs-max-output pass.
 255        * gfx8 and earlier can do 1024.
 256        */
 257       return 256;
 258    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 259       return 4095;
 260    case PIPE_CAP_MAX_GS_INVOCATIONS:
 261       /* The closed driver exposes 127, but 125 is the greatest
 262        * number that works. */
 263       return 125;
 264
 265    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 266       return 2048;
 267
 268    /* Texturing. */
 269    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 270       return 16384;
 271    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 272       return 15; /* 16384 */
 273    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 274       if (sscreen->info.chip_class >= GFX10)
 275          return 14;
 276       /* textures support 8192, but layered rendering supports 2048 */
 277       return 12;
 278    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 279       if (sscreen->info.chip_class >= GFX10)
 280          return 8192;
 281       /* textures support 8192, but layered rendering supports 2048 */
 282       return 2048;
 283
 284    /* Viewports and render targets. */
 285    case PIPE_CAP_MAX_VIEWPORTS:
 286       return SI_MAX_VIEWPORTS;
 287    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 288    case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 289    case PIPE_CAP_MAX_RENDER_TARGETS:
 290       return 8;
 291    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 292       return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
 293
 294    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 295    case PIPE_CAP_MIN_TEXEL_OFFSET:
 296       return -32;
 297
 298    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 299    case PIPE_CAP_MAX_TEXEL_OFFSET:
 300       return 31;
 301
 302    case PIPE_CAP_ENDIANNESS:
 303       return PIPE_ENDIAN_LITTLE;
 304
 305    case PIPE_CAP_VENDOR_ID:
 306       return ATI_VENDOR_ID;
 307    case PIPE_CAP_DEVICE_ID:
 308       return sscreen->info.pci_id;
 309    case PIPE_CAP_VIDEO_MEMORY:
 310       return sscreen->info.vram_size >> 20;
 311    case PIPE_CAP_PCI_GROUP:
 312       return sscreen->info.pci_domain;
 313    case PIPE_CAP_PCI_BUS:
 314       return sscreen->info.pci_bus;
 315    case PIPE_CAP_PCI_DEVICE:
 316       return sscreen->info.pci_dev;
 317    case PIPE_CAP_PCI_FUNCTION:
 318       return sscreen->info.pci_func;
 319    case PIPE_CAP_TGSI_ATOMINC_WRAP:
 320       return LLVM_VERSION_MAJOR >= 10;
 321
 322    default:
 323       return u_pipe_screen_get_param_defaults(pscreen, param);
 324    }
 325 }
 326
 327 static float si_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 328 {
 329    switch (param) {
 330    case PIPE_CAPF_MAX_LINE_WIDTH:
 331    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 332       /* This depends on the quant mode, though the precise interactions
 333        * are unknown. */
 334       return 2048;
 335    case PIPE_CAPF_MAX_POINT_WIDTH:
 336    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 337       return SI_MAX_POINT_SIZE;
 338    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 339       return 16.0f;
 340    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 341       return 16.0f;
 342    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 343    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 344    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 345       return 0.0f;
 346    }
 347    return 0.0f;
 348 }
 349
 350 static int si_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_type shader,
 351                                enum pipe_shader_cap param)
 352 {
 353    struct si_screen *sscreen = (struct si_screen *)pscreen;
 354
 355    switch (shader) {
 356    case PIPE_SHADER_FRAGMENT:
 357    case PIPE_SHADER_VERTEX:
 358    case PIPE_SHADER_GEOMETRY:
 359    case PIPE_SHADER_TESS_CTRL:
 360    case PIPE_SHADER_TESS_EVAL:
 361       break;
 362    case PIPE_SHADER_COMPUTE:
 363       switch (param) {
 364       case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 365          int ir = 1 << PIPE_SHADER_IR_NATIVE;
 366
 367          if (sscreen->info.has_indirect_compute_dispatch)
 368             ir |= 1 << PIPE_SHADER_IR_NIR;
 369
 370          return ir;
 371       }
 372
 373       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 374          uint64_t max_const_buffer_size;
 375          pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_NIR,
 376                                     PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE, &max_const_buffer_size);
 377          return MIN2(max_const_buffer_size, INT_MAX);
 378       }
 379       default:
 380          /* If compute shaders don't require a special value
 381           * for this cap, we can return the same value we
 382           * do for other shader types. */
 383          break;
 384       }
 385       break;
 386    default:
 387       return 0;
 388    }
 389
 390    switch (param) {
 391    /* Shader limits. */
 392    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 393    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 394    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 395    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 396    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 397       return 16384;
 398    case PIPE_SHADER_CAP_MAX_INPUTS:
 399       return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 400    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 401       return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 402    case PIPE_SHADER_CAP_MAX_TEMPS:
 403       return 256; /* Max native temporaries. */
 404    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 405       return MIN2(sscreen->info.max_alloc_size, INT_MAX - 3); /* aligned to 4 */
 406    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 407       return SI_NUM_CONST_BUFFERS;
 408    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 409    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 410       return SI_NUM_SAMPLERS;
 411    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 412       return SI_NUM_SHADER_BUFFERS;
 413    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 414       return SI_NUM_IMAGES;
 415    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 416       return 0;
 417    case PIPE_SHADER_CAP_PREFERRED_IR:
 418       return PIPE_SHADER_IR_NIR;
 419    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 420       return 4;
 421
 422    /* Supported boolean features. */
 423    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 424    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 425    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 426    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 427    case PIPE_SHADER_CAP_INTEGERS:
 428    case PIPE_SHADER_CAP_INT64_ATOMICS:
 429    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 430    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 431    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 432    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 433    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 434    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 435       return 1;
 436
 437    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 438       /* TODO: Indirect indexing of GS inputs is unimplemented. */
 439       if (shader == PIPE_SHADER_GEOMETRY)
 440          return 0;
 441
 442       if (shader == PIPE_SHADER_VERTEX && !sscreen->llvm_has_working_vgpr_indexing)
 443          return 0;
 444
 445       /* TCS and TES load inputs directly from LDS or offchip
 446        * memory, so indirect indexing is always supported.
 447        * PS has to support indirect indexing, because we can't
 448        * lower that to TEMPs for INTERP instructions.
 449        */
 450       return 1;
 451
 452    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 453       return sscreen->llvm_has_working_vgpr_indexing ||
 454              /* TCS stores outputs directly to memory. */
 455              shader == PIPE_SHADER_TESS_CTRL;
 456
 457    /* Unsupported boolean features. */
 458    case PIPE_SHADER_CAP_FP16:
 459    case PIPE_SHADER_CAP_SUBROUTINES:
 460    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 461    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 462    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 463       return 0;
 464    }
 465    return 0;
 466 }
 467
 468 static const struct nir_shader_compiler_options nir_options = {
 469    .lower_scmp = true,
 470    .lower_flrp32 = true,
 471    .lower_flrp64 = true,
 472    .lower_fsat = true,
 473    .lower_fdiv = true,
 474    .lower_bitfield_insert_to_bitfield_select = true,
 475    .lower_bitfield_extract = true,
 476    .lower_sub = true,
 477    .fuse_ffma = true,
 478    .lower_fmod = true,
 479    .lower_pack_snorm_4x8 = true,
 480    .lower_pack_unorm_4x8 = true,
 481    .lower_unpack_snorm_2x16 = true,
 482    .lower_unpack_snorm_4x8 = true,
 483    .lower_unpack_unorm_2x16 = true,
 484    .lower_unpack_unorm_4x8 = true,
 485    .lower_extract_byte = true,
 486    .lower_extract_word = true,
 487    .lower_rotate = true,
 488    .lower_to_scalar = true,
 489    .optimize_sample_mask_in = true,
 490    .max_unroll_iterations = 32,
 491    .use_interpolated_input_intrinsics = true,
 492 };
 493
 494 static const void *si_get_compiler_options(struct pipe_screen *screen, enum pipe_shader_ir ir,
 495                                            enum pipe_shader_type shader)
 496 {
 497    assert(ir == PIPE_SHADER_IR_NIR);
 498    return &nir_options;
 499 }
 500
 501 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 502 {
 503    ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 504 }
 505
 506 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 507 {
 508    struct si_screen *sscreen = (struct si_screen *)pscreen;
 509
 510    ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 511 }
 512
 513 static const char *si_get_name(struct pipe_screen *pscreen)
 514 {
 515    struct si_screen *sscreen = (struct si_screen *)pscreen;
 516
 517    return sscreen->renderer_string;
 518 }
 519
 520 static int si_get_video_param_no_decode(struct pipe_screen *screen, enum pipe_video_profile profile,
 521                                         enum pipe_video_entrypoint entrypoint,
 522                                         enum pipe_video_cap param)
 523 {
 524    switch (param) {
 525    case PIPE_VIDEO_CAP_SUPPORTED:
 526       return vl_profile_supported(screen, profile, entrypoint);
 527    case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 528       return 1;
 529    case PIPE_VIDEO_CAP_MAX_WIDTH:
 530    case PIPE_VIDEO_CAP_MAX_HEIGHT:
 531       return vl_video_buffer_max_size(screen);
 532    case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 533       return PIPE_FORMAT_NV12;
 534    case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 535       return false;
 536    case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 537       return false;
 538    case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 539       return true;
 540    case PIPE_VIDEO_CAP_MAX_LEVEL:
 541       return vl_level_supported(screen, profile);
 542    default:
 543       return 0;
 544    }
 545 }
 546
 547 static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profile profile,
 548                               enum pipe_video_entrypoint entrypoint, enum pipe_video_cap param)
 549 {
 550    struct si_screen *sscreen = (struct si_screen *)screen;
 551    enum pipe_video_format codec = u_reduce_video_profile(profile);
 552
 553    if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 554       switch (param) {
 555       case PIPE_VIDEO_CAP_SUPPORTED:
 556          return (
 557             (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 558              (sscreen->info.family >= CHIP_RAVEN || si_vce_is_fw_version_supported(sscreen))) ||
 559             (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 560              (sscreen->info.family >= CHIP_RAVEN || si_radeon_uvd_enc_supported(sscreen))) ||
 561             (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 && sscreen->info.family >= CHIP_RENOIR));
 562       case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 563          return 1;
 564       case PIPE_VIDEO_CAP_MAX_WIDTH:
 565          return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 566       case PIPE_VIDEO_CAP_MAX_HEIGHT:
 567          return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 568       case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 569          return PIPE_FORMAT_NV12;
 570       case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 571          return false;
 572       case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 573          return false;
 574       case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 575          return true;
 576       case PIPE_VIDEO_CAP_STACKED_FRAMES:
 577          return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 578       default:
 579          return 0;
 580       }
 581    }
 582
 583    switch (param) {
 584    case PIPE_VIDEO_CAP_SUPPORTED:
 585       switch (codec) {
 586       case PIPE_VIDEO_FORMAT_MPEG12:
 587          return profile != PIPE_VIDEO_PROFILE_MPEG1;
 588       case PIPE_VIDEO_FORMAT_MPEG4:
 589          return 1;
 590       case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 591          if ((sscreen->info.family == CHIP_POLARIS10 || sscreen->info.family == CHIP_POLARIS11) &&
 592              sscreen->info.uvd_fw_version < UVD_FW_1_66_16) {
 593             RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 594             return false;
 595          }
 596          return true;
 597       case PIPE_VIDEO_FORMAT_VC1:
 598          return true;
 599       case PIPE_VIDEO_FORMAT_HEVC:
 600          /* Carrizo only supports HEVC Main */
 601          if (sscreen->info.family >= CHIP_STONEY)
 602             return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 603                     profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 604          else if (sscreen->info.family >= CHIP_CARRIZO)
 605             return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 606          return false;
 607       case PIPE_VIDEO_FORMAT_JPEG:
 608          if (sscreen->info.family >= CHIP_RAVEN)
 609             return true;
 610          if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 611             return false;
 612          if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 19)) {
 613             RVID_ERR("No MJPEG support for the kernel version\n");
 614             return false;
 615          }
 616          return true;
 617       case PIPE_VIDEO_FORMAT_VP9:
 618          if (sscreen->info.family < CHIP_RAVEN)
 619             return false;
 620          return true;
 621       default:
 622          return false;
 623       }
 624    case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 625       return 1;
 626    case PIPE_VIDEO_CAP_MAX_WIDTH:
 627       switch (codec) {
 628       case PIPE_VIDEO_FORMAT_HEVC:
 629       case PIPE_VIDEO_FORMAT_VP9:
 630          return (sscreen->info.family < CHIP_RENOIR)
 631                    ? ((sscreen->info.family < CHIP_TONGA) ? 2048 : 4096)
 632                    : 8192;
 633       default:
 634          return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 635       }
 636    case PIPE_VIDEO_CAP_MAX_HEIGHT:
 637       switch (codec) {
 638       case PIPE_VIDEO_FORMAT_HEVC:
 639       case PIPE_VIDEO_FORMAT_VP9:
 640          return (sscreen->info.family < CHIP_RENOIR)
 641                    ? ((sscreen->info.family < CHIP_TONGA) ? 1152 : 4096)
 642                    : 4352;
 643       default:
 644          return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 645       }
 646    case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 647       if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 648          return PIPE_FORMAT_P010;
 649       else if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 650          return PIPE_FORMAT_P016;
 651       else
 652          return PIPE_FORMAT_NV12;
 653
 654    case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 655    case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 656       enum pipe_video_format format = u_reduce_video_profile(profile);
 657
 658       if (format == PIPE_VIDEO_FORMAT_HEVC)
 659          return false; // The firmware doesn't support interlaced HEVC.
 660       else if (format == PIPE_VIDEO_FORMAT_JPEG)
 661          return false;
 662       else if (format == PIPE_VIDEO_FORMAT_VP9)
 663          return false;
 664       return true;
 665    }
 666    case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 667       return true;
 668    case PIPE_VIDEO_CAP_MAX_LEVEL:
 669       switch (profile) {
 670       case PIPE_VIDEO_PROFILE_MPEG1:
 671          return 0;
 672       case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 673       case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 674          return 3;
 675       case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 676          return 3;
 677       case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 678          return 5;
 679       case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 680          return 1;
 681       case PIPE_VIDEO_PROFILE_VC1_MAIN:
 682          return 2;
 683       case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 684          return 4;
 685       case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 686       case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 687       case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 688          return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 689       case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 690       case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 691          return 186;
 692       default:
 693          return 0;
 694       }
 695    default:
 696       return 0;
 697    }
 698 }
 699
 700 static bool si_vid_is_format_supported(struct pipe_screen *screen, enum pipe_format format,
 701                                        enum pipe_video_profile profile,
 702                                        enum pipe_video_entrypoint entrypoint)
 703 {
 704    /* HEVC 10 bit decoding should use P010 instead of NV12 if possible */
 705    if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 706       return (format == PIPE_FORMAT_NV12) || (format == PIPE_FORMAT_P010) ||
 707              (format == PIPE_FORMAT_P016);
 708
 709    /* Vp9 profile 2 supports 10 bit decoding using P016 */
 710    if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 711       return format == PIPE_FORMAT_P016;
 712
 713    /* we can only handle this one with UVD */
 714    if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 715       return format == PIPE_FORMAT_NV12;
 716
 717    return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 718 }
 719
 720 static unsigned get_max_threads_per_block(struct si_screen *screen, enum pipe_shader_ir ir_type)
 721 {
 722    if (ir_type == PIPE_SHADER_IR_NATIVE)
 723       return 256;
 724
 725    /* LLVM 10 only supports 1024 threads per block. */
 726    return 1024;
 727 }
 728
 729 static int si_get_compute_param(struct pipe_screen *screen, enum pipe_shader_ir ir_type,
 730                                 enum pipe_compute_cap param, void *ret)
 731 {
 732    struct si_screen *sscreen = (struct si_screen *)screen;
 733
 734    // TODO: select these params by asic
 735    switch (param) {
 736    case PIPE_COMPUTE_CAP_IR_TARGET: {
 737       const char *gpu, *triple;
 738
 739       triple = "amdgcn-mesa-mesa3d";
 740       gpu = ac_get_llvm_processor_name(sscreen->info.family);
 741       if (ret) {
 742          sprintf(ret, "%s-%s", gpu, triple);
 743       }
 744       /* +2 for dash and terminating NIL byte */
 745       return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 746    }
 747    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 748       if (ret) {
 749          uint64_t *grid_dimension = ret;
 750          grid_dimension[0] = 3;
 751       }
 752       return 1 * sizeof(uint64_t);
 753
 754    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 755       if (ret) {
 756          uint64_t *grid_size = ret;
 757          grid_size[0] = 65535;
 758          grid_size[1] = 65535;
 759          grid_size[2] = 65535;
 760       }
 761       return 3 * sizeof(uint64_t);
 762
 763    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 764       if (ret) {
 765          uint64_t *block_size = ret;
 766          unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 767          block_size[0] = threads_per_block;
 768          block_size[1] = threads_per_block;
 769          block_size[2] = threads_per_block;
 770       }
 771       return 3 * sizeof(uint64_t);
 772
 773    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 774       if (ret) {
 775          uint64_t *max_threads_per_block = ret;
 776          *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 777       }
 778       return sizeof(uint64_t);
 779    case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 780       if (ret) {
 781          uint32_t *address_bits = ret;
 782          address_bits[0] = 64;
 783       }
 784       return 1 * sizeof(uint32_t);
 785
 786    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 787       if (ret) {
 788          uint64_t *max_global_size = ret;
 789          uint64_t max_mem_alloc_size;
 790
 791          si_get_compute_param(screen, ir_type, PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 792                               &max_mem_alloc_size);
 793
 794          /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 795           * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 796           * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 797           * make sure we never report more than
 798           * 4 * MAX_MEM_ALLOC_SIZE.
 799           */
 800          *max_global_size =
 801             MIN2(4 * max_mem_alloc_size, MAX2(sscreen->info.gart_size, sscreen->info.vram_size));
 802       }
 803       return sizeof(uint64_t);
 804
 805    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 806       if (ret) {
 807          uint64_t *max_local_size = ret;
 808          /* Value reported by the closed source driver. */
 809          *max_local_size = 32768;
 810       }
 811       return sizeof(uint64_t);
 812
 813    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 814       if (ret) {
 815          uint64_t *max_input_size = ret;
 816          /* Value reported by the closed source driver. */
 817          *max_input_size = 1024;
 818       }
 819       return sizeof(uint64_t);
 820
 821    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 822       if (ret) {
 823          uint64_t *max_mem_alloc_size = ret;
 824
 825          *max_mem_alloc_size = sscreen->info.max_alloc_size;
 826       }
 827       return sizeof(uint64_t);
 828
 829    case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 830       if (ret) {
 831          uint32_t *max_clock_frequency = ret;
 832          *max_clock_frequency = sscreen->info.max_shader_clock;
 833       }
 834       return sizeof(uint32_t);
 835
 836    case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 837       if (ret) {
 838          uint32_t *max_compute_units = ret;
 839          *max_compute_units = sscreen->info.num_good_compute_units;
 840       }
 841       return sizeof(uint32_t);
 842
 843    case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 844       if (ret) {
 845          uint32_t *images_supported = ret;
 846          *images_supported = 0;
 847       }
 848       return sizeof(uint32_t);
 849    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 850       break; /* unused */
 851    case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 852       if (ret) {
 853          uint32_t *subgroup_size = ret;
 854          *subgroup_size = sscreen->compute_wave_size;
 855       }
 856       return sizeof(uint32_t);
 857    case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 858       if (ret) {
 859          uint64_t *max_variable_threads_per_block = ret;
 860          if (ir_type == PIPE_SHADER_IR_NATIVE)
 861             *max_variable_threads_per_block = 0;
 862          else
 863             *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 864       }
 865       return sizeof(uint64_t);
 866    }
 867
 868    fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 869    return 0;
 870 }
 871
 872 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 873 {
 874    struct si_screen *sscreen = (struct si_screen *)screen;
 875
 876    return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 877           sscreen->info.clock_crystal_freq;
 878 }
 879
 880 static void si_query_memory_info(struct pipe_screen *screen, struct pipe_memory_info *info)
 881 {
 882    struct si_screen *sscreen = (struct si_screen *)screen;
 883    struct radeon_winsys *ws = sscreen->ws;
 884    unsigned vram_usage, gtt_usage;
 885
 886    info->total_device_memory = sscreen->info.vram_size / 1024;
 887    info->total_staging_memory = sscreen->info.gart_size / 1024;
 888
 889    /* The real TTM memory usage is somewhat random, because:
 890     *
 891     * 1) TTM delays freeing memory, because it can only free it after
 892     *    fences expire.
 893     *
 894     * 2) The memory usage can be really low if big VRAM evictions are
 895     *    taking place, but the real usage is well above the size of VRAM.
 896     *
 897     * Instead, return statistics of this process.
 898     */
 899    vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
 900    gtt_usage = ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
 901
 902    info->avail_device_memory =
 903       vram_usage <= info->total_device_memory ? info->total_device_memory - vram_usage : 0;
 904    info->avail_staging_memory =
 905       gtt_usage <= info->total_staging_memory ? info->total_staging_memory - gtt_usage : 0;
 906
 907    info->device_memory_evicted = ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 908
 909    if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 4)
 910       info->nr_device_memory_evictions = ws->query_value(ws, RADEON_NUM_EVICTIONS);
 911    else
 912       /* Just return the number of evicted 64KB pages. */
 913       info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 914 }
 915
 916 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 917 {
 918    struct si_screen *sscreen = (struct si_screen *)pscreen;
 919
 920    return sscreen->disk_shader_cache;
 921 }
 922
 923 static void si_init_renderer_string(struct si_screen *sscreen)
 924 {
 925    char first_name[256], second_name[32] = {}, kernel_version[128] = {};
 926    struct utsname uname_data;
 927
 928    if (sscreen->info.marketing_name) {
 929       snprintf(first_name, sizeof(first_name), "%s", sscreen->info.marketing_name);
 930       snprintf(second_name, sizeof(second_name), "%s, ", sscreen->info.name);
 931    } else {
 932       snprintf(first_name, sizeof(first_name), "AMD %s", sscreen->info.name);
 933    }
 934
 935    if (uname(&uname_data) == 0)
 936       snprintf(kernel_version, sizeof(kernel_version), ", %s", uname_data.release);
 937
 938    snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 939             "%s (%sDRM %i.%i.%i%s, LLVM " MESA_LLVM_VERSION_STRING ")", first_name, second_name,
 940             sscreen->info.drm_major, sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 941             kernel_version);
 942 }
 943
 944 void si_init_screen_get_functions(struct si_screen *sscreen)
 945 {
 946    sscreen->b.get_name = si_get_name;
 947    sscreen->b.get_vendor = si_get_vendor;
 948    sscreen->b.get_device_vendor = si_get_device_vendor;
 949    sscreen->b.get_param = si_get_param;
 950    sscreen->b.get_paramf = si_get_paramf;
 951    sscreen->b.get_compute_param = si_get_compute_param;
 952    sscreen->b.get_timestamp = si_get_timestamp;
 953    sscreen->b.get_shader_param = si_get_shader_param;
 954    sscreen->b.get_compiler_options = si_get_compiler_options;
 955    sscreen->b.get_device_uuid = si_get_device_uuid;
 956    sscreen->b.get_driver_uuid = si_get_driver_uuid;
 957    sscreen->b.query_memory_info = si_query_memory_info;
 958    sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
 959
 960    if (sscreen->info.has_hw_decode) {
 961       sscreen->b.get_video_param = si_get_video_param;
 962       sscreen->b.is_video_format_supported = si_vid_is_format_supported;
 963    } else {
 964       sscreen->b.get_video_param = si_get_video_param_no_decode;
 965       sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 966    }
 967
 968    si_init_renderer_string(sscreen);
 969 }