src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "radeon/radeon_video.h"
  27 #include "radeon/radeon_vce.h"
  28 #include "radeon/radeon_uvd_enc.h"
  29 #include "ac_llvm_util.h"
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32 #include "util/u_screen.h"
  33 #include "util/u_video.h"
  34 #include "compiler/nir/nir.h"
  35
  36 #include <sys/utsname.h>
  37
  38 static const char *si_get_vendor(struct pipe_screen *pscreen)
  39 {
  40         /* Don't change this. Games such as Alien Isolation are broken if this
  41          * returns "Advanced Micro Devices, Inc."
  42          */
  43         return "X.Org";
  44 }
  45
  46 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  47 {
  48         return "AMD";
  49 }
  50
  51 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  52 {
  53         struct si_screen *sscreen = (struct si_screen *)pscreen;
  54
  55         switch (param) {
  56         /* Supported features (boolean caps). */
  57         case PIPE_CAP_ACCELERATED:
  58         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  59         case PIPE_CAP_ANISOTROPIC_FILTER:
  60         case PIPE_CAP_POINT_SPRITE:
  61         case PIPE_CAP_OCCLUSION_QUERY:
  62         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  63         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  64         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  65         case PIPE_CAP_TEXTURE_SWIZZLE:
  66         case PIPE_CAP_DEPTH_CLIP_DISABLE:
  67         case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
  68         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  69         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  70         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  71         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  72         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  73         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  74         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
  75         case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
  76         case PIPE_CAP_VERTEX_SHADER_SATURATE:
  77         case PIPE_CAP_SEAMLESS_CUBE_MAP:
  78         case PIPE_CAP_PRIMITIVE_RESTART:
  79         case PIPE_CAP_CONDITIONAL_RENDER:
  80         case PIPE_CAP_TEXTURE_BARRIER:
  81         case PIPE_CAP_INDEP_BLEND_ENABLE:
  82         case PIPE_CAP_INDEP_BLEND_FUNC:
  83         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  84         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  85         case PIPE_CAP_START_INSTANCE:
  86         case PIPE_CAP_NPOT_TEXTURES:
  87         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  88         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  89         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
  90         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
  91         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  92         case PIPE_CAP_TGSI_INSTANCEID:
  93         case PIPE_CAP_COMPUTE:
  94         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  95         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
  96         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
  97         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  98         case PIPE_CAP_CUBE_MAP_ARRAY:
  99         case PIPE_CAP_SAMPLE_SHADING:
 100         case PIPE_CAP_DRAW_INDIRECT:
 101         case PIPE_CAP_CLIP_HALFZ:
 102         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 103         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 104         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 105         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 106         case PIPE_CAP_TGSI_TEXCOORD:
 107         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 108         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 109         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 110         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 111         case PIPE_CAP_SHAREABLE_SHADERS:
 112         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 113         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 114         case PIPE_CAP_TEXTURE_QUERY_LOD:
 115         case PIPE_CAP_TEXTURE_GATHER_SM5:
 116         case PIPE_CAP_TGSI_TXQS:
 117         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 118         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 119         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 120         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 121         case PIPE_CAP_INVALIDATE_BUFFER:
 122         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 123         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 124         case PIPE_CAP_QUERY_MEMORY_INFO:
 125         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 126         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 127         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 128         case PIPE_CAP_GENERATE_MIPMAP:
 129         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 130         case PIPE_CAP_STRING_MARKER:
 131         case PIPE_CAP_CLEAR_TEXTURE:
 132         case PIPE_CAP_CULL_DISTANCE:
 133         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 134         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 135         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 136         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 137         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 138         case PIPE_CAP_DOUBLES:
 139         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 140         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 141         case PIPE_CAP_BINDLESS_TEXTURE:
 142         case PIPE_CAP_QUERY_TIMESTAMP:
 143         case PIPE_CAP_QUERY_TIME_ELAPSED:
 144         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 145         case PIPE_CAP_MEMOBJ:
 146         case PIPE_CAP_LOAD_CONSTBUF:
 147         case PIPE_CAP_INT64:
 148         case PIPE_CAP_INT64_DIVMOD:
 149         case PIPE_CAP_TGSI_CLOCK:
 150         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 151         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 152         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 153         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 154         case PIPE_CAP_TGSI_BALLOT:
 155         case PIPE_CAP_TGSI_VOTE:
 156         case PIPE_CAP_FBFETCH:
 157         case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
 158         case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 159         case PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA:
 160         case PIPE_CAP_TGSI_DIV:
 161                 return 1;
 162
 163         case PIPE_CAP_QUERY_SO_OVERFLOW:
 164                 return !sscreen->use_ngg_streamout;
 165
 166         case PIPE_CAP_POST_DEPTH_COVERAGE:
 167                 return sscreen->info.chip_class >= GFX10;
 168
 169         case PIPE_CAP_GRAPHICS:
 170                 return sscreen->info.has_graphics;
 171
 172         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 173                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 174
 175         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 176                 return sscreen->info.has_gpu_reset_status_query;
 177
 178         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 179                 return sscreen->info.has_2d_tiling;
 180
 181         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 182                 return SI_MAP_BUFFER_ALIGNMENT;
 183
 184         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 185         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 186         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 187         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 188         case PIPE_CAP_MAX_VERTEX_STREAMS:
 189         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 190         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 191                 return 4;
 192
 193         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 194         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 195                 if (sscreen->info.has_indirect_compute_dispatch)
 196                                 return 450;
 197                 return 420;
 198
 199         case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 200                 /* Optimal number for good TexSubImage performance on Polaris10. */
 201                 return 64 * 1024 * 1024;
 202
 203         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 204         case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 205                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 206
 207         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 208         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 209         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 210                 return HAVE_LLVM < 0x0900 && !sscreen->info.has_unaligned_shader_loads;
 211
 212         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 213                 return sscreen->info.has_sparse_vm_mappings ?
 214                                 RADEON_SPARSE_PAGE_SIZE : 0;
 215
 216         case PIPE_CAP_PACKED_UNIFORMS:
 217         case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
 218                 if (sscreen->options.enable_nir)
 219                         return 1;
 220                 return 0;
 221
 222         case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
 223                 if (sscreen->options.enable_nir)
 224                         return 0;
 225                 return 1;
 226
 227         /* Unsupported features. */
 228         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 229         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 230         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 231         case PIPE_CAP_USER_VERTEX_BUFFERS:
 232         case PIPE_CAP_FAKE_SW_MSAA:
 233         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 234         case PIPE_CAP_VERTEXID_NOBASE:
 235         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 236         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 237         case PIPE_CAP_UMA:
 238         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 239         case PIPE_CAP_TILE_RASTER_ORDER:
 240         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 241         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 242         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 243         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 244         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 245         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 246         case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 247         case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 248         case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 249                 return 0;
 250
 251         case PIPE_CAP_FENCE_SIGNAL:
 252                 return sscreen->info.has_syncobj;
 253
 254         case PIPE_CAP_CONSTBUF0_FLAGS:
 255                 return SI_RESOURCE_FLAG_32BIT;
 256
 257         case PIPE_CAP_NATIVE_FENCE_FD:
 258                 return sscreen->info.has_fence_to_handle;
 259
 260         case PIPE_CAP_DRAW_PARAMETERS:
 261         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 262         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 263                 return sscreen->has_draw_indirect_multi;
 264
 265         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 266                 return 30;
 267
 268         case PIPE_CAP_MAX_VARYINGS:
 269                 return 32;
 270
 271         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 272                 return sscreen->info.chip_class <= GFX8 ?
 273                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 274
 275         /* Stream output. */
 276         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 277         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 278                 return 32*4;
 279
 280         /* Geometry shader output. */
 281         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 282                 /* gfx9 has to report 256 to make piglit/gs-max-output pass.
 283                  * gfx8 and earlier can do 1024.
 284                  */
 285                 return 256;
 286         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 287                 return 4095;
 288         case PIPE_CAP_MAX_GS_INVOCATIONS:
 289                 /* The closed driver exposes 127, but 125 is the greatest
 290                  * number that works. */
 291                 return 125;
 292
 293         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 294                 return 2048;
 295
 296         /* Texturing. */
 297         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 298                 return 16384;
 299         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 300                 return 15; /* 16384 */
 301         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 302                 if (sscreen->info.chip_class >= GFX10)
 303                         return 14;
 304                 /* textures support 8192, but layered rendering supports 2048 */
 305                 return 12;
 306         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 307                 if (sscreen->info.chip_class >= GFX10)
 308                         return 8192;
 309                 /* textures support 8192, but layered rendering supports 2048 */
 310                 return 2048;
 311
 312         /* Viewports and render targets. */
 313         case PIPE_CAP_MAX_VIEWPORTS:
 314                 return SI_MAX_VIEWPORTS;
 315         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 316         case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 317         case PIPE_CAP_MAX_RENDER_TARGETS:
 318                 return 8;
 319         case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 320                 return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
 321
 322         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 323         case PIPE_CAP_MIN_TEXEL_OFFSET:
 324                 return -32;
 325
 326         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 327         case PIPE_CAP_MAX_TEXEL_OFFSET:
 328                 return 31;
 329
 330         case PIPE_CAP_ENDIANNESS:
 331                 return PIPE_ENDIAN_LITTLE;
 332
 333         case PIPE_CAP_VENDOR_ID:
 334                 return ATI_VENDOR_ID;
 335         case PIPE_CAP_DEVICE_ID:
 336                 return sscreen->info.pci_id;
 337         case PIPE_CAP_VIDEO_MEMORY:
 338                 return sscreen->info.vram_size >> 20;
 339         case PIPE_CAP_PCI_GROUP:
 340                 return sscreen->info.pci_domain;
 341         case PIPE_CAP_PCI_BUS:
 342                 return sscreen->info.pci_bus;
 343         case PIPE_CAP_PCI_DEVICE:
 344                 return sscreen->info.pci_dev;
 345         case PIPE_CAP_PCI_FUNCTION:
 346                 return sscreen->info.pci_func;
 347         case PIPE_CAP_TGSI_ATOMINC_WRAP:
 348                 return HAVE_LLVM >= 0x1000;
 349
 350         default:
 351                 return u_pipe_screen_get_param_defaults(pscreen, param);
 352         }
 353 }
 354
 355 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 356 {
 357         switch (param) {
 358         case PIPE_CAPF_MAX_LINE_WIDTH:
 359         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 360                 /* This depends on the quant mode, though the precise interactions
 361                  * are unknown. */
 362                 return 2048;
 363         case PIPE_CAPF_MAX_POINT_WIDTH:
 364         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 365                 return SI_MAX_POINT_SIZE;
 366         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 367                 return 16.0f;
 368         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 369                 return 16.0f;
 370         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 371         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 372         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 373                 return 0.0f;
 374         }
 375         return 0.0f;
 376 }
 377
 378 static int si_get_shader_param(struct pipe_screen* pscreen,
 379                                enum pipe_shader_type shader,
 380                                enum pipe_shader_cap param)
 381 {
 382         struct si_screen *sscreen = (struct si_screen *)pscreen;
 383
 384         switch(shader)
 385         {
 386         case PIPE_SHADER_FRAGMENT:
 387         case PIPE_SHADER_VERTEX:
 388         case PIPE_SHADER_GEOMETRY:
 389         case PIPE_SHADER_TESS_CTRL:
 390         case PIPE_SHADER_TESS_EVAL:
 391                 break;
 392         case PIPE_SHADER_COMPUTE:
 393                 switch (param) {
 394                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 395                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 396
 397                         if (sscreen->info.has_indirect_compute_dispatch)
 398                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 399
 400                         return ir;
 401                 }
 402
 403                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 404                         uint64_t max_const_buffer_size;
 405                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 406                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 407                                 &max_const_buffer_size);
 408                         return MIN2(max_const_buffer_size, INT_MAX);
 409                 }
 410                 default:
 411                         /* If compute shaders don't require a special value
 412                          * for this cap, we can return the same value we
 413                          * do for other shader types. */
 414                         break;
 415                 }
 416                 break;
 417         default:
 418                 return 0;
 419         }
 420
 421         switch (param) {
 422         /* Shader limits. */
 423         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 424         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 425         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 426         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 427         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 428                 return 16384;
 429         case PIPE_SHADER_CAP_MAX_INPUTS:
 430                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 431         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 432                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 433         case PIPE_SHADER_CAP_MAX_TEMPS:
 434                 return 256; /* Max native temporaries. */
 435         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 436                 return MIN2(sscreen->info.max_alloc_size, INT_MAX - 3); /* aligned to 4 */
 437         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 438                 return SI_NUM_CONST_BUFFERS;
 439         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 440         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 441                 return SI_NUM_SAMPLERS;
 442         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 443                 return SI_NUM_SHADER_BUFFERS;
 444         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 445                 return SI_NUM_IMAGES;
 446         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 447                 if (sscreen->options.enable_nir)
 448                         return 0;
 449                 return 32;
 450         case PIPE_SHADER_CAP_PREFERRED_IR:
 451                 if (sscreen->options.enable_nir)
 452                         return PIPE_SHADER_IR_NIR;
 453                 return PIPE_SHADER_IR_TGSI;
 454         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 455                 return 4;
 456
 457         /* Supported boolean features. */
 458         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 459         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 460         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 461         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 462         case PIPE_SHADER_CAP_INTEGERS:
 463         case PIPE_SHADER_CAP_INT64_ATOMICS:
 464         case PIPE_SHADER_CAP_FP16:
 465         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 466         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 467         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 468         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 469         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 470         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 471                 return 1;
 472
 473         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 474                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 475                 if (shader == PIPE_SHADER_GEOMETRY)
 476                         return 0;
 477
 478                 if (shader == PIPE_SHADER_VERTEX &&
 479                     !sscreen->llvm_has_working_vgpr_indexing)
 480                         return 0;
 481
 482                 /* TCS and TES load inputs directly from LDS or offchip
 483                  * memory, so indirect indexing is always supported.
 484                  * PS has to support indirect indexing, because we can't
 485                  * lower that to TEMPs for INTERP instructions.
 486                  */
 487                 return 1;
 488
 489         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 490                 return sscreen->llvm_has_working_vgpr_indexing ||
 491                        /* TCS stores outputs directly to memory. */
 492                        shader == PIPE_SHADER_TESS_CTRL;
 493
 494         /* Unsupported boolean features. */
 495         case PIPE_SHADER_CAP_SUBROUTINES:
 496         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 497         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 498         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 499                 return 0;
 500         case PIPE_SHADER_CAP_SCALAR_ISA:
 501                 return 1;
 502         }
 503         return 0;
 504 }
 505
 506 static const struct nir_shader_compiler_options nir_options = {
 507         .lower_scmp = true,
 508         .lower_flrp32 = true,
 509         .lower_flrp64 = true,
 510         .lower_fsat = true,
 511         .lower_fdiv = true,
 512         .lower_bitfield_insert_to_bitfield_select = true,
 513         .lower_bitfield_extract = true,
 514         .lower_sub = true,
 515         .lower_ffma = true,
 516         .lower_fmod = true,
 517         .lower_pack_snorm_4x8 = true,
 518         .lower_pack_unorm_4x8 = true,
 519         .lower_unpack_snorm_2x16 = true,
 520         .lower_unpack_snorm_4x8 = true,
 521         .lower_unpack_unorm_2x16 = true,
 522         .lower_unpack_unorm_4x8 = true,
 523         .lower_extract_byte = true,
 524         .lower_extract_word = true,
 525         .lower_rotate = true,
 526         .optimize_sample_mask_in = true,
 527         .max_unroll_iterations = 32,
 528         .use_interpolated_input_intrinsics = true,
 529 };
 530
 531 static const void *
 532 si_get_compiler_options(struct pipe_screen *screen,
 533                         enum pipe_shader_ir ir,
 534                         enum pipe_shader_type shader)
 535 {
 536         assert(ir == PIPE_SHADER_IR_NIR);
 537         return &nir_options;
 538 }
 539
 540 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 541 {
 542         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 543 }
 544
 545 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 546 {
 547         struct si_screen *sscreen = (struct si_screen *)pscreen;
 548
 549         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 550 }
 551
 552 static const char* si_get_name(struct pipe_screen *pscreen)
 553 {
 554         struct si_screen *sscreen = (struct si_screen*)pscreen;
 555
 556         return sscreen->renderer_string;
 557 }
 558
 559 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 560                                         enum pipe_video_profile profile,
 561                                         enum pipe_video_entrypoint entrypoint,
 562                                         enum pipe_video_cap param)
 563 {
 564         switch (param) {
 565         case PIPE_VIDEO_CAP_SUPPORTED:
 566                 return vl_profile_supported(screen, profile, entrypoint);
 567         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 568                 return 1;
 569         case PIPE_VIDEO_CAP_MAX_WIDTH:
 570         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 571                 return vl_video_buffer_max_size(screen);
 572         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 573                 return PIPE_FORMAT_NV12;
 574         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 575                 return false;
 576         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 577                 return false;
 578         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 579                 return true;
 580         case PIPE_VIDEO_CAP_MAX_LEVEL:
 581                 return vl_level_supported(screen, profile);
 582         default:
 583                 return 0;
 584         }
 585 }
 586
 587 static int si_get_video_param(struct pipe_screen *screen,
 588                               enum pipe_video_profile profile,
 589                               enum pipe_video_entrypoint entrypoint,
 590                               enum pipe_video_cap param)
 591 {
 592         struct si_screen *sscreen = (struct si_screen *)screen;
 593         enum pipe_video_format codec = u_reduce_video_profile(profile);
 594
 595         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 596                 switch (param) {
 597                 case PIPE_VIDEO_CAP_SUPPORTED:
 598                         return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 599                                 (si_vce_is_fw_version_supported(sscreen) ||
 600                                 sscreen->info.family >= CHIP_RAVEN)) ||
 601                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 602                                 (sscreen->info.family >= CHIP_RAVEN ||
 603                                 si_radeon_uvd_enc_supported(sscreen)));
 604                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 605                         return 1;
 606                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 607                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 608                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 609                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 610                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 611                         return PIPE_FORMAT_NV12;
 612                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 613                         return false;
 614                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 615                         return false;
 616                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 617                         return true;
 618                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 619                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 620                 default:
 621                         return 0;
 622                 }
 623         }
 624
 625         switch (param) {
 626         case PIPE_VIDEO_CAP_SUPPORTED:
 627                 switch (codec) {
 628                 case PIPE_VIDEO_FORMAT_MPEG12:
 629                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 630                 case PIPE_VIDEO_FORMAT_MPEG4:
 631                         return 1;
 632                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 633                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 634                              sscreen->info.family == CHIP_POLARIS11) &&
 635                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 636                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 637                                 return false;
 638                         }
 639                         return true;
 640                 case PIPE_VIDEO_FORMAT_VC1:
 641                         return true;
 642                 case PIPE_VIDEO_FORMAT_HEVC:
 643                         /* Carrizo only supports HEVC Main */
 644                         if (sscreen->info.family >= CHIP_STONEY)
 645                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 646                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 647                         else if (sscreen->info.family >= CHIP_CARRIZO)
 648                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 649                         return false;
 650                 case PIPE_VIDEO_FORMAT_JPEG:
 651                         if (sscreen->info.family >= CHIP_RAVEN)
 652                                 return true;
 653                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 654                                 return false;
 655                         if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 19)) {
 656                                 RVID_ERR("No MJPEG support for the kernel version\n");
 657                                 return false;
 658                         }
 659                         return true;
 660                 case PIPE_VIDEO_FORMAT_VP9:
 661                         if (sscreen->info.family < CHIP_RAVEN)
 662                                 return false;
 663                         return true;
 664                 default:
 665                         return false;
 666                 }
 667         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 668                 return 1;
 669         case PIPE_VIDEO_CAP_MAX_WIDTH:
 670                 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 671         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 672                 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 673         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 674                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 ||
 675                     profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 676                         return PIPE_FORMAT_P016;
 677                 else
 678                         return PIPE_FORMAT_NV12;
 679
 680         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 681         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 682                 enum pipe_video_format format = u_reduce_video_profile(profile);
 683
 684                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 685                         return false; //The firmware doesn't support interlaced HEVC.
 686                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 687                         return false;
 688                 else if (format == PIPE_VIDEO_FORMAT_VP9)
 689                         return false;
 690                 return true;
 691         }
 692         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 693                 return true;
 694         case PIPE_VIDEO_CAP_MAX_LEVEL:
 695                 switch (profile) {
 696                 case PIPE_VIDEO_PROFILE_MPEG1:
 697                         return 0;
 698                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 699                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 700                         return 3;
 701                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 702                         return 3;
 703                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 704                         return 5;
 705                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 706                         return 1;
 707                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 708                         return 2;
 709                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 710                         return 4;
 711                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 712                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 713                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 714                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 715                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 716                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 717                         return 186;
 718                 default:
 719                         return 0;
 720                 }
 721         default:
 722                 return 0;
 723         }
 724 }
 725
 726 static bool si_vid_is_format_supported(struct pipe_screen *screen,
 727                                        enum pipe_format format,
 728                                        enum pipe_video_profile profile,
 729                                        enum pipe_video_entrypoint entrypoint)
 730 {
 731         /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
 732         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 733                 return (format == PIPE_FORMAT_NV12) ||
 734                         (format == PIPE_FORMAT_P016);
 735
 736         /* Vp9 profile 2 supports 10 bit decoding using P016 */
 737         if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 738                 return format == PIPE_FORMAT_P016;
 739
 740
 741         /* we can only handle this one with UVD */
 742         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 743                 return format == PIPE_FORMAT_NV12;
 744
 745         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 746 }
 747
 748 static unsigned get_max_threads_per_block(struct si_screen *screen,
 749                                           enum pipe_shader_ir ir_type)
 750 {
 751         if (ir_type == PIPE_SHADER_IR_NATIVE)
 752                 return 256;
 753
 754         /* Only 16 waves per thread-group on gfx9. */
 755         if (screen->info.chip_class >= GFX9)
 756                 return 1024;
 757
 758         /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
 759          * round number.
 760          */
 761         return 2048;
 762 }
 763
 764 static int si_get_compute_param(struct pipe_screen *screen,
 765                                 enum pipe_shader_ir ir_type,
 766                                 enum pipe_compute_cap param,
 767                                 void *ret)
 768 {
 769         struct si_screen *sscreen = (struct si_screen *)screen;
 770
 771         //TODO: select these params by asic
 772         switch (param) {
 773         case PIPE_COMPUTE_CAP_IR_TARGET: {
 774                 const char *gpu, *triple;
 775
 776                 triple = "amdgcn-mesa-mesa3d";
 777                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 778                 if (ret) {
 779                         sprintf(ret, "%s-%s", gpu, triple);
 780                 }
 781                 /* +2 for dash and terminating NIL byte */
 782                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 783         }
 784         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 785                 if (ret) {
 786                         uint64_t *grid_dimension = ret;
 787                         grid_dimension[0] = 3;
 788                 }
 789                 return 1 * sizeof(uint64_t);
 790
 791         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 792                 if (ret) {
 793                         uint64_t *grid_size = ret;
 794                         grid_size[0] = 65535;
 795                         grid_size[1] = 65535;
 796                         grid_size[2] = 65535;
 797                 }
 798                 return 3 * sizeof(uint64_t) ;
 799
 800         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 801                 if (ret) {
 802                         uint64_t *block_size = ret;
 803                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 804                         block_size[0] = threads_per_block;
 805                         block_size[1] = threads_per_block;
 806                         block_size[2] = threads_per_block;
 807                 }
 808                 return 3 * sizeof(uint64_t);
 809
 810         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 811                 if (ret) {
 812                         uint64_t *max_threads_per_block = ret;
 813                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 814                 }
 815                 return sizeof(uint64_t);
 816         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 817                 if (ret) {
 818                         uint32_t *address_bits = ret;
 819                         address_bits[0] = 64;
 820                 }
 821                 return 1 * sizeof(uint32_t);
 822
 823         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 824                 if (ret) {
 825                         uint64_t *max_global_size = ret;
 826                         uint64_t max_mem_alloc_size;
 827
 828                         si_get_compute_param(screen, ir_type,
 829                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 830                                 &max_mem_alloc_size);
 831
 832                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 833                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 834                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 835                          * make sure we never report more than
 836                          * 4 * MAX_MEM_ALLOC_SIZE.
 837                          */
 838                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 839                                                 MAX2(sscreen->info.gart_size,
 840                                                      sscreen->info.vram_size));
 841                 }
 842                 return sizeof(uint64_t);
 843
 844         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 845                 if (ret) {
 846                         uint64_t *max_local_size = ret;
 847                         /* Value reported by the closed source driver. */
 848                         *max_local_size = 32768;
 849                 }
 850                 return sizeof(uint64_t);
 851
 852         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 853                 if (ret) {
 854                         uint64_t *max_input_size = ret;
 855                         /* Value reported by the closed source driver. */
 856                         *max_input_size = 1024;
 857                 }
 858                 return sizeof(uint64_t);
 859
 860         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 861                 if (ret) {
 862                         uint64_t *max_mem_alloc_size = ret;
 863
 864                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 865                 }
 866                 return sizeof(uint64_t);
 867
 868         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 869                 if (ret) {
 870                         uint32_t *max_clock_frequency = ret;
 871                         *max_clock_frequency = sscreen->info.max_shader_clock;
 872                 }
 873                 return sizeof(uint32_t);
 874
 875         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 876                 if (ret) {
 877                         uint32_t *max_compute_units = ret;
 878                         *max_compute_units = sscreen->info.num_good_compute_units;
 879                 }
 880                 return sizeof(uint32_t);
 881
 882         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 883                 if (ret) {
 884                         uint32_t *images_supported = ret;
 885                         *images_supported = 0;
 886                 }
 887                 return sizeof(uint32_t);
 888         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 889                 break; /* unused */
 890         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 891                 if (ret) {
 892                         uint32_t *subgroup_size = ret;
 893                         *subgroup_size = sscreen->compute_wave_size;
 894                 }
 895                 return sizeof(uint32_t);
 896         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 897                 if (ret) {
 898                         uint64_t *max_variable_threads_per_block = ret;
 899                         if (ir_type == PIPE_SHADER_IR_NATIVE)
 900                                 *max_variable_threads_per_block = 0;
 901                         else
 902                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 903                 }
 904                 return sizeof(uint64_t);
 905         }
 906
 907         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 908         return 0;
 909 }
 910
 911 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 912 {
 913         struct si_screen *sscreen = (struct si_screen*)screen;
 914
 915         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 916                         sscreen->info.clock_crystal_freq;
 917 }
 918
 919 static void si_query_memory_info(struct pipe_screen *screen,
 920                                  struct pipe_memory_info *info)
 921 {
 922         struct si_screen *sscreen = (struct si_screen*)screen;
 923         struct radeon_winsys *ws = sscreen->ws;
 924         unsigned vram_usage, gtt_usage;
 925
 926         info->total_device_memory = sscreen->info.vram_size / 1024;
 927         info->total_staging_memory = sscreen->info.gart_size / 1024;
 928
 929         /* The real TTM memory usage is somewhat random, because:
 930          *
 931          * 1) TTM delays freeing memory, because it can only free it after
 932          *    fences expire.
 933          *
 934          * 2) The memory usage can be really low if big VRAM evictions are
 935          *    taking place, but the real usage is well above the size of VRAM.
 936          *
 937          * Instead, return statistics of this process.
 938          */
 939         vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
 940         gtt_usage =  ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
 941
 942         info->avail_device_memory =
 943                 vram_usage <= info->total_device_memory ?
 944                                 info->total_device_memory - vram_usage : 0;
 945         info->avail_staging_memory =
 946                 gtt_usage <= info->total_staging_memory ?
 947                                 info->total_staging_memory - gtt_usage : 0;
 948
 949         info->device_memory_evicted =
 950                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 951
 952         if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 4)
 953                 info->nr_device_memory_evictions =
 954                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 955         else
 956                 /* Just return the number of evicted 64KB pages. */
 957                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 958 }
 959
 960 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 961 {
 962         struct si_screen *sscreen = (struct si_screen*)pscreen;
 963
 964         return sscreen->disk_shader_cache;
 965 }
 966
 967 static void si_init_renderer_string(struct si_screen *sscreen)
 968 {
 969         char first_name[256], second_name[32] = {}, kernel_version[128] = {};
 970         struct utsname uname_data;
 971
 972         if (sscreen->info.marketing_name) {
 973                 snprintf(first_name, sizeof(first_name), "%s",
 974                          sscreen->info.marketing_name);
 975                 snprintf(second_name, sizeof(second_name), "%s, ",
 976                          sscreen->info.name);
 977         } else {
 978                 snprintf(first_name, sizeof(first_name), "AMD %s",
 979                          sscreen->info.name);
 980         }
 981
 982         if (uname(&uname_data) == 0)
 983                 snprintf(kernel_version, sizeof(kernel_version),
 984                          ", %s", uname_data.release);
 985
 986         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 987                  "%s (%sDRM %i.%i.%i%s, LLVM " MESA_LLVM_VERSION_STRING ")",
 988                  first_name, second_name, sscreen->info.drm_major,
 989                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 990                  kernel_version);
 991 }
 992
 993 void si_init_screen_get_functions(struct si_screen *sscreen)
 994 {
 995         sscreen->b.get_name = si_get_name;
 996         sscreen->b.get_vendor = si_get_vendor;
 997         sscreen->b.get_device_vendor = si_get_device_vendor;
 998         sscreen->b.get_param = si_get_param;
 999         sscreen->b.get_paramf = si_get_paramf;
1000         sscreen->b.get_compute_param = si_get_compute_param;
1001         sscreen->b.get_timestamp = si_get_timestamp;
1002         sscreen->b.get_shader_param = si_get_shader_param;
1003         sscreen->b.get_compiler_options = si_get_compiler_options;
1004         sscreen->b.get_device_uuid = si_get_device_uuid;
1005         sscreen->b.get_driver_uuid = si_get_driver_uuid;
1006         sscreen->b.query_memory_info = si_query_memory_info;
1007         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
1008
1009         if (sscreen->info.has_hw_decode) {
1010                 sscreen->b.get_video_param = si_get_video_param;
1011                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
1012         } else {
1013                 sscreen->b.get_video_param = si_get_video_param_no_decode;
1014                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1015         }
1016
1017         si_init_renderer_string(sscreen);
1018 }