src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "radeon/radeon_video.h"
  27 #include "radeon/radeon_vce.h"
  28 #include "radeon/radeon_uvd_enc.h"
  29 #include "ac_llvm_util.h"
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32 #include "util/u_screen.h"
  33 #include "util/u_video.h"
  34 #include "compiler/nir/nir.h"
  35
  36 #include <llvm/Config/llvm-config.h>
  37 #include <sys/utsname.h>
  38
  39 static const char *si_get_vendor(struct pipe_screen *pscreen)
  40 {
  41         /* Don't change this. Games such as Alien Isolation are broken if this
  42          * returns "Advanced Micro Devices, Inc."
  43          */
  44         return "X.Org";
  45 }
  46
  47 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  48 {
  49         return "AMD";
  50 }
  51
  52 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  53 {
  54         struct si_screen *sscreen = (struct si_screen *)pscreen;
  55
  56         switch (param) {
  57         /* Supported features (boolean caps). */
  58         case PIPE_CAP_ACCELERATED:
  59         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  60         case PIPE_CAP_ANISOTROPIC_FILTER:
  61         case PIPE_CAP_POINT_SPRITE:
  62         case PIPE_CAP_OCCLUSION_QUERY:
  63         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  64         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  65         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  66         case PIPE_CAP_TEXTURE_SWIZZLE:
  67         case PIPE_CAP_DEPTH_CLIP_DISABLE:
  68         case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
  69         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  70         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  71         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  72         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  73         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  74         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  75         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
  76         case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
  77         case PIPE_CAP_VERTEX_SHADER_SATURATE:
  78         case PIPE_CAP_SEAMLESS_CUBE_MAP:
  79         case PIPE_CAP_PRIMITIVE_RESTART:
  80         case PIPE_CAP_CONDITIONAL_RENDER:
  81         case PIPE_CAP_TEXTURE_BARRIER:
  82         case PIPE_CAP_INDEP_BLEND_ENABLE:
  83         case PIPE_CAP_INDEP_BLEND_FUNC:
  84         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  85         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  86         case PIPE_CAP_START_INSTANCE:
  87         case PIPE_CAP_NPOT_TEXTURES:
  88         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  89         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  90         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
  91         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
  92         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  93         case PIPE_CAP_TGSI_INSTANCEID:
  94         case PIPE_CAP_COMPUTE:
  95         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  96         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
  97         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
  98         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  99         case PIPE_CAP_CUBE_MAP_ARRAY:
 100         case PIPE_CAP_SAMPLE_SHADING:
 101         case PIPE_CAP_DRAW_INDIRECT:
 102         case PIPE_CAP_CLIP_HALFZ:
 103         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 104         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 105         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 106         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 107         case PIPE_CAP_TGSI_TEXCOORD:
 108         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 109         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 110         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 111         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 112         case PIPE_CAP_SHAREABLE_SHADERS:
 113         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 114         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 115         case PIPE_CAP_TEXTURE_QUERY_LOD:
 116         case PIPE_CAP_TEXTURE_GATHER_SM5:
 117         case PIPE_CAP_TGSI_TXQS:
 118         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 119         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 120         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 121         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 122         case PIPE_CAP_INVALIDATE_BUFFER:
 123         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 124         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 125         case PIPE_CAP_QUERY_MEMORY_INFO:
 126         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 127         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 128         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 129         case PIPE_CAP_GENERATE_MIPMAP:
 130         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 131         case PIPE_CAP_STRING_MARKER:
 132         case PIPE_CAP_CLEAR_TEXTURE:
 133         case PIPE_CAP_CULL_DISTANCE:
 134         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 135         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 136         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 137         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 138         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 139         case PIPE_CAP_DOUBLES:
 140         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 141         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 142         case PIPE_CAP_BINDLESS_TEXTURE:
 143         case PIPE_CAP_QUERY_TIMESTAMP:
 144         case PIPE_CAP_QUERY_TIME_ELAPSED:
 145         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 146         case PIPE_CAP_MEMOBJ:
 147         case PIPE_CAP_LOAD_CONSTBUF:
 148         case PIPE_CAP_INT64:
 149         case PIPE_CAP_INT64_DIVMOD:
 150         case PIPE_CAP_TGSI_CLOCK:
 151         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 152         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 153         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 154         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 155         case PIPE_CAP_TGSI_BALLOT:
 156         case PIPE_CAP_TGSI_VOTE:
 157         case PIPE_CAP_FBFETCH:
 158         case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
 159         case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 160         case PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA:
 161         case PIPE_CAP_TGSI_DIV:
 162                 return 1;
 163
 164         case PIPE_CAP_QUERY_SO_OVERFLOW:
 165                 return !sscreen->use_ngg_streamout;
 166
 167         case PIPE_CAP_POST_DEPTH_COVERAGE:
 168                 return sscreen->info.chip_class >= GFX10;
 169
 170         case PIPE_CAP_GRAPHICS:
 171                 return sscreen->info.has_graphics;
 172
 173         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 174                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 175
 176         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 177                 return sscreen->info.has_gpu_reset_status_query;
 178
 179         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 180                 return sscreen->info.has_2d_tiling;
 181
 182         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 183                 return SI_MAP_BUFFER_ALIGNMENT;
 184
 185         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 186         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 187         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 188         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 189         case PIPE_CAP_MAX_VERTEX_STREAMS:
 190         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 191         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 192                 return 4;
 193
 194         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 195         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 196                 if (sscreen->info.has_indirect_compute_dispatch)
 197                                 return 450;
 198                 return 420;
 199
 200         case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 201                 /* Optimal number for good TexSubImage performance on Polaris10. */
 202                 return 64 * 1024 * 1024;
 203
 204         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 205         case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 206                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 207
 208         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 209         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 210         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 211                 return LLVM_VERSION_MAJOR < 9 && !sscreen->info.has_unaligned_shader_loads;
 212
 213         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 214                 return sscreen->info.has_sparse_vm_mappings ?
 215                                 RADEON_SPARSE_PAGE_SIZE : 0;
 216
 217         case PIPE_CAP_PACKED_UNIFORMS:
 218         case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
 219                 if (sscreen->options.enable_nir)
 220                         return 1;
 221                 return 0;
 222
 223         case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
 224                 if (sscreen->options.enable_nir)
 225                         return 0;
 226                 return 1;
 227
 228         /* Unsupported features. */
 229         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 230         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 231         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 232         case PIPE_CAP_USER_VERTEX_BUFFERS:
 233         case PIPE_CAP_FAKE_SW_MSAA:
 234         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 235         case PIPE_CAP_VERTEXID_NOBASE:
 236         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 237         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 238         case PIPE_CAP_UMA:
 239         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 240         case PIPE_CAP_TILE_RASTER_ORDER:
 241         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 242         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 243         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 244         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 245         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 246         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 247         case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 248         case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 249         case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 250                 return 0;
 251
 252         case PIPE_CAP_FENCE_SIGNAL:
 253                 return sscreen->info.has_syncobj;
 254
 255         case PIPE_CAP_CONSTBUF0_FLAGS:
 256                 return SI_RESOURCE_FLAG_32BIT;
 257
 258         case PIPE_CAP_NATIVE_FENCE_FD:
 259                 return sscreen->info.has_fence_to_handle;
 260
 261         case PIPE_CAP_DRAW_PARAMETERS:
 262         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 263         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 264                 return sscreen->has_draw_indirect_multi;
 265
 266         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 267                 return 30;
 268
 269         case PIPE_CAP_MAX_VARYINGS:
 270                 return 32;
 271
 272         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 273                 return sscreen->info.chip_class <= GFX8 ?
 274                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 275
 276         /* Stream output. */
 277         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 278         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 279                 return 32*4;
 280
 281         /* Geometry shader output. */
 282         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 283                 /* gfx9 has to report 256 to make piglit/gs-max-output pass.
 284                  * gfx8 and earlier can do 1024.
 285                  */
 286                 return 256;
 287         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 288                 return 4095;
 289         case PIPE_CAP_MAX_GS_INVOCATIONS:
 290                 /* The closed driver exposes 127, but 125 is the greatest
 291                  * number that works. */
 292                 return 125;
 293
 294         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 295                 return 2048;
 296
 297         /* Texturing. */
 298         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 299                 return 16384;
 300         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 301                 return 15; /* 16384 */
 302         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 303                 if (sscreen->info.chip_class >= GFX10)
 304                         return 14;
 305                 /* textures support 8192, but layered rendering supports 2048 */
 306                 return 12;
 307         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 308                 if (sscreen->info.chip_class >= GFX10)
 309                         return 8192;
 310                 /* textures support 8192, but layered rendering supports 2048 */
 311                 return 2048;
 312
 313         /* Viewports and render targets. */
 314         case PIPE_CAP_MAX_VIEWPORTS:
 315                 return SI_MAX_VIEWPORTS;
 316         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 317         case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 318         case PIPE_CAP_MAX_RENDER_TARGETS:
 319                 return 8;
 320         case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 321                 return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
 322
 323         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 324         case PIPE_CAP_MIN_TEXEL_OFFSET:
 325                 return -32;
 326
 327         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 328         case PIPE_CAP_MAX_TEXEL_OFFSET:
 329                 return 31;
 330
 331         case PIPE_CAP_ENDIANNESS:
 332                 return PIPE_ENDIAN_LITTLE;
 333
 334         case PIPE_CAP_VENDOR_ID:
 335                 return ATI_VENDOR_ID;
 336         case PIPE_CAP_DEVICE_ID:
 337                 return sscreen->info.pci_id;
 338         case PIPE_CAP_VIDEO_MEMORY:
 339                 return sscreen->info.vram_size >> 20;
 340         case PIPE_CAP_PCI_GROUP:
 341                 return sscreen->info.pci_domain;
 342         case PIPE_CAP_PCI_BUS:
 343                 return sscreen->info.pci_bus;
 344         case PIPE_CAP_PCI_DEVICE:
 345                 return sscreen->info.pci_dev;
 346         case PIPE_CAP_PCI_FUNCTION:
 347                 return sscreen->info.pci_func;
 348         case PIPE_CAP_TGSI_ATOMINC_WRAP:
 349                 return LLVM_VERSION_MAJOR >= 10;
 350
 351         default:
 352                 return u_pipe_screen_get_param_defaults(pscreen, param);
 353         }
 354 }
 355
 356 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 357 {
 358         switch (param) {
 359         case PIPE_CAPF_MAX_LINE_WIDTH:
 360         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 361                 /* This depends on the quant mode, though the precise interactions
 362                  * are unknown. */
 363                 return 2048;
 364         case PIPE_CAPF_MAX_POINT_WIDTH:
 365         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 366                 return SI_MAX_POINT_SIZE;
 367         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 368                 return 16.0f;
 369         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 370                 return 16.0f;
 371         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 372         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 373         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 374                 return 0.0f;
 375         }
 376         return 0.0f;
 377 }
 378
 379 static int si_get_shader_param(struct pipe_screen* pscreen,
 380                                enum pipe_shader_type shader,
 381                                enum pipe_shader_cap param)
 382 {
 383         struct si_screen *sscreen = (struct si_screen *)pscreen;
 384
 385         switch(shader)
 386         {
 387         case PIPE_SHADER_FRAGMENT:
 388         case PIPE_SHADER_VERTEX:
 389         case PIPE_SHADER_GEOMETRY:
 390         case PIPE_SHADER_TESS_CTRL:
 391         case PIPE_SHADER_TESS_EVAL:
 392                 break;
 393         case PIPE_SHADER_COMPUTE:
 394                 switch (param) {
 395                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 396                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 397
 398                         if (sscreen->info.has_indirect_compute_dispatch)
 399                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 400
 401                         return ir;
 402                 }
 403
 404                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 405                         uint64_t max_const_buffer_size;
 406                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 407                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 408                                 &max_const_buffer_size);
 409                         return MIN2(max_const_buffer_size, INT_MAX);
 410                 }
 411                 default:
 412                         /* If compute shaders don't require a special value
 413                          * for this cap, we can return the same value we
 414                          * do for other shader types. */
 415                         break;
 416                 }
 417                 break;
 418         default:
 419                 return 0;
 420         }
 421
 422         switch (param) {
 423         /* Shader limits. */
 424         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 425         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 426         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 427         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 428         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 429                 return 16384;
 430         case PIPE_SHADER_CAP_MAX_INPUTS:
 431                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 432         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 433                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 434         case PIPE_SHADER_CAP_MAX_TEMPS:
 435                 return 256; /* Max native temporaries. */
 436         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 437                 return MIN2(sscreen->info.max_alloc_size, INT_MAX - 3); /* aligned to 4 */
 438         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 439                 return SI_NUM_CONST_BUFFERS;
 440         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 441         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 442                 return SI_NUM_SAMPLERS;
 443         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 444                 return SI_NUM_SHADER_BUFFERS;
 445         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 446                 return SI_NUM_IMAGES;
 447         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 448                 if (sscreen->options.enable_nir)
 449                         return 0;
 450                 return 32;
 451         case PIPE_SHADER_CAP_PREFERRED_IR:
 452                 if (sscreen->options.enable_nir)
 453                         return PIPE_SHADER_IR_NIR;
 454                 return PIPE_SHADER_IR_TGSI;
 455         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 456                 return 4;
 457
 458         /* Supported boolean features. */
 459         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 460         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 461         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 462         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 463         case PIPE_SHADER_CAP_INTEGERS:
 464         case PIPE_SHADER_CAP_INT64_ATOMICS:
 465         case PIPE_SHADER_CAP_FP16:
 466         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 467         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 468         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 469         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 470         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 471         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 472                 return 1;
 473
 474         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 475                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 476                 if (shader == PIPE_SHADER_GEOMETRY)
 477                         return 0;
 478
 479                 if (shader == PIPE_SHADER_VERTEX &&
 480                     !sscreen->llvm_has_working_vgpr_indexing)
 481                         return 0;
 482
 483                 /* TCS and TES load inputs directly from LDS or offchip
 484                  * memory, so indirect indexing is always supported.
 485                  * PS has to support indirect indexing, because we can't
 486                  * lower that to TEMPs for INTERP instructions.
 487                  */
 488                 return 1;
 489
 490         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 491                 return sscreen->llvm_has_working_vgpr_indexing ||
 492                        /* TCS stores outputs directly to memory. */
 493                        shader == PIPE_SHADER_TESS_CTRL;
 494
 495         /* Unsupported boolean features. */
 496         case PIPE_SHADER_CAP_SUBROUTINES:
 497         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 498         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 499         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 500                 return 0;
 501         case PIPE_SHADER_CAP_SCALAR_ISA:
 502                 return 1;
 503         }
 504         return 0;
 505 }
 506
 507 static const struct nir_shader_compiler_options nir_options = {
 508         .lower_scmp = true,
 509         .lower_flrp32 = true,
 510         .lower_flrp64 = true,
 511         .lower_fsat = true,
 512         .lower_fdiv = true,
 513         .lower_bitfield_insert_to_bitfield_select = true,
 514         .lower_bitfield_extract = true,
 515         .lower_sub = true,
 516         .lower_ffma = true,
 517         .lower_fmod = true,
 518         .lower_pack_snorm_4x8 = true,
 519         .lower_pack_unorm_4x8 = true,
 520         .lower_unpack_snorm_2x16 = true,
 521         .lower_unpack_snorm_4x8 = true,
 522         .lower_unpack_unorm_2x16 = true,
 523         .lower_unpack_unorm_4x8 = true,
 524         .lower_extract_byte = true,
 525         .lower_extract_word = true,
 526         .lower_rotate = true,
 527         .optimize_sample_mask_in = true,
 528         .max_unroll_iterations = 32,
 529         .use_interpolated_input_intrinsics = true,
 530 };
 531
 532 static const void *
 533 si_get_compiler_options(struct pipe_screen *screen,
 534                         enum pipe_shader_ir ir,
 535                         enum pipe_shader_type shader)
 536 {
 537         assert(ir == PIPE_SHADER_IR_NIR);
 538         return &nir_options;
 539 }
 540
 541 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 542 {
 543         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 544 }
 545
 546 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 547 {
 548         struct si_screen *sscreen = (struct si_screen *)pscreen;
 549
 550         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 551 }
 552
 553 static const char* si_get_name(struct pipe_screen *pscreen)
 554 {
 555         struct si_screen *sscreen = (struct si_screen*)pscreen;
 556
 557         return sscreen->renderer_string;
 558 }
 559
 560 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 561                                         enum pipe_video_profile profile,
 562                                         enum pipe_video_entrypoint entrypoint,
 563                                         enum pipe_video_cap param)
 564 {
 565         switch (param) {
 566         case PIPE_VIDEO_CAP_SUPPORTED:
 567                 return vl_profile_supported(screen, profile, entrypoint);
 568         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 569                 return 1;
 570         case PIPE_VIDEO_CAP_MAX_WIDTH:
 571         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 572                 return vl_video_buffer_max_size(screen);
 573         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 574                 return PIPE_FORMAT_NV12;
 575         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 576                 return false;
 577         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 578                 return false;
 579         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 580                 return true;
 581         case PIPE_VIDEO_CAP_MAX_LEVEL:
 582                 return vl_level_supported(screen, profile);
 583         default:
 584                 return 0;
 585         }
 586 }
 587
 588 static int si_get_video_param(struct pipe_screen *screen,
 589                               enum pipe_video_profile profile,
 590                               enum pipe_video_entrypoint entrypoint,
 591                               enum pipe_video_cap param)
 592 {
 593         struct si_screen *sscreen = (struct si_screen *)screen;
 594         enum pipe_video_format codec = u_reduce_video_profile(profile);
 595
 596         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 597                 switch (param) {
 598                 case PIPE_VIDEO_CAP_SUPPORTED:
 599                         return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 600                                 (si_vce_is_fw_version_supported(sscreen) ||
 601                                 sscreen->info.family >= CHIP_RAVEN)) ||
 602                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 603                                 (sscreen->info.family >= CHIP_RAVEN ||
 604                                 si_radeon_uvd_enc_supported(sscreen)));
 605                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 606                         return 1;
 607                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 608                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 609                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 610                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 611                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 612                         return PIPE_FORMAT_NV12;
 613                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 614                         return false;
 615                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 616                         return false;
 617                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 618                         return true;
 619                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 620                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 621                 default:
 622                         return 0;
 623                 }
 624         }
 625
 626         switch (param) {
 627         case PIPE_VIDEO_CAP_SUPPORTED:
 628                 switch (codec) {
 629                 case PIPE_VIDEO_FORMAT_MPEG12:
 630                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 631                 case PIPE_VIDEO_FORMAT_MPEG4:
 632                         return 1;
 633                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 634                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 635                              sscreen->info.family == CHIP_POLARIS11) &&
 636                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 637                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 638                                 return false;
 639                         }
 640                         return true;
 641                 case PIPE_VIDEO_FORMAT_VC1:
 642                         return true;
 643                 case PIPE_VIDEO_FORMAT_HEVC:
 644                         /* Carrizo only supports HEVC Main */
 645                         if (sscreen->info.family >= CHIP_STONEY)
 646                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 647                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 648                         else if (sscreen->info.family >= CHIP_CARRIZO)
 649                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 650                         return false;
 651                 case PIPE_VIDEO_FORMAT_JPEG:
 652                         if (sscreen->info.family >= CHIP_RAVEN)
 653                                 return true;
 654                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 655                                 return false;
 656                         if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 19)) {
 657                                 RVID_ERR("No MJPEG support for the kernel version\n");
 658                                 return false;
 659                         }
 660                         return true;
 661                 case PIPE_VIDEO_FORMAT_VP9:
 662                         if (sscreen->info.family < CHIP_RAVEN)
 663                                 return false;
 664                         return true;
 665                 default:
 666                         return false;
 667                 }
 668         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 669                 return 1;
 670         case PIPE_VIDEO_CAP_MAX_WIDTH:
 671                 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 672         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 673                 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 674         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 675                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 ||
 676                     profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 677                         return PIPE_FORMAT_P016;
 678                 else
 679                         return PIPE_FORMAT_NV12;
 680
 681         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 682         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 683                 enum pipe_video_format format = u_reduce_video_profile(profile);
 684
 685                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 686                         return false; //The firmware doesn't support interlaced HEVC.
 687                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 688                         return false;
 689                 else if (format == PIPE_VIDEO_FORMAT_VP9)
 690                         return false;
 691                 return true;
 692         }
 693         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 694                 return true;
 695         case PIPE_VIDEO_CAP_MAX_LEVEL:
 696                 switch (profile) {
 697                 case PIPE_VIDEO_PROFILE_MPEG1:
 698                         return 0;
 699                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 700                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 701                         return 3;
 702                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 703                         return 3;
 704                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 705                         return 5;
 706                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 707                         return 1;
 708                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 709                         return 2;
 710                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 711                         return 4;
 712                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 713                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 714                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 715                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 716                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 717                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 718                         return 186;
 719                 default:
 720                         return 0;
 721                 }
 722         default:
 723                 return 0;
 724         }
 725 }
 726
 727 static bool si_vid_is_format_supported(struct pipe_screen *screen,
 728                                        enum pipe_format format,
 729                                        enum pipe_video_profile profile,
 730                                        enum pipe_video_entrypoint entrypoint)
 731 {
 732         /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
 733         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 734                 return (format == PIPE_FORMAT_NV12) ||
 735                         (format == PIPE_FORMAT_P016);
 736
 737         /* Vp9 profile 2 supports 10 bit decoding using P016 */
 738         if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 739                 return format == PIPE_FORMAT_P016;
 740
 741
 742         /* we can only handle this one with UVD */
 743         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 744                 return format == PIPE_FORMAT_NV12;
 745
 746         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 747 }
 748
 749 static unsigned get_max_threads_per_block(struct si_screen *screen,
 750                                           enum pipe_shader_ir ir_type)
 751 {
 752         if (ir_type == PIPE_SHADER_IR_NATIVE)
 753                 return 256;
 754
 755         /* LLVM 10 only supports 1024 threads per block. */
 756         return 1024;
 757 }
 758
 759 static int si_get_compute_param(struct pipe_screen *screen,
 760                                 enum pipe_shader_ir ir_type,
 761                                 enum pipe_compute_cap param,
 762                                 void *ret)
 763 {
 764         struct si_screen *sscreen = (struct si_screen *)screen;
 765
 766         //TODO: select these params by asic
 767         switch (param) {
 768         case PIPE_COMPUTE_CAP_IR_TARGET: {
 769                 const char *gpu, *triple;
 770
 771                 triple = "amdgcn-mesa-mesa3d";
 772                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 773                 if (ret) {
 774                         sprintf(ret, "%s-%s", gpu, triple);
 775                 }
 776                 /* +2 for dash and terminating NIL byte */
 777                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 778         }
 779         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 780                 if (ret) {
 781                         uint64_t *grid_dimension = ret;
 782                         grid_dimension[0] = 3;
 783                 }
 784                 return 1 * sizeof(uint64_t);
 785
 786         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 787                 if (ret) {
 788                         uint64_t *grid_size = ret;
 789                         grid_size[0] = 65535;
 790                         grid_size[1] = 65535;
 791                         grid_size[2] = 65535;
 792                 }
 793                 return 3 * sizeof(uint64_t) ;
 794
 795         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 796                 if (ret) {
 797                         uint64_t *block_size = ret;
 798                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 799                         block_size[0] = threads_per_block;
 800                         block_size[1] = threads_per_block;
 801                         block_size[2] = threads_per_block;
 802                 }
 803                 return 3 * sizeof(uint64_t);
 804
 805         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 806                 if (ret) {
 807                         uint64_t *max_threads_per_block = ret;
 808                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 809                 }
 810                 return sizeof(uint64_t);
 811         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 812                 if (ret) {
 813                         uint32_t *address_bits = ret;
 814                         address_bits[0] = 64;
 815                 }
 816                 return 1 * sizeof(uint32_t);
 817
 818         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 819                 if (ret) {
 820                         uint64_t *max_global_size = ret;
 821                         uint64_t max_mem_alloc_size;
 822
 823                         si_get_compute_param(screen, ir_type,
 824                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 825                                 &max_mem_alloc_size);
 826
 827                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 828                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 829                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 830                          * make sure we never report more than
 831                          * 4 * MAX_MEM_ALLOC_SIZE.
 832                          */
 833                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 834                                                 MAX2(sscreen->info.gart_size,
 835                                                      sscreen->info.vram_size));
 836                 }
 837                 return sizeof(uint64_t);
 838
 839         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 840                 if (ret) {
 841                         uint64_t *max_local_size = ret;
 842                         /* Value reported by the closed source driver. */
 843                         *max_local_size = 32768;
 844                 }
 845                 return sizeof(uint64_t);
 846
 847         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 848                 if (ret) {
 849                         uint64_t *max_input_size = ret;
 850                         /* Value reported by the closed source driver. */
 851                         *max_input_size = 1024;
 852                 }
 853                 return sizeof(uint64_t);
 854
 855         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 856                 if (ret) {
 857                         uint64_t *max_mem_alloc_size = ret;
 858
 859                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 860                 }
 861                 return sizeof(uint64_t);
 862
 863         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 864                 if (ret) {
 865                         uint32_t *max_clock_frequency = ret;
 866                         *max_clock_frequency = sscreen->info.max_shader_clock;
 867                 }
 868                 return sizeof(uint32_t);
 869
 870         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 871                 if (ret) {
 872                         uint32_t *max_compute_units = ret;
 873                         *max_compute_units = sscreen->info.num_good_compute_units;
 874                 }
 875                 return sizeof(uint32_t);
 876
 877         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 878                 if (ret) {
 879                         uint32_t *images_supported = ret;
 880                         *images_supported = 0;
 881                 }
 882                 return sizeof(uint32_t);
 883         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 884                 break; /* unused */
 885         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 886                 if (ret) {
 887                         uint32_t *subgroup_size = ret;
 888                         *subgroup_size = sscreen->compute_wave_size;
 889                 }
 890                 return sizeof(uint32_t);
 891         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 892                 if (ret) {
 893                         uint64_t *max_variable_threads_per_block = ret;
 894                         if (ir_type == PIPE_SHADER_IR_NATIVE)
 895                                 *max_variable_threads_per_block = 0;
 896                         else
 897                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 898                 }
 899                 return sizeof(uint64_t);
 900         }
 901
 902         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 903         return 0;
 904 }
 905
 906 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 907 {
 908         struct si_screen *sscreen = (struct si_screen*)screen;
 909
 910         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 911                         sscreen->info.clock_crystal_freq;
 912 }
 913
 914 static void si_query_memory_info(struct pipe_screen *screen,
 915                                  struct pipe_memory_info *info)
 916 {
 917         struct si_screen *sscreen = (struct si_screen*)screen;
 918         struct radeon_winsys *ws = sscreen->ws;
 919         unsigned vram_usage, gtt_usage;
 920
 921         info->total_device_memory = sscreen->info.vram_size / 1024;
 922         info->total_staging_memory = sscreen->info.gart_size / 1024;
 923
 924         /* The real TTM memory usage is somewhat random, because:
 925          *
 926          * 1) TTM delays freeing memory, because it can only free it after
 927          *    fences expire.
 928          *
 929          * 2) The memory usage can be really low if big VRAM evictions are
 930          *    taking place, but the real usage is well above the size of VRAM.
 931          *
 932          * Instead, return statistics of this process.
 933          */
 934         vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
 935         gtt_usage =  ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
 936
 937         info->avail_device_memory =
 938                 vram_usage <= info->total_device_memory ?
 939                                 info->total_device_memory - vram_usage : 0;
 940         info->avail_staging_memory =
 941                 gtt_usage <= info->total_staging_memory ?
 942                                 info->total_staging_memory - gtt_usage : 0;
 943
 944         info->device_memory_evicted =
 945                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 946
 947         if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 4)
 948                 info->nr_device_memory_evictions =
 949                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 950         else
 951                 /* Just return the number of evicted 64KB pages. */
 952                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 953 }
 954
 955 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 956 {
 957         struct si_screen *sscreen = (struct si_screen*)pscreen;
 958
 959         return sscreen->disk_shader_cache;
 960 }
 961
 962 static void si_init_renderer_string(struct si_screen *sscreen)
 963 {
 964         char first_name[256], second_name[32] = {}, kernel_version[128] = {};
 965         struct utsname uname_data;
 966
 967         if (sscreen->info.marketing_name) {
 968                 snprintf(first_name, sizeof(first_name), "%s",
 969                          sscreen->info.marketing_name);
 970                 snprintf(second_name, sizeof(second_name), "%s, ",
 971                          sscreen->info.name);
 972         } else {
 973                 snprintf(first_name, sizeof(first_name), "AMD %s",
 974                          sscreen->info.name);
 975         }
 976
 977         if (uname(&uname_data) == 0)
 978                 snprintf(kernel_version, sizeof(kernel_version),
 979                          ", %s", uname_data.release);
 980
 981         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 982                  "%s (%sDRM %i.%i.%i%s, LLVM " MESA_LLVM_VERSION_STRING ")",
 983                  first_name, second_name, sscreen->info.drm_major,
 984                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 985                  kernel_version);
 986 }
 987
 988 void si_init_screen_get_functions(struct si_screen *sscreen)
 989 {
 990         sscreen->b.get_name = si_get_name;
 991         sscreen->b.get_vendor = si_get_vendor;
 992         sscreen->b.get_device_vendor = si_get_device_vendor;
 993         sscreen->b.get_param = si_get_param;
 994         sscreen->b.get_paramf = si_get_paramf;
 995         sscreen->b.get_compute_param = si_get_compute_param;
 996         sscreen->b.get_timestamp = si_get_timestamp;
 997         sscreen->b.get_shader_param = si_get_shader_param;
 998         sscreen->b.get_compiler_options = si_get_compiler_options;
 999         sscreen->b.get_device_uuid = si_get_device_uuid;
1000         sscreen->b.get_driver_uuid = si_get_driver_uuid;
1001         sscreen->b.query_memory_info = si_query_memory_info;
1002         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
1003
1004         if (sscreen->info.has_hw_decode) {
1005                 sscreen->b.get_video_param = si_get_video_param;
1006                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
1007         } else {
1008                 sscreen->b.get_video_param = si_get_video_param_no_decode;
1009                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1010         }
1011
1012         si_init_renderer_string(sscreen);
1013 }