src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "radeon/radeon_video.h"
  27 #include "radeon/radeon_vce.h"
  28 #include "radeon/radeon_uvd_enc.h"
  29 #include "vl/vl_decoder.h"
  30 #include "vl/vl_video_buffer.h"
  31 #include "util/u_screen.h"
  32 #include "util/u_video.h"
  33 #include "compiler/nir/nir.h"
  34
  35 #include <sys/utsname.h>
  36
  37 static const char *si_get_vendor(struct pipe_screen *pscreen)
  38 {
  39         /* Don't change this. Games such as Alien Isolation are broken if this
  40          * returns "Advanced Micro Devices, Inc."
  41          */
  42         return "X.Org";
  43 }
  44
  45 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  46 {
  47         return "AMD";
  48 }
  49
  50 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  51 {
  52         struct si_screen *sscreen = (struct si_screen *)pscreen;
  53
  54         switch (param) {
  55         /* Supported features (boolean caps). */
  56         case PIPE_CAP_ACCELERATED:
  57         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  58         case PIPE_CAP_ANISOTROPIC_FILTER:
  59         case PIPE_CAP_POINT_SPRITE:
  60         case PIPE_CAP_OCCLUSION_QUERY:
  61         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  62         case PIPE_CAP_TEXTURE_SHADOW_LOD:
  63         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  64         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  65         case PIPE_CAP_TEXTURE_SWIZZLE:
  66         case PIPE_CAP_DEPTH_CLIP_DISABLE:
  67         case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
  68         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  69         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  70         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  71         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  72         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  73         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  74         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
  75         case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
  76         case PIPE_CAP_VERTEX_SHADER_SATURATE:
  77         case PIPE_CAP_SEAMLESS_CUBE_MAP:
  78         case PIPE_CAP_PRIMITIVE_RESTART:
  79         case PIPE_CAP_CONDITIONAL_RENDER:
  80         case PIPE_CAP_TEXTURE_BARRIER:
  81         case PIPE_CAP_INDEP_BLEND_ENABLE:
  82         case PIPE_CAP_INDEP_BLEND_FUNC:
  83         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  84         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  85         case PIPE_CAP_START_INSTANCE:
  86         case PIPE_CAP_NPOT_TEXTURES:
  87         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  88         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  89         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
  90         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
  91         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  92         case PIPE_CAP_TGSI_INSTANCEID:
  93         case PIPE_CAP_COMPUTE:
  94         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  95         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
  96         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
  97         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  98         case PIPE_CAP_CUBE_MAP_ARRAY:
  99         case PIPE_CAP_SAMPLE_SHADING:
 100         case PIPE_CAP_DRAW_INDIRECT:
 101         case PIPE_CAP_CLIP_HALFZ:
 102         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 103         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 104         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 105         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 106         case PIPE_CAP_TGSI_TEXCOORD:
 107         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 108         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 109         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 110         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 111         case PIPE_CAP_SHAREABLE_SHADERS:
 112         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 113         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 114         case PIPE_CAP_TEXTURE_QUERY_LOD:
 115         case PIPE_CAP_TEXTURE_GATHER_SM5:
 116         case PIPE_CAP_TGSI_TXQS:
 117         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 118         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 119         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 120         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 121         case PIPE_CAP_INVALIDATE_BUFFER:
 122         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 123         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 124         case PIPE_CAP_QUERY_MEMORY_INFO:
 125         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 126         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 127         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 128         case PIPE_CAP_GENERATE_MIPMAP:
 129         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 130         case PIPE_CAP_STRING_MARKER:
 131         case PIPE_CAP_CLEAR_TEXTURE:
 132         case PIPE_CAP_CULL_DISTANCE:
 133         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 134         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 135         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 136         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 137         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 138         case PIPE_CAP_DOUBLES:
 139         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 140         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 141         case PIPE_CAP_BINDLESS_TEXTURE:
 142         case PIPE_CAP_QUERY_TIMESTAMP:
 143         case PIPE_CAP_QUERY_TIME_ELAPSED:
 144         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 145         case PIPE_CAP_MEMOBJ:
 146         case PIPE_CAP_LOAD_CONSTBUF:
 147         case PIPE_CAP_INT64:
 148         case PIPE_CAP_INT64_DIVMOD:
 149         case PIPE_CAP_TGSI_CLOCK:
 150         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 151         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 152         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 153         case PIPE_CAP_TGSI_BALLOT:
 154         case PIPE_CAP_TGSI_VOTE:
 155         case PIPE_CAP_FBFETCH:
 156         case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
 157         case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 158         case PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA:
 159         case PIPE_CAP_TGSI_DIV:
 160         case PIPE_CAP_PACKED_UNIFORMS:
 161         case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
 162         case PIPE_CAP_GL_SPIRV:
 163                 return 1;
 164
 165         case PIPE_CAP_QUERY_SO_OVERFLOW:
 166                 return !sscreen->use_ngg_streamout;
 167
 168         case PIPE_CAP_POST_DEPTH_COVERAGE:
 169                 return sscreen->info.chip_class >= GFX10;
 170
 171         case PIPE_CAP_GRAPHICS:
 172                 return sscreen->info.has_graphics;
 173
 174         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 175                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 176
 177         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 178                 return sscreen->info.has_gpu_reset_status_query;
 179
 180         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 181                 return sscreen->info.has_2d_tiling;
 182
 183         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 184                 return SI_MAP_BUFFER_ALIGNMENT;
 185
 186         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 187         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 188         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 189         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 190         case PIPE_CAP_MAX_VERTEX_STREAMS:
 191         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 192         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 193                 return 4;
 194
 195         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 196         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 197                 if (!sscreen->info.has_indirect_compute_dispatch)
 198                         return 420;
 199                 return 460;
 200
 201         case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 202                 /* Optimal number for good TexSubImage performance on Polaris10. */
 203                 return 64 * 1024 * 1024;
 204
 205         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 206         case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 207                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 208
 209         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 210         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 211         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 212                 return LLVM_VERSION_MAJOR < 9 && !sscreen->info.has_unaligned_shader_loads;
 213
 214         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 215                 return sscreen->info.has_sparse_vm_mappings ?
 216                                 RADEON_SPARSE_PAGE_SIZE : 0;
 217
 218
 219         case PIPE_CAP_UMA:
 220                 return 0;
 221
 222         case PIPE_CAP_FENCE_SIGNAL:
 223                 return sscreen->info.has_syncobj;
 224
 225         case PIPE_CAP_CONSTBUF0_FLAGS:
 226                 return SI_RESOURCE_FLAG_32BIT;
 227
 228         case PIPE_CAP_NATIVE_FENCE_FD:
 229                 return sscreen->info.has_fence_to_handle;
 230
 231         case PIPE_CAP_DRAW_PARAMETERS:
 232         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 233         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 234                 return sscreen->has_draw_indirect_multi;
 235
 236         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 237                 return 30;
 238
 239         case PIPE_CAP_MAX_VARYINGS:
 240                 return 32;
 241
 242         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 243                 return sscreen->info.chip_class <= GFX8 ?
 244                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 245
 246         /* Stream output. */
 247         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 248         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 249                 return 32*4;
 250
 251         /* Geometry shader output. */
 252         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 253                 /* gfx9 has to report 256 to make piglit/gs-max-output pass.
 254                  * gfx8 and earlier can do 1024.
 255                  */
 256                 return 256;
 257         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 258                 return 4095;
 259         case PIPE_CAP_MAX_GS_INVOCATIONS:
 260                 /* The closed driver exposes 127, but 125 is the greatest
 261                  * number that works. */
 262                 return 125;
 263
 264         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 265                 return 2048;
 266
 267         /* Texturing. */
 268         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 269                 return 16384;
 270         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 271                 return 15; /* 16384 */
 272         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 273                 if (sscreen->info.chip_class >= GFX10)
 274                         return 14;
 275                 /* textures support 8192, but layered rendering supports 2048 */
 276                 return 12;
 277         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 278                 if (sscreen->info.chip_class >= GFX10)
 279                         return 8192;
 280                 /* textures support 8192, but layered rendering supports 2048 */
 281                 return 2048;
 282
 283         /* Viewports and render targets. */
 284         case PIPE_CAP_MAX_VIEWPORTS:
 285                 return SI_MAX_VIEWPORTS;
 286         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 287         case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 288         case PIPE_CAP_MAX_RENDER_TARGETS:
 289                 return 8;
 290         case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 291                 return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
 292
 293         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 294         case PIPE_CAP_MIN_TEXEL_OFFSET:
 295                 return -32;
 296
 297         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 298         case PIPE_CAP_MAX_TEXEL_OFFSET:
 299                 return 31;
 300
 301         case PIPE_CAP_ENDIANNESS:
 302                 return PIPE_ENDIAN_LITTLE;
 303
 304         case PIPE_CAP_VENDOR_ID:
 305                 return ATI_VENDOR_ID;
 306         case PIPE_CAP_DEVICE_ID:
 307                 return sscreen->info.pci_id;
 308         case PIPE_CAP_VIDEO_MEMORY:
 309                 return sscreen->info.vram_size >> 20;
 310         case PIPE_CAP_PCI_GROUP:
 311                 return sscreen->info.pci_domain;
 312         case PIPE_CAP_PCI_BUS:
 313                 return sscreen->info.pci_bus;
 314         case PIPE_CAP_PCI_DEVICE:
 315                 return sscreen->info.pci_dev;
 316         case PIPE_CAP_PCI_FUNCTION:
 317                 return sscreen->info.pci_func;
 318         case PIPE_CAP_TGSI_ATOMINC_WRAP:
 319                 return LLVM_VERSION_MAJOR >= 10;
 320
 321         default:
 322                 return u_pipe_screen_get_param_defaults(pscreen, param);
 323         }
 324 }
 325
 326 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 327 {
 328         switch (param) {
 329         case PIPE_CAPF_MAX_LINE_WIDTH:
 330         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 331                 /* This depends on the quant mode, though the precise interactions
 332                  * are unknown. */
 333                 return 2048;
 334         case PIPE_CAPF_MAX_POINT_WIDTH:
 335         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 336                 return SI_MAX_POINT_SIZE;
 337         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 338                 return 16.0f;
 339         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 340                 return 16.0f;
 341         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 342         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 343         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 344                 return 0.0f;
 345         }
 346         return 0.0f;
 347 }
 348
 349 static int si_get_shader_param(struct pipe_screen* pscreen,
 350                                enum pipe_shader_type shader,
 351                                enum pipe_shader_cap param)
 352 {
 353         struct si_screen *sscreen = (struct si_screen *)pscreen;
 354
 355         switch(shader)
 356         {
 357         case PIPE_SHADER_FRAGMENT:
 358         case PIPE_SHADER_VERTEX:
 359         case PIPE_SHADER_GEOMETRY:
 360         case PIPE_SHADER_TESS_CTRL:
 361         case PIPE_SHADER_TESS_EVAL:
 362                 break;
 363         case PIPE_SHADER_COMPUTE:
 364                 switch (param) {
 365                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 366                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 367
 368                         if (sscreen->info.has_indirect_compute_dispatch)
 369                                 ir |= 1 << PIPE_SHADER_IR_NIR;
 370
 371                         return ir;
 372                 }
 373
 374                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 375                         uint64_t max_const_buffer_size;
 376                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_NIR,
 377                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 378                                 &max_const_buffer_size);
 379                         return MIN2(max_const_buffer_size, INT_MAX);
 380                 }
 381                 default:
 382                         /* If compute shaders don't require a special value
 383                          * for this cap, we can return the same value we
 384                          * do for other shader types. */
 385                         break;
 386                 }
 387                 break;
 388         default:
 389                 return 0;
 390         }
 391
 392         switch (param) {
 393         /* Shader limits. */
 394         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 395         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 396         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 397         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 398         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 399                 return 16384;
 400         case PIPE_SHADER_CAP_MAX_INPUTS:
 401                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 402         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 403                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 404         case PIPE_SHADER_CAP_MAX_TEMPS:
 405                 return 256; /* Max native temporaries. */
 406         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 407                 return MIN2(sscreen->info.max_alloc_size, INT_MAX - 3); /* aligned to 4 */
 408         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 409                 return SI_NUM_CONST_BUFFERS;
 410         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 411         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 412                 return SI_NUM_SAMPLERS;
 413         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 414                 return SI_NUM_SHADER_BUFFERS;
 415         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 416                 return SI_NUM_IMAGES;
 417         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 418                 return 0;
 419         case PIPE_SHADER_CAP_PREFERRED_IR:
 420                 return PIPE_SHADER_IR_NIR;
 421         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 422                 return 4;
 423
 424         /* Supported boolean features. */
 425         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 426         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 427         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 428         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 429         case PIPE_SHADER_CAP_INTEGERS:
 430         case PIPE_SHADER_CAP_INT64_ATOMICS:
 431         case PIPE_SHADER_CAP_FP16:
 432         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 433         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 434         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 435         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 436         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 437         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 438                 return 1;
 439
 440         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 441                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 442                 if (shader == PIPE_SHADER_GEOMETRY)
 443                         return 0;
 444
 445                 if (shader == PIPE_SHADER_VERTEX &&
 446                     !sscreen->llvm_has_working_vgpr_indexing)
 447                         return 0;
 448
 449                 /* TCS and TES load inputs directly from LDS or offchip
 450                  * memory, so indirect indexing is always supported.
 451                  * PS has to support indirect indexing, because we can't
 452                  * lower that to TEMPs for INTERP instructions.
 453                  */
 454                 return 1;
 455
 456         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 457                 return sscreen->llvm_has_working_vgpr_indexing ||
 458                        /* TCS stores outputs directly to memory. */
 459                        shader == PIPE_SHADER_TESS_CTRL;
 460
 461         /* Unsupported boolean features. */
 462         case PIPE_SHADER_CAP_SUBROUTINES:
 463         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 464         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 465         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 466                 return 0;
 467         }
 468         return 0;
 469 }
 470
 471 static const struct nir_shader_compiler_options nir_options = {
 472         .lower_scmp = true,
 473         .lower_flrp32 = true,
 474         .lower_flrp64 = true,
 475         .lower_fsat = true,
 476         .lower_fdiv = true,
 477         .lower_bitfield_insert_to_bitfield_select = true,
 478         .lower_bitfield_extract = true,
 479         .lower_sub = true,
 480         .fuse_ffma = true,
 481         .lower_fmod = true,
 482         .lower_pack_snorm_4x8 = true,
 483         .lower_pack_unorm_4x8 = true,
 484         .lower_unpack_snorm_2x16 = true,
 485         .lower_unpack_snorm_4x8 = true,
 486         .lower_unpack_unorm_2x16 = true,
 487         .lower_unpack_unorm_4x8 = true,
 488         .lower_extract_byte = true,
 489         .lower_extract_word = true,
 490         .lower_rotate = true,
 491         .lower_to_scalar = true,
 492         .optimize_sample_mask_in = true,
 493         .max_unroll_iterations = 32,
 494         .use_interpolated_input_intrinsics = true,
 495 };
 496
 497 static const void *
 498 si_get_compiler_options(struct pipe_screen *screen,
 499                         enum pipe_shader_ir ir,
 500                         enum pipe_shader_type shader)
 501 {
 502         assert(ir == PIPE_SHADER_IR_NIR);
 503         return &nir_options;
 504 }
 505
 506 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 507 {
 508         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 509 }
 510
 511 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 512 {
 513         struct si_screen *sscreen = (struct si_screen *)pscreen;
 514
 515         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 516 }
 517
 518 static const char* si_get_name(struct pipe_screen *pscreen)
 519 {
 520         struct si_screen *sscreen = (struct si_screen*)pscreen;
 521
 522         return sscreen->renderer_string;
 523 }
 524
 525 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 526                                         enum pipe_video_profile profile,
 527                                         enum pipe_video_entrypoint entrypoint,
 528                                         enum pipe_video_cap param)
 529 {
 530         switch (param) {
 531         case PIPE_VIDEO_CAP_SUPPORTED:
 532                 return vl_profile_supported(screen, profile, entrypoint);
 533         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 534                 return 1;
 535         case PIPE_VIDEO_CAP_MAX_WIDTH:
 536         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 537                 return vl_video_buffer_max_size(screen);
 538         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 539                 return PIPE_FORMAT_NV12;
 540         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 541                 return false;
 542         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 543                 return false;
 544         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 545                 return true;
 546         case PIPE_VIDEO_CAP_MAX_LEVEL:
 547                 return vl_level_supported(screen, profile);
 548         default:
 549                 return 0;
 550         }
 551 }
 552
 553 static int si_get_video_param(struct pipe_screen *screen,
 554                               enum pipe_video_profile profile,
 555                               enum pipe_video_entrypoint entrypoint,
 556                               enum pipe_video_cap param)
 557 {
 558         struct si_screen *sscreen = (struct si_screen *)screen;
 559         enum pipe_video_format codec = u_reduce_video_profile(profile);
 560
 561         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 562                 switch (param) {
 563                 case PIPE_VIDEO_CAP_SUPPORTED:
 564                         return ((codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 565                                 (sscreen->info.family >= CHIP_RAVEN ||
 566                                  si_vce_is_fw_version_supported(sscreen))) ||
 567                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 568                                 (sscreen->info.family >= CHIP_RAVEN ||
 569                                  si_radeon_uvd_enc_supported(sscreen))) ||
 570                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 &&
 571                                  sscreen->info.family >= CHIP_RENOIR));
 572                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 573                         return 1;
 574                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 575                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 576                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 577                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 578                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 579                         return PIPE_FORMAT_NV12;
 580                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 581                         return false;
 582                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 583                         return false;
 584                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 585                         return true;
 586                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 587                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 588                 default:
 589                         return 0;
 590                 }
 591         }
 592
 593         switch (param) {
 594         case PIPE_VIDEO_CAP_SUPPORTED:
 595                 switch (codec) {
 596                 case PIPE_VIDEO_FORMAT_MPEG12:
 597                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 598                 case PIPE_VIDEO_FORMAT_MPEG4:
 599                         return 1;
 600                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 601                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 602                              sscreen->info.family == CHIP_POLARIS11) &&
 603                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 604                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 605                                 return false;
 606                         }
 607                         return true;
 608                 case PIPE_VIDEO_FORMAT_VC1:
 609                         return true;
 610                 case PIPE_VIDEO_FORMAT_HEVC:
 611                         /* Carrizo only supports HEVC Main */
 612                         if (sscreen->info.family >= CHIP_STONEY)
 613                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 614                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 615                         else if (sscreen->info.family >= CHIP_CARRIZO)
 616                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 617                         return false;
 618                 case PIPE_VIDEO_FORMAT_JPEG:
 619                         if (sscreen->info.family >= CHIP_RAVEN)
 620                                 return true;
 621                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 622                                 return false;
 623                         if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 19)) {
 624                                 RVID_ERR("No MJPEG support for the kernel version\n");
 625                                 return false;
 626                         }
 627                         return true;
 628                 case PIPE_VIDEO_FORMAT_VP9:
 629                         if (sscreen->info.family < CHIP_RAVEN)
 630                                 return false;
 631                         return true;
 632                 default:
 633                         return false;
 634                 }
 635         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 636                 return 1;
 637         case PIPE_VIDEO_CAP_MAX_WIDTH:
 638                 switch (codec) {
 639                 case PIPE_VIDEO_FORMAT_HEVC:
 640                 case PIPE_VIDEO_FORMAT_VP9:
 641                         return (sscreen->info.family < CHIP_RENOIR) ?
 642                                ((sscreen->info.family < CHIP_TONGA) ? 2048 : 4096) :
 643                                8192;
 644                 default:
 645                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 646                 }
 647         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 648                 switch (codec) {
 649                 case PIPE_VIDEO_FORMAT_HEVC:
 650                 case PIPE_VIDEO_FORMAT_VP9:
 651                         return (sscreen->info.family < CHIP_RENOIR) ?
 652                                ((sscreen->info.family < CHIP_TONGA) ? 1152 : 4096) :
 653                                4352;
 654                 default:
 655                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 656                 }
 657         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 658                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 659                         return PIPE_FORMAT_P010;
 660                 else if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 661                         return PIPE_FORMAT_P016;
 662                 else
 663                         return PIPE_FORMAT_NV12;
 664
 665         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 666         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 667                 enum pipe_video_format format = u_reduce_video_profile(profile);
 668
 669                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 670                         return false; //The firmware doesn't support interlaced HEVC.
 671                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 672                         return false;
 673                 else if (format == PIPE_VIDEO_FORMAT_VP9)
 674                         return false;
 675                 return true;
 676         }
 677         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 678                 return true;
 679         case PIPE_VIDEO_CAP_MAX_LEVEL:
 680                 switch (profile) {
 681                 case PIPE_VIDEO_PROFILE_MPEG1:
 682                         return 0;
 683                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 684                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 685                         return 3;
 686                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 687                         return 3;
 688                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 689                         return 5;
 690                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 691                         return 1;
 692                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 693                         return 2;
 694                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 695                         return 4;
 696                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 697                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 698                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 699                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 700                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 701                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 702                         return 186;
 703                 default:
 704                         return 0;
 705                 }
 706         default:
 707                 return 0;
 708         }
 709 }
 710
 711 static bool si_vid_is_format_supported(struct pipe_screen *screen,
 712                                        enum pipe_format format,
 713                                        enum pipe_video_profile profile,
 714                                        enum pipe_video_entrypoint entrypoint)
 715 {
 716         /* HEVC 10 bit decoding should use P010 instead of NV12 if possible */
 717         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 718                 return (format == PIPE_FORMAT_NV12) ||
 719                        (format == PIPE_FORMAT_P010) ||
 720                        (format == PIPE_FORMAT_P016);
 721
 722         /* Vp9 profile 2 supports 10 bit decoding using P016 */
 723         if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 724                 return format == PIPE_FORMAT_P016;
 725
 726
 727         /* we can only handle this one with UVD */
 728         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 729                 return format == PIPE_FORMAT_NV12;
 730
 731         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 732 }
 733
 734 static unsigned get_max_threads_per_block(struct si_screen *screen,
 735                                           enum pipe_shader_ir ir_type)
 736 {
 737         if (ir_type == PIPE_SHADER_IR_NATIVE)
 738                 return 256;
 739
 740         /* LLVM 10 only supports 1024 threads per block. */
 741         return 1024;
 742 }
 743
 744 static int si_get_compute_param(struct pipe_screen *screen,
 745                                 enum pipe_shader_ir ir_type,
 746                                 enum pipe_compute_cap param,
 747                                 void *ret)
 748 {
 749         struct si_screen *sscreen = (struct si_screen *)screen;
 750
 751         //TODO: select these params by asic
 752         switch (param) {
 753         case PIPE_COMPUTE_CAP_IR_TARGET: {
 754                 const char *gpu, *triple;
 755
 756                 triple = "amdgcn-mesa-mesa3d";
 757                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 758                 if (ret) {
 759                         sprintf(ret, "%s-%s", gpu, triple);
 760                 }
 761                 /* +2 for dash and terminating NIL byte */
 762                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 763         }
 764         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 765                 if (ret) {
 766                         uint64_t *grid_dimension = ret;
 767                         grid_dimension[0] = 3;
 768                 }
 769                 return 1 * sizeof(uint64_t);
 770
 771         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 772                 if (ret) {
 773                         uint64_t *grid_size = ret;
 774                         grid_size[0] = 65535;
 775                         grid_size[1] = 65535;
 776                         grid_size[2] = 65535;
 777                 }
 778                 return 3 * sizeof(uint64_t) ;
 779
 780         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 781                 if (ret) {
 782                         uint64_t *block_size = ret;
 783                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 784                         block_size[0] = threads_per_block;
 785                         block_size[1] = threads_per_block;
 786                         block_size[2] = threads_per_block;
 787                 }
 788                 return 3 * sizeof(uint64_t);
 789
 790         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 791                 if (ret) {
 792                         uint64_t *max_threads_per_block = ret;
 793                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 794                 }
 795                 return sizeof(uint64_t);
 796         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 797                 if (ret) {
 798                         uint32_t *address_bits = ret;
 799                         address_bits[0] = 64;
 800                 }
 801                 return 1 * sizeof(uint32_t);
 802
 803         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 804                 if (ret) {
 805                         uint64_t *max_global_size = ret;
 806                         uint64_t max_mem_alloc_size;
 807
 808                         si_get_compute_param(screen, ir_type,
 809                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 810                                 &max_mem_alloc_size);
 811
 812                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 813                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 814                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 815                          * make sure we never report more than
 816                          * 4 * MAX_MEM_ALLOC_SIZE.
 817                          */
 818                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 819                                                 MAX2(sscreen->info.gart_size,
 820                                                      sscreen->info.vram_size));
 821                 }
 822                 return sizeof(uint64_t);
 823
 824         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 825                 if (ret) {
 826                         uint64_t *max_local_size = ret;
 827                         /* Value reported by the closed source driver. */
 828                         *max_local_size = 32768;
 829                 }
 830                 return sizeof(uint64_t);
 831
 832         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 833                 if (ret) {
 834                         uint64_t *max_input_size = ret;
 835                         /* Value reported by the closed source driver. */
 836                         *max_input_size = 1024;
 837                 }
 838                 return sizeof(uint64_t);
 839
 840         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 841                 if (ret) {
 842                         uint64_t *max_mem_alloc_size = ret;
 843
 844                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 845                 }
 846                 return sizeof(uint64_t);
 847
 848         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 849                 if (ret) {
 850                         uint32_t *max_clock_frequency = ret;
 851                         *max_clock_frequency = sscreen->info.max_shader_clock;
 852                 }
 853                 return sizeof(uint32_t);
 854
 855         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 856                 if (ret) {
 857                         uint32_t *max_compute_units = ret;
 858                         *max_compute_units = sscreen->info.num_good_compute_units;
 859                 }
 860                 return sizeof(uint32_t);
 861
 862         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 863                 if (ret) {
 864                         uint32_t *images_supported = ret;
 865                         *images_supported = 0;
 866                 }
 867                 return sizeof(uint32_t);
 868         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 869                 break; /* unused */
 870         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 871                 if (ret) {
 872                         uint32_t *subgroup_size = ret;
 873                         *subgroup_size = sscreen->compute_wave_size;
 874                 }
 875                 return sizeof(uint32_t);
 876         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 877                 if (ret) {
 878                         uint64_t *max_variable_threads_per_block = ret;
 879                         if (ir_type == PIPE_SHADER_IR_NATIVE)
 880                                 *max_variable_threads_per_block = 0;
 881                         else
 882                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 883                 }
 884                 return sizeof(uint64_t);
 885         }
 886
 887         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 888         return 0;
 889 }
 890
 891 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 892 {
 893         struct si_screen *sscreen = (struct si_screen*)screen;
 894
 895         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 896                         sscreen->info.clock_crystal_freq;
 897 }
 898
 899 static void si_query_memory_info(struct pipe_screen *screen,
 900                                  struct pipe_memory_info *info)
 901 {
 902         struct si_screen *sscreen = (struct si_screen*)screen;
 903         struct radeon_winsys *ws = sscreen->ws;
 904         unsigned vram_usage, gtt_usage;
 905
 906         info->total_device_memory = sscreen->info.vram_size / 1024;
 907         info->total_staging_memory = sscreen->info.gart_size / 1024;
 908
 909         /* The real TTM memory usage is somewhat random, because:
 910          *
 911          * 1) TTM delays freeing memory, because it can only free it after
 912          *    fences expire.
 913          *
 914          * 2) The memory usage can be really low if big VRAM evictions are
 915          *    taking place, but the real usage is well above the size of VRAM.
 916          *
 917          * Instead, return statistics of this process.
 918          */
 919         vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
 920         gtt_usage =  ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
 921
 922         info->avail_device_memory =
 923                 vram_usage <= info->total_device_memory ?
 924                                 info->total_device_memory - vram_usage : 0;
 925         info->avail_staging_memory =
 926                 gtt_usage <= info->total_staging_memory ?
 927                                 info->total_staging_memory - gtt_usage : 0;
 928
 929         info->device_memory_evicted =
 930                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 931
 932         if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 4)
 933                 info->nr_device_memory_evictions =
 934                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 935         else
 936                 /* Just return the number of evicted 64KB pages. */
 937                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 938 }
 939
 940 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 941 {
 942         struct si_screen *sscreen = (struct si_screen*)pscreen;
 943
 944         return sscreen->disk_shader_cache;
 945 }
 946
 947 static void si_init_renderer_string(struct si_screen *sscreen)
 948 {
 949         char first_name[256], second_name[32] = {}, kernel_version[128] = {};
 950         struct utsname uname_data;
 951
 952         if (sscreen->info.marketing_name) {
 953                 snprintf(first_name, sizeof(first_name), "%s",
 954                          sscreen->info.marketing_name);
 955                 snprintf(second_name, sizeof(second_name), "%s, ",
 956                          sscreen->info.name);
 957         } else {
 958                 snprintf(first_name, sizeof(first_name), "AMD %s",
 959                          sscreen->info.name);
 960         }
 961
 962         if (uname(&uname_data) == 0)
 963                 snprintf(kernel_version, sizeof(kernel_version),
 964                          ", %s", uname_data.release);
 965
 966         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 967                  "%s (%sDRM %i.%i.%i%s, LLVM " MESA_LLVM_VERSION_STRING ")",
 968                  first_name, second_name, sscreen->info.drm_major,
 969                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 970                  kernel_version);
 971 }
 972
 973 void si_init_screen_get_functions(struct si_screen *sscreen)
 974 {
 975         sscreen->b.get_name = si_get_name;
 976         sscreen->b.get_vendor = si_get_vendor;
 977         sscreen->b.get_device_vendor = si_get_device_vendor;
 978         sscreen->b.get_param = si_get_param;
 979         sscreen->b.get_paramf = si_get_paramf;
 980         sscreen->b.get_compute_param = si_get_compute_param;
 981         sscreen->b.get_timestamp = si_get_timestamp;
 982         sscreen->b.get_shader_param = si_get_shader_param;
 983         sscreen->b.get_compiler_options = si_get_compiler_options;
 984         sscreen->b.get_device_uuid = si_get_device_uuid;
 985         sscreen->b.get_driver_uuid = si_get_driver_uuid;
 986         sscreen->b.query_memory_info = si_query_memory_info;
 987         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
 988
 989         if (sscreen->info.has_hw_decode) {
 990                 sscreen->b.get_video_param = si_get_video_param;
 991                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
 992         } else {
 993                 sscreen->b.get_video_param = si_get_video_param_no_decode;
 994                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 995         }
 996
 997         si_init_renderer_string(sscreen);
 998 }