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gallium: add PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES
[mesa.git] / src / gallium / drivers / radeonsi / si_get.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_pipe.h"
26 #include "radeon/radeon_video.h"
27 #include "radeon/radeon_vce.h"
28 #include "radeon/radeon_uvd_enc.h"
29 #include "vl/vl_decoder.h"
30 #include "vl/vl_video_buffer.h"
31 #include "util/u_screen.h"
32 #include "util/u_video.h"
33 #include "compiler/nir/nir.h"
34
35 #include <sys/utsname.h>
36
37 static const char *si_get_vendor(struct pipe_screen *pscreen)
38 {
39 /* Don't change this. Games such as Alien Isolation are broken if this
40 * returns "Advanced Micro Devices, Inc."
41 */
42 return "X.Org";
43 }
44
45 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
46 {
47 return "AMD";
48 }
49
50 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
51 {
52 struct si_screen *sscreen = (struct si_screen *)pscreen;
53
54 switch (param) {
55 /* Supported features (boolean caps). */
56 case PIPE_CAP_ACCELERATED:
57 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
58 case PIPE_CAP_ANISOTROPIC_FILTER:
59 case PIPE_CAP_POINT_SPRITE:
60 case PIPE_CAP_OCCLUSION_QUERY:
61 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
62 case PIPE_CAP_TEXTURE_SHADOW_LOD:
63 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
64 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
65 case PIPE_CAP_TEXTURE_SWIZZLE:
66 case PIPE_CAP_DEPTH_CLIP_DISABLE:
67 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
68 case PIPE_CAP_SHADER_STENCIL_EXPORT:
69 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
70 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
71 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
72 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
73 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
74 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
75 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
76 case PIPE_CAP_VERTEX_SHADER_SATURATE:
77 case PIPE_CAP_SEAMLESS_CUBE_MAP:
78 case PIPE_CAP_PRIMITIVE_RESTART:
79 case PIPE_CAP_CONDITIONAL_RENDER:
80 case PIPE_CAP_TEXTURE_BARRIER:
81 case PIPE_CAP_INDEP_BLEND_ENABLE:
82 case PIPE_CAP_INDEP_BLEND_FUNC:
83 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
84 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
85 case PIPE_CAP_START_INSTANCE:
86 case PIPE_CAP_NPOT_TEXTURES:
87 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
88 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
89 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
90 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
91 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
92 case PIPE_CAP_TGSI_INSTANCEID:
93 case PIPE_CAP_COMPUTE:
94 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
95 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
96 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
97 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
98 case PIPE_CAP_CUBE_MAP_ARRAY:
99 case PIPE_CAP_SAMPLE_SHADING:
100 case PIPE_CAP_DRAW_INDIRECT:
101 case PIPE_CAP_CLIP_HALFZ:
102 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
103 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
104 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
105 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
106 case PIPE_CAP_TGSI_TEXCOORD:
107 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
108 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
109 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
110 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
111 case PIPE_CAP_SHAREABLE_SHADERS:
112 case PIPE_CAP_DEPTH_BOUNDS_TEST:
113 case PIPE_CAP_SAMPLER_VIEW_TARGET:
114 case PIPE_CAP_TEXTURE_QUERY_LOD:
115 case PIPE_CAP_TEXTURE_GATHER_SM5:
116 case PIPE_CAP_TGSI_TXQS:
117 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
118 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
119 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
120 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
121 case PIPE_CAP_INVALIDATE_BUFFER:
122 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
123 case PIPE_CAP_QUERY_BUFFER_OBJECT:
124 case PIPE_CAP_QUERY_MEMORY_INFO:
125 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
126 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
127 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
128 case PIPE_CAP_GENERATE_MIPMAP:
129 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
130 case PIPE_CAP_STRING_MARKER:
131 case PIPE_CAP_CLEAR_TEXTURE:
132 case PIPE_CAP_CULL_DISTANCE:
133 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
134 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
135 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
136 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
137 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
138 case PIPE_CAP_DOUBLES:
139 case PIPE_CAP_TGSI_TEX_TXF_LZ:
140 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
141 case PIPE_CAP_BINDLESS_TEXTURE:
142 case PIPE_CAP_QUERY_TIMESTAMP:
143 case PIPE_CAP_QUERY_TIME_ELAPSED:
144 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
145 case PIPE_CAP_MEMOBJ:
146 case PIPE_CAP_LOAD_CONSTBUF:
147 case PIPE_CAP_INT64:
148 case PIPE_CAP_INT64_DIVMOD:
149 case PIPE_CAP_TGSI_CLOCK:
150 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
151 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
152 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
153 case PIPE_CAP_TGSI_BALLOT:
154 case PIPE_CAP_TGSI_VOTE:
155 case PIPE_CAP_FBFETCH:
156 case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
157 case PIPE_CAP_IMAGE_LOAD_FORMATTED:
158 case PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA:
159 case PIPE_CAP_TGSI_DIV:
160 case PIPE_CAP_PACKED_UNIFORMS:
161 case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
162 case PIPE_CAP_GL_SPIRV:
163 case PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES:
164 return 1;
165
166 case PIPE_CAP_QUERY_SO_OVERFLOW:
167 return !sscreen->use_ngg_streamout;
168
169 case PIPE_CAP_POST_DEPTH_COVERAGE:
170 return sscreen->info.chip_class >= GFX10;
171
172 case PIPE_CAP_GRAPHICS:
173 return sscreen->info.has_graphics;
174
175 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
176 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
177
178 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
179 return sscreen->info.has_gpu_reset_status_query;
180
181 case PIPE_CAP_TEXTURE_MULTISAMPLE:
182 return sscreen->info.has_2d_tiling;
183
184 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
185 return SI_MAP_BUFFER_ALIGNMENT;
186
187 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
188 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
189 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
190 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
191 case PIPE_CAP_MAX_VERTEX_STREAMS:
192 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
193 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
194 return 4;
195
196 case PIPE_CAP_GLSL_FEATURE_LEVEL:
197 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
198 if (!sscreen->info.has_indirect_compute_dispatch)
199 return 420;
200 return 460;
201
202 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
203 /* Optimal number for good TexSubImage performance on Polaris10. */
204 return 64 * 1024 * 1024;
205
206 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
207 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
208 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
209
210 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
211 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
212 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
213 return LLVM_VERSION_MAJOR < 9 && !sscreen->info.has_unaligned_shader_loads;
214
215 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
216 return sscreen->info.has_sparse_vm_mappings ?
217 RADEON_SPARSE_PAGE_SIZE : 0;
218
219
220 case PIPE_CAP_UMA:
221 return 0;
222
223 case PIPE_CAP_FENCE_SIGNAL:
224 return sscreen->info.has_syncobj;
225
226 case PIPE_CAP_CONSTBUF0_FLAGS:
227 return SI_RESOURCE_FLAG_32BIT;
228
229 case PIPE_CAP_NATIVE_FENCE_FD:
230 return sscreen->info.has_fence_to_handle;
231
232 case PIPE_CAP_DRAW_PARAMETERS:
233 case PIPE_CAP_MULTI_DRAW_INDIRECT:
234 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
235 return sscreen->has_draw_indirect_multi;
236
237 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
238 return 30;
239
240 case PIPE_CAP_MAX_VARYINGS:
241 return 32;
242
243 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
244 return sscreen->info.chip_class <= GFX8 ?
245 PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
246
247 /* Stream output. */
248 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
249 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
250 return 32*4;
251
252 /* Geometry shader output. */
253 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
254 /* gfx9 has to report 256 to make piglit/gs-max-output pass.
255 * gfx8 and earlier can do 1024.
256 */
257 return 256;
258 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
259 return 4095;
260 case PIPE_CAP_MAX_GS_INVOCATIONS:
261 /* The closed driver exposes 127, but 125 is the greatest
262 * number that works. */
263 return 125;
264
265 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
266 return 2048;
267
268 /* Texturing. */
269 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
270 return 16384;
271 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
272 return 15; /* 16384 */
273 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
274 if (sscreen->info.chip_class >= GFX10)
275 return 14;
276 /* textures support 8192, but layered rendering supports 2048 */
277 return 12;
278 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
279 if (sscreen->info.chip_class >= GFX10)
280 return 8192;
281 /* textures support 8192, but layered rendering supports 2048 */
282 return 2048;
283
284 /* Viewports and render targets. */
285 case PIPE_CAP_MAX_VIEWPORTS:
286 return SI_MAX_VIEWPORTS;
287 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
288 case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
289 case PIPE_CAP_MAX_RENDER_TARGETS:
290 return 8;
291 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
292 return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
293
294 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
295 case PIPE_CAP_MIN_TEXEL_OFFSET:
296 return -32;
297
298 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
299 case PIPE_CAP_MAX_TEXEL_OFFSET:
300 return 31;
301
302 case PIPE_CAP_ENDIANNESS:
303 return PIPE_ENDIAN_LITTLE;
304
305 case PIPE_CAP_VENDOR_ID:
306 return ATI_VENDOR_ID;
307 case PIPE_CAP_DEVICE_ID:
308 return sscreen->info.pci_id;
309 case PIPE_CAP_VIDEO_MEMORY:
310 return sscreen->info.vram_size >> 20;
311 case PIPE_CAP_PCI_GROUP:
312 return sscreen->info.pci_domain;
313 case PIPE_CAP_PCI_BUS:
314 return sscreen->info.pci_bus;
315 case PIPE_CAP_PCI_DEVICE:
316 return sscreen->info.pci_dev;
317 case PIPE_CAP_PCI_FUNCTION:
318 return sscreen->info.pci_func;
319 case PIPE_CAP_TGSI_ATOMINC_WRAP:
320 return LLVM_VERSION_MAJOR >= 10;
321
322 default:
323 return u_pipe_screen_get_param_defaults(pscreen, param);
324 }
325 }
326
327 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
328 {
329 switch (param) {
330 case PIPE_CAPF_MAX_LINE_WIDTH:
331 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
332 /* This depends on the quant mode, though the precise interactions
333 * are unknown. */
334 return 2048;
335 case PIPE_CAPF_MAX_POINT_WIDTH:
336 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
337 return SI_MAX_POINT_SIZE;
338 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
339 return 16.0f;
340 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
341 return 16.0f;
342 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
343 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
344 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
345 return 0.0f;
346 }
347 return 0.0f;
348 }
349
350 static int si_get_shader_param(struct pipe_screen* pscreen,
351 enum pipe_shader_type shader,
352 enum pipe_shader_cap param)
353 {
354 struct si_screen *sscreen = (struct si_screen *)pscreen;
355
356 switch(shader)
357 {
358 case PIPE_SHADER_FRAGMENT:
359 case PIPE_SHADER_VERTEX:
360 case PIPE_SHADER_GEOMETRY:
361 case PIPE_SHADER_TESS_CTRL:
362 case PIPE_SHADER_TESS_EVAL:
363 break;
364 case PIPE_SHADER_COMPUTE:
365 switch (param) {
366 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
367 int ir = 1 << PIPE_SHADER_IR_NATIVE;
368
369 if (sscreen->info.has_indirect_compute_dispatch)
370 ir |= 1 << PIPE_SHADER_IR_NIR;
371
372 return ir;
373 }
374
375 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
376 uint64_t max_const_buffer_size;
377 pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_NIR,
378 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
379 &max_const_buffer_size);
380 return MIN2(max_const_buffer_size, INT_MAX);
381 }
382 default:
383 /* If compute shaders don't require a special value
384 * for this cap, we can return the same value we
385 * do for other shader types. */
386 break;
387 }
388 break;
389 default:
390 return 0;
391 }
392
393 switch (param) {
394 /* Shader limits. */
395 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
396 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
397 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
398 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
399 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
400 return 16384;
401 case PIPE_SHADER_CAP_MAX_INPUTS:
402 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
403 case PIPE_SHADER_CAP_MAX_OUTPUTS:
404 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
405 case PIPE_SHADER_CAP_MAX_TEMPS:
406 return 256; /* Max native temporaries. */
407 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
408 return MIN2(sscreen->info.max_alloc_size, INT_MAX - 3); /* aligned to 4 */
409 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
410 return SI_NUM_CONST_BUFFERS;
411 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
412 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
413 return SI_NUM_SAMPLERS;
414 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
415 return SI_NUM_SHADER_BUFFERS;
416 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
417 return SI_NUM_IMAGES;
418 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
419 return 0;
420 case PIPE_SHADER_CAP_PREFERRED_IR:
421 return PIPE_SHADER_IR_NIR;
422 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
423 return 4;
424
425 /* Supported boolean features. */
426 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
427 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
428 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
429 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
430 case PIPE_SHADER_CAP_INTEGERS:
431 case PIPE_SHADER_CAP_INT64_ATOMICS:
432 case PIPE_SHADER_CAP_FP16:
433 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
434 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
435 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
436 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
437 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
438 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
439 return 1;
440
441 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
442 /* TODO: Indirect indexing of GS inputs is unimplemented. */
443 if (shader == PIPE_SHADER_GEOMETRY)
444 return 0;
445
446 if (shader == PIPE_SHADER_VERTEX &&
447 !sscreen->llvm_has_working_vgpr_indexing)
448 return 0;
449
450 /* TCS and TES load inputs directly from LDS or offchip
451 * memory, so indirect indexing is always supported.
452 * PS has to support indirect indexing, because we can't
453 * lower that to TEMPs for INTERP instructions.
454 */
455 return 1;
456
457 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
458 return sscreen->llvm_has_working_vgpr_indexing ||
459 /* TCS stores outputs directly to memory. */
460 shader == PIPE_SHADER_TESS_CTRL;
461
462 /* Unsupported boolean features. */
463 case PIPE_SHADER_CAP_SUBROUTINES:
464 case PIPE_SHADER_CAP_SUPPORTED_IRS:
465 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
466 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
467 return 0;
468 }
469 return 0;
470 }
471
472 static const struct nir_shader_compiler_options nir_options = {
473 .lower_scmp = true,
474 .lower_flrp32 = true,
475 .lower_flrp64 = true,
476 .lower_fsat = true,
477 .lower_fdiv = true,
478 .lower_bitfield_insert_to_bitfield_select = true,
479 .lower_bitfield_extract = true,
480 .lower_sub = true,
481 .fuse_ffma = true,
482 .lower_fmod = true,
483 .lower_pack_snorm_4x8 = true,
484 .lower_pack_unorm_4x8 = true,
485 .lower_unpack_snorm_2x16 = true,
486 .lower_unpack_snorm_4x8 = true,
487 .lower_unpack_unorm_2x16 = true,
488 .lower_unpack_unorm_4x8 = true,
489 .lower_extract_byte = true,
490 .lower_extract_word = true,
491 .lower_rotate = true,
492 .lower_to_scalar = true,
493 .optimize_sample_mask_in = true,
494 .max_unroll_iterations = 32,
495 .use_interpolated_input_intrinsics = true,
496 };
497
498 static const void *
499 si_get_compiler_options(struct pipe_screen *screen,
500 enum pipe_shader_ir ir,
501 enum pipe_shader_type shader)
502 {
503 assert(ir == PIPE_SHADER_IR_NIR);
504 return &nir_options;
505 }
506
507 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
508 {
509 ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
510 }
511
512 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
513 {
514 struct si_screen *sscreen = (struct si_screen *)pscreen;
515
516 ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
517 }
518
519 static const char* si_get_name(struct pipe_screen *pscreen)
520 {
521 struct si_screen *sscreen = (struct si_screen*)pscreen;
522
523 return sscreen->renderer_string;
524 }
525
526 static int si_get_video_param_no_decode(struct pipe_screen *screen,
527 enum pipe_video_profile profile,
528 enum pipe_video_entrypoint entrypoint,
529 enum pipe_video_cap param)
530 {
531 switch (param) {
532 case PIPE_VIDEO_CAP_SUPPORTED:
533 return vl_profile_supported(screen, profile, entrypoint);
534 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
535 return 1;
536 case PIPE_VIDEO_CAP_MAX_WIDTH:
537 case PIPE_VIDEO_CAP_MAX_HEIGHT:
538 return vl_video_buffer_max_size(screen);
539 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
540 return PIPE_FORMAT_NV12;
541 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
542 return false;
543 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
544 return false;
545 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
546 return true;
547 case PIPE_VIDEO_CAP_MAX_LEVEL:
548 return vl_level_supported(screen, profile);
549 default:
550 return 0;
551 }
552 }
553
554 static int si_get_video_param(struct pipe_screen *screen,
555 enum pipe_video_profile profile,
556 enum pipe_video_entrypoint entrypoint,
557 enum pipe_video_cap param)
558 {
559 struct si_screen *sscreen = (struct si_screen *)screen;
560 enum pipe_video_format codec = u_reduce_video_profile(profile);
561
562 if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
563 switch (param) {
564 case PIPE_VIDEO_CAP_SUPPORTED:
565 return ((codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
566 (sscreen->info.family >= CHIP_RAVEN ||
567 si_vce_is_fw_version_supported(sscreen))) ||
568 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
569 (sscreen->info.family >= CHIP_RAVEN ||
570 si_radeon_uvd_enc_supported(sscreen))) ||
571 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 &&
572 sscreen->info.family >= CHIP_RENOIR));
573 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
574 return 1;
575 case PIPE_VIDEO_CAP_MAX_WIDTH:
576 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
577 case PIPE_VIDEO_CAP_MAX_HEIGHT:
578 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
579 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
580 return PIPE_FORMAT_NV12;
581 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
582 return false;
583 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
584 return false;
585 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
586 return true;
587 case PIPE_VIDEO_CAP_STACKED_FRAMES:
588 return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
589 default:
590 return 0;
591 }
592 }
593
594 switch (param) {
595 case PIPE_VIDEO_CAP_SUPPORTED:
596 switch (codec) {
597 case PIPE_VIDEO_FORMAT_MPEG12:
598 return profile != PIPE_VIDEO_PROFILE_MPEG1;
599 case PIPE_VIDEO_FORMAT_MPEG4:
600 return 1;
601 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
602 if ((sscreen->info.family == CHIP_POLARIS10 ||
603 sscreen->info.family == CHIP_POLARIS11) &&
604 sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
605 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
606 return false;
607 }
608 return true;
609 case PIPE_VIDEO_FORMAT_VC1:
610 return true;
611 case PIPE_VIDEO_FORMAT_HEVC:
612 /* Carrizo only supports HEVC Main */
613 if (sscreen->info.family >= CHIP_STONEY)
614 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
615 profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
616 else if (sscreen->info.family >= CHIP_CARRIZO)
617 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
618 return false;
619 case PIPE_VIDEO_FORMAT_JPEG:
620 if (sscreen->info.family >= CHIP_RAVEN)
621 return true;
622 if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
623 return false;
624 if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 19)) {
625 RVID_ERR("No MJPEG support for the kernel version\n");
626 return false;
627 }
628 return true;
629 case PIPE_VIDEO_FORMAT_VP9:
630 if (sscreen->info.family < CHIP_RAVEN)
631 return false;
632 return true;
633 default:
634 return false;
635 }
636 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
637 return 1;
638 case PIPE_VIDEO_CAP_MAX_WIDTH:
639 switch (codec) {
640 case PIPE_VIDEO_FORMAT_HEVC:
641 case PIPE_VIDEO_FORMAT_VP9:
642 return (sscreen->info.family < CHIP_RENOIR) ?
643 ((sscreen->info.family < CHIP_TONGA) ? 2048 : 4096) :
644 8192;
645 default:
646 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
647 }
648 case PIPE_VIDEO_CAP_MAX_HEIGHT:
649 switch (codec) {
650 case PIPE_VIDEO_FORMAT_HEVC:
651 case PIPE_VIDEO_FORMAT_VP9:
652 return (sscreen->info.family < CHIP_RENOIR) ?
653 ((sscreen->info.family < CHIP_TONGA) ? 1152 : 4096) :
654 4352;
655 default:
656 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
657 }
658 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
659 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
660 return PIPE_FORMAT_P010;
661 else if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
662 return PIPE_FORMAT_P016;
663 else
664 return PIPE_FORMAT_NV12;
665
666 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
667 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
668 enum pipe_video_format format = u_reduce_video_profile(profile);
669
670 if (format == PIPE_VIDEO_FORMAT_HEVC)
671 return false; //The firmware doesn't support interlaced HEVC.
672 else if (format == PIPE_VIDEO_FORMAT_JPEG)
673 return false;
674 else if (format == PIPE_VIDEO_FORMAT_VP9)
675 return false;
676 return true;
677 }
678 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
679 return true;
680 case PIPE_VIDEO_CAP_MAX_LEVEL:
681 switch (profile) {
682 case PIPE_VIDEO_PROFILE_MPEG1:
683 return 0;
684 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
685 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
686 return 3;
687 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
688 return 3;
689 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
690 return 5;
691 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
692 return 1;
693 case PIPE_VIDEO_PROFILE_VC1_MAIN:
694 return 2;
695 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
696 return 4;
697 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
698 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
699 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
700 return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
701 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
702 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
703 return 186;
704 default:
705 return 0;
706 }
707 default:
708 return 0;
709 }
710 }
711
712 static bool si_vid_is_format_supported(struct pipe_screen *screen,
713 enum pipe_format format,
714 enum pipe_video_profile profile,
715 enum pipe_video_entrypoint entrypoint)
716 {
717 /* HEVC 10 bit decoding should use P010 instead of NV12 if possible */
718 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
719 return (format == PIPE_FORMAT_NV12) ||
720 (format == PIPE_FORMAT_P010) ||
721 (format == PIPE_FORMAT_P016);
722
723 /* Vp9 profile 2 supports 10 bit decoding using P016 */
724 if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
725 return format == PIPE_FORMAT_P016;
726
727
728 /* we can only handle this one with UVD */
729 if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
730 return format == PIPE_FORMAT_NV12;
731
732 return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
733 }
734
735 static unsigned get_max_threads_per_block(struct si_screen *screen,
736 enum pipe_shader_ir ir_type)
737 {
738 if (ir_type == PIPE_SHADER_IR_NATIVE)
739 return 256;
740
741 /* LLVM 10 only supports 1024 threads per block. */
742 return 1024;
743 }
744
745 static int si_get_compute_param(struct pipe_screen *screen,
746 enum pipe_shader_ir ir_type,
747 enum pipe_compute_cap param,
748 void *ret)
749 {
750 struct si_screen *sscreen = (struct si_screen *)screen;
751
752 //TODO: select these params by asic
753 switch (param) {
754 case PIPE_COMPUTE_CAP_IR_TARGET: {
755 const char *gpu, *triple;
756
757 triple = "amdgcn-mesa-mesa3d";
758 gpu = ac_get_llvm_processor_name(sscreen->info.family);
759 if (ret) {
760 sprintf(ret, "%s-%s", gpu, triple);
761 }
762 /* +2 for dash and terminating NIL byte */
763 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
764 }
765 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
766 if (ret) {
767 uint64_t *grid_dimension = ret;
768 grid_dimension[0] = 3;
769 }
770 return 1 * sizeof(uint64_t);
771
772 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
773 if (ret) {
774 uint64_t *grid_size = ret;
775 grid_size[0] = 65535;
776 grid_size[1] = 65535;
777 grid_size[2] = 65535;
778 }
779 return 3 * sizeof(uint64_t) ;
780
781 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
782 if (ret) {
783 uint64_t *block_size = ret;
784 unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
785 block_size[0] = threads_per_block;
786 block_size[1] = threads_per_block;
787 block_size[2] = threads_per_block;
788 }
789 return 3 * sizeof(uint64_t);
790
791 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
792 if (ret) {
793 uint64_t *max_threads_per_block = ret;
794 *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
795 }
796 return sizeof(uint64_t);
797 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
798 if (ret) {
799 uint32_t *address_bits = ret;
800 address_bits[0] = 64;
801 }
802 return 1 * sizeof(uint32_t);
803
804 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
805 if (ret) {
806 uint64_t *max_global_size = ret;
807 uint64_t max_mem_alloc_size;
808
809 si_get_compute_param(screen, ir_type,
810 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
811 &max_mem_alloc_size);
812
813 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
814 * 1/4 of the MAX_GLOBAL_SIZE. Since the
815 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
816 * make sure we never report more than
817 * 4 * MAX_MEM_ALLOC_SIZE.
818 */
819 *max_global_size = MIN2(4 * max_mem_alloc_size,
820 MAX2(sscreen->info.gart_size,
821 sscreen->info.vram_size));
822 }
823 return sizeof(uint64_t);
824
825 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
826 if (ret) {
827 uint64_t *max_local_size = ret;
828 /* Value reported by the closed source driver. */
829 *max_local_size = 32768;
830 }
831 return sizeof(uint64_t);
832
833 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
834 if (ret) {
835 uint64_t *max_input_size = ret;
836 /* Value reported by the closed source driver. */
837 *max_input_size = 1024;
838 }
839 return sizeof(uint64_t);
840
841 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
842 if (ret) {
843 uint64_t *max_mem_alloc_size = ret;
844
845 *max_mem_alloc_size = sscreen->info.max_alloc_size;
846 }
847 return sizeof(uint64_t);
848
849 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
850 if (ret) {
851 uint32_t *max_clock_frequency = ret;
852 *max_clock_frequency = sscreen->info.max_shader_clock;
853 }
854 return sizeof(uint32_t);
855
856 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
857 if (ret) {
858 uint32_t *max_compute_units = ret;
859 *max_compute_units = sscreen->info.num_good_compute_units;
860 }
861 return sizeof(uint32_t);
862
863 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
864 if (ret) {
865 uint32_t *images_supported = ret;
866 *images_supported = 0;
867 }
868 return sizeof(uint32_t);
869 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
870 break; /* unused */
871 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
872 if (ret) {
873 uint32_t *subgroup_size = ret;
874 *subgroup_size = sscreen->compute_wave_size;
875 }
876 return sizeof(uint32_t);
877 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
878 if (ret) {
879 uint64_t *max_variable_threads_per_block = ret;
880 if (ir_type == PIPE_SHADER_IR_NATIVE)
881 *max_variable_threads_per_block = 0;
882 else
883 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
884 }
885 return sizeof(uint64_t);
886 }
887
888 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
889 return 0;
890 }
891
892 static uint64_t si_get_timestamp(struct pipe_screen *screen)
893 {
894 struct si_screen *sscreen = (struct si_screen*)screen;
895
896 return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
897 sscreen->info.clock_crystal_freq;
898 }
899
900 static void si_query_memory_info(struct pipe_screen *screen,
901 struct pipe_memory_info *info)
902 {
903 struct si_screen *sscreen = (struct si_screen*)screen;
904 struct radeon_winsys *ws = sscreen->ws;
905 unsigned vram_usage, gtt_usage;
906
907 info->total_device_memory = sscreen->info.vram_size / 1024;
908 info->total_staging_memory = sscreen->info.gart_size / 1024;
909
910 /* The real TTM memory usage is somewhat random, because:
911 *
912 * 1) TTM delays freeing memory, because it can only free it after
913 * fences expire.
914 *
915 * 2) The memory usage can be really low if big VRAM evictions are
916 * taking place, but the real usage is well above the size of VRAM.
917 *
918 * Instead, return statistics of this process.
919 */
920 vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
921 gtt_usage = ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
922
923 info->avail_device_memory =
924 vram_usage <= info->total_device_memory ?
925 info->total_device_memory - vram_usage : 0;
926 info->avail_staging_memory =
927 gtt_usage <= info->total_staging_memory ?
928 info->total_staging_memory - gtt_usage : 0;
929
930 info->device_memory_evicted =
931 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
932
933 if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 4)
934 info->nr_device_memory_evictions =
935 ws->query_value(ws, RADEON_NUM_EVICTIONS);
936 else
937 /* Just return the number of evicted 64KB pages. */
938 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
939 }
940
941 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
942 {
943 struct si_screen *sscreen = (struct si_screen*)pscreen;
944
945 return sscreen->disk_shader_cache;
946 }
947
948 static void si_init_renderer_string(struct si_screen *sscreen)
949 {
950 char first_name[256], second_name[32] = {}, kernel_version[128] = {};
951 struct utsname uname_data;
952
953 if (sscreen->info.marketing_name) {
954 snprintf(first_name, sizeof(first_name), "%s",
955 sscreen->info.marketing_name);
956 snprintf(second_name, sizeof(second_name), "%s, ",
957 sscreen->info.name);
958 } else {
959 snprintf(first_name, sizeof(first_name), "AMD %s",
960 sscreen->info.name);
961 }
962
963 if (uname(&uname_data) == 0)
964 snprintf(kernel_version, sizeof(kernel_version),
965 ", %s", uname_data.release);
966
967 snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
968 "%s (%sDRM %i.%i.%i%s, LLVM " MESA_LLVM_VERSION_STRING ")",
969 first_name, second_name, sscreen->info.drm_major,
970 sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
971 kernel_version);
972 }
973
974 void si_init_screen_get_functions(struct si_screen *sscreen)
975 {
976 sscreen->b.get_name = si_get_name;
977 sscreen->b.get_vendor = si_get_vendor;
978 sscreen->b.get_device_vendor = si_get_device_vendor;
979 sscreen->b.get_param = si_get_param;
980 sscreen->b.get_paramf = si_get_paramf;
981 sscreen->b.get_compute_param = si_get_compute_param;
982 sscreen->b.get_timestamp = si_get_timestamp;
983 sscreen->b.get_shader_param = si_get_shader_param;
984 sscreen->b.get_compiler_options = si_get_compiler_options;
985 sscreen->b.get_device_uuid = si_get_device_uuid;
986 sscreen->b.get_driver_uuid = si_get_driver_uuid;
987 sscreen->b.query_memory_info = si_query_memory_info;
988 sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
989
990 if (sscreen->info.has_hw_decode) {
991 sscreen->b.get_video_param = si_get_video_param;
992 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
993 } else {
994 sscreen->b.get_video_param = si_get_video_param_no_decode;
995 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
996 }
997
998 si_init_renderer_string(sscreen);
999 }