src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "radeon/radeon_video.h"
  26 #include "radeon/radeon_vce.h"
  27 #include "radeon/radeon_uvd_enc.h"
  28 #include "ac_llvm_util.h"
  29 #include "vl/vl_decoder.h"
  30 #include "vl/vl_video_buffer.h"
  31 #include "util/u_video.h"
  32 #include "compiler/nir/nir.h"
  33
  34 #include <sys/utsname.h>
  35
  36 static const char *si_get_vendor(struct pipe_screen *pscreen)
  37 {
  38         /* Don't change this. Games such as Alien Isolation are broken if this
  39          * returns "Advanced Micro Devices, Inc."
  40          */
  41         return "X.Org";
  42 }
  43
  44 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  45 {
  46         return "AMD";
  47 }
  48
  49 static const char *si_get_marketing_name(struct radeon_winsys *ws)
  50 {
  51         if (!ws->get_chip_name)
  52                 return NULL;
  53         return ws->get_chip_name(ws);
  54 }
  55
  56 const char *si_get_family_name(const struct si_screen *sscreen)
  57 {
  58         switch (sscreen->info.family) {
  59         case CHIP_TAHITI: return "AMD TAHITI";
  60         case CHIP_PITCAIRN: return "AMD PITCAIRN";
  61         case CHIP_VERDE: return "AMD CAPE VERDE";
  62         case CHIP_OLAND: return "AMD OLAND";
  63         case CHIP_HAINAN: return "AMD HAINAN";
  64         case CHIP_BONAIRE: return "AMD BONAIRE";
  65         case CHIP_KAVERI: return "AMD KAVERI";
  66         case CHIP_KABINI: return "AMD KABINI";
  67         case CHIP_HAWAII: return "AMD HAWAII";
  68         case CHIP_MULLINS: return "AMD MULLINS";
  69         case CHIP_TONGA: return "AMD TONGA";
  70         case CHIP_ICELAND: return "AMD ICELAND";
  71         case CHIP_CARRIZO: return "AMD CARRIZO";
  72         case CHIP_FIJI: return "AMD FIJI";
  73         case CHIP_POLARIS10: return "AMD POLARIS10";
  74         case CHIP_POLARIS11: return "AMD POLARIS11";
  75         case CHIP_POLARIS12: return "AMD POLARIS12";
  76         case CHIP_STONEY: return "AMD STONEY";
  77         case CHIP_VEGA10: return "AMD VEGA10";
  78         case CHIP_RAVEN: return "AMD RAVEN";
  79         default: return "AMD unknown";
  80         }
  81 }
  82
  83 static bool si_have_tgsi_compute(struct si_screen *sscreen)
  84 {
  85         /* Old kernels disallowed some register writes for SI
  86          * that are used for indirect dispatches. */
  87         return (sscreen->info.chip_class >= CIK ||
  88                 sscreen->info.drm_major == 3 ||
  89                 (sscreen->info.drm_major == 2 &&
  90                  sscreen->info.drm_minor >= 45));
  91 }
  92
  93 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  94 {
  95         struct si_screen *sscreen = (struct si_screen *)pscreen;
  96
  97         switch (param) {
  98         /* Supported features (boolean caps). */
  99         case PIPE_CAP_ACCELERATED:
 100         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 101         case PIPE_CAP_ANISOTROPIC_FILTER:
 102         case PIPE_CAP_POINT_SPRITE:
 103         case PIPE_CAP_OCCLUSION_QUERY:
 104         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 105         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 106         case PIPE_CAP_TEXTURE_SWIZZLE:
 107         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 108         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 109         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 110         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 111         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 112         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 113         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 114         case PIPE_CAP_SM3:
 115         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 116         case PIPE_CAP_PRIMITIVE_RESTART:
 117         case PIPE_CAP_CONDITIONAL_RENDER:
 118         case PIPE_CAP_TEXTURE_BARRIER:
 119         case PIPE_CAP_INDEP_BLEND_ENABLE:
 120         case PIPE_CAP_INDEP_BLEND_FUNC:
 121         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 122         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 123         case PIPE_CAP_START_INSTANCE:
 124         case PIPE_CAP_NPOT_TEXTURES:
 125         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 126         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 127         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 128         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 129         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 130         case PIPE_CAP_TGSI_INSTANCEID:
 131         case PIPE_CAP_COMPUTE:
 132         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 133         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 134         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 135         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 136         case PIPE_CAP_CUBE_MAP_ARRAY:
 137         case PIPE_CAP_SAMPLE_SHADING:
 138         case PIPE_CAP_DRAW_INDIRECT:
 139         case PIPE_CAP_CLIP_HALFZ:
 140         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 141         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 142         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 143         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 144         case PIPE_CAP_TGSI_TEXCOORD:
 145         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 146         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 147         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 148         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 149         case PIPE_CAP_SHAREABLE_SHADERS:
 150         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 151         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 152         case PIPE_CAP_TEXTURE_QUERY_LOD:
 153         case PIPE_CAP_TEXTURE_GATHER_SM5:
 154         case PIPE_CAP_TGSI_TXQS:
 155         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 156         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 157         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 158         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 159         case PIPE_CAP_INVALIDATE_BUFFER:
 160         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 161         case PIPE_CAP_QUERY_MEMORY_INFO:
 162         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 163         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 164         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 165         case PIPE_CAP_GENERATE_MIPMAP:
 166         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 167         case PIPE_CAP_STRING_MARKER:
 168         case PIPE_CAP_CLEAR_TEXTURE:
 169         case PIPE_CAP_CULL_DISTANCE:
 170         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 171         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 172         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 173         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 174         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 175         case PIPE_CAP_DOUBLES:
 176         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 177         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 178         case PIPE_CAP_BINDLESS_TEXTURE:
 179         case PIPE_CAP_QUERY_TIMESTAMP:
 180         case PIPE_CAP_QUERY_TIME_ELAPSED:
 181         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 182         case PIPE_CAP_QUERY_SO_OVERFLOW:
 183         case PIPE_CAP_MEMOBJ:
 184         case PIPE_CAP_LOAD_CONSTBUF:
 185         case PIPE_CAP_INT64:
 186         case PIPE_CAP_INT64_DIVMOD:
 187         case PIPE_CAP_TGSI_CLOCK:
 188         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 189         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 190         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 191         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 192         case PIPE_CAP_TGSI_VOTE:
 193                 return 1;
 194
 195         case PIPE_CAP_TGSI_BALLOT:
 196                 return HAVE_LLVM >= 0x0500;
 197
 198         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 199                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 200
 201         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 202                 return (sscreen->info.drm_major == 2 &&
 203                         sscreen->info.drm_minor >= 43) ||
 204                        sscreen->info.drm_major == 3;
 205
 206         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 207                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 208                 return sscreen->info.chip_class < CIK ||
 209                        (sscreen->info.drm_major == 2 &&
 210                         sscreen->info.drm_minor >= 35) ||
 211                        sscreen->info.drm_major == 3;
 212
 213         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 214                 return R600_MAP_BUFFER_ALIGNMENT;
 215
 216         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 217         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 218         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 219         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 220         case PIPE_CAP_MAX_VERTEX_STREAMS:
 221         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 222                 return 4;
 223
 224         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 225                 if (si_have_tgsi_compute(sscreen))
 226                         return 450;
 227                 return 420;
 228
 229         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 230                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 231
 232         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 233         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 234         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 235                 /* SI doesn't support unaligned loads.
 236                  * CIK needs DRM 2.50.0 on radeon. */
 237                 return sscreen->info.chip_class == SI ||
 238                        (sscreen->info.drm_major == 2 &&
 239                         sscreen->info.drm_minor < 50);
 240
 241         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 242                 /* TODO: GFX9 hangs. */
 243                 if (sscreen->info.chip_class >= GFX9)
 244                         return 0;
 245                 /* Disable on SI due to VM faults in CP DMA. Enable once these
 246                  * faults are mitigated in software.
 247                  */
 248                 if (sscreen->info.chip_class >= CIK &&
 249                     sscreen->info.drm_major == 3 &&
 250                     sscreen->info.drm_minor >= 13)
 251                         return RADEON_SPARSE_PAGE_SIZE;
 252                 return 0;
 253
 254         /* Unsupported features. */
 255         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 256         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 257         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 258         case PIPE_CAP_USER_VERTEX_BUFFERS:
 259         case PIPE_CAP_FAKE_SW_MSAA:
 260         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 261         case PIPE_CAP_VERTEXID_NOBASE:
 262         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 263         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 264         case PIPE_CAP_TGSI_FS_FBFETCH:
 265         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 266         case PIPE_CAP_UMA:
 267         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 268         case PIPE_CAP_POST_DEPTH_COVERAGE:
 269         case PIPE_CAP_TILE_RASTER_ORDER:
 270         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 271         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 272                 return 0;
 273
 274         case PIPE_CAP_FENCE_SIGNAL:
 275                 return sscreen->info.has_syncobj;
 276
 277         case PIPE_CAP_CONSTBUF0_FLAGS:
 278                 return R600_RESOURCE_FLAG_32BIT;
 279
 280         case PIPE_CAP_NATIVE_FENCE_FD:
 281                 return sscreen->info.has_fence_to_handle;
 282
 283         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 284                 return si_have_tgsi_compute(sscreen);
 285
 286         case PIPE_CAP_DRAW_PARAMETERS:
 287         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 288         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 289                 return sscreen->has_draw_indirect_multi;
 290
 291         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 292                 return 30;
 293
 294         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 295                 return sscreen->info.chip_class <= VI ?
 296                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 297
 298         /* Stream output. */
 299         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 300         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 301                 return 32*4;
 302
 303         /* Geometry shader output. */
 304         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 305                 return 1024;
 306         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 307                 return 4095;
 308
 309         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 310                 return 2048;
 311
 312         /* Texturing. */
 313         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 314         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 315                 return 15; /* 16384 */
 316         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 317                 /* textures support 8192, but layered rendering supports 2048 */
 318                 return 12;
 319         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 320                 /* textures support 8192, but layered rendering supports 2048 */
 321                 return 2048;
 322
 323         /* Viewports and render targets. */
 324         case PIPE_CAP_MAX_VIEWPORTS:
 325                 return SI_MAX_VIEWPORTS;
 326         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 327         case PIPE_CAP_MAX_RENDER_TARGETS:
 328                 return 8;
 329
 330         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 331         case PIPE_CAP_MIN_TEXEL_OFFSET:
 332                 return -32;
 333
 334         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 335         case PIPE_CAP_MAX_TEXEL_OFFSET:
 336                 return 31;
 337
 338         case PIPE_CAP_ENDIANNESS:
 339                 return PIPE_ENDIAN_LITTLE;
 340
 341         case PIPE_CAP_VENDOR_ID:
 342                 return ATI_VENDOR_ID;
 343         case PIPE_CAP_DEVICE_ID:
 344                 return sscreen->info.pci_id;
 345         case PIPE_CAP_VIDEO_MEMORY:
 346                 return sscreen->info.vram_size >> 20;
 347         case PIPE_CAP_PCI_GROUP:
 348                 return sscreen->info.pci_domain;
 349         case PIPE_CAP_PCI_BUS:
 350                 return sscreen->info.pci_bus;
 351         case PIPE_CAP_PCI_DEVICE:
 352                 return sscreen->info.pci_dev;
 353         case PIPE_CAP_PCI_FUNCTION:
 354                 return sscreen->info.pci_func;
 355         }
 356         return 0;
 357 }
 358
 359 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 360 {
 361         switch (param) {
 362         case PIPE_CAPF_MAX_LINE_WIDTH:
 363         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 364         case PIPE_CAPF_MAX_POINT_WIDTH:
 365         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 366                 return 8192.0f;
 367         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 368                 return 16.0f;
 369         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 370                 return 16.0f;
 371         }
 372         return 0.0f;
 373 }
 374
 375 static int si_get_shader_param(struct pipe_screen* pscreen,
 376                                enum pipe_shader_type shader,
 377                                enum pipe_shader_cap param)
 378 {
 379         struct si_screen *sscreen = (struct si_screen *)pscreen;
 380
 381         switch(shader)
 382         {
 383         case PIPE_SHADER_FRAGMENT:
 384         case PIPE_SHADER_VERTEX:
 385         case PIPE_SHADER_GEOMETRY:
 386         case PIPE_SHADER_TESS_CTRL:
 387         case PIPE_SHADER_TESS_EVAL:
 388                 break;
 389         case PIPE_SHADER_COMPUTE:
 390                 switch (param) {
 391                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 392                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 393
 394                         if (si_have_tgsi_compute(sscreen))
 395                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 396
 397                         return ir;
 398                 }
 399
 400                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 401                         uint64_t max_const_buffer_size;
 402                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 403                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 404                                 &max_const_buffer_size);
 405                         return MIN2(max_const_buffer_size, INT_MAX);
 406                 }
 407                 default:
 408                         /* If compute shaders don't require a special value
 409                          * for this cap, we can return the same value we
 410                          * do for other shader types. */
 411                         break;
 412                 }
 413                 break;
 414         default:
 415                 return 0;
 416         }
 417
 418         switch (param) {
 419         /* Shader limits. */
 420         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 421         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 422         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 423         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 424         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 425                 return 16384;
 426         case PIPE_SHADER_CAP_MAX_INPUTS:
 427                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 428         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 429                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 430         case PIPE_SHADER_CAP_MAX_TEMPS:
 431                 return 256; /* Max native temporaries. */
 432         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 433                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 434         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 435                 return SI_NUM_CONST_BUFFERS;
 436         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 437         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 438                 return SI_NUM_SAMPLERS;
 439         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 440                 return SI_NUM_SHADER_BUFFERS;
 441         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 442                 return SI_NUM_IMAGES;
 443         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 444                 if (sscreen->debug_flags & DBG(NIR))
 445                         return 0;
 446                 return 32;
 447         case PIPE_SHADER_CAP_PREFERRED_IR:
 448                 if (sscreen->debug_flags & DBG(NIR))
 449                         return PIPE_SHADER_IR_NIR;
 450                 return PIPE_SHADER_IR_TGSI;
 451         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 452                 return 4;
 453
 454         /* Supported boolean features. */
 455         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 456         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 457         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 458         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 459         case PIPE_SHADER_CAP_INTEGERS:
 460         case PIPE_SHADER_CAP_INT64_ATOMICS:
 461         case PIPE_SHADER_CAP_FP16:
 462         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 463         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 464         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 465         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 466         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 467         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 468                 return 1;
 469
 470         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 471                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 472                 return shader != PIPE_SHADER_GEOMETRY &&
 473                        (sscreen->llvm_has_working_vgpr_indexing ||
 474                         /* TCS and TES load inputs directly from LDS or
 475                          * offchip memory, so indirect indexing is trivial. */
 476                         shader == PIPE_SHADER_TESS_CTRL ||
 477                         shader == PIPE_SHADER_TESS_EVAL);
 478
 479         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 480                 return sscreen->llvm_has_working_vgpr_indexing ||
 481                        /* TCS stores outputs directly to memory. */
 482                        shader == PIPE_SHADER_TESS_CTRL;
 483
 484         /* Unsupported boolean features. */
 485         case PIPE_SHADER_CAP_SUBROUTINES:
 486         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 487         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 488         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 489                 return 0;
 490         }
 491         return 0;
 492 }
 493
 494 static const struct nir_shader_compiler_options nir_options = {
 495         .vertex_id_zero_based = true,
 496         .lower_scmp = true,
 497         .lower_flrp32 = true,
 498         .lower_flrp64 = true,
 499         .lower_fsat = true,
 500         .lower_fdiv = true,
 501         .lower_sub = true,
 502         .lower_ffma = true,
 503         .lower_pack_snorm_2x16 = true,
 504         .lower_pack_snorm_4x8 = true,
 505         .lower_pack_unorm_2x16 = true,
 506         .lower_pack_unorm_4x8 = true,
 507         .lower_unpack_snorm_2x16 = true,
 508         .lower_unpack_snorm_4x8 = true,
 509         .lower_unpack_unorm_2x16 = true,
 510         .lower_unpack_unorm_4x8 = true,
 511         .lower_extract_byte = true,
 512         .lower_extract_word = true,
 513         .max_unroll_iterations = 32,
 514         .native_integers = true,
 515 };
 516
 517 static const void *
 518 si_get_compiler_options(struct pipe_screen *screen,
 519                         enum pipe_shader_ir ir,
 520                         enum pipe_shader_type shader)
 521 {
 522         assert(ir == PIPE_SHADER_IR_NIR);
 523         return &nir_options;
 524 }
 525
 526 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 527 {
 528         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 529 }
 530
 531 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 532 {
 533         struct si_screen *sscreen = (struct si_screen *)pscreen;
 534
 535         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 536 }
 537
 538 static const char* si_get_name(struct pipe_screen *pscreen)
 539 {
 540         struct si_screen *sscreen = (struct si_screen*)pscreen;
 541
 542         return sscreen->renderer_string;
 543 }
 544
 545 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 546                                         enum pipe_video_profile profile,
 547                                         enum pipe_video_entrypoint entrypoint,
 548                                         enum pipe_video_cap param)
 549 {
 550         switch (param) {
 551         case PIPE_VIDEO_CAP_SUPPORTED:
 552                 return vl_profile_supported(screen, profile, entrypoint);
 553         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 554                 return 1;
 555         case PIPE_VIDEO_CAP_MAX_WIDTH:
 556         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 557                 return vl_video_buffer_max_size(screen);
 558         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 559                 return PIPE_FORMAT_NV12;
 560         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 561                 return false;
 562         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 563                 return false;
 564         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 565                 return true;
 566         case PIPE_VIDEO_CAP_MAX_LEVEL:
 567                 return vl_level_supported(screen, profile);
 568         default:
 569                 return 0;
 570         }
 571 }
 572
 573 static int si_get_video_param(struct pipe_screen *screen,
 574                               enum pipe_video_profile profile,
 575                               enum pipe_video_entrypoint entrypoint,
 576                               enum pipe_video_cap param)
 577 {
 578         struct si_screen *sscreen = (struct si_screen *)screen;
 579         enum pipe_video_format codec = u_reduce_video_profile(profile);
 580
 581         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 582                 switch (param) {
 583                 case PIPE_VIDEO_CAP_SUPPORTED:
 584                         return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 585                                 (si_vce_is_fw_version_supported(sscreen) ||
 586                                 sscreen->info.family == CHIP_RAVEN)) ||
 587                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 588                                 (sscreen->info.family == CHIP_RAVEN ||
 589                                 si_radeon_uvd_enc_supported(sscreen)));
 590                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 591                         return 1;
 592                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 593                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 594                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 595                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 596                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 597                         return PIPE_FORMAT_NV12;
 598                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 599                         return false;
 600                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 601                         return false;
 602                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 603                         return true;
 604                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 605                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 606                 default:
 607                         return 0;
 608                 }
 609         }
 610
 611         switch (param) {
 612         case PIPE_VIDEO_CAP_SUPPORTED:
 613                 switch (codec) {
 614                 case PIPE_VIDEO_FORMAT_MPEG12:
 615                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 616                 case PIPE_VIDEO_FORMAT_MPEG4:
 617                         return 1;
 618                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 619                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 620                              sscreen->info.family == CHIP_POLARIS11) &&
 621                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 622                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 623                                 return false;
 624                         }
 625                         return true;
 626                 case PIPE_VIDEO_FORMAT_VC1:
 627                         return true;
 628                 case PIPE_VIDEO_FORMAT_HEVC:
 629                         /* Carrizo only supports HEVC Main */
 630                         if (sscreen->info.family >= CHIP_STONEY)
 631                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 632                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 633                         else if (sscreen->info.family >= CHIP_CARRIZO)
 634                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 635                         return false;
 636                 case PIPE_VIDEO_FORMAT_JPEG:
 637                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 638                                 return false;
 639                         if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
 640                                 RVID_ERR("No MJPEG support for the kernel version\n");
 641                                 return false;
 642                         }
 643                         return true;
 644                 default:
 645                         return false;
 646                 }
 647         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 648                 return 1;
 649         case PIPE_VIDEO_CAP_MAX_WIDTH:
 650                 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 651         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 652                 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 653         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 654                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 655                         return PIPE_FORMAT_P016;
 656                 else
 657                         return PIPE_FORMAT_NV12;
 658
 659         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 660         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 661                 enum pipe_video_format format = u_reduce_video_profile(profile);
 662
 663                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 664                         return false; //The firmware doesn't support interlaced HEVC.
 665                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 666                         return false;
 667                 return true;
 668         }
 669         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 670                 return true;
 671         case PIPE_VIDEO_CAP_MAX_LEVEL:
 672                 switch (profile) {
 673                 case PIPE_VIDEO_PROFILE_MPEG1:
 674                         return 0;
 675                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 676                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 677                         return 3;
 678                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 679                         return 3;
 680                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 681                         return 5;
 682                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 683                         return 1;
 684                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 685                         return 2;
 686                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 687                         return 4;
 688                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 689                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 690                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 691                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 692                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 693                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 694                         return 186;
 695                 default:
 696                         return 0;
 697                 }
 698         default:
 699                 return 0;
 700         }
 701 }
 702
 703 static boolean si_vid_is_format_supported(struct pipe_screen *screen,
 704                                           enum pipe_format format,
 705                                           enum pipe_video_profile profile,
 706                                           enum pipe_video_entrypoint entrypoint)
 707 {
 708         /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
 709         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 710                 return (format == PIPE_FORMAT_NV12) ||
 711                         (format == PIPE_FORMAT_P016);
 712
 713         /* we can only handle this one with UVD */
 714         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 715                 return format == PIPE_FORMAT_NV12;
 716
 717         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 718 }
 719
 720 static unsigned get_max_threads_per_block(struct si_screen *screen,
 721                                           enum pipe_shader_ir ir_type)
 722 {
 723         if (ir_type == PIPE_SHADER_IR_NATIVE)
 724                 return 256;
 725
 726         /* Only 16 waves per thread-group on gfx9. */
 727         if (screen->info.chip_class >= GFX9)
 728                 return 1024;
 729
 730         /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
 731          * round number.
 732          */
 733         return 2048;
 734 }
 735
 736 static int si_get_compute_param(struct pipe_screen *screen,
 737                                 enum pipe_shader_ir ir_type,
 738                                 enum pipe_compute_cap param,
 739                                 void *ret)
 740 {
 741         struct si_screen *sscreen = (struct si_screen *)screen;
 742
 743         //TODO: select these params by asic
 744         switch (param) {
 745         case PIPE_COMPUTE_CAP_IR_TARGET: {
 746                 const char *gpu, *triple;
 747
 748                 triple = "amdgcn-mesa-mesa3d";
 749                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 750                 if (ret) {
 751                         sprintf(ret, "%s-%s", gpu, triple);
 752                 }
 753                 /* +2 for dash and terminating NIL byte */
 754                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 755         }
 756         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 757                 if (ret) {
 758                         uint64_t *grid_dimension = ret;
 759                         grid_dimension[0] = 3;
 760                 }
 761                 return 1 * sizeof(uint64_t);
 762
 763         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 764                 if (ret) {
 765                         uint64_t *grid_size = ret;
 766                         grid_size[0] = 65535;
 767                         grid_size[1] = 65535;
 768                         grid_size[2] = 65535;
 769                 }
 770                 return 3 * sizeof(uint64_t) ;
 771
 772         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 773                 if (ret) {
 774                         uint64_t *block_size = ret;
 775                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 776                         block_size[0] = threads_per_block;
 777                         block_size[1] = threads_per_block;
 778                         block_size[2] = threads_per_block;
 779                 }
 780                 return 3 * sizeof(uint64_t);
 781
 782         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 783                 if (ret) {
 784                         uint64_t *max_threads_per_block = ret;
 785                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 786                 }
 787                 return sizeof(uint64_t);
 788         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 789                 if (ret) {
 790                         uint32_t *address_bits = ret;
 791                         address_bits[0] = 64;
 792                 }
 793                 return 1 * sizeof(uint32_t);
 794
 795         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 796                 if (ret) {
 797                         uint64_t *max_global_size = ret;
 798                         uint64_t max_mem_alloc_size;
 799
 800                         si_get_compute_param(screen, ir_type,
 801                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 802                                 &max_mem_alloc_size);
 803
 804                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 805                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 806                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 807                          * make sure we never report more than
 808                          * 4 * MAX_MEM_ALLOC_SIZE.
 809                          */
 810                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 811                                                 MAX2(sscreen->info.gart_size,
 812                                                      sscreen->info.vram_size));
 813                 }
 814                 return sizeof(uint64_t);
 815
 816         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 817                 if (ret) {
 818                         uint64_t *max_local_size = ret;
 819                         /* Value reported by the closed source driver. */
 820                         *max_local_size = 32768;
 821                 }
 822                 return sizeof(uint64_t);
 823
 824         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 825                 if (ret) {
 826                         uint64_t *max_input_size = ret;
 827                         /* Value reported by the closed source driver. */
 828                         *max_input_size = 1024;
 829                 }
 830                 return sizeof(uint64_t);
 831
 832         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 833                 if (ret) {
 834                         uint64_t *max_mem_alloc_size = ret;
 835
 836                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 837                 }
 838                 return sizeof(uint64_t);
 839
 840         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 841                 if (ret) {
 842                         uint32_t *max_clock_frequency = ret;
 843                         *max_clock_frequency = sscreen->info.max_shader_clock;
 844                 }
 845                 return sizeof(uint32_t);
 846
 847         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 848                 if (ret) {
 849                         uint32_t *max_compute_units = ret;
 850                         *max_compute_units = sscreen->info.num_good_compute_units;
 851                 }
 852                 return sizeof(uint32_t);
 853
 854         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 855                 if (ret) {
 856                         uint32_t *images_supported = ret;
 857                         *images_supported = 0;
 858                 }
 859                 return sizeof(uint32_t);
 860         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 861                 break; /* unused */
 862         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 863                 if (ret) {
 864                         uint32_t *subgroup_size = ret;
 865                         *subgroup_size = 64;
 866                 }
 867                 return sizeof(uint32_t);
 868         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 869                 if (ret) {
 870                         uint64_t *max_variable_threads_per_block = ret;
 871                         if (ir_type == PIPE_SHADER_IR_NATIVE)
 872                                 *max_variable_threads_per_block = 0;
 873                         else
 874                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 875                 }
 876                 return sizeof(uint64_t);
 877         }
 878
 879         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 880         return 0;
 881 }
 882
 883 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 884 {
 885         struct si_screen *sscreen = (struct si_screen*)screen;
 886
 887         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 888                         sscreen->info.clock_crystal_freq;
 889 }
 890
 891 static void si_query_memory_info(struct pipe_screen *screen,
 892                                  struct pipe_memory_info *info)
 893 {
 894         struct si_screen *sscreen = (struct si_screen*)screen;
 895         struct radeon_winsys *ws = sscreen->ws;
 896         unsigned vram_usage, gtt_usage;
 897
 898         info->total_device_memory = sscreen->info.vram_size / 1024;
 899         info->total_staging_memory = sscreen->info.gart_size / 1024;
 900
 901         /* The real TTM memory usage is somewhat random, because:
 902          *
 903          * 1) TTM delays freeing memory, because it can only free it after
 904          *    fences expire.
 905          *
 906          * 2) The memory usage can be really low if big VRAM evictions are
 907          *    taking place, but the real usage is well above the size of VRAM.
 908          *
 909          * Instead, return statistics of this process.
 910          */
 911         vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
 912         gtt_usage =  ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
 913
 914         info->avail_device_memory =
 915                 vram_usage <= info->total_device_memory ?
 916                                 info->total_device_memory - vram_usage : 0;
 917         info->avail_staging_memory =
 918                 gtt_usage <= info->total_staging_memory ?
 919                                 info->total_staging_memory - gtt_usage : 0;
 920
 921         info->device_memory_evicted =
 922                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 923
 924         if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
 925                 info->nr_device_memory_evictions =
 926                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 927         else
 928                 /* Just return the number of evicted 64KB pages. */
 929                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 930 }
 931
 932 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 933 {
 934         struct si_screen *sscreen = (struct si_screen*)pscreen;
 935
 936         return sscreen->disk_shader_cache;
 937 }
 938
 939 static void si_init_renderer_string(struct si_screen *sscreen)
 940 {
 941         struct radeon_winsys *ws = sscreen->ws;
 942         char family_name[32] = {}, llvm_string[32] = {}, kernel_version[128] = {};
 943         struct utsname uname_data;
 944
 945         const char *chip_name = si_get_marketing_name(ws);
 946
 947         if (chip_name)
 948                 snprintf(family_name, sizeof(family_name), "%s / ",
 949                          si_get_family_name(sscreen) + 4);
 950         else
 951                 chip_name = si_get_family_name(sscreen);
 952
 953         if (uname(&uname_data) == 0)
 954                 snprintf(kernel_version, sizeof(kernel_version),
 955                          " / %s", uname_data.release);
 956
 957         if (HAVE_LLVM > 0) {
 958                 snprintf(llvm_string, sizeof(llvm_string),
 959                          ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
 960                          HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
 961         }
 962
 963         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 964                  "%s (%sDRM %i.%i.%i%s%s)",
 965                  chip_name, family_name, sscreen->info.drm_major,
 966                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 967                  kernel_version, llvm_string);
 968 }
 969
 970 void si_init_screen_get_functions(struct si_screen *sscreen)
 971 {
 972         sscreen->b.get_name = si_get_name;
 973         sscreen->b.get_vendor = si_get_vendor;
 974         sscreen->b.get_device_vendor = si_get_device_vendor;
 975         sscreen->b.get_param = si_get_param;
 976         sscreen->b.get_paramf = si_get_paramf;
 977         sscreen->b.get_compute_param = si_get_compute_param;
 978         sscreen->b.get_timestamp = si_get_timestamp;
 979         sscreen->b.get_shader_param = si_get_shader_param;
 980         sscreen->b.get_compiler_options = si_get_compiler_options;
 981         sscreen->b.get_device_uuid = si_get_device_uuid;
 982         sscreen->b.get_driver_uuid = si_get_driver_uuid;
 983         sscreen->b.query_memory_info = si_query_memory_info;
 984         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
 985
 986         if (sscreen->info.has_hw_decode) {
 987                 sscreen->b.get_video_param = si_get_video_param;
 988                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
 989         } else {
 990                 sscreen->b.get_video_param = si_get_video_param_no_decode;
 991                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 992         }
 993
 994         si_init_renderer_string(sscreen);
 995 }