src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "radeon/radeon_video.h"
  27 #include "radeon/radeon_vce.h"
  28 #include "radeon/radeon_uvd_enc.h"
  29 #include "vl/vl_decoder.h"
  30 #include "vl/vl_video_buffer.h"
  31 #include "util/u_screen.h"
  32 #include "util/u_video.h"
  33 #include "compiler/nir/nir.h"
  34
  35 #include <sys/utsname.h>
  36
  37 static const char *si_get_vendor(struct pipe_screen *pscreen)
  38 {
  39         /* Don't change this. Games such as Alien Isolation are broken if this
  40          * returns "Advanced Micro Devices, Inc."
  41          */
  42         return "X.Org";
  43 }
  44
  45 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  46 {
  47         return "AMD";
  48 }
  49
  50 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  51 {
  52         struct si_screen *sscreen = (struct si_screen *)pscreen;
  53
  54         switch (param) {
  55         /* Supported features (boolean caps). */
  56         case PIPE_CAP_ACCELERATED:
  57         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  58         case PIPE_CAP_ANISOTROPIC_FILTER:
  59         case PIPE_CAP_POINT_SPRITE:
  60         case PIPE_CAP_OCCLUSION_QUERY:
  61         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  62         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  63         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  64         case PIPE_CAP_TEXTURE_SWIZZLE:
  65         case PIPE_CAP_DEPTH_CLIP_DISABLE:
  66         case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
  67         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  68         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  69         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  70         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  71         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  72         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  73         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
  74         case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
  75         case PIPE_CAP_VERTEX_SHADER_SATURATE:
  76         case PIPE_CAP_SEAMLESS_CUBE_MAP:
  77         case PIPE_CAP_PRIMITIVE_RESTART:
  78         case PIPE_CAP_CONDITIONAL_RENDER:
  79         case PIPE_CAP_TEXTURE_BARRIER:
  80         case PIPE_CAP_INDEP_BLEND_ENABLE:
  81         case PIPE_CAP_INDEP_BLEND_FUNC:
  82         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  83         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  84         case PIPE_CAP_START_INSTANCE:
  85         case PIPE_CAP_NPOT_TEXTURES:
  86         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  87         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  88         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
  89         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
  90         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  91         case PIPE_CAP_TGSI_INSTANCEID:
  92         case PIPE_CAP_COMPUTE:
  93         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  94         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
  95         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
  96         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  97         case PIPE_CAP_CUBE_MAP_ARRAY:
  98         case PIPE_CAP_SAMPLE_SHADING:
  99         case PIPE_CAP_DRAW_INDIRECT:
 100         case PIPE_CAP_CLIP_HALFZ:
 101         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 102         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 103         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 104         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 105         case PIPE_CAP_TGSI_TEXCOORD:
 106         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 107         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 108         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 109         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 110         case PIPE_CAP_SHAREABLE_SHADERS:
 111         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 112         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 113         case PIPE_CAP_TEXTURE_QUERY_LOD:
 114         case PIPE_CAP_TEXTURE_GATHER_SM5:
 115         case PIPE_CAP_TGSI_TXQS:
 116         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 117         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 118         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 119         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 120         case PIPE_CAP_INVALIDATE_BUFFER:
 121         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 122         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 123         case PIPE_CAP_QUERY_MEMORY_INFO:
 124         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 125         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 126         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 127         case PIPE_CAP_GENERATE_MIPMAP:
 128         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 129         case PIPE_CAP_STRING_MARKER:
 130         case PIPE_CAP_CLEAR_TEXTURE:
 131         case PIPE_CAP_CULL_DISTANCE:
 132         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 133         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 134         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 135         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 136         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 137         case PIPE_CAP_DOUBLES:
 138         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 139         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 140         case PIPE_CAP_BINDLESS_TEXTURE:
 141         case PIPE_CAP_QUERY_TIMESTAMP:
 142         case PIPE_CAP_QUERY_TIME_ELAPSED:
 143         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 144         case PIPE_CAP_MEMOBJ:
 145         case PIPE_CAP_LOAD_CONSTBUF:
 146         case PIPE_CAP_INT64:
 147         case PIPE_CAP_INT64_DIVMOD:
 148         case PIPE_CAP_TGSI_CLOCK:
 149         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 150         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 151         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 152         case PIPE_CAP_TGSI_BALLOT:
 153         case PIPE_CAP_TGSI_VOTE:
 154         case PIPE_CAP_FBFETCH:
 155         case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
 156         case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 157         case PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA:
 158         case PIPE_CAP_TGSI_DIV:
 159         case PIPE_CAP_PACKED_UNIFORMS:
 160         case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
 161         case PIPE_CAP_GL_SPIRV:
 162                 return 1;
 163
 164         case PIPE_CAP_QUERY_SO_OVERFLOW:
 165                 return !sscreen->use_ngg_streamout;
 166
 167         case PIPE_CAP_POST_DEPTH_COVERAGE:
 168                 return sscreen->info.chip_class >= GFX10;
 169
 170         case PIPE_CAP_GRAPHICS:
 171                 return sscreen->info.has_graphics;
 172
 173         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 174                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 175
 176         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 177                 return sscreen->info.has_gpu_reset_status_query;
 178
 179         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 180                 return sscreen->info.has_2d_tiling;
 181
 182         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 183                 return SI_MAP_BUFFER_ALIGNMENT;
 184
 185         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 186         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 187         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 188         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 189         case PIPE_CAP_MAX_VERTEX_STREAMS:
 190         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 191         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 192                 return 4;
 193
 194         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 195         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 196                 if (!sscreen->info.has_indirect_compute_dispatch)
 197                         return 420;
 198                 return 460;
 199
 200         case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 201                 /* Optimal number for good TexSubImage performance on Polaris10. */
 202                 return 64 * 1024 * 1024;
 203
 204         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 205         case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 206                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 207
 208         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 209         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 210         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 211                 return LLVM_VERSION_MAJOR < 9 && !sscreen->info.has_unaligned_shader_loads;
 212
 213         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 214                 return sscreen->info.has_sparse_vm_mappings ?
 215                                 RADEON_SPARSE_PAGE_SIZE : 0;
 216
 217
 218         case PIPE_CAP_UMA:
 219                 return 0;
 220
 221         case PIPE_CAP_FENCE_SIGNAL:
 222                 return sscreen->info.has_syncobj;
 223
 224         case PIPE_CAP_CONSTBUF0_FLAGS:
 225                 return SI_RESOURCE_FLAG_32BIT;
 226
 227         case PIPE_CAP_NATIVE_FENCE_FD:
 228                 return sscreen->info.has_fence_to_handle;
 229
 230         case PIPE_CAP_DRAW_PARAMETERS:
 231         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 232         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 233                 return sscreen->has_draw_indirect_multi;
 234
 235         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 236                 return 30;
 237
 238         case PIPE_CAP_MAX_VARYINGS:
 239                 return 32;
 240
 241         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 242                 return sscreen->info.chip_class <= GFX8 ?
 243                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 244
 245         /* Stream output. */
 246         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 247         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 248                 return 32*4;
 249
 250         /* Geometry shader output. */
 251         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 252                 /* gfx9 has to report 256 to make piglit/gs-max-output pass.
 253                  * gfx8 and earlier can do 1024.
 254                  */
 255                 return 256;
 256         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 257                 return 4095;
 258         case PIPE_CAP_MAX_GS_INVOCATIONS:
 259                 /* The closed driver exposes 127, but 125 is the greatest
 260                  * number that works. */
 261                 return 125;
 262
 263         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 264                 return 2048;
 265
 266         /* Texturing. */
 267         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 268                 return 16384;
 269         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 270                 return 15; /* 16384 */
 271         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 272                 if (sscreen->info.chip_class >= GFX10)
 273                         return 14;
 274                 /* textures support 8192, but layered rendering supports 2048 */
 275                 return 12;
 276         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 277                 if (sscreen->info.chip_class >= GFX10)
 278                         return 8192;
 279                 /* textures support 8192, but layered rendering supports 2048 */
 280                 return 2048;
 281
 282         /* Viewports and render targets. */
 283         case PIPE_CAP_MAX_VIEWPORTS:
 284                 return SI_MAX_VIEWPORTS;
 285         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 286         case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 287         case PIPE_CAP_MAX_RENDER_TARGETS:
 288                 return 8;
 289         case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 290                 return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
 291
 292         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 293         case PIPE_CAP_MIN_TEXEL_OFFSET:
 294                 return -32;
 295
 296         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 297         case PIPE_CAP_MAX_TEXEL_OFFSET:
 298                 return 31;
 299
 300         case PIPE_CAP_ENDIANNESS:
 301                 return PIPE_ENDIAN_LITTLE;
 302
 303         case PIPE_CAP_VENDOR_ID:
 304                 return ATI_VENDOR_ID;
 305         case PIPE_CAP_DEVICE_ID:
 306                 return sscreen->info.pci_id;
 307         case PIPE_CAP_VIDEO_MEMORY:
 308                 return sscreen->info.vram_size >> 20;
 309         case PIPE_CAP_PCI_GROUP:
 310                 return sscreen->info.pci_domain;
 311         case PIPE_CAP_PCI_BUS:
 312                 return sscreen->info.pci_bus;
 313         case PIPE_CAP_PCI_DEVICE:
 314                 return sscreen->info.pci_dev;
 315         case PIPE_CAP_PCI_FUNCTION:
 316                 return sscreen->info.pci_func;
 317         case PIPE_CAP_TGSI_ATOMINC_WRAP:
 318                 return LLVM_VERSION_MAJOR >= 10;
 319
 320         default:
 321                 return u_pipe_screen_get_param_defaults(pscreen, param);
 322         }
 323 }
 324
 325 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 326 {
 327         switch (param) {
 328         case PIPE_CAPF_MAX_LINE_WIDTH:
 329         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 330                 /* This depends on the quant mode, though the precise interactions
 331                  * are unknown. */
 332                 return 2048;
 333         case PIPE_CAPF_MAX_POINT_WIDTH:
 334         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 335                 return SI_MAX_POINT_SIZE;
 336         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 337                 return 16.0f;
 338         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 339                 return 16.0f;
 340         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 341         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 342         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 343                 return 0.0f;
 344         }
 345         return 0.0f;
 346 }
 347
 348 static int si_get_shader_param(struct pipe_screen* pscreen,
 349                                enum pipe_shader_type shader,
 350                                enum pipe_shader_cap param)
 351 {
 352         struct si_screen *sscreen = (struct si_screen *)pscreen;
 353
 354         switch(shader)
 355         {
 356         case PIPE_SHADER_FRAGMENT:
 357         case PIPE_SHADER_VERTEX:
 358         case PIPE_SHADER_GEOMETRY:
 359         case PIPE_SHADER_TESS_CTRL:
 360         case PIPE_SHADER_TESS_EVAL:
 361                 break;
 362         case PIPE_SHADER_COMPUTE:
 363                 switch (param) {
 364                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 365                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 366
 367                         if (sscreen->info.has_indirect_compute_dispatch)
 368                                 ir |= 1 << PIPE_SHADER_IR_NIR;
 369
 370                         return ir;
 371                 }
 372
 373                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 374                         uint64_t max_const_buffer_size;
 375                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_NIR,
 376                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 377                                 &max_const_buffer_size);
 378                         return MIN2(max_const_buffer_size, INT_MAX);
 379                 }
 380                 default:
 381                         /* If compute shaders don't require a special value
 382                          * for this cap, we can return the same value we
 383                          * do for other shader types. */
 384                         break;
 385                 }
 386                 break;
 387         default:
 388                 return 0;
 389         }
 390
 391         switch (param) {
 392         /* Shader limits. */
 393         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 394         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 395         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 396         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 397         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 398                 return 16384;
 399         case PIPE_SHADER_CAP_MAX_INPUTS:
 400                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 401         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 402                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 403         case PIPE_SHADER_CAP_MAX_TEMPS:
 404                 return 256; /* Max native temporaries. */
 405         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 406                 return MIN2(sscreen->info.max_alloc_size, INT_MAX - 3); /* aligned to 4 */
 407         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 408                 return SI_NUM_CONST_BUFFERS;
 409         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 410         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 411                 return SI_NUM_SAMPLERS;
 412         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 413                 return SI_NUM_SHADER_BUFFERS;
 414         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 415                 return SI_NUM_IMAGES;
 416         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 417                 return 0;
 418         case PIPE_SHADER_CAP_PREFERRED_IR:
 419                 return PIPE_SHADER_IR_NIR;
 420         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 421                 return 4;
 422
 423         /* Supported boolean features. */
 424         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 425         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 426         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 427         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 428         case PIPE_SHADER_CAP_INTEGERS:
 429         case PIPE_SHADER_CAP_INT64_ATOMICS:
 430         case PIPE_SHADER_CAP_FP16:
 431         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 432         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 433         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 434         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 435         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 436         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 437                 return 1;
 438
 439         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 440                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 441                 if (shader == PIPE_SHADER_GEOMETRY)
 442                         return 0;
 443
 444                 if (shader == PIPE_SHADER_VERTEX &&
 445                     !sscreen->llvm_has_working_vgpr_indexing)
 446                         return 0;
 447
 448                 /* TCS and TES load inputs directly from LDS or offchip
 449                  * memory, so indirect indexing is always supported.
 450                  * PS has to support indirect indexing, because we can't
 451                  * lower that to TEMPs for INTERP instructions.
 452                  */
 453                 return 1;
 454
 455         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 456                 return sscreen->llvm_has_working_vgpr_indexing ||
 457                        /* TCS stores outputs directly to memory. */
 458                        shader == PIPE_SHADER_TESS_CTRL;
 459
 460         /* Unsupported boolean features. */
 461         case PIPE_SHADER_CAP_SUBROUTINES:
 462         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 463         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 464         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 465                 return 0;
 466         }
 467         return 0;
 468 }
 469
 470 static const struct nir_shader_compiler_options nir_options = {
 471         .lower_scmp = true,
 472         .lower_flrp32 = true,
 473         .lower_flrp64 = true,
 474         .lower_fsat = true,
 475         .lower_fdiv = true,
 476         .lower_bitfield_insert_to_bitfield_select = true,
 477         .lower_bitfield_extract = true,
 478         .lower_sub = true,
 479         .fuse_ffma = true,
 480         .lower_fmod = true,
 481         .lower_pack_snorm_4x8 = true,
 482         .lower_pack_unorm_4x8 = true,
 483         .lower_unpack_snorm_2x16 = true,
 484         .lower_unpack_snorm_4x8 = true,
 485         .lower_unpack_unorm_2x16 = true,
 486         .lower_unpack_unorm_4x8 = true,
 487         .lower_extract_byte = true,
 488         .lower_extract_word = true,
 489         .lower_rotate = true,
 490         .lower_to_scalar = true,
 491         .optimize_sample_mask_in = true,
 492         .max_unroll_iterations = 32,
 493         .use_interpolated_input_intrinsics = true,
 494 };
 495
 496 static const void *
 497 si_get_compiler_options(struct pipe_screen *screen,
 498                         enum pipe_shader_ir ir,
 499                         enum pipe_shader_type shader)
 500 {
 501         assert(ir == PIPE_SHADER_IR_NIR);
 502         return &nir_options;
 503 }
 504
 505 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 506 {
 507         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 508 }
 509
 510 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 511 {
 512         struct si_screen *sscreen = (struct si_screen *)pscreen;
 513
 514         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 515 }
 516
 517 static const char* si_get_name(struct pipe_screen *pscreen)
 518 {
 519         struct si_screen *sscreen = (struct si_screen*)pscreen;
 520
 521         return sscreen->renderer_string;
 522 }
 523
 524 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 525                                         enum pipe_video_profile profile,
 526                                         enum pipe_video_entrypoint entrypoint,
 527                                         enum pipe_video_cap param)
 528 {
 529         switch (param) {
 530         case PIPE_VIDEO_CAP_SUPPORTED:
 531                 return vl_profile_supported(screen, profile, entrypoint);
 532         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 533                 return 1;
 534         case PIPE_VIDEO_CAP_MAX_WIDTH:
 535         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 536                 return vl_video_buffer_max_size(screen);
 537         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 538                 return PIPE_FORMAT_NV12;
 539         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 540                 return false;
 541         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 542                 return false;
 543         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 544                 return true;
 545         case PIPE_VIDEO_CAP_MAX_LEVEL:
 546                 return vl_level_supported(screen, profile);
 547         default:
 548                 return 0;
 549         }
 550 }
 551
 552 static int si_get_video_param(struct pipe_screen *screen,
 553                               enum pipe_video_profile profile,
 554                               enum pipe_video_entrypoint entrypoint,
 555                               enum pipe_video_cap param)
 556 {
 557         struct si_screen *sscreen = (struct si_screen *)screen;
 558         enum pipe_video_format codec = u_reduce_video_profile(profile);
 559
 560         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 561                 switch (param) {
 562                 case PIPE_VIDEO_CAP_SUPPORTED:
 563                         return ((codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 564                                 (sscreen->info.family >= CHIP_RAVEN ||
 565                                  si_vce_is_fw_version_supported(sscreen))) ||
 566                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 567                                 (sscreen->info.family >= CHIP_RAVEN ||
 568                                  si_radeon_uvd_enc_supported(sscreen))) ||
 569                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 &&
 570                                  sscreen->info.family >= CHIP_RENOIR));
 571                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 572                         return 1;
 573                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 574                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 575                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 576                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 577                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 578                         return PIPE_FORMAT_NV12;
 579                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 580                         return false;
 581                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 582                         return false;
 583                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 584                         return true;
 585                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 586                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 587                 default:
 588                         return 0;
 589                 }
 590         }
 591
 592         switch (param) {
 593         case PIPE_VIDEO_CAP_SUPPORTED:
 594                 switch (codec) {
 595                 case PIPE_VIDEO_FORMAT_MPEG12:
 596                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 597                 case PIPE_VIDEO_FORMAT_MPEG4:
 598                         return 1;
 599                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 600                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 601                              sscreen->info.family == CHIP_POLARIS11) &&
 602                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 603                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 604                                 return false;
 605                         }
 606                         return true;
 607                 case PIPE_VIDEO_FORMAT_VC1:
 608                         return true;
 609                 case PIPE_VIDEO_FORMAT_HEVC:
 610                         /* Carrizo only supports HEVC Main */
 611                         if (sscreen->info.family >= CHIP_STONEY)
 612                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 613                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 614                         else if (sscreen->info.family >= CHIP_CARRIZO)
 615                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 616                         return false;
 617                 case PIPE_VIDEO_FORMAT_JPEG:
 618                         if (sscreen->info.family >= CHIP_RAVEN)
 619                                 return true;
 620                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 621                                 return false;
 622                         if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 19)) {
 623                                 RVID_ERR("No MJPEG support for the kernel version\n");
 624                                 return false;
 625                         }
 626                         return true;
 627                 case PIPE_VIDEO_FORMAT_VP9:
 628                         if (sscreen->info.family < CHIP_RAVEN)
 629                                 return false;
 630                         return true;
 631                 default:
 632                         return false;
 633                 }
 634         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 635                 return 1;
 636         case PIPE_VIDEO_CAP_MAX_WIDTH:
 637                 switch (codec) {
 638                 case PIPE_VIDEO_FORMAT_HEVC:
 639                 case PIPE_VIDEO_FORMAT_VP9:
 640                         return (sscreen->info.family < CHIP_RENOIR) ?
 641                                ((sscreen->info.family < CHIP_TONGA) ? 2048 : 4096) :
 642                                8192;
 643                 default:
 644                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 645                 }
 646         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 647                 switch (codec) {
 648                 case PIPE_VIDEO_FORMAT_HEVC:
 649                 case PIPE_VIDEO_FORMAT_VP9:
 650                         return (sscreen->info.family < CHIP_RENOIR) ?
 651                                ((sscreen->info.family < CHIP_TONGA) ? 1152 : 4096) :
 652                                4352;
 653                 default:
 654                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 655                 }
 656         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 657                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 658                         return PIPE_FORMAT_P010;
 659                 else if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 660                         return PIPE_FORMAT_P016;
 661                 else
 662                         return PIPE_FORMAT_NV12;
 663
 664         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 665         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 666                 enum pipe_video_format format = u_reduce_video_profile(profile);
 667
 668                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 669                         return false; //The firmware doesn't support interlaced HEVC.
 670                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 671                         return false;
 672                 else if (format == PIPE_VIDEO_FORMAT_VP9)
 673                         return false;
 674                 return true;
 675         }
 676         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 677                 return true;
 678         case PIPE_VIDEO_CAP_MAX_LEVEL:
 679                 switch (profile) {
 680                 case PIPE_VIDEO_PROFILE_MPEG1:
 681                         return 0;
 682                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 683                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 684                         return 3;
 685                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 686                         return 3;
 687                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 688                         return 5;
 689                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 690                         return 1;
 691                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 692                         return 2;
 693                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 694                         return 4;
 695                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 696                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 697                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 698                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 699                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 700                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 701                         return 186;
 702                 default:
 703                         return 0;
 704                 }
 705         default:
 706                 return 0;
 707         }
 708 }
 709
 710 static bool si_vid_is_format_supported(struct pipe_screen *screen,
 711                                        enum pipe_format format,
 712                                        enum pipe_video_profile profile,
 713                                        enum pipe_video_entrypoint entrypoint)
 714 {
 715         /* HEVC 10 bit decoding should use P010 instead of NV12 if possible */
 716         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 717                 return (format == PIPE_FORMAT_NV12) ||
 718                        (format == PIPE_FORMAT_P010) ||
 719                        (format == PIPE_FORMAT_P016);
 720
 721         /* Vp9 profile 2 supports 10 bit decoding using P016 */
 722         if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 723                 return format == PIPE_FORMAT_P016;
 724
 725
 726         /* we can only handle this one with UVD */
 727         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 728                 return format == PIPE_FORMAT_NV12;
 729
 730         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 731 }
 732
 733 static unsigned get_max_threads_per_block(struct si_screen *screen,
 734                                           enum pipe_shader_ir ir_type)
 735 {
 736         if (ir_type == PIPE_SHADER_IR_NATIVE)
 737                 return 256;
 738
 739         /* LLVM 10 only supports 1024 threads per block. */
 740         return 1024;
 741 }
 742
 743 static int si_get_compute_param(struct pipe_screen *screen,
 744                                 enum pipe_shader_ir ir_type,
 745                                 enum pipe_compute_cap param,
 746                                 void *ret)
 747 {
 748         struct si_screen *sscreen = (struct si_screen *)screen;
 749
 750         //TODO: select these params by asic
 751         switch (param) {
 752         case PIPE_COMPUTE_CAP_IR_TARGET: {
 753                 const char *gpu, *triple;
 754
 755                 triple = "amdgcn-mesa-mesa3d";
 756                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 757                 if (ret) {
 758                         sprintf(ret, "%s-%s", gpu, triple);
 759                 }
 760                 /* +2 for dash and terminating NIL byte */
 761                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 762         }
 763         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 764                 if (ret) {
 765                         uint64_t *grid_dimension = ret;
 766                         grid_dimension[0] = 3;
 767                 }
 768                 return 1 * sizeof(uint64_t);
 769
 770         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 771                 if (ret) {
 772                         uint64_t *grid_size = ret;
 773                         grid_size[0] = 65535;
 774                         grid_size[1] = 65535;
 775                         grid_size[2] = 65535;
 776                 }
 777                 return 3 * sizeof(uint64_t) ;
 778
 779         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 780                 if (ret) {
 781                         uint64_t *block_size = ret;
 782                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 783                         block_size[0] = threads_per_block;
 784                         block_size[1] = threads_per_block;
 785                         block_size[2] = threads_per_block;
 786                 }
 787                 return 3 * sizeof(uint64_t);
 788
 789         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 790                 if (ret) {
 791                         uint64_t *max_threads_per_block = ret;
 792                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 793                 }
 794                 return sizeof(uint64_t);
 795         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 796                 if (ret) {
 797                         uint32_t *address_bits = ret;
 798                         address_bits[0] = 64;
 799                 }
 800                 return 1 * sizeof(uint32_t);
 801
 802         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 803                 if (ret) {
 804                         uint64_t *max_global_size = ret;
 805                         uint64_t max_mem_alloc_size;
 806
 807                         si_get_compute_param(screen, ir_type,
 808                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 809                                 &max_mem_alloc_size);
 810
 811                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 812                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 813                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 814                          * make sure we never report more than
 815                          * 4 * MAX_MEM_ALLOC_SIZE.
 816                          */
 817                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 818                                                 MAX2(sscreen->info.gart_size,
 819                                                      sscreen->info.vram_size));
 820                 }
 821                 return sizeof(uint64_t);
 822
 823         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 824                 if (ret) {
 825                         uint64_t *max_local_size = ret;
 826                         /* Value reported by the closed source driver. */
 827                         *max_local_size = 32768;
 828                 }
 829                 return sizeof(uint64_t);
 830
 831         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 832                 if (ret) {
 833                         uint64_t *max_input_size = ret;
 834                         /* Value reported by the closed source driver. */
 835                         *max_input_size = 1024;
 836                 }
 837                 return sizeof(uint64_t);
 838
 839         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 840                 if (ret) {
 841                         uint64_t *max_mem_alloc_size = ret;
 842
 843                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 844                 }
 845                 return sizeof(uint64_t);
 846
 847         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 848                 if (ret) {
 849                         uint32_t *max_clock_frequency = ret;
 850                         *max_clock_frequency = sscreen->info.max_shader_clock;
 851                 }
 852                 return sizeof(uint32_t);
 853
 854         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 855                 if (ret) {
 856                         uint32_t *max_compute_units = ret;
 857                         *max_compute_units = sscreen->info.num_good_compute_units;
 858                 }
 859                 return sizeof(uint32_t);
 860
 861         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 862                 if (ret) {
 863                         uint32_t *images_supported = ret;
 864                         *images_supported = 0;
 865                 }
 866                 return sizeof(uint32_t);
 867         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 868                 break; /* unused */
 869         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 870                 if (ret) {
 871                         uint32_t *subgroup_size = ret;
 872                         *subgroup_size = sscreen->compute_wave_size;
 873                 }
 874                 return sizeof(uint32_t);
 875         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 876                 if (ret) {
 877                         uint64_t *max_variable_threads_per_block = ret;
 878                         if (ir_type == PIPE_SHADER_IR_NATIVE)
 879                                 *max_variable_threads_per_block = 0;
 880                         else
 881                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 882                 }
 883                 return sizeof(uint64_t);
 884         }
 885
 886         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 887         return 0;
 888 }
 889
 890 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 891 {
 892         struct si_screen *sscreen = (struct si_screen*)screen;
 893
 894         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 895                         sscreen->info.clock_crystal_freq;
 896 }
 897
 898 static void si_query_memory_info(struct pipe_screen *screen,
 899                                  struct pipe_memory_info *info)
 900 {
 901         struct si_screen *sscreen = (struct si_screen*)screen;
 902         struct radeon_winsys *ws = sscreen->ws;
 903         unsigned vram_usage, gtt_usage;
 904
 905         info->total_device_memory = sscreen->info.vram_size / 1024;
 906         info->total_staging_memory = sscreen->info.gart_size / 1024;
 907
 908         /* The real TTM memory usage is somewhat random, because:
 909          *
 910          * 1) TTM delays freeing memory, because it can only free it after
 911          *    fences expire.
 912          *
 913          * 2) The memory usage can be really low if big VRAM evictions are
 914          *    taking place, but the real usage is well above the size of VRAM.
 915          *
 916          * Instead, return statistics of this process.
 917          */
 918         vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
 919         gtt_usage =  ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
 920
 921         info->avail_device_memory =
 922                 vram_usage <= info->total_device_memory ?
 923                                 info->total_device_memory - vram_usage : 0;
 924         info->avail_staging_memory =
 925                 gtt_usage <= info->total_staging_memory ?
 926                                 info->total_staging_memory - gtt_usage : 0;
 927
 928         info->device_memory_evicted =
 929                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 930
 931         if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 4)
 932                 info->nr_device_memory_evictions =
 933                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 934         else
 935                 /* Just return the number of evicted 64KB pages. */
 936                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 937 }
 938
 939 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 940 {
 941         struct si_screen *sscreen = (struct si_screen*)pscreen;
 942
 943         return sscreen->disk_shader_cache;
 944 }
 945
 946 static void si_init_renderer_string(struct si_screen *sscreen)
 947 {
 948         char first_name[256], second_name[32] = {}, kernel_version[128] = {};
 949         struct utsname uname_data;
 950
 951         if (sscreen->info.marketing_name) {
 952                 snprintf(first_name, sizeof(first_name), "%s",
 953                          sscreen->info.marketing_name);
 954                 snprintf(second_name, sizeof(second_name), "%s, ",
 955                          sscreen->info.name);
 956         } else {
 957                 snprintf(first_name, sizeof(first_name), "AMD %s",
 958                          sscreen->info.name);
 959         }
 960
 961         if (uname(&uname_data) == 0)
 962                 snprintf(kernel_version, sizeof(kernel_version),
 963                          ", %s", uname_data.release);
 964
 965         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 966                  "%s (%sDRM %i.%i.%i%s, LLVM " MESA_LLVM_VERSION_STRING ")",
 967                  first_name, second_name, sscreen->info.drm_major,
 968                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 969                  kernel_version);
 970 }
 971
 972 void si_init_screen_get_functions(struct si_screen *sscreen)
 973 {
 974         sscreen->b.get_name = si_get_name;
 975         sscreen->b.get_vendor = si_get_vendor;
 976         sscreen->b.get_device_vendor = si_get_device_vendor;
 977         sscreen->b.get_param = si_get_param;
 978         sscreen->b.get_paramf = si_get_paramf;
 979         sscreen->b.get_compute_param = si_get_compute_param;
 980         sscreen->b.get_timestamp = si_get_timestamp;
 981         sscreen->b.get_shader_param = si_get_shader_param;
 982         sscreen->b.get_compiler_options = si_get_compiler_options;
 983         sscreen->b.get_device_uuid = si_get_device_uuid;
 984         sscreen->b.get_driver_uuid = si_get_driver_uuid;
 985         sscreen->b.query_memory_info = si_query_memory_info;
 986         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
 987
 988         if (sscreen->info.has_hw_decode) {
 989                 sscreen->b.get_video_param = si_get_video_param;
 990                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
 991         } else {
 992                 sscreen->b.get_video_param = si_get_video_param_no_decode;
 993                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 994         }
 995
 996         si_init_renderer_string(sscreen);
 997 }