src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "radeon/radeon_video.h"
  27 #include "radeon/radeon_vce.h"
  28 #include "radeon/radeon_uvd_enc.h"
  29 #include "ac_llvm_util.h"
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32 #include "util/u_screen.h"
  33 #include "util/u_video.h"
  34 #include "compiler/nir/nir.h"
  35
  36 #include <sys/utsname.h>
  37
  38 static const char *si_get_vendor(struct pipe_screen *pscreen)
  39 {
  40         /* Don't change this. Games such as Alien Isolation are broken if this
  41          * returns "Advanced Micro Devices, Inc."
  42          */
  43         return "X.Org";
  44 }
  45
  46 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  47 {
  48         return "AMD";
  49 }
  50
  51 static const char *si_get_marketing_name(struct radeon_winsys *ws)
  52 {
  53         if (!ws->get_chip_name)
  54                 return NULL;
  55         return ws->get_chip_name(ws);
  56 }
  57
  58 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  59 {
  60         struct si_screen *sscreen = (struct si_screen *)pscreen;
  61
  62         switch (param) {
  63         /* Supported features (boolean caps). */
  64         case PIPE_CAP_ACCELERATED:
  65         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  66         case PIPE_CAP_ANISOTROPIC_FILTER:
  67         case PIPE_CAP_POINT_SPRITE:
  68         case PIPE_CAP_OCCLUSION_QUERY:
  69         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  70         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  71         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  72         case PIPE_CAP_TEXTURE_SWIZZLE:
  73         case PIPE_CAP_DEPTH_CLIP_DISABLE:
  74         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  75         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  76         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  77         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  78         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  79         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  80         case PIPE_CAP_SM3:
  81         case PIPE_CAP_SEAMLESS_CUBE_MAP:
  82         case PIPE_CAP_PRIMITIVE_RESTART:
  83         case PIPE_CAP_CONDITIONAL_RENDER:
  84         case PIPE_CAP_TEXTURE_BARRIER:
  85         case PIPE_CAP_INDEP_BLEND_ENABLE:
  86         case PIPE_CAP_INDEP_BLEND_FUNC:
  87         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  88         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  89         case PIPE_CAP_START_INSTANCE:
  90         case PIPE_CAP_NPOT_TEXTURES:
  91         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  92         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  93         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
  94         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
  95         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  96         case PIPE_CAP_TGSI_INSTANCEID:
  97         case PIPE_CAP_COMPUTE:
  98         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  99         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 100         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 101         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 102         case PIPE_CAP_CUBE_MAP_ARRAY:
 103         case PIPE_CAP_SAMPLE_SHADING:
 104         case PIPE_CAP_DRAW_INDIRECT:
 105         case PIPE_CAP_CLIP_HALFZ:
 106         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 107         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 108         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 109         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 110         case PIPE_CAP_TGSI_TEXCOORD:
 111         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 112         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 113         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 114         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 115         case PIPE_CAP_SHAREABLE_SHADERS:
 116         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 117         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 118         case PIPE_CAP_TEXTURE_QUERY_LOD:
 119         case PIPE_CAP_TEXTURE_GATHER_SM5:
 120         case PIPE_CAP_TGSI_TXQS:
 121         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 122         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 123         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 124         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 125         case PIPE_CAP_INVALIDATE_BUFFER:
 126         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 127         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 128         case PIPE_CAP_QUERY_MEMORY_INFO:
 129         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 130         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 131         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 132         case PIPE_CAP_GENERATE_MIPMAP:
 133         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 134         case PIPE_CAP_STRING_MARKER:
 135         case PIPE_CAP_CLEAR_TEXTURE:
 136         case PIPE_CAP_CULL_DISTANCE:
 137         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 138         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 139         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 140         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 141         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 142         case PIPE_CAP_DOUBLES:
 143         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 144         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 145         case PIPE_CAP_BINDLESS_TEXTURE:
 146         case PIPE_CAP_QUERY_TIMESTAMP:
 147         case PIPE_CAP_QUERY_TIME_ELAPSED:
 148         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 149         case PIPE_CAP_QUERY_SO_OVERFLOW:
 150         case PIPE_CAP_MEMOBJ:
 151         case PIPE_CAP_LOAD_CONSTBUF:
 152         case PIPE_CAP_INT64:
 153         case PIPE_CAP_INT64_DIVMOD:
 154         case PIPE_CAP_TGSI_CLOCK:
 155         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 156         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 157         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 158         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 159         case PIPE_CAP_TGSI_BALLOT:
 160         case PIPE_CAP_TGSI_VOTE:
 161         case PIPE_CAP_TGSI_FS_FBFETCH:
 162                 return 1;
 163
 164         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 165                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 166
 167         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 168                 return sscreen->info.has_gpu_reset_status_query ||
 169                        sscreen->info.has_gpu_reset_counter_query;
 170
 171         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 172                 return sscreen->info.has_2d_tiling;
 173
 174         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 175                 return SI_MAP_BUFFER_ALIGNMENT;
 176
 177         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 178         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 179         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 180         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 181         case PIPE_CAP_MAX_VERTEX_STREAMS:
 182         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 183         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 184                 return 4;
 185
 186         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 187         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 188                 if (sscreen->info.has_indirect_compute_dispatch)
 189                                 return 450;
 190                 return 420;
 191
 192         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 193         case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 194                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 195
 196         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 197         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 198         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 199                 return !sscreen->info.has_unaligned_shader_loads;
 200
 201         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 202                 return sscreen->info.has_sparse_vm_mappings ?
 203                                 RADEON_SPARSE_PAGE_SIZE : 0;
 204
 205         case PIPE_CAP_PACKED_UNIFORMS:
 206                 if (sscreen->debug_flags & DBG(NIR))
 207                         return 1;
 208                 return 0;
 209
 210         /* Unsupported features. */
 211         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 212         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 213         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 214         case PIPE_CAP_USER_VERTEX_BUFFERS:
 215         case PIPE_CAP_FAKE_SW_MSAA:
 216         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 217         case PIPE_CAP_VERTEXID_NOBASE:
 218         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 219         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 220         case PIPE_CAP_UMA:
 221         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 222         case PIPE_CAP_POST_DEPTH_COVERAGE:
 223         case PIPE_CAP_TILE_RASTER_ORDER:
 224         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 225         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 226         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 227         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 228         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 229         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 230         case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 231         case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 232         case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 233                 return 0;
 234
 235         case PIPE_CAP_FENCE_SIGNAL:
 236                 return sscreen->info.has_syncobj;
 237
 238         case PIPE_CAP_CONSTBUF0_FLAGS:
 239                 return SI_RESOURCE_FLAG_32BIT;
 240
 241         case PIPE_CAP_NATIVE_FENCE_FD:
 242                 return sscreen->info.has_fence_to_handle;
 243
 244         case PIPE_CAP_DRAW_PARAMETERS:
 245         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 246         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 247                 return sscreen->has_draw_indirect_multi;
 248
 249         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 250                 return 30;
 251
 252         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 253                 return sscreen->info.chip_class <= VI ?
 254                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 255
 256         /* Stream output. */
 257         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 258         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 259                 return 32*4;
 260
 261         /* Geometry shader output. */
 262         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 263                 return 1024;
 264         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 265                 return 4095;
 266         case PIPE_CAP_MAX_GS_INVOCATIONS:
 267                 /* The closed driver exposes 127, but 125 is the greatest
 268                  * number that works. */
 269                 return 125;
 270
 271         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 272                 return 2048;
 273
 274         /* Texturing. */
 275         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 276         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 277                 return 15; /* 16384 */
 278         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 279                 /* textures support 8192, but layered rendering supports 2048 */
 280                 return 12;
 281         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 282                 /* textures support 8192, but layered rendering supports 2048 */
 283                 return 2048;
 284
 285         /* Viewports and render targets. */
 286         case PIPE_CAP_MAX_VIEWPORTS:
 287                 return SI_MAX_VIEWPORTS;
 288         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 289         case PIPE_CAP_MAX_RENDER_TARGETS:
 290                 return 8;
 291         case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 292                 return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
 293
 294         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 295         case PIPE_CAP_MIN_TEXEL_OFFSET:
 296                 return -32;
 297
 298         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 299         case PIPE_CAP_MAX_TEXEL_OFFSET:
 300                 return 31;
 301
 302         case PIPE_CAP_ENDIANNESS:
 303                 return PIPE_ENDIAN_LITTLE;
 304
 305         case PIPE_CAP_VENDOR_ID:
 306                 return ATI_VENDOR_ID;
 307         case PIPE_CAP_DEVICE_ID:
 308                 return sscreen->info.pci_id;
 309         case PIPE_CAP_VIDEO_MEMORY:
 310                 return sscreen->info.vram_size >> 20;
 311         case PIPE_CAP_PCI_GROUP:
 312                 return sscreen->info.pci_domain;
 313         case PIPE_CAP_PCI_BUS:
 314                 return sscreen->info.pci_bus;
 315         case PIPE_CAP_PCI_DEVICE:
 316                 return sscreen->info.pci_dev;
 317         case PIPE_CAP_PCI_FUNCTION:
 318                 return sscreen->info.pci_func;
 319
 320         default:
 321                 return u_pipe_screen_get_param_defaults(pscreen, param);
 322         }
 323 }
 324
 325 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 326 {
 327         switch (param) {
 328         case PIPE_CAPF_MAX_LINE_WIDTH:
 329         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 330         case PIPE_CAPF_MAX_POINT_WIDTH:
 331         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 332                 return 8192.0f;
 333         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 334                 return 16.0f;
 335         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 336                 return 16.0f;
 337         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 338         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 339         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 340                 return 0.0f;
 341         }
 342         return 0.0f;
 343 }
 344
 345 static int si_get_shader_param(struct pipe_screen* pscreen,
 346                                enum pipe_shader_type shader,
 347                                enum pipe_shader_cap param)
 348 {
 349         struct si_screen *sscreen = (struct si_screen *)pscreen;
 350
 351         switch(shader)
 352         {
 353         case PIPE_SHADER_FRAGMENT:
 354         case PIPE_SHADER_VERTEX:
 355         case PIPE_SHADER_GEOMETRY:
 356         case PIPE_SHADER_TESS_CTRL:
 357         case PIPE_SHADER_TESS_EVAL:
 358                 break;
 359         case PIPE_SHADER_COMPUTE:
 360                 switch (param) {
 361                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 362                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 363
 364                         if (sscreen->info.has_indirect_compute_dispatch)
 365                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 366
 367                         return ir;
 368                 }
 369
 370                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 371                         uint64_t max_const_buffer_size;
 372                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 373                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 374                                 &max_const_buffer_size);
 375                         return MIN2(max_const_buffer_size, INT_MAX);
 376                 }
 377                 default:
 378                         /* If compute shaders don't require a special value
 379                          * for this cap, we can return the same value we
 380                          * do for other shader types. */
 381                         break;
 382                 }
 383                 break;
 384         default:
 385                 return 0;
 386         }
 387
 388         switch (param) {
 389         /* Shader limits. */
 390         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 391         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 392         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 393         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 394         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 395                 return 16384;
 396         case PIPE_SHADER_CAP_MAX_INPUTS:
 397                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 398         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 399                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 400         case PIPE_SHADER_CAP_MAX_TEMPS:
 401                 return 256; /* Max native temporaries. */
 402         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 403                 return MIN2(sscreen->info.max_alloc_size, INT_MAX - 3); /* aligned to 4 */
 404         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 405                 return SI_NUM_CONST_BUFFERS;
 406         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 407         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 408                 return SI_NUM_SAMPLERS;
 409         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 410                 return SI_NUM_SHADER_BUFFERS;
 411         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 412                 return SI_NUM_IMAGES;
 413         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 414                 if (sscreen->debug_flags & DBG(NIR))
 415                         return 0;
 416                 return 32;
 417         case PIPE_SHADER_CAP_PREFERRED_IR:
 418                 if (sscreen->debug_flags & DBG(NIR))
 419                         return PIPE_SHADER_IR_NIR;
 420                 return PIPE_SHADER_IR_TGSI;
 421         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 422                 return 4;
 423
 424         /* Supported boolean features. */
 425         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 426         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 427         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 428         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 429         case PIPE_SHADER_CAP_INTEGERS:
 430         case PIPE_SHADER_CAP_INT64_ATOMICS:
 431         case PIPE_SHADER_CAP_FP16:
 432         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 433         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 434         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 435         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 436         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 437         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 438                 return 1;
 439
 440         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 441                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 442                 if (shader == PIPE_SHADER_GEOMETRY)
 443                         return 0;
 444
 445                 if (shader == PIPE_SHADER_VERTEX &&
 446                     !sscreen->llvm_has_working_vgpr_indexing)
 447                         return 0;
 448
 449                 /* Doing indirect indexing on GFX9 with LLVM 6.0 hangs.
 450                  * This means we don't support INTERP instructions with
 451                  * indirect indexing on inputs.
 452                  */
 453                 if (shader == PIPE_SHADER_FRAGMENT &&
 454                     !sscreen->llvm_has_working_vgpr_indexing &&
 455                     HAVE_LLVM < 0x0700)
 456                         return 0;
 457
 458                 /* TCS and TES load inputs directly from LDS or offchip
 459                  * memory, so indirect indexing is always supported.
 460                  * PS has to support indirect indexing, because we can't
 461                  * lower that to TEMPs for INTERP instructions.
 462                  */
 463                 return 1;
 464
 465         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 466                 return sscreen->llvm_has_working_vgpr_indexing ||
 467                        /* TCS stores outputs directly to memory. */
 468                        shader == PIPE_SHADER_TESS_CTRL;
 469
 470         /* Unsupported boolean features. */
 471         case PIPE_SHADER_CAP_SUBROUTINES:
 472         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 473         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 474         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 475                 return 0;
 476         case PIPE_SHADER_CAP_SCALAR_ISA:
 477                 return 1;
 478         }
 479         return 0;
 480 }
 481
 482 static const struct nir_shader_compiler_options nir_options = {
 483         .lower_scmp = true,
 484         .lower_flrp32 = true,
 485         .lower_flrp64 = true,
 486         .lower_fpow = true,
 487         .lower_fsat = true,
 488         .lower_fdiv = true,
 489         .lower_sub = true,
 490         .lower_ffma = true,
 491         .lower_pack_snorm_2x16 = true,
 492         .lower_pack_snorm_4x8 = true,
 493         .lower_pack_unorm_2x16 = true,
 494         .lower_pack_unorm_4x8 = true,
 495         .lower_unpack_snorm_2x16 = true,
 496         .lower_unpack_snorm_4x8 = true,
 497         .lower_unpack_unorm_2x16 = true,
 498         .lower_unpack_unorm_4x8 = true,
 499         .lower_extract_byte = true,
 500         .lower_extract_word = true,
 501         .max_unroll_iterations = 32,
 502         .native_integers = true,
 503 };
 504
 505 static const void *
 506 si_get_compiler_options(struct pipe_screen *screen,
 507                         enum pipe_shader_ir ir,
 508                         enum pipe_shader_type shader)
 509 {
 510         assert(ir == PIPE_SHADER_IR_NIR);
 511         return &nir_options;
 512 }
 513
 514 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 515 {
 516         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 517 }
 518
 519 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 520 {
 521         struct si_screen *sscreen = (struct si_screen *)pscreen;
 522
 523         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 524 }
 525
 526 static const char* si_get_name(struct pipe_screen *pscreen)
 527 {
 528         struct si_screen *sscreen = (struct si_screen*)pscreen;
 529
 530         return sscreen->renderer_string;
 531 }
 532
 533 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 534                                         enum pipe_video_profile profile,
 535                                         enum pipe_video_entrypoint entrypoint,
 536                                         enum pipe_video_cap param)
 537 {
 538         switch (param) {
 539         case PIPE_VIDEO_CAP_SUPPORTED:
 540                 return vl_profile_supported(screen, profile, entrypoint);
 541         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 542                 return 1;
 543         case PIPE_VIDEO_CAP_MAX_WIDTH:
 544         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 545                 return vl_video_buffer_max_size(screen);
 546         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 547                 return PIPE_FORMAT_NV12;
 548         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 549                 return false;
 550         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 551                 return false;
 552         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 553                 return true;
 554         case PIPE_VIDEO_CAP_MAX_LEVEL:
 555                 return vl_level_supported(screen, profile);
 556         default:
 557                 return 0;
 558         }
 559 }
 560
 561 static int si_get_video_param(struct pipe_screen *screen,
 562                               enum pipe_video_profile profile,
 563                               enum pipe_video_entrypoint entrypoint,
 564                               enum pipe_video_cap param)
 565 {
 566         struct si_screen *sscreen = (struct si_screen *)screen;
 567         enum pipe_video_format codec = u_reduce_video_profile(profile);
 568
 569         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 570                 switch (param) {
 571                 case PIPE_VIDEO_CAP_SUPPORTED:
 572                         return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 573                                 (si_vce_is_fw_version_supported(sscreen) ||
 574                                 sscreen->info.family == CHIP_RAVEN)) ||
 575                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 576                                 (sscreen->info.family == CHIP_RAVEN ||
 577                                 si_radeon_uvd_enc_supported(sscreen)));
 578                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 579                         return 1;
 580                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 581                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 582                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 583                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 584                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 585                         return PIPE_FORMAT_NV12;
 586                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 587                         return false;
 588                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 589                         return false;
 590                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 591                         return true;
 592                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 593                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 594                 default:
 595                         return 0;
 596                 }
 597         }
 598
 599         switch (param) {
 600         case PIPE_VIDEO_CAP_SUPPORTED:
 601                 switch (codec) {
 602                 case PIPE_VIDEO_FORMAT_MPEG12:
 603                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 604                 case PIPE_VIDEO_FORMAT_MPEG4:
 605                         return 1;
 606                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 607                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 608                              sscreen->info.family == CHIP_POLARIS11) &&
 609                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 610                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 611                                 return false;
 612                         }
 613                         return true;
 614                 case PIPE_VIDEO_FORMAT_VC1:
 615                         return true;
 616                 case PIPE_VIDEO_FORMAT_HEVC:
 617                         /* Carrizo only supports HEVC Main */
 618                         if (sscreen->info.family >= CHIP_STONEY)
 619                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 620                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 621                         else if (sscreen->info.family >= CHIP_CARRIZO)
 622                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 623                         return false;
 624                 case PIPE_VIDEO_FORMAT_JPEG:
 625                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 626                                 return false;
 627                         if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
 628                                 RVID_ERR("No MJPEG support for the kernel version\n");
 629                                 return false;
 630                         }
 631                         return true;
 632                 case PIPE_VIDEO_FORMAT_VP9:
 633                         if (sscreen->info.family < CHIP_RAVEN)
 634                                 return false;
 635                         return true;
 636                 default:
 637                         return false;
 638                 }
 639         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 640                 return 1;
 641         case PIPE_VIDEO_CAP_MAX_WIDTH:
 642                 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 643         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 644                 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 645         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 646                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 ||
 647                     profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 648                         return PIPE_FORMAT_P016;
 649                 else
 650                         return PIPE_FORMAT_NV12;
 651
 652         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 653         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 654                 enum pipe_video_format format = u_reduce_video_profile(profile);
 655
 656                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 657                         return false; //The firmware doesn't support interlaced HEVC.
 658                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 659                         return false;
 660                 else if (format == PIPE_VIDEO_FORMAT_VP9)
 661                         return false;
 662                 return true;
 663         }
 664         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 665                 return true;
 666         case PIPE_VIDEO_CAP_MAX_LEVEL:
 667                 switch (profile) {
 668                 case PIPE_VIDEO_PROFILE_MPEG1:
 669                         return 0;
 670                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 671                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 672                         return 3;
 673                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 674                         return 3;
 675                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 676                         return 5;
 677                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 678                         return 1;
 679                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 680                         return 2;
 681                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 682                         return 4;
 683                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 684                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 685                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 686                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 687                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 688                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 689                         return 186;
 690                 default:
 691                         return 0;
 692                 }
 693         default:
 694                 return 0;
 695         }
 696 }
 697
 698 static boolean si_vid_is_format_supported(struct pipe_screen *screen,
 699                                           enum pipe_format format,
 700                                           enum pipe_video_profile profile,
 701                                           enum pipe_video_entrypoint entrypoint)
 702 {
 703         /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
 704         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 705                 return (format == PIPE_FORMAT_NV12) ||
 706                         (format == PIPE_FORMAT_P016);
 707
 708         /* we can only handle this one with UVD */
 709         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 710                 return format == PIPE_FORMAT_NV12;
 711
 712         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 713 }
 714
 715 static unsigned get_max_threads_per_block(struct si_screen *screen,
 716                                           enum pipe_shader_ir ir_type)
 717 {
 718         if (ir_type == PIPE_SHADER_IR_NATIVE)
 719                 return 256;
 720
 721         /* Only 16 waves per thread-group on gfx9. */
 722         if (screen->info.chip_class >= GFX9)
 723                 return 1024;
 724
 725         /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
 726          * round number.
 727          */
 728         return 2048;
 729 }
 730
 731 static int si_get_compute_param(struct pipe_screen *screen,
 732                                 enum pipe_shader_ir ir_type,
 733                                 enum pipe_compute_cap param,
 734                                 void *ret)
 735 {
 736         struct si_screen *sscreen = (struct si_screen *)screen;
 737
 738         //TODO: select these params by asic
 739         switch (param) {
 740         case PIPE_COMPUTE_CAP_IR_TARGET: {
 741                 const char *gpu, *triple;
 742
 743                 triple = "amdgcn-mesa-mesa3d";
 744                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 745                 if (ret) {
 746                         sprintf(ret, "%s-%s", gpu, triple);
 747                 }
 748                 /* +2 for dash and terminating NIL byte */
 749                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 750         }
 751         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 752                 if (ret) {
 753                         uint64_t *grid_dimension = ret;
 754                         grid_dimension[0] = 3;
 755                 }
 756                 return 1 * sizeof(uint64_t);
 757
 758         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 759                 if (ret) {
 760                         uint64_t *grid_size = ret;
 761                         grid_size[0] = 65535;
 762                         grid_size[1] = 65535;
 763                         grid_size[2] = 65535;
 764                 }
 765                 return 3 * sizeof(uint64_t) ;
 766
 767         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 768                 if (ret) {
 769                         uint64_t *block_size = ret;
 770                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 771                         block_size[0] = threads_per_block;
 772                         block_size[1] = threads_per_block;
 773                         block_size[2] = threads_per_block;
 774                 }
 775                 return 3 * sizeof(uint64_t);
 776
 777         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 778                 if (ret) {
 779                         uint64_t *max_threads_per_block = ret;
 780                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 781                 }
 782                 return sizeof(uint64_t);
 783         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 784                 if (ret) {
 785                         uint32_t *address_bits = ret;
 786                         address_bits[0] = 64;
 787                 }
 788                 return 1 * sizeof(uint32_t);
 789
 790         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 791                 if (ret) {
 792                         uint64_t *max_global_size = ret;
 793                         uint64_t max_mem_alloc_size;
 794
 795                         si_get_compute_param(screen, ir_type,
 796                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 797                                 &max_mem_alloc_size);
 798
 799                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 800                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 801                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 802                          * make sure we never report more than
 803                          * 4 * MAX_MEM_ALLOC_SIZE.
 804                          */
 805                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 806                                                 MAX2(sscreen->info.gart_size,
 807                                                      sscreen->info.vram_size));
 808                 }
 809                 return sizeof(uint64_t);
 810
 811         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 812                 if (ret) {
 813                         uint64_t *max_local_size = ret;
 814                         /* Value reported by the closed source driver. */
 815                         *max_local_size = 32768;
 816                 }
 817                 return sizeof(uint64_t);
 818
 819         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 820                 if (ret) {
 821                         uint64_t *max_input_size = ret;
 822                         /* Value reported by the closed source driver. */
 823                         *max_input_size = 1024;
 824                 }
 825                 return sizeof(uint64_t);
 826
 827         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 828                 if (ret) {
 829                         uint64_t *max_mem_alloc_size = ret;
 830
 831                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 832                 }
 833                 return sizeof(uint64_t);
 834
 835         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 836                 if (ret) {
 837                         uint32_t *max_clock_frequency = ret;
 838                         *max_clock_frequency = sscreen->info.max_shader_clock;
 839                 }
 840                 return sizeof(uint32_t);
 841
 842         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 843                 if (ret) {
 844                         uint32_t *max_compute_units = ret;
 845                         *max_compute_units = sscreen->info.num_good_compute_units;
 846                 }
 847                 return sizeof(uint32_t);
 848
 849         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 850                 if (ret) {
 851                         uint32_t *images_supported = ret;
 852                         *images_supported = 0;
 853                 }
 854                 return sizeof(uint32_t);
 855         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 856                 break; /* unused */
 857         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 858                 if (ret) {
 859                         uint32_t *subgroup_size = ret;
 860                         *subgroup_size = 64;
 861                 }
 862                 return sizeof(uint32_t);
 863         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 864                 if (ret) {
 865                         uint64_t *max_variable_threads_per_block = ret;
 866                         if (ir_type == PIPE_SHADER_IR_NATIVE)
 867                                 *max_variable_threads_per_block = 0;
 868                         else
 869                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 870                 }
 871                 return sizeof(uint64_t);
 872         }
 873
 874         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 875         return 0;
 876 }
 877
 878 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 879 {
 880         struct si_screen *sscreen = (struct si_screen*)screen;
 881
 882         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 883                         sscreen->info.clock_crystal_freq;
 884 }
 885
 886 static void si_query_memory_info(struct pipe_screen *screen,
 887                                  struct pipe_memory_info *info)
 888 {
 889         struct si_screen *sscreen = (struct si_screen*)screen;
 890         struct radeon_winsys *ws = sscreen->ws;
 891         unsigned vram_usage, gtt_usage;
 892
 893         info->total_device_memory = sscreen->info.vram_size / 1024;
 894         info->total_staging_memory = sscreen->info.gart_size / 1024;
 895
 896         /* The real TTM memory usage is somewhat random, because:
 897          *
 898          * 1) TTM delays freeing memory, because it can only free it after
 899          *    fences expire.
 900          *
 901          * 2) The memory usage can be really low if big VRAM evictions are
 902          *    taking place, but the real usage is well above the size of VRAM.
 903          *
 904          * Instead, return statistics of this process.
 905          */
 906         vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
 907         gtt_usage =  ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
 908
 909         info->avail_device_memory =
 910                 vram_usage <= info->total_device_memory ?
 911                                 info->total_device_memory - vram_usage : 0;
 912         info->avail_staging_memory =
 913                 gtt_usage <= info->total_staging_memory ?
 914                                 info->total_staging_memory - gtt_usage : 0;
 915
 916         info->device_memory_evicted =
 917                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 918
 919         if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
 920                 info->nr_device_memory_evictions =
 921                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 922         else
 923                 /* Just return the number of evicted 64KB pages. */
 924                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 925 }
 926
 927 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 928 {
 929         struct si_screen *sscreen = (struct si_screen*)pscreen;
 930
 931         return sscreen->disk_shader_cache;
 932 }
 933
 934 static void si_init_renderer_string(struct si_screen *sscreen)
 935 {
 936         struct radeon_winsys *ws = sscreen->ws;
 937         char first_name[256], second_name[32] = {}, kernel_version[128] = {};
 938         struct utsname uname_data;
 939
 940         const char *marketing_name = si_get_marketing_name(ws);
 941
 942         if (marketing_name) {
 943                 snprintf(first_name, sizeof(first_name), "%s", marketing_name);
 944                 snprintf(second_name, sizeof(second_name), "%s, ",
 945                          sscreen->info.name);
 946         } else {
 947                 snprintf(first_name, sizeof(first_name), "AMD %s",
 948                          sscreen->info.name);
 949         }
 950
 951         if (uname(&uname_data) == 0)
 952                 snprintf(kernel_version, sizeof(kernel_version),
 953                          ", %s", uname_data.release);
 954
 955         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 956                  "%s (%sDRM %i.%i.%i%s, LLVM %i.%i.%i)",
 957                  first_name, second_name, sscreen->info.drm_major,
 958                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 959                  kernel_version,
 960                  (HAVE_LLVM >> 8) & 0xff,
 961                  HAVE_LLVM & 0xff,
 962                  MESA_LLVM_VERSION_PATCH);
 963 }
 964
 965 void si_init_screen_get_functions(struct si_screen *sscreen)
 966 {
 967         sscreen->b.get_name = si_get_name;
 968         sscreen->b.get_vendor = si_get_vendor;
 969         sscreen->b.get_device_vendor = si_get_device_vendor;
 970         sscreen->b.get_param = si_get_param;
 971         sscreen->b.get_paramf = si_get_paramf;
 972         sscreen->b.get_compute_param = si_get_compute_param;
 973         sscreen->b.get_timestamp = si_get_timestamp;
 974         sscreen->b.get_shader_param = si_get_shader_param;
 975         sscreen->b.get_compiler_options = si_get_compiler_options;
 976         sscreen->b.get_device_uuid = si_get_device_uuid;
 977         sscreen->b.get_driver_uuid = si_get_driver_uuid;
 978         sscreen->b.query_memory_info = si_query_memory_info;
 979         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
 980
 981         if (sscreen->info.has_hw_decode) {
 982                 sscreen->b.get_video_param = si_get_video_param;
 983                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
 984         } else {
 985                 sscreen->b.get_video_param = si_get_video_param_no_decode;
 986                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 987         }
 988
 989         si_init_renderer_string(sscreen);
 990 }