2 * Copyright 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "radeon/radeon_video.h"
27 #include "radeon/radeon_vce.h"
28 #include "radeon/radeon_uvd_enc.h"
29 #include "ac_llvm_util.h"
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32 #include "util/u_video.h"
33 #include "compiler/nir/nir.h"
35 #include <sys/utsname.h>
37 static const char *si_get_vendor(struct pipe_screen
*pscreen
)
39 /* Don't change this. Games such as Alien Isolation are broken if this
40 * returns "Advanced Micro Devices, Inc."
45 static const char *si_get_device_vendor(struct pipe_screen
*pscreen
)
50 static const char *si_get_marketing_name(struct radeon_winsys
*ws
)
52 if (!ws
->get_chip_name
)
54 return ws
->get_chip_name(ws
);
57 const char *si_get_family_name(const struct si_screen
*sscreen
)
59 switch (sscreen
->info
.family
) {
60 case CHIP_TAHITI
: return "AMD TAHITI";
61 case CHIP_PITCAIRN
: return "AMD PITCAIRN";
62 case CHIP_VERDE
: return "AMD CAPE VERDE";
63 case CHIP_OLAND
: return "AMD OLAND";
64 case CHIP_HAINAN
: return "AMD HAINAN";
65 case CHIP_BONAIRE
: return "AMD BONAIRE";
66 case CHIP_KAVERI
: return "AMD KAVERI";
67 case CHIP_KABINI
: return "AMD KABINI";
68 case CHIP_HAWAII
: return "AMD HAWAII";
69 case CHIP_MULLINS
: return "AMD MULLINS";
70 case CHIP_TONGA
: return "AMD TONGA";
71 case CHIP_ICELAND
: return "AMD ICELAND";
72 case CHIP_CARRIZO
: return "AMD CARRIZO";
73 case CHIP_FIJI
: return "AMD FIJI";
74 case CHIP_STONEY
: return "AMD STONEY";
75 case CHIP_POLARIS10
: return "AMD POLARIS10";
76 case CHIP_POLARIS11
: return "AMD POLARIS11";
77 case CHIP_POLARIS12
: return "AMD POLARIS12";
78 case CHIP_VEGAM
: return "AMD VEGAM";
79 case CHIP_VEGA10
: return "AMD VEGA10";
80 case CHIP_VEGA12
: return "AMD VEGA12";
81 case CHIP_RAVEN
: return "AMD RAVEN";
82 default: return "AMD unknown";
86 static int si_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
88 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
91 /* Supported features (boolean caps). */
92 case PIPE_CAP_ACCELERATED
:
93 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
94 case PIPE_CAP_ANISOTROPIC_FILTER
:
95 case PIPE_CAP_POINT_SPRITE
:
96 case PIPE_CAP_OCCLUSION_QUERY
:
97 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
98 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
99 case PIPE_CAP_TEXTURE_SWIZZLE
:
100 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
101 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
102 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
103 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
104 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
105 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
106 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
108 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
109 case PIPE_CAP_PRIMITIVE_RESTART
:
110 case PIPE_CAP_CONDITIONAL_RENDER
:
111 case PIPE_CAP_TEXTURE_BARRIER
:
112 case PIPE_CAP_INDEP_BLEND_ENABLE
:
113 case PIPE_CAP_INDEP_BLEND_FUNC
:
114 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
115 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
116 case PIPE_CAP_START_INSTANCE
:
117 case PIPE_CAP_NPOT_TEXTURES
:
118 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
119 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
120 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
121 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
122 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
123 case PIPE_CAP_TGSI_INSTANCEID
:
124 case PIPE_CAP_COMPUTE
:
125 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
126 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
127 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
128 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
129 case PIPE_CAP_CUBE_MAP_ARRAY
:
130 case PIPE_CAP_SAMPLE_SHADING
:
131 case PIPE_CAP_DRAW_INDIRECT
:
132 case PIPE_CAP_CLIP_HALFZ
:
133 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
134 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
135 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
136 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
137 case PIPE_CAP_TGSI_TEXCOORD
:
138 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
139 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
140 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
141 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
142 case PIPE_CAP_SHAREABLE_SHADERS
:
143 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
144 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
145 case PIPE_CAP_TEXTURE_QUERY_LOD
:
146 case PIPE_CAP_TEXTURE_GATHER_SM5
:
147 case PIPE_CAP_TGSI_TXQS
:
148 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
149 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
150 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
151 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
152 case PIPE_CAP_INVALIDATE_BUFFER
:
153 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
154 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
155 case PIPE_CAP_QUERY_MEMORY_INFO
:
156 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
157 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
158 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
159 case PIPE_CAP_GENERATE_MIPMAP
:
160 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
161 case PIPE_CAP_STRING_MARKER
:
162 case PIPE_CAP_CLEAR_TEXTURE
:
163 case PIPE_CAP_CULL_DISTANCE
:
164 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
165 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
166 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
167 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
168 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
169 case PIPE_CAP_DOUBLES
:
170 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
171 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
172 case PIPE_CAP_BINDLESS_TEXTURE
:
173 case PIPE_CAP_QUERY_TIMESTAMP
:
174 case PIPE_CAP_QUERY_TIME_ELAPSED
:
175 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
176 case PIPE_CAP_QUERY_SO_OVERFLOW
:
177 case PIPE_CAP_MEMOBJ
:
178 case PIPE_CAP_LOAD_CONSTBUF
:
180 case PIPE_CAP_INT64_DIVMOD
:
181 case PIPE_CAP_TGSI_CLOCK
:
182 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
183 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
184 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
:
185 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
186 case PIPE_CAP_TGSI_VOTE
:
187 case PIPE_CAP_TGSI_FS_FBFETCH
:
190 case PIPE_CAP_TGSI_BALLOT
:
191 return HAVE_LLVM
>= 0x0500;
193 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
194 return !SI_BIG_ENDIAN
&& sscreen
->info
.has_userptr
;
196 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
197 return sscreen
->info
.has_gpu_reset_status_query
||
198 sscreen
->info
.has_gpu_reset_counter_query
;
200 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
201 /* 2D tiling on CIK is supported since DRM 2.35.0 */
202 return sscreen
->info
.chip_class
< CIK
||
203 (sscreen
->info
.drm_major
== 2 &&
204 sscreen
->info
.drm_minor
>= 35) ||
205 sscreen
->info
.drm_major
== 3;
207 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
208 return SI_MAP_BUFFER_ALIGNMENT
;
210 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
211 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
212 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
213 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
214 case PIPE_CAP_MAX_VERTEX_STREAMS
:
215 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
218 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
219 if (sscreen
->info
.has_indirect_compute_dispatch
)
223 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
224 return MIN2(sscreen
->info
.max_alloc_size
, INT_MAX
);
226 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
227 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
228 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
229 return !sscreen
->info
.has_unaligned_shader_loads
;
231 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
232 return sscreen
->info
.has_sparse_vm_mappings
?
233 RADEON_SPARSE_PAGE_SIZE
: 0;
235 case PIPE_CAP_PACKED_UNIFORMS
:
236 if (sscreen
->debug_flags
& DBG(NIR
))
240 /* Unsupported features. */
241 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
242 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
243 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
244 case PIPE_CAP_USER_VERTEX_BUFFERS
:
245 case PIPE_CAP_FAKE_SW_MSAA
:
246 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
247 case PIPE_CAP_VERTEXID_NOBASE
:
248 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
249 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
250 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
252 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
253 case PIPE_CAP_POST_DEPTH_COVERAGE
:
254 case PIPE_CAP_TILE_RASTER_ORDER
:
255 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES
:
256 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
257 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES
:
258 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES
:
259 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES
:
260 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES
:
261 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE
:
262 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS
:
265 case PIPE_CAP_FENCE_SIGNAL
:
266 return sscreen
->info
.has_syncobj
;
268 case PIPE_CAP_CONSTBUF0_FLAGS
:
269 return SI_RESOURCE_FLAG_32BIT
;
271 case PIPE_CAP_NATIVE_FENCE_FD
:
272 return sscreen
->info
.has_fence_to_handle
;
274 case PIPE_CAP_DRAW_PARAMETERS
:
275 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
276 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
277 return sscreen
->has_draw_indirect_multi
;
279 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
282 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
283 return sscreen
->info
.chip_class
<= VI
?
284 PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600
: 0;
287 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
288 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
291 /* Geometry shader output. */
292 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
294 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
297 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
301 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
302 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
303 return 15; /* 16384 */
304 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
305 /* textures support 8192, but layered rendering supports 2048 */
307 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
308 /* textures support 8192, but layered rendering supports 2048 */
311 /* Viewports and render targets. */
312 case PIPE_CAP_MAX_VIEWPORTS
:
313 return SI_MAX_VIEWPORTS
;
314 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
315 case PIPE_CAP_MAX_RENDER_TARGETS
:
318 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
319 case PIPE_CAP_MIN_TEXEL_OFFSET
:
322 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
323 case PIPE_CAP_MAX_TEXEL_OFFSET
:
326 case PIPE_CAP_ENDIANNESS
:
327 return PIPE_ENDIAN_LITTLE
;
329 case PIPE_CAP_VENDOR_ID
:
330 return ATI_VENDOR_ID
;
331 case PIPE_CAP_DEVICE_ID
:
332 return sscreen
->info
.pci_id
;
333 case PIPE_CAP_VIDEO_MEMORY
:
334 return sscreen
->info
.vram_size
>> 20;
335 case PIPE_CAP_PCI_GROUP
:
336 return sscreen
->info
.pci_domain
;
337 case PIPE_CAP_PCI_BUS
:
338 return sscreen
->info
.pci_bus
;
339 case PIPE_CAP_PCI_DEVICE
:
340 return sscreen
->info
.pci_dev
;
341 case PIPE_CAP_PCI_FUNCTION
:
342 return sscreen
->info
.pci_func
;
347 static float si_get_paramf(struct pipe_screen
* pscreen
, enum pipe_capf param
)
350 case PIPE_CAPF_MAX_LINE_WIDTH
:
351 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
352 case PIPE_CAPF_MAX_POINT_WIDTH
:
353 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
355 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
357 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
359 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
360 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
361 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
367 static int si_get_shader_param(struct pipe_screen
* pscreen
,
368 enum pipe_shader_type shader
,
369 enum pipe_shader_cap param
)
371 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
375 case PIPE_SHADER_FRAGMENT
:
376 case PIPE_SHADER_VERTEX
:
377 case PIPE_SHADER_GEOMETRY
:
378 case PIPE_SHADER_TESS_CTRL
:
379 case PIPE_SHADER_TESS_EVAL
:
381 case PIPE_SHADER_COMPUTE
:
383 case PIPE_SHADER_CAP_SUPPORTED_IRS
: {
384 int ir
= 1 << PIPE_SHADER_IR_NATIVE
;
386 if (sscreen
->info
.has_indirect_compute_dispatch
)
387 ir
|= 1 << PIPE_SHADER_IR_TGSI
;
392 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
: {
393 uint64_t max_const_buffer_size
;
394 pscreen
->get_compute_param(pscreen
, PIPE_SHADER_IR_TGSI
,
395 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
396 &max_const_buffer_size
);
397 return MIN2(max_const_buffer_size
, INT_MAX
);
400 /* If compute shaders don't require a special value
401 * for this cap, we can return the same value we
402 * do for other shader types. */
412 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
413 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
414 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
415 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
416 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
418 case PIPE_SHADER_CAP_MAX_INPUTS
:
419 return shader
== PIPE_SHADER_VERTEX
? SI_MAX_ATTRIBS
: 32;
420 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
421 return shader
== PIPE_SHADER_FRAGMENT
? 8 : 32;
422 case PIPE_SHADER_CAP_MAX_TEMPS
:
423 return 256; /* Max native temporaries. */
424 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
425 return 4096 * sizeof(float[4]); /* actually only memory limits this */
426 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
427 return SI_NUM_CONST_BUFFERS
;
428 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
429 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
430 return SI_NUM_SAMPLERS
;
431 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
432 return SI_NUM_SHADER_BUFFERS
;
433 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
434 return SI_NUM_IMAGES
;
435 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
436 if (sscreen
->debug_flags
& DBG(NIR
))
439 case PIPE_SHADER_CAP_PREFERRED_IR
:
440 if (sscreen
->debug_flags
& DBG(NIR
))
441 return PIPE_SHADER_IR_NIR
;
442 return PIPE_SHADER_IR_TGSI
;
443 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
446 /* Supported boolean features. */
447 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
448 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
449 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
450 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
451 case PIPE_SHADER_CAP_INTEGERS
:
452 case PIPE_SHADER_CAP_INT64_ATOMICS
:
453 case PIPE_SHADER_CAP_FP16
:
454 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
455 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
456 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
457 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
458 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
459 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
462 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
463 /* TODO: Indirect indexing of GS inputs is unimplemented. */
464 if (shader
== PIPE_SHADER_GEOMETRY
)
467 if (shader
== PIPE_SHADER_VERTEX
&&
468 !sscreen
->llvm_has_working_vgpr_indexing
)
471 /* Doing indirect indexing on GFX9 with LLVM 6.0 hangs.
472 * This means we don't support INTERP instructions with
473 * indirect indexing on inputs.
475 if (shader
== PIPE_SHADER_FRAGMENT
&&
476 !sscreen
->llvm_has_working_vgpr_indexing
&&
480 /* TCS and TES load inputs directly from LDS or offchip
481 * memory, so indirect indexing is always supported.
482 * PS has to support indirect indexing, because we can't
483 * lower that to TEMPs for INTERP instructions.
487 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
488 return sscreen
->llvm_has_working_vgpr_indexing
||
489 /* TCS stores outputs directly to memory. */
490 shader
== PIPE_SHADER_TESS_CTRL
;
492 /* Unsupported boolean features. */
493 case PIPE_SHADER_CAP_SUBROUTINES
:
494 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
495 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
496 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
502 static const struct nir_shader_compiler_options nir_options
= {
504 .lower_flrp32
= true,
505 .lower_flrp64
= true,
511 .lower_pack_snorm_2x16
= true,
512 .lower_pack_snorm_4x8
= true,
513 .lower_pack_unorm_2x16
= true,
514 .lower_pack_unorm_4x8
= true,
515 .lower_unpack_snorm_2x16
= true,
516 .lower_unpack_snorm_4x8
= true,
517 .lower_unpack_unorm_2x16
= true,
518 .lower_unpack_unorm_4x8
= true,
519 .lower_extract_byte
= true,
520 .lower_extract_word
= true,
521 .max_unroll_iterations
= 32,
522 .native_integers
= true,
526 si_get_compiler_options(struct pipe_screen
*screen
,
527 enum pipe_shader_ir ir
,
528 enum pipe_shader_type shader
)
530 assert(ir
== PIPE_SHADER_IR_NIR
);
534 static void si_get_driver_uuid(struct pipe_screen
*pscreen
, char *uuid
)
536 ac_compute_driver_uuid(uuid
, PIPE_UUID_SIZE
);
539 static void si_get_device_uuid(struct pipe_screen
*pscreen
, char *uuid
)
541 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
543 ac_compute_device_uuid(&sscreen
->info
, uuid
, PIPE_UUID_SIZE
);
546 static const char* si_get_name(struct pipe_screen
*pscreen
)
548 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
550 return sscreen
->renderer_string
;
553 static int si_get_video_param_no_decode(struct pipe_screen
*screen
,
554 enum pipe_video_profile profile
,
555 enum pipe_video_entrypoint entrypoint
,
556 enum pipe_video_cap param
)
559 case PIPE_VIDEO_CAP_SUPPORTED
:
560 return vl_profile_supported(screen
, profile
, entrypoint
);
561 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
563 case PIPE_VIDEO_CAP_MAX_WIDTH
:
564 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
565 return vl_video_buffer_max_size(screen
);
566 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
567 return PIPE_FORMAT_NV12
;
568 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
570 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
572 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
574 case PIPE_VIDEO_CAP_MAX_LEVEL
:
575 return vl_level_supported(screen
, profile
);
581 static int si_get_video_param(struct pipe_screen
*screen
,
582 enum pipe_video_profile profile
,
583 enum pipe_video_entrypoint entrypoint
,
584 enum pipe_video_cap param
)
586 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
587 enum pipe_video_format codec
= u_reduce_video_profile(profile
);
589 if (entrypoint
== PIPE_VIDEO_ENTRYPOINT_ENCODE
) {
591 case PIPE_VIDEO_CAP_SUPPORTED
:
592 return (codec
== PIPE_VIDEO_FORMAT_MPEG4_AVC
&&
593 (si_vce_is_fw_version_supported(sscreen
) ||
594 sscreen
->info
.family
== CHIP_RAVEN
)) ||
595 (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
&&
596 (sscreen
->info
.family
== CHIP_RAVEN
||
597 si_radeon_uvd_enc_supported(sscreen
)));
598 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
600 case PIPE_VIDEO_CAP_MAX_WIDTH
:
601 return (sscreen
->info
.family
< CHIP_TONGA
) ? 2048 : 4096;
602 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
603 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1152 : 2304;
604 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
605 return PIPE_FORMAT_NV12
;
606 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
608 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
610 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
612 case PIPE_VIDEO_CAP_STACKED_FRAMES
:
613 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1 : 2;
620 case PIPE_VIDEO_CAP_SUPPORTED
:
622 case PIPE_VIDEO_FORMAT_MPEG12
:
623 return profile
!= PIPE_VIDEO_PROFILE_MPEG1
;
624 case PIPE_VIDEO_FORMAT_MPEG4
:
626 case PIPE_VIDEO_FORMAT_MPEG4_AVC
:
627 if ((sscreen
->info
.family
== CHIP_POLARIS10
||
628 sscreen
->info
.family
== CHIP_POLARIS11
) &&
629 sscreen
->info
.uvd_fw_version
< UVD_FW_1_66_16
) {
630 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
634 case PIPE_VIDEO_FORMAT_VC1
:
636 case PIPE_VIDEO_FORMAT_HEVC
:
637 /* Carrizo only supports HEVC Main */
638 if (sscreen
->info
.family
>= CHIP_STONEY
)
639 return (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
||
640 profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
);
641 else if (sscreen
->info
.family
>= CHIP_CARRIZO
)
642 return profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN
;
644 case PIPE_VIDEO_FORMAT_JPEG
:
645 if (sscreen
->info
.family
< CHIP_CARRIZO
|| sscreen
->info
.family
>= CHIP_VEGA10
)
647 if (!(sscreen
->info
.drm_major
== 3 && sscreen
->info
.drm_minor
>= 19)) {
648 RVID_ERR("No MJPEG support for the kernel version\n");
652 case PIPE_VIDEO_FORMAT_VP9
:
653 if (sscreen
->info
.family
< CHIP_RAVEN
)
659 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
661 case PIPE_VIDEO_CAP_MAX_WIDTH
:
662 return (sscreen
->info
.family
< CHIP_TONGA
) ? 2048 : 4096;
663 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
664 return (sscreen
->info
.family
< CHIP_TONGA
) ? 1152 : 4096;
665 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
666 if (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
||
667 profile
== PIPE_VIDEO_PROFILE_VP9_PROFILE2
)
668 return PIPE_FORMAT_P016
;
670 return PIPE_FORMAT_NV12
;
672 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
673 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
: {
674 enum pipe_video_format format
= u_reduce_video_profile(profile
);
676 if (format
== PIPE_VIDEO_FORMAT_HEVC
)
677 return false; //The firmware doesn't support interlaced HEVC.
678 else if (format
== PIPE_VIDEO_FORMAT_JPEG
)
680 else if (format
== PIPE_VIDEO_FORMAT_VP9
)
684 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
686 case PIPE_VIDEO_CAP_MAX_LEVEL
:
688 case PIPE_VIDEO_PROFILE_MPEG1
:
690 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE
:
691 case PIPE_VIDEO_PROFILE_MPEG2_MAIN
:
693 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE
:
695 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE
:
697 case PIPE_VIDEO_PROFILE_VC1_SIMPLE
:
699 case PIPE_VIDEO_PROFILE_VC1_MAIN
:
701 case PIPE_VIDEO_PROFILE_VC1_ADVANCED
:
703 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE
:
704 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN
:
705 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH
:
706 return (sscreen
->info
.family
< CHIP_TONGA
) ? 41 : 52;
707 case PIPE_VIDEO_PROFILE_HEVC_MAIN
:
708 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10
:
718 static boolean
si_vid_is_format_supported(struct pipe_screen
*screen
,
719 enum pipe_format format
,
720 enum pipe_video_profile profile
,
721 enum pipe_video_entrypoint entrypoint
)
723 /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
724 if (profile
== PIPE_VIDEO_PROFILE_HEVC_MAIN_10
)
725 return (format
== PIPE_FORMAT_NV12
) ||
726 (format
== PIPE_FORMAT_P016
);
728 /* we can only handle this one with UVD */
729 if (profile
!= PIPE_VIDEO_PROFILE_UNKNOWN
)
730 return format
== PIPE_FORMAT_NV12
;
732 return vl_video_buffer_is_format_supported(screen
, format
, profile
, entrypoint
);
735 static unsigned get_max_threads_per_block(struct si_screen
*screen
,
736 enum pipe_shader_ir ir_type
)
738 if (ir_type
== PIPE_SHADER_IR_NATIVE
)
741 /* Only 16 waves per thread-group on gfx9. */
742 if (screen
->info
.chip_class
>= GFX9
)
745 /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
751 static int si_get_compute_param(struct pipe_screen
*screen
,
752 enum pipe_shader_ir ir_type
,
753 enum pipe_compute_cap param
,
756 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
758 //TODO: select these params by asic
760 case PIPE_COMPUTE_CAP_IR_TARGET
: {
761 const char *gpu
, *triple
;
763 triple
= "amdgcn-mesa-mesa3d";
764 gpu
= ac_get_llvm_processor_name(sscreen
->info
.family
);
766 sprintf(ret
, "%s-%s", gpu
, triple
);
768 /* +2 for dash and terminating NIL byte */
769 return (strlen(triple
) + strlen(gpu
) + 2) * sizeof(char);
771 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
773 uint64_t *grid_dimension
= ret
;
774 grid_dimension
[0] = 3;
776 return 1 * sizeof(uint64_t);
778 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
780 uint64_t *grid_size
= ret
;
781 grid_size
[0] = 65535;
782 grid_size
[1] = 65535;
783 grid_size
[2] = 65535;
785 return 3 * sizeof(uint64_t) ;
787 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
789 uint64_t *block_size
= ret
;
790 unsigned threads_per_block
= get_max_threads_per_block(sscreen
, ir_type
);
791 block_size
[0] = threads_per_block
;
792 block_size
[1] = threads_per_block
;
793 block_size
[2] = threads_per_block
;
795 return 3 * sizeof(uint64_t);
797 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
799 uint64_t *max_threads_per_block
= ret
;
800 *max_threads_per_block
= get_max_threads_per_block(sscreen
, ir_type
);
802 return sizeof(uint64_t);
803 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
805 uint32_t *address_bits
= ret
;
806 address_bits
[0] = 64;
808 return 1 * sizeof(uint32_t);
810 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
812 uint64_t *max_global_size
= ret
;
813 uint64_t max_mem_alloc_size
;
815 si_get_compute_param(screen
, ir_type
,
816 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
817 &max_mem_alloc_size
);
819 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
820 * 1/4 of the MAX_GLOBAL_SIZE. Since the
821 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
822 * make sure we never report more than
823 * 4 * MAX_MEM_ALLOC_SIZE.
825 *max_global_size
= MIN2(4 * max_mem_alloc_size
,
826 MAX2(sscreen
->info
.gart_size
,
827 sscreen
->info
.vram_size
));
829 return sizeof(uint64_t);
831 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
833 uint64_t *max_local_size
= ret
;
834 /* Value reported by the closed source driver. */
835 *max_local_size
= 32768;
837 return sizeof(uint64_t);
839 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
841 uint64_t *max_input_size
= ret
;
842 /* Value reported by the closed source driver. */
843 *max_input_size
= 1024;
845 return sizeof(uint64_t);
847 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
849 uint64_t *max_mem_alloc_size
= ret
;
851 *max_mem_alloc_size
= sscreen
->info
.max_alloc_size
;
853 return sizeof(uint64_t);
855 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
857 uint32_t *max_clock_frequency
= ret
;
858 *max_clock_frequency
= sscreen
->info
.max_shader_clock
;
860 return sizeof(uint32_t);
862 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
864 uint32_t *max_compute_units
= ret
;
865 *max_compute_units
= sscreen
->info
.num_good_compute_units
;
867 return sizeof(uint32_t);
869 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
871 uint32_t *images_supported
= ret
;
872 *images_supported
= 0;
874 return sizeof(uint32_t);
875 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
877 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
879 uint32_t *subgroup_size
= ret
;
882 return sizeof(uint32_t);
883 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
885 uint64_t *max_variable_threads_per_block
= ret
;
886 if (ir_type
== PIPE_SHADER_IR_NATIVE
)
887 *max_variable_threads_per_block
= 0;
889 *max_variable_threads_per_block
= SI_MAX_VARIABLE_THREADS_PER_BLOCK
;
891 return sizeof(uint64_t);
894 fprintf(stderr
, "unknown PIPE_COMPUTE_CAP %d\n", param
);
898 static uint64_t si_get_timestamp(struct pipe_screen
*screen
)
900 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
902 return 1000000 * sscreen
->ws
->query_value(sscreen
->ws
, RADEON_TIMESTAMP
) /
903 sscreen
->info
.clock_crystal_freq
;
906 static void si_query_memory_info(struct pipe_screen
*screen
,
907 struct pipe_memory_info
*info
)
909 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
910 struct radeon_winsys
*ws
= sscreen
->ws
;
911 unsigned vram_usage
, gtt_usage
;
913 info
->total_device_memory
= sscreen
->info
.vram_size
/ 1024;
914 info
->total_staging_memory
= sscreen
->info
.gart_size
/ 1024;
916 /* The real TTM memory usage is somewhat random, because:
918 * 1) TTM delays freeing memory, because it can only free it after
921 * 2) The memory usage can be really low if big VRAM evictions are
922 * taking place, but the real usage is well above the size of VRAM.
924 * Instead, return statistics of this process.
926 vram_usage
= ws
->query_value(ws
, RADEON_REQUESTED_VRAM_MEMORY
) / 1024;
927 gtt_usage
= ws
->query_value(ws
, RADEON_REQUESTED_GTT_MEMORY
) / 1024;
929 info
->avail_device_memory
=
930 vram_usage
<= info
->total_device_memory
?
931 info
->total_device_memory
- vram_usage
: 0;
932 info
->avail_staging_memory
=
933 gtt_usage
<= info
->total_staging_memory
?
934 info
->total_staging_memory
- gtt_usage
: 0;
936 info
->device_memory_evicted
=
937 ws
->query_value(ws
, RADEON_NUM_BYTES_MOVED
) / 1024;
939 if (sscreen
->info
.drm_major
== 3 && sscreen
->info
.drm_minor
>= 4)
940 info
->nr_device_memory_evictions
=
941 ws
->query_value(ws
, RADEON_NUM_EVICTIONS
);
943 /* Just return the number of evicted 64KB pages. */
944 info
->nr_device_memory_evictions
= info
->device_memory_evicted
/ 64;
947 static struct disk_cache
*si_get_disk_shader_cache(struct pipe_screen
*pscreen
)
949 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
951 return sscreen
->disk_shader_cache
;
954 static void si_init_renderer_string(struct si_screen
*sscreen
)
956 struct radeon_winsys
*ws
= sscreen
->ws
;
957 char family_name
[32] = {}, kernel_version
[128] = {};
958 struct utsname uname_data
;
960 const char *chip_name
= si_get_marketing_name(ws
);
963 snprintf(family_name
, sizeof(family_name
), "%s, ",
964 si_get_family_name(sscreen
) + 4);
966 chip_name
= si_get_family_name(sscreen
);
968 if (uname(&uname_data
) == 0)
969 snprintf(kernel_version
, sizeof(kernel_version
),
970 ", %s", uname_data
.release
);
972 snprintf(sscreen
->renderer_string
, sizeof(sscreen
->renderer_string
),
973 "%s (%sDRM %i.%i.%i%s, LLVM %i.%i.%i)",
974 chip_name
, family_name
, sscreen
->info
.drm_major
,
975 sscreen
->info
.drm_minor
, sscreen
->info
.drm_patchlevel
,
977 (HAVE_LLVM
>> 8) & 0xff,
979 MESA_LLVM_VERSION_PATCH
);
982 void si_init_screen_get_functions(struct si_screen
*sscreen
)
984 sscreen
->b
.get_name
= si_get_name
;
985 sscreen
->b
.get_vendor
= si_get_vendor
;
986 sscreen
->b
.get_device_vendor
= si_get_device_vendor
;
987 sscreen
->b
.get_param
= si_get_param
;
988 sscreen
->b
.get_paramf
= si_get_paramf
;
989 sscreen
->b
.get_compute_param
= si_get_compute_param
;
990 sscreen
->b
.get_timestamp
= si_get_timestamp
;
991 sscreen
->b
.get_shader_param
= si_get_shader_param
;
992 sscreen
->b
.get_compiler_options
= si_get_compiler_options
;
993 sscreen
->b
.get_device_uuid
= si_get_device_uuid
;
994 sscreen
->b
.get_driver_uuid
= si_get_driver_uuid
;
995 sscreen
->b
.query_memory_info
= si_query_memory_info
;
996 sscreen
->b
.get_disk_shader_cache
= si_get_disk_shader_cache
;
998 if (sscreen
->info
.has_hw_decode
) {
999 sscreen
->b
.get_video_param
= si_get_video_param
;
1000 sscreen
->b
.is_video_format_supported
= si_vid_is_format_supported
;
1002 sscreen
->b
.get_video_param
= si_get_video_param_no_decode
;
1003 sscreen
->b
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
1006 si_init_renderer_string(sscreen
);