src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "radeon/radeon_video.h"
  27 #include "radeon/radeon_vce.h"
  28 #include "radeon/radeon_uvd_enc.h"
  29 #include "vl/vl_decoder.h"
  30 #include "vl/vl_video_buffer.h"
  31 #include "util/u_screen.h"
  32 #include "util/u_video.h"
  33 #include "compiler/nir/nir.h"
  34
  35 #include <sys/utsname.h>
  36
  37 static const char *si_get_vendor(struct pipe_screen *pscreen)
  38 {
  39         /* Don't change this. Games such as Alien Isolation are broken if this
  40          * returns "Advanced Micro Devices, Inc."
  41          */
  42         return "X.Org";
  43 }
  44
  45 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  46 {
  47         return "AMD";
  48 }
  49
  50 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  51 {
  52         struct si_screen *sscreen = (struct si_screen *)pscreen;
  53
  54         switch (param) {
  55         /* Supported features (boolean caps). */
  56         case PIPE_CAP_ACCELERATED:
  57         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  58         case PIPE_CAP_ANISOTROPIC_FILTER:
  59         case PIPE_CAP_POINT_SPRITE:
  60         case PIPE_CAP_OCCLUSION_QUERY:
  61         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  62         case PIPE_CAP_TEXTURE_SHADOW_LOD:
  63         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  64         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  65         case PIPE_CAP_TEXTURE_SWIZZLE:
  66         case PIPE_CAP_DEPTH_CLIP_DISABLE:
  67         case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
  68         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  69         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  70         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  71         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  72         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  73         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  74         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
  75         case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
  76         case PIPE_CAP_VERTEX_SHADER_SATURATE:
  77         case PIPE_CAP_SEAMLESS_CUBE_MAP:
  78         case PIPE_CAP_PRIMITIVE_RESTART:
  79         case PIPE_CAP_CONDITIONAL_RENDER:
  80         case PIPE_CAP_TEXTURE_BARRIER:
  81         case PIPE_CAP_INDEP_BLEND_ENABLE:
  82         case PIPE_CAP_INDEP_BLEND_FUNC:
  83         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  84         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  85         case PIPE_CAP_START_INSTANCE:
  86         case PIPE_CAP_NPOT_TEXTURES:
  87         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  88         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  89         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
  90         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
  91         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  92         case PIPE_CAP_TGSI_INSTANCEID:
  93         case PIPE_CAP_COMPUTE:
  94         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  95         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
  96         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
  97         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  98         case PIPE_CAP_CUBE_MAP_ARRAY:
  99         case PIPE_CAP_SAMPLE_SHADING:
 100         case PIPE_CAP_DRAW_INDIRECT:
 101         case PIPE_CAP_CLIP_HALFZ:
 102         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 103         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 104         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 105         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 106         case PIPE_CAP_TGSI_TEXCOORD:
 107         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 108         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 109         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 110         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 111         case PIPE_CAP_SHAREABLE_SHADERS:
 112         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 113         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 114         case PIPE_CAP_TEXTURE_QUERY_LOD:
 115         case PIPE_CAP_TEXTURE_GATHER_SM5:
 116         case PIPE_CAP_TGSI_TXQS:
 117         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 118         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 119         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 120         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 121         case PIPE_CAP_INVALIDATE_BUFFER:
 122         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 123         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 124         case PIPE_CAP_QUERY_MEMORY_INFO:
 125         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 126         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 127         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 128         case PIPE_CAP_GENERATE_MIPMAP:
 129         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 130         case PIPE_CAP_STRING_MARKER:
 131         case PIPE_CAP_CLEAR_TEXTURE:
 132         case PIPE_CAP_CULL_DISTANCE:
 133         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 134         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 135         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 136         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 137         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 138         case PIPE_CAP_DOUBLES:
 139         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 140         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 141         case PIPE_CAP_BINDLESS_TEXTURE:
 142         case PIPE_CAP_QUERY_TIMESTAMP:
 143         case PIPE_CAP_QUERY_TIME_ELAPSED:
 144         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 145         case PIPE_CAP_MEMOBJ:
 146         case PIPE_CAP_LOAD_CONSTBUF:
 147         case PIPE_CAP_INT64:
 148         case PIPE_CAP_INT64_DIVMOD:
 149         case PIPE_CAP_TGSI_CLOCK:
 150         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 151         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 152         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 153         case PIPE_CAP_TGSI_BALLOT:
 154         case PIPE_CAP_TGSI_VOTE:
 155         case PIPE_CAP_FBFETCH:
 156         case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
 157         case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 158         case PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA:
 159         case PIPE_CAP_TGSI_DIV:
 160         case PIPE_CAP_PACKED_UNIFORMS:
 161         case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
 162         case PIPE_CAP_GL_SPIRV:
 163         case PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES:
 164                 return 1;
 165
 166         case PIPE_CAP_QUERY_SO_OVERFLOW:
 167                 return !sscreen->use_ngg_streamout;
 168
 169         case PIPE_CAP_POST_DEPTH_COVERAGE:
 170                 return sscreen->info.chip_class >= GFX10;
 171
 172         case PIPE_CAP_GRAPHICS:
 173                 return sscreen->info.has_graphics;
 174
 175         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 176                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 177
 178         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 179                 return sscreen->info.has_gpu_reset_status_query;
 180
 181         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 182                 return sscreen->info.has_2d_tiling;
 183
 184         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 185                 return SI_MAP_BUFFER_ALIGNMENT;
 186
 187         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 188         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 189         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 190         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 191         case PIPE_CAP_MAX_VERTEX_STREAMS:
 192         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 193         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 194                 return 4;
 195
 196         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 197         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 198                 if (!sscreen->info.has_indirect_compute_dispatch)
 199                         return 420;
 200                 return 460;
 201
 202         case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 203                 /* Optimal number for good TexSubImage performance on Polaris10. */
 204                 return 64 * 1024 * 1024;
 205
 206         case PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE:
 207                 return 4096 * 1024;
 208
 209         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 210         case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 211                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 212
 213         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 214         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 215         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 216                 return LLVM_VERSION_MAJOR < 9 && !sscreen->info.has_unaligned_shader_loads;
 217
 218         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 219                 return sscreen->info.has_sparse_vm_mappings ?
 220                                 RADEON_SPARSE_PAGE_SIZE : 0;
 221
 222
 223         case PIPE_CAP_UMA:
 224                 return 0;
 225
 226         case PIPE_CAP_FENCE_SIGNAL:
 227                 return sscreen->info.has_syncobj;
 228
 229         case PIPE_CAP_CONSTBUF0_FLAGS:
 230                 return SI_RESOURCE_FLAG_32BIT;
 231
 232         case PIPE_CAP_NATIVE_FENCE_FD:
 233                 return sscreen->info.has_fence_to_handle;
 234
 235         case PIPE_CAP_DRAW_PARAMETERS:
 236         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 237         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 238                 return sscreen->has_draw_indirect_multi;
 239
 240         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 241                 return 30;
 242
 243         case PIPE_CAP_MAX_VARYINGS:
 244                 return 32;
 245
 246         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 247                 return sscreen->info.chip_class <= GFX8 ?
 248                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 249
 250         /* Stream output. */
 251         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 252         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 253                 return 32*4;
 254
 255         /* Geometry shader output. */
 256         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 257                 /* gfx9 has to report 256 to make piglit/gs-max-output pass.
 258                  * gfx8 and earlier can do 1024.
 259                  */
 260                 return 256;
 261         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 262                 return 4095;
 263         case PIPE_CAP_MAX_GS_INVOCATIONS:
 264                 /* The closed driver exposes 127, but 125 is the greatest
 265                  * number that works. */
 266                 return 125;
 267
 268         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 269                 return 2048;
 270
 271         /* Texturing. */
 272         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 273                 return 16384;
 274         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 275                 return 15; /* 16384 */
 276         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 277                 if (sscreen->info.chip_class >= GFX10)
 278                         return 14;
 279                 /* textures support 8192, but layered rendering supports 2048 */
 280                 return 12;
 281         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 282                 if (sscreen->info.chip_class >= GFX10)
 283                         return 8192;
 284                 /* textures support 8192, but layered rendering supports 2048 */
 285                 return 2048;
 286
 287         /* Viewports and render targets. */
 288         case PIPE_CAP_MAX_VIEWPORTS:
 289                 return SI_MAX_VIEWPORTS;
 290         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 291         case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 292         case PIPE_CAP_MAX_RENDER_TARGETS:
 293                 return 8;
 294         case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 295                 return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
 296
 297         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 298         case PIPE_CAP_MIN_TEXEL_OFFSET:
 299                 return -32;
 300
 301         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 302         case PIPE_CAP_MAX_TEXEL_OFFSET:
 303                 return 31;
 304
 305         case PIPE_CAP_ENDIANNESS:
 306                 return PIPE_ENDIAN_LITTLE;
 307
 308         case PIPE_CAP_VENDOR_ID:
 309                 return ATI_VENDOR_ID;
 310         case PIPE_CAP_DEVICE_ID:
 311                 return sscreen->info.pci_id;
 312         case PIPE_CAP_VIDEO_MEMORY:
 313                 return sscreen->info.vram_size >> 20;
 314         case PIPE_CAP_PCI_GROUP:
 315                 return sscreen->info.pci_domain;
 316         case PIPE_CAP_PCI_BUS:
 317                 return sscreen->info.pci_bus;
 318         case PIPE_CAP_PCI_DEVICE:
 319                 return sscreen->info.pci_dev;
 320         case PIPE_CAP_PCI_FUNCTION:
 321                 return sscreen->info.pci_func;
 322         case PIPE_CAP_TGSI_ATOMINC_WRAP:
 323                 return LLVM_VERSION_MAJOR >= 10;
 324
 325         default:
 326                 return u_pipe_screen_get_param_defaults(pscreen, param);
 327         }
 328 }
 329
 330 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 331 {
 332         switch (param) {
 333         case PIPE_CAPF_MAX_LINE_WIDTH:
 334         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 335                 /* This depends on the quant mode, though the precise interactions
 336                  * are unknown. */
 337                 return 2048;
 338         case PIPE_CAPF_MAX_POINT_WIDTH:
 339         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 340                 return SI_MAX_POINT_SIZE;
 341         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 342                 return 16.0f;
 343         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 344                 return 16.0f;
 345         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 346         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 347         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 348                 return 0.0f;
 349         }
 350         return 0.0f;
 351 }
 352
 353 static int si_get_shader_param(struct pipe_screen* pscreen,
 354                                enum pipe_shader_type shader,
 355                                enum pipe_shader_cap param)
 356 {
 357         struct si_screen *sscreen = (struct si_screen *)pscreen;
 358
 359         switch(shader)
 360         {
 361         case PIPE_SHADER_FRAGMENT:
 362         case PIPE_SHADER_VERTEX:
 363         case PIPE_SHADER_GEOMETRY:
 364         case PIPE_SHADER_TESS_CTRL:
 365         case PIPE_SHADER_TESS_EVAL:
 366                 break;
 367         case PIPE_SHADER_COMPUTE:
 368                 switch (param) {
 369                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 370                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 371
 372                         if (sscreen->info.has_indirect_compute_dispatch)
 373                                 ir |= 1 << PIPE_SHADER_IR_NIR;
 374
 375                         return ir;
 376                 }
 377
 378                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 379                         uint64_t max_const_buffer_size;
 380                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_NIR,
 381                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 382                                 &max_const_buffer_size);
 383                         return MIN2(max_const_buffer_size, INT_MAX);
 384                 }
 385                 default:
 386                         /* If compute shaders don't require a special value
 387                          * for this cap, we can return the same value we
 388                          * do for other shader types. */
 389                         break;
 390                 }
 391                 break;
 392         default:
 393                 return 0;
 394         }
 395
 396         switch (param) {
 397         /* Shader limits. */
 398         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 399         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 400         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 401         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 402         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 403                 return 16384;
 404         case PIPE_SHADER_CAP_MAX_INPUTS:
 405                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 406         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 407                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 408         case PIPE_SHADER_CAP_MAX_TEMPS:
 409                 return 256; /* Max native temporaries. */
 410         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 411                 return MIN2(sscreen->info.max_alloc_size, INT_MAX - 3); /* aligned to 4 */
 412         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 413                 return SI_NUM_CONST_BUFFERS;
 414         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 415         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 416                 return SI_NUM_SAMPLERS;
 417         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 418                 return SI_NUM_SHADER_BUFFERS;
 419         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 420                 return SI_NUM_IMAGES;
 421         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 422                 return 0;
 423         case PIPE_SHADER_CAP_PREFERRED_IR:
 424                 return PIPE_SHADER_IR_NIR;
 425         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 426                 return 4;
 427
 428         /* Supported boolean features. */
 429         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 430         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 431         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 432         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 433         case PIPE_SHADER_CAP_INTEGERS:
 434         case PIPE_SHADER_CAP_INT64_ATOMICS:
 435         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 436         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 437         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 438         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 439         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 440         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 441                 return 1;
 442
 443         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 444                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 445                 if (shader == PIPE_SHADER_GEOMETRY)
 446                         return 0;
 447
 448                 if (shader == PIPE_SHADER_VERTEX &&
 449                     !sscreen->llvm_has_working_vgpr_indexing)
 450                         return 0;
 451
 452                 /* TCS and TES load inputs directly from LDS or offchip
 453                  * memory, so indirect indexing is always supported.
 454                  * PS has to support indirect indexing, because we can't
 455                  * lower that to TEMPs for INTERP instructions.
 456                  */
 457                 return 1;
 458
 459         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 460                 return sscreen->llvm_has_working_vgpr_indexing ||
 461                        /* TCS stores outputs directly to memory. */
 462                        shader == PIPE_SHADER_TESS_CTRL;
 463
 464         /* Unsupported boolean features. */
 465         case PIPE_SHADER_CAP_FP16:
 466         case PIPE_SHADER_CAP_SUBROUTINES:
 467         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 468         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 469         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 470                 return 0;
 471         }
 472         return 0;
 473 }
 474
 475 static const struct nir_shader_compiler_options nir_options = {
 476         .lower_scmp = true,
 477         .lower_flrp32 = true,
 478         .lower_flrp64 = true,
 479         .lower_fsat = true,
 480         .lower_fdiv = true,
 481         .lower_bitfield_insert_to_bitfield_select = true,
 482         .lower_bitfield_extract = true,
 483         .lower_sub = true,
 484         .fuse_ffma = true,
 485         .lower_fmod = true,
 486         .lower_pack_snorm_4x8 = true,
 487         .lower_pack_unorm_4x8 = true,
 488         .lower_unpack_snorm_2x16 = true,
 489         .lower_unpack_snorm_4x8 = true,
 490         .lower_unpack_unorm_2x16 = true,
 491         .lower_unpack_unorm_4x8 = true,
 492         .lower_extract_byte = true,
 493         .lower_extract_word = true,
 494         .lower_rotate = true,
 495         .lower_to_scalar = true,
 496         .optimize_sample_mask_in = true,
 497         .max_unroll_iterations = 32,
 498         .use_interpolated_input_intrinsics = true,
 499 };
 500
 501 static const void *
 502 si_get_compiler_options(struct pipe_screen *screen,
 503                         enum pipe_shader_ir ir,
 504                         enum pipe_shader_type shader)
 505 {
 506         assert(ir == PIPE_SHADER_IR_NIR);
 507         return &nir_options;
 508 }
 509
 510 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 511 {
 512         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 513 }
 514
 515 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 516 {
 517         struct si_screen *sscreen = (struct si_screen *)pscreen;
 518
 519         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 520 }
 521
 522 static const char* si_get_name(struct pipe_screen *pscreen)
 523 {
 524         struct si_screen *sscreen = (struct si_screen*)pscreen;
 525
 526         return sscreen->renderer_string;
 527 }
 528
 529 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 530                                         enum pipe_video_profile profile,
 531                                         enum pipe_video_entrypoint entrypoint,
 532                                         enum pipe_video_cap param)
 533 {
 534         switch (param) {
 535         case PIPE_VIDEO_CAP_SUPPORTED:
 536                 return vl_profile_supported(screen, profile, entrypoint);
 537         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 538                 return 1;
 539         case PIPE_VIDEO_CAP_MAX_WIDTH:
 540         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 541                 return vl_video_buffer_max_size(screen);
 542         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 543                 return PIPE_FORMAT_NV12;
 544         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 545                 return false;
 546         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 547                 return false;
 548         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 549                 return true;
 550         case PIPE_VIDEO_CAP_MAX_LEVEL:
 551                 return vl_level_supported(screen, profile);
 552         default:
 553                 return 0;
 554         }
 555 }
 556
 557 static int si_get_video_param(struct pipe_screen *screen,
 558                               enum pipe_video_profile profile,
 559                               enum pipe_video_entrypoint entrypoint,
 560                               enum pipe_video_cap param)
 561 {
 562         struct si_screen *sscreen = (struct si_screen *)screen;
 563         enum pipe_video_format codec = u_reduce_video_profile(profile);
 564
 565         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 566                 switch (param) {
 567                 case PIPE_VIDEO_CAP_SUPPORTED:
 568                         return ((codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 569                                 (sscreen->info.family >= CHIP_RAVEN ||
 570                                  si_vce_is_fw_version_supported(sscreen))) ||
 571                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 572                                 (sscreen->info.family >= CHIP_RAVEN ||
 573                                  si_radeon_uvd_enc_supported(sscreen))) ||
 574                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 &&
 575                                  sscreen->info.family >= CHIP_RENOIR));
 576                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 577                         return 1;
 578                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 579                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 580                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 581                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 582                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 583                         return PIPE_FORMAT_NV12;
 584                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 585                         return false;
 586                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 587                         return false;
 588                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 589                         return true;
 590                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 591                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 592                 default:
 593                         return 0;
 594                 }
 595         }
 596
 597         switch (param) {
 598         case PIPE_VIDEO_CAP_SUPPORTED:
 599                 switch (codec) {
 600                 case PIPE_VIDEO_FORMAT_MPEG12:
 601                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 602                 case PIPE_VIDEO_FORMAT_MPEG4:
 603                         return 1;
 604                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 605                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 606                              sscreen->info.family == CHIP_POLARIS11) &&
 607                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 608                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 609                                 return false;
 610                         }
 611                         return true;
 612                 case PIPE_VIDEO_FORMAT_VC1:
 613                         return true;
 614                 case PIPE_VIDEO_FORMAT_HEVC:
 615                         /* Carrizo only supports HEVC Main */
 616                         if (sscreen->info.family >= CHIP_STONEY)
 617                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 618                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 619                         else if (sscreen->info.family >= CHIP_CARRIZO)
 620                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 621                         return false;
 622                 case PIPE_VIDEO_FORMAT_JPEG:
 623                         if (sscreen->info.family >= CHIP_RAVEN)
 624                                 return true;
 625                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 626                                 return false;
 627                         if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 19)) {
 628                                 RVID_ERR("No MJPEG support for the kernel version\n");
 629                                 return false;
 630                         }
 631                         return true;
 632                 case PIPE_VIDEO_FORMAT_VP9:
 633                         if (sscreen->info.family < CHIP_RAVEN)
 634                                 return false;
 635                         return true;
 636                 default:
 637                         return false;
 638                 }
 639         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 640                 return 1;
 641         case PIPE_VIDEO_CAP_MAX_WIDTH:
 642                 switch (codec) {
 643                 case PIPE_VIDEO_FORMAT_HEVC:
 644                 case PIPE_VIDEO_FORMAT_VP9:
 645                         return (sscreen->info.family < CHIP_RENOIR) ?
 646                                ((sscreen->info.family < CHIP_TONGA) ? 2048 : 4096) :
 647                                8192;
 648                 default:
 649                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 650                 }
 651         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 652                 switch (codec) {
 653                 case PIPE_VIDEO_FORMAT_HEVC:
 654                 case PIPE_VIDEO_FORMAT_VP9:
 655                         return (sscreen->info.family < CHIP_RENOIR) ?
 656                                ((sscreen->info.family < CHIP_TONGA) ? 1152 : 4096) :
 657                                4352;
 658                 default:
 659                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 660                 }
 661         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 662                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 663                         return PIPE_FORMAT_P010;
 664                 else if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 665                         return PIPE_FORMAT_P016;
 666                 else
 667                         return PIPE_FORMAT_NV12;
 668
 669         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 670         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 671                 enum pipe_video_format format = u_reduce_video_profile(profile);
 672
 673                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 674                         return false; //The firmware doesn't support interlaced HEVC.
 675                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 676                         return false;
 677                 else if (format == PIPE_VIDEO_FORMAT_VP9)
 678                         return false;
 679                 return true;
 680         }
 681         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 682                 return true;
 683         case PIPE_VIDEO_CAP_MAX_LEVEL:
 684                 switch (profile) {
 685                 case PIPE_VIDEO_PROFILE_MPEG1:
 686                         return 0;
 687                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 688                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 689                         return 3;
 690                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 691                         return 3;
 692                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 693                         return 5;
 694                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 695                         return 1;
 696                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 697                         return 2;
 698                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 699                         return 4;
 700                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 701                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 702                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 703                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 704                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 705                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 706                         return 186;
 707                 default:
 708                         return 0;
 709                 }
 710         default:
 711                 return 0;
 712         }
 713 }
 714
 715 static bool si_vid_is_format_supported(struct pipe_screen *screen,
 716                                        enum pipe_format format,
 717                                        enum pipe_video_profile profile,
 718                                        enum pipe_video_entrypoint entrypoint)
 719 {
 720         /* HEVC 10 bit decoding should use P010 instead of NV12 if possible */
 721         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 722                 return (format == PIPE_FORMAT_NV12) ||
 723                        (format == PIPE_FORMAT_P010) ||
 724                        (format == PIPE_FORMAT_P016);
 725
 726         /* Vp9 profile 2 supports 10 bit decoding using P016 */
 727         if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 728                 return format == PIPE_FORMAT_P016;
 729
 730
 731         /* we can only handle this one with UVD */
 732         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 733                 return format == PIPE_FORMAT_NV12;
 734
 735         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 736 }
 737
 738 static unsigned get_max_threads_per_block(struct si_screen *screen,
 739                                           enum pipe_shader_ir ir_type)
 740 {
 741         if (ir_type == PIPE_SHADER_IR_NATIVE)
 742                 return 256;
 743
 744         /* LLVM 10 only supports 1024 threads per block. */
 745         return 1024;
 746 }
 747
 748 static int si_get_compute_param(struct pipe_screen *screen,
 749                                 enum pipe_shader_ir ir_type,
 750                                 enum pipe_compute_cap param,
 751                                 void *ret)
 752 {
 753         struct si_screen *sscreen = (struct si_screen *)screen;
 754
 755         //TODO: select these params by asic
 756         switch (param) {
 757         case PIPE_COMPUTE_CAP_IR_TARGET: {
 758                 const char *gpu, *triple;
 759
 760                 triple = "amdgcn-mesa-mesa3d";
 761                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 762                 if (ret) {
 763                         sprintf(ret, "%s-%s", gpu, triple);
 764                 }
 765                 /* +2 for dash and terminating NIL byte */
 766                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 767         }
 768         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 769                 if (ret) {
 770                         uint64_t *grid_dimension = ret;
 771                         grid_dimension[0] = 3;
 772                 }
 773                 return 1 * sizeof(uint64_t);
 774
 775         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 776                 if (ret) {
 777                         uint64_t *grid_size = ret;
 778                         grid_size[0] = 65535;
 779                         grid_size[1] = 65535;
 780                         grid_size[2] = 65535;
 781                 }
 782                 return 3 * sizeof(uint64_t) ;
 783
 784         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 785                 if (ret) {
 786                         uint64_t *block_size = ret;
 787                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 788                         block_size[0] = threads_per_block;
 789                         block_size[1] = threads_per_block;
 790                         block_size[2] = threads_per_block;
 791                 }
 792                 return 3 * sizeof(uint64_t);
 793
 794         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 795                 if (ret) {
 796                         uint64_t *max_threads_per_block = ret;
 797                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 798                 }
 799                 return sizeof(uint64_t);
 800         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 801                 if (ret) {
 802                         uint32_t *address_bits = ret;
 803                         address_bits[0] = 64;
 804                 }
 805                 return 1 * sizeof(uint32_t);
 806
 807         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 808                 if (ret) {
 809                         uint64_t *max_global_size = ret;
 810                         uint64_t max_mem_alloc_size;
 811
 812                         si_get_compute_param(screen, ir_type,
 813                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 814                                 &max_mem_alloc_size);
 815
 816                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 817                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 818                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 819                          * make sure we never report more than
 820                          * 4 * MAX_MEM_ALLOC_SIZE.
 821                          */
 822                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 823                                                 MAX2(sscreen->info.gart_size,
 824                                                      sscreen->info.vram_size));
 825                 }
 826                 return sizeof(uint64_t);
 827
 828         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 829                 if (ret) {
 830                         uint64_t *max_local_size = ret;
 831                         /* Value reported by the closed source driver. */
 832                         *max_local_size = 32768;
 833                 }
 834                 return sizeof(uint64_t);
 835
 836         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 837                 if (ret) {
 838                         uint64_t *max_input_size = ret;
 839                         /* Value reported by the closed source driver. */
 840                         *max_input_size = 1024;
 841                 }
 842                 return sizeof(uint64_t);
 843
 844         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 845                 if (ret) {
 846                         uint64_t *max_mem_alloc_size = ret;
 847
 848                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 849                 }
 850                 return sizeof(uint64_t);
 851
 852         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 853                 if (ret) {
 854                         uint32_t *max_clock_frequency = ret;
 855                         *max_clock_frequency = sscreen->info.max_shader_clock;
 856                 }
 857                 return sizeof(uint32_t);
 858
 859         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 860                 if (ret) {
 861                         uint32_t *max_compute_units = ret;
 862                         *max_compute_units = sscreen->info.num_good_compute_units;
 863                 }
 864                 return sizeof(uint32_t);
 865
 866         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 867                 if (ret) {
 868                         uint32_t *images_supported = ret;
 869                         *images_supported = 0;
 870                 }
 871                 return sizeof(uint32_t);
 872         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 873                 break; /* unused */
 874         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 875                 if (ret) {
 876                         uint32_t *subgroup_size = ret;
 877                         *subgroup_size = sscreen->compute_wave_size;
 878                 }
 879                 return sizeof(uint32_t);
 880         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 881                 if (ret) {
 882                         uint64_t *max_variable_threads_per_block = ret;
 883                         if (ir_type == PIPE_SHADER_IR_NATIVE)
 884                                 *max_variable_threads_per_block = 0;
 885                         else
 886                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 887                 }
 888                 return sizeof(uint64_t);
 889         }
 890
 891         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 892         return 0;
 893 }
 894
 895 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 896 {
 897         struct si_screen *sscreen = (struct si_screen*)screen;
 898
 899         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 900                         sscreen->info.clock_crystal_freq;
 901 }
 902
 903 static void si_query_memory_info(struct pipe_screen *screen,
 904                                  struct pipe_memory_info *info)
 905 {
 906         struct si_screen *sscreen = (struct si_screen*)screen;
 907         struct radeon_winsys *ws = sscreen->ws;
 908         unsigned vram_usage, gtt_usage;
 909
 910         info->total_device_memory = sscreen->info.vram_size / 1024;
 911         info->total_staging_memory = sscreen->info.gart_size / 1024;
 912
 913         /* The real TTM memory usage is somewhat random, because:
 914          *
 915          * 1) TTM delays freeing memory, because it can only free it after
 916          *    fences expire.
 917          *
 918          * 2) The memory usage can be really low if big VRAM evictions are
 919          *    taking place, but the real usage is well above the size of VRAM.
 920          *
 921          * Instead, return statistics of this process.
 922          */
 923         vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
 924         gtt_usage =  ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
 925
 926         info->avail_device_memory =
 927                 vram_usage <= info->total_device_memory ?
 928                                 info->total_device_memory - vram_usage : 0;
 929         info->avail_staging_memory =
 930                 gtt_usage <= info->total_staging_memory ?
 931                                 info->total_staging_memory - gtt_usage : 0;
 932
 933         info->device_memory_evicted =
 934                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 935
 936         if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 4)
 937                 info->nr_device_memory_evictions =
 938                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 939         else
 940                 /* Just return the number of evicted 64KB pages. */
 941                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 942 }
 943
 944 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 945 {
 946         struct si_screen *sscreen = (struct si_screen*)pscreen;
 947
 948         return sscreen->disk_shader_cache;
 949 }
 950
 951 static void si_init_renderer_string(struct si_screen *sscreen)
 952 {
 953         char first_name[256], second_name[32] = {}, kernel_version[128] = {};
 954         struct utsname uname_data;
 955
 956         if (sscreen->info.marketing_name) {
 957                 snprintf(first_name, sizeof(first_name), "%s",
 958                          sscreen->info.marketing_name);
 959                 snprintf(second_name, sizeof(second_name), "%s, ",
 960                          sscreen->info.name);
 961         } else {
 962                 snprintf(first_name, sizeof(first_name), "AMD %s",
 963                          sscreen->info.name);
 964         }
 965
 966         if (uname(&uname_data) == 0)
 967                 snprintf(kernel_version, sizeof(kernel_version),
 968                          ", %s", uname_data.release);
 969
 970         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 971                  "%s (%sDRM %i.%i.%i%s, LLVM " MESA_LLVM_VERSION_STRING ")",
 972                  first_name, second_name, sscreen->info.drm_major,
 973                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 974                  kernel_version);
 975 }
 976
 977 void si_init_screen_get_functions(struct si_screen *sscreen)
 978 {
 979         sscreen->b.get_name = si_get_name;
 980         sscreen->b.get_vendor = si_get_vendor;
 981         sscreen->b.get_device_vendor = si_get_device_vendor;
 982         sscreen->b.get_param = si_get_param;
 983         sscreen->b.get_paramf = si_get_paramf;
 984         sscreen->b.get_compute_param = si_get_compute_param;
 985         sscreen->b.get_timestamp = si_get_timestamp;
 986         sscreen->b.get_shader_param = si_get_shader_param;
 987         sscreen->b.get_compiler_options = si_get_compiler_options;
 988         sscreen->b.get_device_uuid = si_get_device_uuid;
 989         sscreen->b.get_driver_uuid = si_get_driver_uuid;
 990         sscreen->b.query_memory_info = si_query_memory_info;
 991         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
 992
 993         if (sscreen->info.has_hw_decode) {
 994                 sscreen->b.get_video_param = si_get_video_param;
 995                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
 996         } else {
 997                 sscreen->b.get_video_param = si_get_video_param_no_decode;
 998                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 999         }
1000
1001         si_init_renderer_string(sscreen);
1002 }