src/gallium/drivers/radeonsi/si_get.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "radeon/radeon_video.h"
  27 #include "radeon/radeon_vce.h"
  28 #include "radeon/radeon_uvd_enc.h"
  29 #include "ac_llvm_util.h"
  30 #include "vl/vl_decoder.h"
  31 #include "vl/vl_video_buffer.h"
  32 #include "util/u_screen.h"
  33 #include "util/u_video.h"
  34 #include "compiler/nir/nir.h"
  35
  36 #include <sys/utsname.h>
  37
  38 static const char *si_get_vendor(struct pipe_screen *pscreen)
  39 {
  40         /* Don't change this. Games such as Alien Isolation are broken if this
  41          * returns "Advanced Micro Devices, Inc."
  42          */
  43         return "X.Org";
  44 }
  45
  46 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
  47 {
  48         return "AMD";
  49 }
  50
  51 static const char *si_get_marketing_name(struct radeon_winsys *ws)
  52 {
  53         if (!ws->get_chip_name)
  54                 return NULL;
  55         return ws->get_chip_name(ws);
  56 }
  57
  58 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  59 {
  60         struct si_screen *sscreen = (struct si_screen *)pscreen;
  61
  62         switch (param) {
  63         /* Supported features (boolean caps). */
  64         case PIPE_CAP_ACCELERATED:
  65         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  66         case PIPE_CAP_ANISOTROPIC_FILTER:
  67         case PIPE_CAP_POINT_SPRITE:
  68         case PIPE_CAP_OCCLUSION_QUERY:
  69         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  70         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
  71         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  72         case PIPE_CAP_TEXTURE_SWIZZLE:
  73         case PIPE_CAP_DEPTH_CLIP_DISABLE:
  74         case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
  75         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  76         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  77         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  78         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  79         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  80         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  81         case PIPE_CAP_SM3:
  82         case PIPE_CAP_SEAMLESS_CUBE_MAP:
  83         case PIPE_CAP_PRIMITIVE_RESTART:
  84         case PIPE_CAP_CONDITIONAL_RENDER:
  85         case PIPE_CAP_TEXTURE_BARRIER:
  86         case PIPE_CAP_INDEP_BLEND_ENABLE:
  87         case PIPE_CAP_INDEP_BLEND_FUNC:
  88         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  89         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  90         case PIPE_CAP_START_INSTANCE:
  91         case PIPE_CAP_NPOT_TEXTURES:
  92         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  93         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  94         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
  95         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
  96         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  97         case PIPE_CAP_TGSI_INSTANCEID:
  98         case PIPE_CAP_COMPUTE:
  99         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 100         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 101         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 102         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 103         case PIPE_CAP_CUBE_MAP_ARRAY:
 104         case PIPE_CAP_SAMPLE_SHADING:
 105         case PIPE_CAP_DRAW_INDIRECT:
 106         case PIPE_CAP_CLIP_HALFZ:
 107         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 108         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 109         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 110         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 111         case PIPE_CAP_TGSI_TEXCOORD:
 112         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 113         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 114         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 115         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 116         case PIPE_CAP_SHAREABLE_SHADERS:
 117         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 118         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 119         case PIPE_CAP_TEXTURE_QUERY_LOD:
 120         case PIPE_CAP_TEXTURE_GATHER_SM5:
 121         case PIPE_CAP_TGSI_TXQS:
 122         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 123         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 124         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 125         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 126         case PIPE_CAP_INVALIDATE_BUFFER:
 127         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 128         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 129         case PIPE_CAP_QUERY_MEMORY_INFO:
 130         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 131         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 132         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 133         case PIPE_CAP_GENERATE_MIPMAP:
 134         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 135         case PIPE_CAP_STRING_MARKER:
 136         case PIPE_CAP_CLEAR_TEXTURE:
 137         case PIPE_CAP_CULL_DISTANCE:
 138         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 139         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 140         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 141         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 142         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 143         case PIPE_CAP_DOUBLES:
 144         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 145         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 146         case PIPE_CAP_BINDLESS_TEXTURE:
 147         case PIPE_CAP_QUERY_TIMESTAMP:
 148         case PIPE_CAP_QUERY_TIME_ELAPSED:
 149         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 150         case PIPE_CAP_QUERY_SO_OVERFLOW:
 151         case PIPE_CAP_MEMOBJ:
 152         case PIPE_CAP_LOAD_CONSTBUF:
 153         case PIPE_CAP_INT64:
 154         case PIPE_CAP_INT64_DIVMOD:
 155         case PIPE_CAP_TGSI_CLOCK:
 156         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 157         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 158         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 159         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 160         case PIPE_CAP_TGSI_BALLOT:
 161         case PIPE_CAP_TGSI_VOTE:
 162         case PIPE_CAP_TGSI_FS_FBFETCH:
 163         case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
 164         case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 165                 return 1;
 166
 167         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 168                 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
 169
 170         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 171                 return sscreen->info.has_gpu_reset_status_query ||
 172                        sscreen->info.has_gpu_reset_counter_query;
 173
 174         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 175                 return sscreen->info.has_2d_tiling;
 176
 177         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 178                 return SI_MAP_BUFFER_ALIGNMENT;
 179
 180         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 181         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 182         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 183         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 184         case PIPE_CAP_MAX_VERTEX_STREAMS:
 185         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 186         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 187                 return 4;
 188
 189         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 190         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 191                 if (sscreen->info.has_indirect_compute_dispatch)
 192                                 return 450;
 193                 return 420;
 194
 195         case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 196                 /* Optimal number for good TexSubImage performance on Polaris10. */
 197                 return 64 * 1024 * 1024;
 198
 199         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 200         case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 201                 return MIN2(sscreen->info.max_alloc_size, INT_MAX);
 202
 203         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 204         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 205         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 206                 return !sscreen->info.has_unaligned_shader_loads;
 207
 208         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 209                 return sscreen->info.has_sparse_vm_mappings ?
 210                                 RADEON_SPARSE_PAGE_SIZE : 0;
 211
 212         case PIPE_CAP_PACKED_UNIFORMS:
 213                 if (sscreen->debug_flags & DBG(NIR))
 214                         return 1;
 215                 return 0;
 216
 217         /* Unsupported features. */
 218         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 219         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 220         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 221         case PIPE_CAP_USER_VERTEX_BUFFERS:
 222         case PIPE_CAP_FAKE_SW_MSAA:
 223         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 224         case PIPE_CAP_VERTEXID_NOBASE:
 225         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 226         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 227         case PIPE_CAP_UMA:
 228         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 229         case PIPE_CAP_POST_DEPTH_COVERAGE:
 230         case PIPE_CAP_TILE_RASTER_ORDER:
 231         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 232         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 233         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 234         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 235         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 236         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 237         case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 238         case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 239         case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 240                 return 0;
 241
 242         case PIPE_CAP_FENCE_SIGNAL:
 243                 return sscreen->info.has_syncobj;
 244
 245         case PIPE_CAP_CONSTBUF0_FLAGS:
 246                 return SI_RESOURCE_FLAG_32BIT;
 247
 248         case PIPE_CAP_NATIVE_FENCE_FD:
 249                 return sscreen->info.has_fence_to_handle;
 250
 251         case PIPE_CAP_DRAW_PARAMETERS:
 252         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 253         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 254                 return sscreen->has_draw_indirect_multi;
 255
 256         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 257                 return 30;
 258
 259         case PIPE_CAP_MAX_VARYINGS:
 260                 return 32;
 261
 262         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 263                 return sscreen->info.chip_class <= VI ?
 264                         PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
 265
 266         /* Stream output. */
 267         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 268         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 269                 return 32*4;
 270
 271         /* Geometry shader output. */
 272         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 273                 return 1024;
 274         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 275                 return 4095;
 276         case PIPE_CAP_MAX_GS_INVOCATIONS:
 277                 /* The closed driver exposes 127, but 125 is the greatest
 278                  * number that works. */
 279                 return 125;
 280
 281         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 282                 return 2048;
 283
 284         /* Texturing. */
 285         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 286         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 287                 return 15; /* 16384 */
 288         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 289                 /* textures support 8192, but layered rendering supports 2048 */
 290                 return 12;
 291         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 292                 /* textures support 8192, but layered rendering supports 2048 */
 293                 return 2048;
 294
 295         /* Viewports and render targets. */
 296         case PIPE_CAP_MAX_VIEWPORTS:
 297                 return SI_MAX_VIEWPORTS;
 298         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 299         case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
 300         case PIPE_CAP_MAX_RENDER_TARGETS:
 301                 return 8;
 302         case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 303                 return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
 304
 305         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 306         case PIPE_CAP_MIN_TEXEL_OFFSET:
 307                 return -32;
 308
 309         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 310         case PIPE_CAP_MAX_TEXEL_OFFSET:
 311                 return 31;
 312
 313         case PIPE_CAP_ENDIANNESS:
 314                 return PIPE_ENDIAN_LITTLE;
 315
 316         case PIPE_CAP_VENDOR_ID:
 317                 return ATI_VENDOR_ID;
 318         case PIPE_CAP_DEVICE_ID:
 319                 return sscreen->info.pci_id;
 320         case PIPE_CAP_VIDEO_MEMORY:
 321                 return sscreen->info.vram_size >> 20;
 322         case PIPE_CAP_PCI_GROUP:
 323                 return sscreen->info.pci_domain;
 324         case PIPE_CAP_PCI_BUS:
 325                 return sscreen->info.pci_bus;
 326         case PIPE_CAP_PCI_DEVICE:
 327                 return sscreen->info.pci_dev;
 328         case PIPE_CAP_PCI_FUNCTION:
 329                 return sscreen->info.pci_func;
 330
 331         default:
 332                 return u_pipe_screen_get_param_defaults(pscreen, param);
 333         }
 334 }
 335
 336 static float si_get_paramf(struct pipe_screen* pscreen, enum pipe_capf param)
 337 {
 338         switch (param) {
 339         case PIPE_CAPF_MAX_LINE_WIDTH:
 340         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 341                 /* This depends on the quant mode, though the precise interactions
 342                  * are unknown. */
 343                 return 2048;
 344         case PIPE_CAPF_MAX_POINT_WIDTH:
 345         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 346                 return SI_MAX_POINT_SIZE;
 347         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 348                 return 16.0f;
 349         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 350                 return 16.0f;
 351         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 352         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 353         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 354                 return 0.0f;
 355         }
 356         return 0.0f;
 357 }
 358
 359 static int si_get_shader_param(struct pipe_screen* pscreen,
 360                                enum pipe_shader_type shader,
 361                                enum pipe_shader_cap param)
 362 {
 363         struct si_screen *sscreen = (struct si_screen *)pscreen;
 364
 365         switch(shader)
 366         {
 367         case PIPE_SHADER_FRAGMENT:
 368         case PIPE_SHADER_VERTEX:
 369         case PIPE_SHADER_GEOMETRY:
 370         case PIPE_SHADER_TESS_CTRL:
 371         case PIPE_SHADER_TESS_EVAL:
 372                 break;
 373         case PIPE_SHADER_COMPUTE:
 374                 switch (param) {
 375                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 376                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 377
 378                         if (sscreen->info.has_indirect_compute_dispatch)
 379                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 380
 381                         return ir;
 382                 }
 383
 384                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 385                         uint64_t max_const_buffer_size;
 386                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 387                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 388                                 &max_const_buffer_size);
 389                         return MIN2(max_const_buffer_size, INT_MAX);
 390                 }
 391                 default:
 392                         /* If compute shaders don't require a special value
 393                          * for this cap, we can return the same value we
 394                          * do for other shader types. */
 395                         break;
 396                 }
 397                 break;
 398         default:
 399                 return 0;
 400         }
 401
 402         switch (param) {
 403         /* Shader limits. */
 404         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 405         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 406         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 407         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 408         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 409                 return 16384;
 410         case PIPE_SHADER_CAP_MAX_INPUTS:
 411                 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
 412         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 413                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 414         case PIPE_SHADER_CAP_MAX_TEMPS:
 415                 return 256; /* Max native temporaries. */
 416         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 417                 return MIN2(sscreen->info.max_alloc_size, INT_MAX - 3); /* aligned to 4 */
 418         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 419                 return SI_NUM_CONST_BUFFERS;
 420         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 421         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 422                 return SI_NUM_SAMPLERS;
 423         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 424                 return SI_NUM_SHADER_BUFFERS;
 425         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 426                 return SI_NUM_IMAGES;
 427         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 428                 if (sscreen->debug_flags & DBG(NIR))
 429                         return 0;
 430                 return 32;
 431         case PIPE_SHADER_CAP_PREFERRED_IR:
 432                 if (sscreen->debug_flags & DBG(NIR))
 433                         return PIPE_SHADER_IR_NIR;
 434                 return PIPE_SHADER_IR_TGSI;
 435         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 436                 return 4;
 437
 438         /* Supported boolean features. */
 439         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 440         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 441         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 442         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 443         case PIPE_SHADER_CAP_INTEGERS:
 444         case PIPE_SHADER_CAP_INT64_ATOMICS:
 445         case PIPE_SHADER_CAP_FP16:
 446         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 447         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 448         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 449         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 450         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 451         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 452                 return 1;
 453
 454         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 455                 /* TODO: Indirect indexing of GS inputs is unimplemented. */
 456                 if (shader == PIPE_SHADER_GEOMETRY)
 457                         return 0;
 458
 459                 if (shader == PIPE_SHADER_VERTEX &&
 460                     !sscreen->llvm_has_working_vgpr_indexing)
 461                         return 0;
 462
 463                 /* TCS and TES load inputs directly from LDS or offchip
 464                  * memory, so indirect indexing is always supported.
 465                  * PS has to support indirect indexing, because we can't
 466                  * lower that to TEMPs for INTERP instructions.
 467                  */
 468                 return 1;
 469
 470         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 471                 return sscreen->llvm_has_working_vgpr_indexing ||
 472                        /* TCS stores outputs directly to memory. */
 473                        shader == PIPE_SHADER_TESS_CTRL;
 474
 475         /* Unsupported boolean features. */
 476         case PIPE_SHADER_CAP_SUBROUTINES:
 477         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 478         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 479         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 480                 return 0;
 481         case PIPE_SHADER_CAP_SCALAR_ISA:
 482                 return 1;
 483         }
 484         return 0;
 485 }
 486
 487 static const struct nir_shader_compiler_options nir_options = {
 488         .lower_scmp = true,
 489         .lower_flrp32 = true,
 490         .lower_flrp64 = true,
 491         .lower_fsat = true,
 492         .lower_fdiv = true,
 493         .lower_sub = true,
 494         .lower_ffma = true,
 495         .lower_pack_snorm_2x16 = true,
 496         .lower_pack_snorm_4x8 = true,
 497         .lower_pack_unorm_2x16 = true,
 498         .lower_pack_unorm_4x8 = true,
 499         .lower_unpack_snorm_2x16 = true,
 500         .lower_unpack_snorm_4x8 = true,
 501         .lower_unpack_unorm_2x16 = true,
 502         .lower_unpack_unorm_4x8 = true,
 503         .lower_extract_byte = true,
 504         .lower_extract_word = true,
 505         .optimize_sample_mask_in = true,
 506         .max_unroll_iterations = 32,
 507         .native_integers = true,
 508 };
 509
 510 static const void *
 511 si_get_compiler_options(struct pipe_screen *screen,
 512                         enum pipe_shader_ir ir,
 513                         enum pipe_shader_type shader)
 514 {
 515         assert(ir == PIPE_SHADER_IR_NIR);
 516         return &nir_options;
 517 }
 518
 519 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 520 {
 521         ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
 522 }
 523
 524 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 525 {
 526         struct si_screen *sscreen = (struct si_screen *)pscreen;
 527
 528         ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
 529 }
 530
 531 static const char* si_get_name(struct pipe_screen *pscreen)
 532 {
 533         struct si_screen *sscreen = (struct si_screen*)pscreen;
 534
 535         return sscreen->renderer_string;
 536 }
 537
 538 static int si_get_video_param_no_decode(struct pipe_screen *screen,
 539                                         enum pipe_video_profile profile,
 540                                         enum pipe_video_entrypoint entrypoint,
 541                                         enum pipe_video_cap param)
 542 {
 543         switch (param) {
 544         case PIPE_VIDEO_CAP_SUPPORTED:
 545                 return vl_profile_supported(screen, profile, entrypoint);
 546         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 547                 return 1;
 548         case PIPE_VIDEO_CAP_MAX_WIDTH:
 549         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 550                 return vl_video_buffer_max_size(screen);
 551         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 552                 return PIPE_FORMAT_NV12;
 553         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 554                 return false;
 555         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 556                 return false;
 557         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 558                 return true;
 559         case PIPE_VIDEO_CAP_MAX_LEVEL:
 560                 return vl_level_supported(screen, profile);
 561         default:
 562                 return 0;
 563         }
 564 }
 565
 566 static int si_get_video_param(struct pipe_screen *screen,
 567                               enum pipe_video_profile profile,
 568                               enum pipe_video_entrypoint entrypoint,
 569                               enum pipe_video_cap param)
 570 {
 571         struct si_screen *sscreen = (struct si_screen *)screen;
 572         enum pipe_video_format codec = u_reduce_video_profile(profile);
 573
 574         if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
 575                 switch (param) {
 576                 case PIPE_VIDEO_CAP_SUPPORTED:
 577                         return (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
 578                                 (si_vce_is_fw_version_supported(sscreen) ||
 579                                  sscreen->info.family == CHIP_RAVEN ||
 580                                  sscreen->info.family == CHIP_RAVEN2)) ||
 581                                 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
 582                                 (sscreen->info.family == CHIP_RAVEN ||
 583                                  sscreen->info.family == CHIP_RAVEN2 ||
 584                                  si_radeon_uvd_enc_supported(sscreen)));
 585                 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 586                         return 1;
 587                 case PIPE_VIDEO_CAP_MAX_WIDTH:
 588                         return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 589                 case PIPE_VIDEO_CAP_MAX_HEIGHT:
 590                         return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
 591                 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 592                         return PIPE_FORMAT_NV12;
 593                 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 594                         return false;
 595                 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 596                         return false;
 597                 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 598                         return true;
 599                 case PIPE_VIDEO_CAP_STACKED_FRAMES:
 600                         return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
 601                 default:
 602                         return 0;
 603                 }
 604         }
 605
 606         switch (param) {
 607         case PIPE_VIDEO_CAP_SUPPORTED:
 608                 switch (codec) {
 609                 case PIPE_VIDEO_FORMAT_MPEG12:
 610                         return profile != PIPE_VIDEO_PROFILE_MPEG1;
 611                 case PIPE_VIDEO_FORMAT_MPEG4:
 612                         return 1;
 613                 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
 614                         if ((sscreen->info.family == CHIP_POLARIS10 ||
 615                              sscreen->info.family == CHIP_POLARIS11) &&
 616                             sscreen->info.uvd_fw_version < UVD_FW_1_66_16 ) {
 617                                 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
 618                                 return false;
 619                         }
 620                         return true;
 621                 case PIPE_VIDEO_FORMAT_VC1:
 622                         return true;
 623                 case PIPE_VIDEO_FORMAT_HEVC:
 624                         /* Carrizo only supports HEVC Main */
 625                         if (sscreen->info.family >= CHIP_STONEY)
 626                                 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
 627                                         profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
 628                         else if (sscreen->info.family >= CHIP_CARRIZO)
 629                                 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
 630                         return false;
 631                 case PIPE_VIDEO_FORMAT_JPEG:
 632                         if (sscreen->info.family == CHIP_RAVEN ||
 633                             sscreen->info.family == CHIP_RAVEN2)
 634                                 return true;
 635                         if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
 636                                 return false;
 637                         if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
 638                                 RVID_ERR("No MJPEG support for the kernel version\n");
 639                                 return false;
 640                         }
 641                         return true;
 642                 case PIPE_VIDEO_FORMAT_VP9:
 643                         if (sscreen->info.family < CHIP_RAVEN)
 644                                 return false;
 645                         return true;
 646                 default:
 647                         return false;
 648                 }
 649         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 650                 return 1;
 651         case PIPE_VIDEO_CAP_MAX_WIDTH:
 652                 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
 653         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 654                 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
 655         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 656                 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 ||
 657                     profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
 658                         return PIPE_FORMAT_P016;
 659                 else
 660                         return PIPE_FORMAT_NV12;
 661
 662         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 663         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
 664                 enum pipe_video_format format = u_reduce_video_profile(profile);
 665
 666                 if (format == PIPE_VIDEO_FORMAT_HEVC)
 667                         return false; //The firmware doesn't support interlaced HEVC.
 668                 else if (format == PIPE_VIDEO_FORMAT_JPEG)
 669                         return false;
 670                 else if (format == PIPE_VIDEO_FORMAT_VP9)
 671                         return false;
 672                 return true;
 673         }
 674         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 675                 return true;
 676         case PIPE_VIDEO_CAP_MAX_LEVEL:
 677                 switch (profile) {
 678                 case PIPE_VIDEO_PROFILE_MPEG1:
 679                         return 0;
 680                 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
 681                 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
 682                         return 3;
 683                 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
 684                         return 3;
 685                 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
 686                         return 5;
 687                 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
 688                         return 1;
 689                 case PIPE_VIDEO_PROFILE_VC1_MAIN:
 690                         return 2;
 691                 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
 692                         return 4;
 693                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
 694                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
 695                 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
 696                         return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
 697                 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
 698                 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
 699                         return 186;
 700                 default:
 701                         return 0;
 702                 }
 703         default:
 704                 return 0;
 705         }
 706 }
 707
 708 static boolean si_vid_is_format_supported(struct pipe_screen *screen,
 709                                           enum pipe_format format,
 710                                           enum pipe_video_profile profile,
 711                                           enum pipe_video_entrypoint entrypoint)
 712 {
 713         /* HEVC 10 bit decoding should use P016 instead of NV12 if possible */
 714         if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
 715                 return (format == PIPE_FORMAT_NV12) ||
 716                         (format == PIPE_FORMAT_P016);
 717
 718         /* we can only handle this one with UVD */
 719         if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
 720                 return format == PIPE_FORMAT_NV12;
 721
 722         return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
 723 }
 724
 725 static unsigned get_max_threads_per_block(struct si_screen *screen,
 726                                           enum pipe_shader_ir ir_type)
 727 {
 728         if (ir_type == PIPE_SHADER_IR_NATIVE)
 729                 return 256;
 730
 731         /* Only 16 waves per thread-group on gfx9. */
 732         if (screen->info.chip_class >= GFX9)
 733                 return 1024;
 734
 735         /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
 736          * round number.
 737          */
 738         return 2048;
 739 }
 740
 741 static int si_get_compute_param(struct pipe_screen *screen,
 742                                 enum pipe_shader_ir ir_type,
 743                                 enum pipe_compute_cap param,
 744                                 void *ret)
 745 {
 746         struct si_screen *sscreen = (struct si_screen *)screen;
 747
 748         //TODO: select these params by asic
 749         switch (param) {
 750         case PIPE_COMPUTE_CAP_IR_TARGET: {
 751                 const char *gpu, *triple;
 752
 753                 triple = "amdgcn-mesa-mesa3d";
 754                 gpu = ac_get_llvm_processor_name(sscreen->info.family);
 755                 if (ret) {
 756                         sprintf(ret, "%s-%s", gpu, triple);
 757                 }
 758                 /* +2 for dash and terminating NIL byte */
 759                 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
 760         }
 761         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 762                 if (ret) {
 763                         uint64_t *grid_dimension = ret;
 764                         grid_dimension[0] = 3;
 765                 }
 766                 return 1 * sizeof(uint64_t);
 767
 768         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 769                 if (ret) {
 770                         uint64_t *grid_size = ret;
 771                         grid_size[0] = 65535;
 772                         grid_size[1] = 65535;
 773                         grid_size[2] = 65535;
 774                 }
 775                 return 3 * sizeof(uint64_t) ;
 776
 777         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 778                 if (ret) {
 779                         uint64_t *block_size = ret;
 780                         unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 781                         block_size[0] = threads_per_block;
 782                         block_size[1] = threads_per_block;
 783                         block_size[2] = threads_per_block;
 784                 }
 785                 return 3 * sizeof(uint64_t);
 786
 787         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 788                 if (ret) {
 789                         uint64_t *max_threads_per_block = ret;
 790                         *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
 791                 }
 792                 return sizeof(uint64_t);
 793         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 794                 if (ret) {
 795                         uint32_t *address_bits = ret;
 796                         address_bits[0] = 64;
 797                 }
 798                 return 1 * sizeof(uint32_t);
 799
 800         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 801                 if (ret) {
 802                         uint64_t *max_global_size = ret;
 803                         uint64_t max_mem_alloc_size;
 804
 805                         si_get_compute_param(screen, ir_type,
 806                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 807                                 &max_mem_alloc_size);
 808
 809                         /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
 810                          * 1/4 of the MAX_GLOBAL_SIZE.  Since the
 811                          * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
 812                          * make sure we never report more than
 813                          * 4 * MAX_MEM_ALLOC_SIZE.
 814                          */
 815                         *max_global_size = MIN2(4 * max_mem_alloc_size,
 816                                                 MAX2(sscreen->info.gart_size,
 817                                                      sscreen->info.vram_size));
 818                 }
 819                 return sizeof(uint64_t);
 820
 821         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 822                 if (ret) {
 823                         uint64_t *max_local_size = ret;
 824                         /* Value reported by the closed source driver. */
 825                         *max_local_size = 32768;
 826                 }
 827                 return sizeof(uint64_t);
 828
 829         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 830                 if (ret) {
 831                         uint64_t *max_input_size = ret;
 832                         /* Value reported by the closed source driver. */
 833                         *max_input_size = 1024;
 834                 }
 835                 return sizeof(uint64_t);
 836
 837         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 838                 if (ret) {
 839                         uint64_t *max_mem_alloc_size = ret;
 840
 841                         *max_mem_alloc_size = sscreen->info.max_alloc_size;
 842                 }
 843                 return sizeof(uint64_t);
 844
 845         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 846                 if (ret) {
 847                         uint32_t *max_clock_frequency = ret;
 848                         *max_clock_frequency = sscreen->info.max_shader_clock;
 849                 }
 850                 return sizeof(uint32_t);
 851
 852         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 853                 if (ret) {
 854                         uint32_t *max_compute_units = ret;
 855                         *max_compute_units = sscreen->info.num_good_compute_units;
 856                 }
 857                 return sizeof(uint32_t);
 858
 859         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 860                 if (ret) {
 861                         uint32_t *images_supported = ret;
 862                         *images_supported = 0;
 863                 }
 864                 return sizeof(uint32_t);
 865         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 866                 break; /* unused */
 867         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 868                 if (ret) {
 869                         uint32_t *subgroup_size = ret;
 870                         *subgroup_size = 64;
 871                 }
 872                 return sizeof(uint32_t);
 873         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 874                 if (ret) {
 875                         uint64_t *max_variable_threads_per_block = ret;
 876                         if (ir_type == PIPE_SHADER_IR_NATIVE)
 877                                 *max_variable_threads_per_block = 0;
 878                         else
 879                                 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
 880                 }
 881                 return sizeof(uint64_t);
 882         }
 883
 884         fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 885         return 0;
 886 }
 887
 888 static uint64_t si_get_timestamp(struct pipe_screen *screen)
 889 {
 890         struct si_screen *sscreen = (struct si_screen*)screen;
 891
 892         return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
 893                         sscreen->info.clock_crystal_freq;
 894 }
 895
 896 static void si_query_memory_info(struct pipe_screen *screen,
 897                                  struct pipe_memory_info *info)
 898 {
 899         struct si_screen *sscreen = (struct si_screen*)screen;
 900         struct radeon_winsys *ws = sscreen->ws;
 901         unsigned vram_usage, gtt_usage;
 902
 903         info->total_device_memory = sscreen->info.vram_size / 1024;
 904         info->total_staging_memory = sscreen->info.gart_size / 1024;
 905
 906         /* The real TTM memory usage is somewhat random, because:
 907          *
 908          * 1) TTM delays freeing memory, because it can only free it after
 909          *    fences expire.
 910          *
 911          * 2) The memory usage can be really low if big VRAM evictions are
 912          *    taking place, but the real usage is well above the size of VRAM.
 913          *
 914          * Instead, return statistics of this process.
 915          */
 916         vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
 917         gtt_usage =  ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
 918
 919         info->avail_device_memory =
 920                 vram_usage <= info->total_device_memory ?
 921                                 info->total_device_memory - vram_usage : 0;
 922         info->avail_staging_memory =
 923                 gtt_usage <= info->total_staging_memory ?
 924                                 info->total_staging_memory - gtt_usage : 0;
 925
 926         info->device_memory_evicted =
 927                 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
 928
 929         if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
 930                 info->nr_device_memory_evictions =
 931                         ws->query_value(ws, RADEON_NUM_EVICTIONS);
 932         else
 933                 /* Just return the number of evicted 64KB pages. */
 934                 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
 935 }
 936
 937 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
 938 {
 939         struct si_screen *sscreen = (struct si_screen*)pscreen;
 940
 941         return sscreen->disk_shader_cache;
 942 }
 943
 944 static void si_init_renderer_string(struct si_screen *sscreen)
 945 {
 946         struct radeon_winsys *ws = sscreen->ws;
 947         char first_name[256], second_name[32] = {}, kernel_version[128] = {};
 948         struct utsname uname_data;
 949
 950         const char *marketing_name = si_get_marketing_name(ws);
 951
 952         if (marketing_name) {
 953                 snprintf(first_name, sizeof(first_name), "%s", marketing_name);
 954                 snprintf(second_name, sizeof(second_name), "%s, ",
 955                          sscreen->info.name);
 956         } else {
 957                 snprintf(first_name, sizeof(first_name), "AMD %s",
 958                          sscreen->info.name);
 959         }
 960
 961         if (uname(&uname_data) == 0)
 962                 snprintf(kernel_version, sizeof(kernel_version),
 963                          ", %s", uname_data.release);
 964
 965         snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
 966                  "%s (%sDRM %i.%i.%i%s, LLVM " MESA_LLVM_VERSION_STRING ")",
 967                  first_name, second_name, sscreen->info.drm_major,
 968                  sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
 969                  kernel_version);
 970 }
 971
 972 void si_init_screen_get_functions(struct si_screen *sscreen)
 973 {
 974         sscreen->b.get_name = si_get_name;
 975         sscreen->b.get_vendor = si_get_vendor;
 976         sscreen->b.get_device_vendor = si_get_device_vendor;
 977         sscreen->b.get_param = si_get_param;
 978         sscreen->b.get_paramf = si_get_paramf;
 979         sscreen->b.get_compute_param = si_get_compute_param;
 980         sscreen->b.get_timestamp = si_get_timestamp;
 981         sscreen->b.get_shader_param = si_get_shader_param;
 982         sscreen->b.get_compiler_options = si_get_compiler_options;
 983         sscreen->b.get_device_uuid = si_get_device_uuid;
 984         sscreen->b.get_driver_uuid = si_get_driver_uuid;
 985         sscreen->b.query_memory_info = si_query_memory_info;
 986         sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
 987
 988         if (sscreen->info.has_hw_decode) {
 989                 sscreen->b.get_video_param = si_get_video_param;
 990                 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
 991         } else {
 992                 sscreen->b.get_video_param = si_get_video_param_no_decode;
 993                 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
 994         }
 995
 996         si_init_renderer_string(sscreen);
 997 }